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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #ifndef _INTEL_GUC_H_ | |
25 | #define _INTEL_GUC_H_ | |
26 | ||
27 | #include "intel_guc_fwif.h" | |
28 | #include "i915_guc_reg.h" | |
29 | ||
e73bdd20 CW |
30 | struct drm_i915_gem_request; |
31 | ||
44a28b1d DG |
32 | struct i915_guc_client { |
33 | struct drm_i915_gem_object *client_obj; | |
d1675198 | 34 | struct intel_context *owner; |
44a28b1d DG |
35 | struct intel_guc *guc; |
36 | uint32_t priority; | |
37 | uint32_t ctx_index; | |
38 | ||
39 | uint32_t proc_desc_offset; | |
40 | uint32_t doorbell_offset; | |
41 | uint32_t cookie; | |
42 | uint16_t doorbell_id; | |
43 | uint16_t padding; /* Maintain alignment */ | |
44 | ||
45 | uint32_t wq_offset; | |
46 | uint32_t wq_size; | |
44a28b1d | 47 | uint32_t wq_tail; |
a7e02199 | 48 | uint32_t wq_head; |
44a28b1d DG |
49 | |
50 | /* GuC submission statistics & status */ | |
397097b0 | 51 | uint64_t submissions[GUC_MAX_ENGINES_NUM]; |
44a28b1d DG |
52 | uint32_t q_fail; |
53 | uint32_t b_fail; | |
54 | int retcode; | |
55 | }; | |
56 | ||
33a732f4 AD |
57 | enum intel_guc_fw_status { |
58 | GUC_FIRMWARE_FAIL = -1, | |
59 | GUC_FIRMWARE_NONE = 0, | |
60 | GUC_FIRMWARE_PENDING, | |
61 | GUC_FIRMWARE_SUCCESS | |
62 | }; | |
63 | ||
64 | /* | |
65 | * This structure encapsulates all the data needed during the process | |
66 | * of fetching, caching, and loading the firmware image into the GuC. | |
67 | */ | |
68 | struct intel_guc_fw { | |
69 | struct drm_device * guc_dev; | |
70 | const char * guc_fw_path; | |
71 | size_t guc_fw_size; | |
72 | struct drm_i915_gem_object * guc_fw_obj; | |
73 | enum intel_guc_fw_status guc_fw_fetch_status; | |
74 | enum intel_guc_fw_status guc_fw_load_status; | |
75 | ||
76 | uint16_t guc_fw_major_wanted; | |
77 | uint16_t guc_fw_minor_wanted; | |
78 | uint16_t guc_fw_major_found; | |
79 | uint16_t guc_fw_minor_found; | |
feda33ef AD |
80 | |
81 | uint32_t header_size; | |
82 | uint32_t header_offset; | |
83 | uint32_t rsa_size; | |
84 | uint32_t rsa_offset; | |
85 | uint32_t ucode_size; | |
86 | uint32_t ucode_offset; | |
33a732f4 AD |
87 | }; |
88 | ||
89 | struct intel_guc { | |
90 | struct intel_guc_fw guc_fw; | |
33a732f4 | 91 | uint32_t log_flags; |
4c7e77fc | 92 | struct drm_i915_gem_object *log_obj; |
bac427f8 | 93 | |
68371a95 AD |
94 | struct drm_i915_gem_object *ads_obj; |
95 | ||
bac427f8 AD |
96 | struct drm_i915_gem_object *ctx_pool_obj; |
97 | struct ida ctx_ids; | |
44a28b1d DG |
98 | |
99 | struct i915_guc_client *execbuf_client; | |
100 | ||
44a28b1d DG |
101 | DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS); |
102 | uint32_t db_cacheline; /* Cyclic counter mod pagesize */ | |
103 | ||
104 | /* Action status & statistics */ | |
105 | uint64_t action_count; /* Total commands issued */ | |
106 | uint32_t action_cmd; /* Last command word */ | |
107 | uint32_t action_status; /* Last return status */ | |
108 | uint32_t action_fail; /* Total number of failures */ | |
109 | int32_t action_err; /* Last error code */ | |
110 | ||
397097b0 AD |
111 | uint64_t submissions[GUC_MAX_ENGINES_NUM]; |
112 | uint32_t last_seqno[GUC_MAX_ENGINES_NUM]; | |
33a732f4 AD |
113 | }; |
114 | ||
115 | /* intel_guc_loader.c */ | |
116 | extern void intel_guc_ucode_init(struct drm_device *dev); | |
117 | extern int intel_guc_ucode_load(struct drm_device *dev); | |
118 | extern void intel_guc_ucode_fini(struct drm_device *dev); | |
119 | extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status); | |
a1c41994 AD |
120 | extern int intel_guc_suspend(struct drm_device *dev); |
121 | extern int intel_guc_resume(struct drm_device *dev); | |
33a732f4 | 122 | |
bac427f8 AD |
123 | /* i915_guc_submission.c */ |
124 | int i915_guc_submission_init(struct drm_device *dev); | |
44a28b1d DG |
125 | int i915_guc_submission_enable(struct drm_device *dev); |
126 | int i915_guc_submit(struct i915_guc_client *client, | |
127 | struct drm_i915_gem_request *rq); | |
128 | void i915_guc_submission_disable(struct drm_device *dev); | |
bac427f8 | 129 | void i915_guc_submission_fini(struct drm_device *dev); |
a7e02199 | 130 | int i915_guc_wq_check_space(struct i915_guc_client *client); |
bac427f8 | 131 | |
33a732f4 | 132 | #endif |