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2617268f DG |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | #ifndef _INTEL_GUC_FWIF_H | |
24 | #define _INTEL_GUC_FWIF_H | |
25 | ||
26 | /* | |
27 | * This file is partially autogenerated, although currently with some manual | |
28 | * fixups afterwards. In future, it should be entirely autogenerated, in order | |
29 | * to ensure that the definitions herein remain in sync with those used by the | |
30 | * GuC's own firmware. | |
31 | * | |
32 | * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. | |
33 | */ | |
34 | ||
2617268f | 35 | #define GFXCORE_FAMILY_GEN9 12 |
33a732f4 | 36 | #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff |
2617268f | 37 | |
44a28b1d | 38 | #define GUC_CTX_PRIORITY_KMD_HIGH 0 |
2617268f | 39 | #define GUC_CTX_PRIORITY_HIGH 1 |
44a28b1d DG |
40 | #define GUC_CTX_PRIORITY_KMD_NORMAL 2 |
41 | #define GUC_CTX_PRIORITY_NORMAL 3 | |
463704d0 | 42 | #define GUC_CTX_PRIORITY_NUM 4 |
2617268f DG |
43 | |
44 | #define GUC_MAX_GPU_CONTEXTS 1024 | |
aa557ab0 | 45 | #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS |
2617268f | 46 | |
397097b0 AD |
47 | #define GUC_RENDER_ENGINE 0 |
48 | #define GUC_VIDEO_ENGINE 1 | |
49 | #define GUC_BLITTER_ENGINE 2 | |
50 | #define GUC_VIDEOENHANCE_ENGINE 3 | |
51 | #define GUC_VIDEO_ENGINE2 4 | |
52 | #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) | |
53 | ||
2617268f DG |
54 | /* Work queue item header definitions */ |
55 | #define WQ_STATUS_ACTIVE 1 | |
56 | #define WQ_STATUS_SUSPENDED 2 | |
57 | #define WQ_STATUS_CMD_ERROR 3 | |
58 | #define WQ_STATUS_ENGINE_ID_NOT_USED 4 | |
59 | #define WQ_STATUS_SUSPENDED_FROM_RESET 5 | |
60 | #define WQ_TYPE_SHIFT 0 | |
61 | #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) | |
62 | #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) | |
63 | #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) | |
64 | #define WQ_TARGET_SHIFT 10 | |
65 | #define WQ_LEN_SHIFT 16 | |
66 | #define WQ_NO_WCFLUSH_WAIT (1 << 27) | |
67 | #define WQ_PRESENT_WORKLOAD (1 << 28) | |
68 | #define WQ_WORKLOAD_SHIFT 29 | |
69 | #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) | |
70 | #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) | |
71 | #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) | |
72 | ||
73 | #define WQ_RING_TAIL_SHIFT 20 | |
74 | #define WQ_RING_TAIL_MASK (0x7FF << WQ_RING_TAIL_SHIFT) | |
75 | ||
76 | #define GUC_DOORBELL_ENABLED 1 | |
77 | #define GUC_DOORBELL_DISABLED 0 | |
78 | ||
79 | #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) | |
80 | #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) | |
81 | #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) | |
82 | #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) | |
83 | #define GUC_CTX_DESC_ATTR_RESET (1 << 4) | |
84 | #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) | |
85 | #define GUC_CTX_DESC_ATTR_PCH (1 << 6) | |
aa557ab0 | 86 | #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7) |
2617268f DG |
87 | |
88 | /* The guc control data is 10 DWORDs */ | |
89 | #define GUC_CTL_CTXINFO 0 | |
90 | #define GUC_CTL_CTXNUM_IN16_SHIFT 0 | |
91 | #define GUC_CTL_BASE_ADDR_SHIFT 12 | |
68371a95 | 92 | |
2617268f DG |
93 | #define GUC_CTL_ARAT_HIGH 1 |
94 | #define GUC_CTL_ARAT_LOW 2 | |
68371a95 | 95 | |
2617268f DG |
96 | #define GUC_CTL_DEVICE_INFO 3 |
97 | #define GUC_CTL_GTTYPE_SHIFT 0 | |
98 | #define GUC_CTL_COREFAMILY_SHIFT 7 | |
68371a95 | 99 | |
2617268f DG |
100 | #define GUC_CTL_LOG_PARAMS 4 |
101 | #define GUC_LOG_VALID (1 << 0) | |
102 | #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) | |
103 | #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) | |
104 | #define GUC_LOG_CRASH_PAGES 1 | |
105 | #define GUC_LOG_CRASH_SHIFT 4 | |
106 | #define GUC_LOG_DPC_PAGES 3 | |
107 | #define GUC_LOG_DPC_SHIFT 6 | |
108 | #define GUC_LOG_ISR_PAGES 3 | |
109 | #define GUC_LOG_ISR_SHIFT 9 | |
110 | #define GUC_LOG_BUF_ADDR_SHIFT 12 | |
68371a95 | 111 | |
2617268f | 112 | #define GUC_CTL_PAGE_FAULT_CONTROL 5 |
68371a95 | 113 | |
2617268f DG |
114 | #define GUC_CTL_WA 6 |
115 | #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) | |
68371a95 | 116 | |
2617268f DG |
117 | #define GUC_CTL_FEATURE 7 |
118 | #define GUC_CTL_VCS2_ENABLED (1 << 0) | |
119 | #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) | |
120 | #define GUC_CTL_FEATURE2 (1 << 2) | |
121 | #define GUC_CTL_POWER_GATING (1 << 3) | |
122 | #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) | |
123 | #define GUC_CTL_PREEMPTION_LOG (1 << 5) | |
124 | #define GUC_CTL_ENABLE_SLPC (1 << 7) | |
aa557ab0 | 125 | #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) |
68371a95 | 126 | |
2617268f DG |
127 | #define GUC_CTL_DEBUG 8 |
128 | #define GUC_LOG_VERBOSITY_SHIFT 0 | |
129 | #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) | |
130 | #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) | |
131 | #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) | |
132 | #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) | |
133 | /* Verbosity range-check limits, without the shift */ | |
134 | #define GUC_LOG_VERBOSITY_MIN 0 | |
135 | #define GUC_LOG_VERBOSITY_MAX 3 | |
68371a95 AD |
136 | #define GUC_LOG_VERBOSITY_MASK 0x0000000f |
137 | #define GUC_LOG_DESTINATION_MASK (3 << 4) | |
138 | #define GUC_LOG_DISABLED (1 << 6) | |
139 | #define GUC_PROFILE_ENABLED (1 << 7) | |
140 | #define GUC_WQ_TRACK_ENABLED (1 << 8) | |
141 | #define GUC_ADS_ENABLED (1 << 9) | |
142 | #define GUC_DEBUG_RESERVED (1 << 10) | |
143 | #define GUC_ADS_ADDR_SHIFT 11 | |
144 | #define GUC_ADS_ADDR_MASK 0xfffff800 | |
145 | ||
aa557ab0 | 146 | #define GUC_CTL_RSRVD 9 |
2617268f | 147 | |
68371a95 | 148 | #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ |
2617268f | 149 | |
feda33ef AD |
150 | /** |
151 | * DOC: GuC Firmware Layout | |
152 | * | |
153 | * The GuC firmware layout looks like this: | |
154 | * | |
155 | * +-------------------------------+ | |
156 | * | guc_css_header | | |
157 | * | contains major/minor version | | |
158 | * +-------------------------------+ | |
159 | * | uCode | | |
160 | * +-------------------------------+ | |
161 | * | RSA signature | | |
162 | * +-------------------------------+ | |
163 | * | modulus key | | |
164 | * +-------------------------------+ | |
165 | * | exponent val | | |
166 | * +-------------------------------+ | |
167 | * | |
168 | * The firmware may or may not have modulus key and exponent data. The header, | |
169 | * uCode and RSA signature are must-have components that will be used by driver. | |
170 | * Length of each components, which is all in dwords, can be found in header. | |
171 | * In the case that modulus and exponent are not present in fw, a.k.a truncated | |
172 | * image, the length value still appears in header. | |
173 | * | |
174 | * Driver will do some basic fw size validation based on the following rules: | |
175 | * | |
176 | * 1. Header, uCode and RSA are must-have components. | |
177 | * 2. All firmware components, if they present, are in the sequence illustrated | |
178 | * in the layout table above. | |
179 | * 3. Length info of each component can be found in header, in dwords. | |
180 | * 4. Modulus and exponent key are not required by driver. They may not appear | |
181 | * in fw. So driver will load a truncated firmware in this case. | |
182 | */ | |
183 | ||
184 | struct guc_css_header { | |
185 | uint32_t module_type; | |
186 | /* header_size includes all non-uCode bits, including css_header, rsa | |
187 | * key, modulus key and exponent data. */ | |
188 | uint32_t header_size_dw; | |
189 | uint32_t header_version; | |
190 | uint32_t module_id; | |
191 | uint32_t module_vendor; | |
192 | union { | |
193 | struct { | |
194 | uint8_t day; | |
195 | uint8_t month; | |
196 | uint16_t year; | |
197 | }; | |
198 | uint32_t date; | |
199 | }; | |
200 | uint32_t size_dw; /* uCode plus header_size_dw */ | |
201 | uint32_t key_size_dw; | |
202 | uint32_t modulus_size_dw; | |
203 | uint32_t exponent_size_dw; | |
204 | union { | |
205 | struct { | |
206 | uint8_t hour; | |
207 | uint8_t min; | |
208 | uint16_t sec; | |
209 | }; | |
210 | uint32_t time; | |
211 | }; | |
212 | ||
213 | char username[8]; | |
214 | char buildnumber[12]; | |
215 | uint32_t device_id; | |
216 | uint32_t guc_sw_version; | |
217 | uint32_t prod_preprod_fw; | |
218 | uint32_t reserved[12]; | |
219 | uint32_t header_info; | |
220 | } __packed; | |
221 | ||
2617268f DG |
222 | struct guc_doorbell_info { |
223 | u32 db_status; | |
224 | u32 cookie; | |
225 | u32 reserved[14]; | |
226 | } __packed; | |
227 | ||
228 | union guc_doorbell_qw { | |
229 | struct { | |
230 | u32 db_status; | |
231 | u32 cookie; | |
232 | }; | |
233 | u64 value_qw; | |
234 | } __packed; | |
235 | ||
236 | #define GUC_MAX_DOORBELLS 256 | |
237 | #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) | |
238 | ||
239 | #define GUC_DB_SIZE (PAGE_SIZE) | |
240 | #define GUC_WQ_SIZE (PAGE_SIZE * 2) | |
241 | ||
242 | /* Work item for submitting workloads into work queue of GuC. */ | |
243 | struct guc_wq_item { | |
244 | u32 header; | |
245 | u32 context_desc; | |
246 | u32 ring_tail; | |
247 | u32 fence_id; | |
248 | } __packed; | |
249 | ||
250 | struct guc_process_desc { | |
251 | u32 context_id; | |
252 | u64 db_base_addr; | |
253 | u32 head; | |
254 | u32 tail; | |
255 | u32 error_offset; | |
256 | u64 wq_base_addr; | |
257 | u32 wq_size_bytes; | |
258 | u32 wq_status; | |
259 | u32 engine_presence; | |
260 | u32 priority; | |
261 | u32 reserved[30]; | |
262 | } __packed; | |
263 | ||
264 | /* engine id and context id is packed into guc_execlist_context.context_id*/ | |
265 | #define GUC_ELC_CTXID_OFFSET 0 | |
266 | #define GUC_ELC_ENGINE_OFFSET 29 | |
267 | ||
268 | /* The execlist context including software and HW information */ | |
269 | struct guc_execlist_context { | |
270 | u32 context_desc; | |
271 | u32 context_id; | |
272 | u32 ring_status; | |
273 | u32 ring_lcra; | |
274 | u32 ring_begin; | |
275 | u32 ring_end; | |
276 | u32 ring_next_free_location; | |
277 | u32 ring_current_tail_pointer_value; | |
278 | u8 engine_state_submit_value; | |
279 | u8 engine_state_wait_value; | |
280 | u16 pagefault_count; | |
281 | u16 engine_submit_queue_count; | |
282 | } __packed; | |
283 | ||
284 | /*Context descriptor for communicating between uKernel and Driver*/ | |
285 | struct guc_context_desc { | |
286 | u32 sched_common_area; | |
287 | u32 context_id; | |
288 | u32 pas_id; | |
289 | u8 engines_used; | |
290 | u64 db_trigger_cpu; | |
291 | u32 db_trigger_uk; | |
292 | u64 db_trigger_phy; | |
293 | u16 db_id; | |
294 | ||
397097b0 | 295 | struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; |
2617268f DG |
296 | |
297 | u8 attribute; | |
298 | ||
299 | u32 priority; | |
300 | ||
301 | u32 wq_sampled_tail_offset; | |
302 | u32 wq_total_submit_enqueues; | |
303 | ||
304 | u32 process_desc; | |
305 | u32 wq_addr; | |
306 | u32 wq_size; | |
307 | ||
308 | u32 engine_presence; | |
309 | ||
aa557ab0 AD |
310 | u8 engine_suspended; |
311 | ||
312 | u8 reserved0[3]; | |
2617268f DG |
313 | u64 reserved1[1]; |
314 | ||
315 | u64 desc_private; | |
316 | } __packed; | |
317 | ||
93f25318 AD |
318 | #define GUC_FORCEWAKE_RENDER (1 << 0) |
319 | #define GUC_FORCEWAKE_MEDIA (1 << 1) | |
320 | ||
a1c41994 AD |
321 | #define GUC_POWER_UNSPECIFIED 0 |
322 | #define GUC_POWER_D0 1 | |
323 | #define GUC_POWER_D1 2 | |
324 | #define GUC_POWER_D2 3 | |
325 | #define GUC_POWER_D3 4 | |
326 | ||
463704d0 AD |
327 | /* Scheduling policy settings */ |
328 | ||
329 | /* Reset engine upon preempt failure */ | |
330 | #define POLICY_RESET_ENGINE (1<<0) | |
331 | /* Preempt to idle on quantum expiry */ | |
332 | #define POLICY_PREEMPT_TO_IDLE (1<<1) | |
333 | ||
334 | #define POLICY_MAX_NUM_WI 15 | |
335 | ||
336 | struct guc_policy { | |
337 | /* Time for one workload to execute. (in micro seconds) */ | |
338 | u32 execution_quantum; | |
339 | u32 reserved1; | |
340 | ||
341 | /* Time to wait for a preemption request to completed before issuing a | |
342 | * reset. (in micro seconds). */ | |
343 | u32 preemption_time; | |
344 | ||
345 | /* How much time to allow to run after the first fault is observed. | |
346 | * Then preempt afterwards. (in micro seconds) */ | |
347 | u32 fault_time; | |
348 | ||
349 | u32 policy_flags; | |
350 | u32 reserved[2]; | |
351 | } __packed; | |
352 | ||
353 | struct guc_policies { | |
397097b0 | 354 | struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; |
463704d0 AD |
355 | |
356 | /* In micro seconds. How much time to allow before DPC processing is | |
357 | * called back via interrupt (to prevent DPC queue drain starving). | |
358 | * Typically 1000s of micro seconds (example only, not granularity). */ | |
359 | u32 dpc_promote_time; | |
360 | ||
361 | /* Must be set to take these new values. */ | |
362 | u32 is_valid; | |
363 | ||
364 | /* Max number of WIs to process per call. A large value may keep CS | |
365 | * idle. */ | |
366 | u32 max_num_work_items; | |
367 | ||
368 | u32 reserved[19]; | |
369 | } __packed; | |
370 | ||
5c148e04 AD |
371 | /* GuC MMIO reg state struct */ |
372 | ||
373 | #define GUC_REGSET_FLAGS_NONE 0x0 | |
374 | #define GUC_REGSET_POWERCYCLE 0x1 | |
375 | #define GUC_REGSET_MASKED 0x2 | |
376 | #define GUC_REGSET_ENGINERESET 0x4 | |
377 | #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 | |
378 | #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 | |
379 | ||
f3272e7a | 380 | #define GUC_REGSET_MAX_REGISTERS 25 |
5c148e04 AD |
381 | #define GUC_MMIO_WHITE_LIST_START 0x24d0 |
382 | #define GUC_MMIO_WHITE_LIST_MAX 12 | |
383 | #define GUC_S3_SAVE_SPACE_PAGES 10 | |
384 | ||
385 | struct guc_mmio_regset { | |
386 | struct __packed { | |
387 | u32 offset; | |
388 | u32 value; | |
389 | u32 flags; | |
390 | } registers[GUC_REGSET_MAX_REGISTERS]; | |
391 | ||
392 | u32 values_valid; | |
393 | u32 number_of_registers; | |
394 | } __packed; | |
395 | ||
396 | struct guc_mmio_reg_state { | |
397 | struct guc_mmio_regset global_reg; | |
397097b0 | 398 | struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; |
5c148e04 AD |
399 | |
400 | /* MMIO registers that are set as non privileged */ | |
401 | struct __packed { | |
402 | u32 mmio_start; | |
403 | u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; | |
404 | u32 count; | |
397097b0 | 405 | } mmio_white_list[GUC_MAX_ENGINES_NUM]; |
5c148e04 AD |
406 | } __packed; |
407 | ||
68371a95 AD |
408 | /* GuC Additional Data Struct */ |
409 | ||
410 | struct guc_ads { | |
411 | u32 reg_state_addr; | |
412 | u32 reg_state_buffer; | |
413 | u32 golden_context_lrca; | |
414 | u32 scheduler_policies; | |
415 | u32 reserved0[3]; | |
397097b0 | 416 | u32 eng_state_size[GUC_MAX_ENGINES_NUM]; |
68371a95 AD |
417 | u32 reserved2[4]; |
418 | } __packed; | |
419 | ||
2617268f DG |
420 | /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ |
421 | enum host2guc_action { | |
422 | HOST2GUC_ACTION_DEFAULT = 0x0, | |
423 | HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, | |
424 | HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, | |
425 | HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, | |
a1c41994 AD |
426 | HOST2GUC_ACTION_ENTER_S_STATE = 0x501, |
427 | HOST2GUC_ACTION_EXIT_S_STATE = 0x502, | |
2617268f DG |
428 | HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, |
429 | HOST2GUC_ACTION_LIMIT | |
430 | }; | |
431 | ||
432 | /* | |
433 | * The GuC sends its response to a command by overwriting the | |
434 | * command in SS0. The response is distinguishable from a command | |
435 | * by the fact that all the MASK bits are set. The remaining bits | |
436 | * give more detail. | |
437 | */ | |
438 | #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) | |
439 | #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) | |
440 | #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) | |
441 | ||
442 | /* GUC will return status back to SOFT_SCRATCH_O_REG */ | |
443 | enum guc2host_status { | |
444 | GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), | |
445 | GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), | |
446 | GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), | |
447 | GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) | |
448 | }; | |
449 | ||
450 | #endif |