Commit | Line | Data |
---|---|---|
33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Vinit Azad <vinit.azad@intel.com> | |
25 | * Ben Widawsky <ben@bwidawsk.net> | |
26 | * Dave Gordon <david.s.gordon@intel.com> | |
27 | * Alex Dai <yu.dai@intel.com> | |
28 | */ | |
29 | #include <linux/firmware.h> | |
30 | #include "i915_drv.h" | |
31 | #include "intel_guc.h" | |
32 | ||
33 | /** | |
feda33ef | 34 | * DOC: GuC-specific firmware loader |
33a732f4 AD |
35 | * |
36 | * intel_guc: | |
37 | * Top level structure of guc. It handles firmware loading and manages client | |
38 | * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy | |
39 | * ExecList submission. | |
40 | * | |
41 | * Firmware versioning: | |
42 | * The firmware build process will generate a version header file with major and | |
43 | * minor version defined. The versions are built into CSS header of firmware. | |
44 | * i915 kernel driver set the minimal firmware version required per platform. | |
45 | * The firmware installation package will install (symbolic link) proper version | |
46 | * of firmware. | |
47 | * | |
48 | * GuC address space: | |
49 | * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), | |
50 | * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is | |
51 | * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects | |
52 | * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. | |
53 | * | |
54 | * Firmware log: | |
55 | * Firmware log is enabled by setting i915.guc_log_level to non-negative level. | |
56 | * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from | |
57 | * i915_guc_load_status will print out firmware loading status and scratch | |
58 | * registers value. | |
59 | * | |
60 | */ | |
61 | ||
4d3ba7e4 | 62 | #define I915_SKL_GUC_UCODE "i915/skl_guc_ver6_1.bin" |
33a732f4 AD |
63 | MODULE_FIRMWARE(I915_SKL_GUC_UCODE); |
64 | ||
57bf5c81 NH |
65 | #define I915_BXT_GUC_UCODE "i915/bxt_guc_ver8_7.bin" |
66 | MODULE_FIRMWARE(I915_BXT_GUC_UCODE); | |
67 | ||
ff64cc16 PA |
68 | #define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin" |
69 | MODULE_FIRMWARE(I915_KBL_GUC_UCODE); | |
70 | ||
33a732f4 AD |
71 | /* User-friendly representation of an enum */ |
72 | const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status) | |
73 | { | |
74 | switch (status) { | |
75 | case GUC_FIRMWARE_FAIL: | |
76 | return "FAIL"; | |
77 | case GUC_FIRMWARE_NONE: | |
78 | return "NONE"; | |
79 | case GUC_FIRMWARE_PENDING: | |
80 | return "PENDING"; | |
81 | case GUC_FIRMWARE_SUCCESS: | |
82 | return "SUCCESS"; | |
83 | default: | |
84 | return "UNKNOWN!"; | |
85 | } | |
86 | }; | |
87 | ||
4df001d3 DG |
88 | static void direct_interrupts_to_host(struct drm_i915_private *dev_priv) |
89 | { | |
e2f80391 | 90 | struct intel_engine_cs *engine; |
b4ac5afc | 91 | int irqs; |
4df001d3 | 92 | |
fa7545a4 | 93 | /* tell all command streamers NOT to forward interrupts or vblank to GuC */ |
4df001d3 DG |
94 | irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER); |
95 | irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING); | |
b4ac5afc | 96 | for_each_engine(engine, dev_priv) |
e2f80391 | 97 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 98 | |
4df001d3 DG |
99 | /* route all GT interrupts to the host */ |
100 | I915_WRITE(GUC_BCS_RCS_IER, 0); | |
101 | I915_WRITE(GUC_VCS2_VCS1_IER, 0); | |
102 | I915_WRITE(GUC_WD_VECS_IER, 0); | |
103 | } | |
104 | ||
105 | static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv) | |
106 | { | |
e2f80391 | 107 | struct intel_engine_cs *engine; |
b4ac5afc | 108 | int irqs; |
1800ad25 | 109 | u32 tmp; |
4df001d3 | 110 | |
fa7545a4 DG |
111 | /* tell all command streamers to forward interrupts (but not vblank) to GuC */ |
112 | irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING); | |
b4ac5afc | 113 | for_each_engine(engine, dev_priv) |
e2f80391 | 114 | I915_WRITE(RING_MODE_GEN7(engine), irqs); |
4df001d3 | 115 | |
4df001d3 DG |
116 | /* route USER_INTERRUPT to Host, all others are sent to GuC. */ |
117 | irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
118 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
119 | /* These three registers have the same bit definitions */ | |
120 | I915_WRITE(GUC_BCS_RCS_IER, ~irqs); | |
121 | I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs); | |
122 | I915_WRITE(GUC_WD_VECS_IER, ~irqs); | |
1800ad25 SAK |
123 | |
124 | /* | |
125 | * If GuC has routed PM interrupts to itself, don't keep it. | |
126 | * and keep other interrupts those are unmasked by GuC. | |
127 | */ | |
128 | tmp = I915_READ(GEN6_PMINTRMSK); | |
129 | if (tmp & GEN8_PMINTR_REDIRECT_TO_NON_DISP) { | |
130 | dev_priv->rps.pm_intr_keep |= ~(tmp & ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); | |
131 | dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
132 | } | |
4df001d3 DG |
133 | } |
134 | ||
33a732f4 AD |
135 | static u32 get_gttype(struct drm_i915_private *dev_priv) |
136 | { | |
137 | /* XXX: GT type based on PCI device ID? field seems unused by fw */ | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static u32 get_core_family(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | switch (INTEL_INFO(dev_priv)->gen) { | |
144 | case 9: | |
145 | return GFXCORE_FAMILY_GEN9; | |
146 | ||
147 | default: | |
148 | DRM_ERROR("GUC: unsupported core family\n"); | |
149 | return GFXCORE_FAMILY_UNKNOWN; | |
150 | } | |
151 | } | |
152 | ||
153 | static void set_guc_init_params(struct drm_i915_private *dev_priv) | |
154 | { | |
155 | struct intel_guc *guc = &dev_priv->guc; | |
156 | u32 params[GUC_CTL_MAX_DWORDS]; | |
157 | int i; | |
158 | ||
159 | memset(¶ms, 0, sizeof(params)); | |
160 | ||
161 | params[GUC_CTL_DEVICE_INFO] |= | |
162 | (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) | | |
163 | (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT); | |
164 | ||
165 | /* | |
166 | * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one | |
167 | * second. This ARAR is calculated by: | |
168 | * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 | |
169 | */ | |
170 | params[GUC_CTL_ARAT_HIGH] = 0; | |
171 | params[GUC_CTL_ARAT_LOW] = 100000000; | |
172 | ||
173 | params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; | |
174 | ||
175 | params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER | | |
176 | GUC_CTL_VCS2_ENABLED; | |
177 | ||
178 | if (i915.guc_log_level >= 0) { | |
179 | params[GUC_CTL_LOG_PARAMS] = guc->log_flags; | |
180 | params[GUC_CTL_DEBUG] = | |
181 | i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT; | |
182 | } | |
183 | ||
b6a5cd7e AD |
184 | if (guc->ads_obj) { |
185 | u32 ads = (u32)i915_gem_obj_ggtt_offset(guc->ads_obj) | |
186 | >> PAGE_SHIFT; | |
187 | params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT; | |
188 | params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED; | |
189 | } | |
190 | ||
bac427f8 AD |
191 | /* If GuC submission is enabled, set up additional parameters here */ |
192 | if (i915.enable_guc_submission) { | |
193 | u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); | |
194 | u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; | |
195 | ||
196 | pgs >>= PAGE_SHIFT; | |
197 | params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) | | |
198 | (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT); | |
199 | ||
200 | params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS; | |
201 | ||
202 | /* Unmask this bit to enable the GuC's internal scheduler */ | |
203 | params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER; | |
204 | } | |
205 | ||
33a732f4 AD |
206 | I915_WRITE(SOFT_SCRATCH(0), 0); |
207 | ||
208 | for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) | |
209 | I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); | |
210 | } | |
211 | ||
212 | /* | |
213 | * Read the GuC status register (GUC_STATUS) and store it in the | |
214 | * specified location; then return a boolean indicating whether | |
215 | * the value matches either of two values representing completion | |
216 | * of the GuC boot process. | |
217 | * | |
36894e8b | 218 | * This is used for polling the GuC status in a wait_for() |
33a732f4 AD |
219 | * loop below. |
220 | */ | |
221 | static inline bool guc_ucode_response(struct drm_i915_private *dev_priv, | |
222 | u32 *status) | |
223 | { | |
224 | u32 val = I915_READ(GUC_STATUS); | |
0d44d3fa | 225 | u32 uk_val = val & GS_UKERNEL_MASK; |
33a732f4 | 226 | *status = val; |
0d44d3fa AD |
227 | return (uk_val == GS_UKERNEL_READY || |
228 | ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE)); | |
33a732f4 AD |
229 | } |
230 | ||
231 | /* | |
232 | * Transfer the firmware image to RAM for execution by the microcontroller. | |
233 | * | |
33a732f4 AD |
234 | * Architecturally, the DMA engine is bidirectional, and can potentially even |
235 | * transfer between GTT locations. This functionality is left out of the API | |
236 | * for now as there is no need for it. | |
237 | * | |
238 | * Note that GuC needs the CSS header plus uKernel code to be copied by the | |
239 | * DMA engine in one operation, whereas the RSA signature is loaded via MMIO. | |
240 | */ | |
33a732f4 AD |
241 | static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv) |
242 | { | |
243 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
244 | struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj; | |
245 | unsigned long offset; | |
246 | struct sg_table *sg = fw_obj->pages; | |
feda33ef | 247 | u32 status, rsa[UOS_RSA_SCRATCH_MAX_COUNT]; |
33a732f4 AD |
248 | int i, ret = 0; |
249 | ||
feda33ef AD |
250 | /* where RSA signature starts */ |
251 | offset = guc_fw->rsa_offset; | |
33a732f4 AD |
252 | |
253 | /* Copy RSA signature from the fw image to HW for verification */ | |
feda33ef AD |
254 | sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, sizeof(rsa), offset); |
255 | for (i = 0; i < UOS_RSA_SCRATCH_MAX_COUNT; i++) | |
ab9cc558 | 256 | I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]); |
33a732f4 | 257 | |
feda33ef AD |
258 | /* The header plus uCode will be copied to WOPCM via DMA, excluding any |
259 | * other components */ | |
260 | I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size); | |
261 | ||
33a732f4 | 262 | /* Set the source address for the new blob */ |
feda33ef | 263 | offset = i915_gem_obj_ggtt_offset(fw_obj) + guc_fw->header_offset; |
33a732f4 AD |
264 | I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset)); |
265 | I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF); | |
266 | ||
267 | /* | |
268 | * Set the DMA destination. Current uCode expects the code to be | |
269 | * loaded at 8k; locations below this are used for the stack. | |
270 | */ | |
271 | I915_WRITE(DMA_ADDR_1_LOW, 0x2000); | |
272 | I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM); | |
273 | ||
274 | /* Finally start the DMA */ | |
275 | I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA)); | |
276 | ||
277 | /* | |
36894e8b | 278 | * Wait for the DMA to complete & the GuC to start up. |
33a732f4 AD |
279 | * NB: Docs recommend not using the interrupt for completion. |
280 | * Measurements indicate this should take no more than 20ms, so a | |
281 | * timeout here indicates that the GuC has failed and is unusable. | |
282 | * (Higher levels of the driver will attempt to fall back to | |
283 | * execlist mode if this happens.) | |
284 | */ | |
36894e8b | 285 | ret = wait_for(guc_ucode_response(dev_priv, &status), 100); |
33a732f4 AD |
286 | |
287 | DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n", | |
288 | I915_READ(DMA_CTRL), status); | |
289 | ||
290 | if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) { | |
291 | DRM_ERROR("GuC firmware signature verification failed\n"); | |
292 | ret = -ENOEXEC; | |
293 | } | |
294 | ||
295 | DRM_DEBUG_DRIVER("returning %d\n", ret); | |
296 | ||
297 | return ret; | |
298 | } | |
299 | ||
74aa156b PA |
300 | static u32 guc_wopcm_size(struct drm_i915_private *dev_priv) |
301 | { | |
302 | u32 wopcm_size = GUC_WOPCM_TOP; | |
303 | ||
304 | /* On BXT, the top of WOPCM is reserved for RC6 context */ | |
305 | if (IS_BROXTON(dev_priv)) | |
306 | wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED; | |
307 | ||
308 | return wopcm_size; | |
309 | } | |
310 | ||
33a732f4 AD |
311 | /* |
312 | * Load the GuC firmware blob into the MinuteIA. | |
313 | */ | |
314 | static int guc_ucode_xfer(struct drm_i915_private *dev_priv) | |
315 | { | |
316 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; | |
91c8a326 | 317 | struct drm_device *dev = &dev_priv->drm; |
33a732f4 AD |
318 | int ret; |
319 | ||
320 | ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false); | |
321 | if (ret) { | |
322 | DRM_DEBUG_DRIVER("set-domain failed %d\n", ret); | |
323 | return ret; | |
324 | } | |
325 | ||
326 | ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0); | |
327 | if (ret) { | |
328 | DRM_DEBUG_DRIVER("pin failed %d\n", ret); | |
329 | return ret; | |
330 | } | |
331 | ||
332 | /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */ | |
333 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
334 | ||
335 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
336 | ||
337 | /* init WOPCM */ | |
74aa156b | 338 | I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv)); |
33a732f4 AD |
339 | I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); |
340 | ||
341 | /* Enable MIA caching. GuC clock gating is disabled. */ | |
342 | I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); | |
343 | ||
b970b486 | 344 | /* WaDisableMinuteIaClockGating:skl,bxt */ |
e87a005d | 345 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
cbdc12a9 | 346 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
b970b486 NH |
347 | I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) & |
348 | ~GUC_ENABLE_MIA_CLOCK_GATING)); | |
349 | } | |
350 | ||
33a732f4 | 351 | /* WaC6DisallowByGfxPause*/ |
65fe29ee TG |
352 | if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) || |
353 | IS_BXT_REVID(dev, 0, BXT_REVID_B0)) | |
354 | I915_WRITE(GEN6_GFXPAUSE, 0x30FFF); | |
33a732f4 AD |
355 | |
356 | if (IS_BROXTON(dev)) | |
357 | I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
358 | else | |
359 | I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); | |
360 | ||
361 | if (IS_GEN9(dev)) { | |
362 | /* DOP Clock Gating Enable for GuC clocks */ | |
363 | I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | | |
364 | I915_READ(GEN7_MISCCPCTL))); | |
365 | ||
366 | /* allows for 5us before GT can go to RC6 */ | |
367 | I915_WRITE(GUC_ARAT_C6DIS, 0x1FF); | |
368 | } | |
369 | ||
370 | set_guc_init_params(dev_priv); | |
371 | ||
372 | ret = guc_ucode_xfer_dma(dev_priv); | |
373 | ||
374 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
375 | ||
376 | /* | |
377 | * We keep the object pages for reuse during resume. But we can unpin it | |
378 | * now that DMA has completed, so it doesn't continue to take up space. | |
379 | */ | |
380 | i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj); | |
381 | ||
382 | return ret; | |
383 | } | |
384 | ||
6b332fa2 AS |
385 | static int i915_reset_guc(struct drm_i915_private *dev_priv) |
386 | { | |
387 | int ret; | |
388 | u32 guc_status; | |
389 | ||
390 | ret = intel_guc_reset(dev_priv); | |
391 | if (ret) { | |
392 | DRM_ERROR("GuC reset failed, ret = %d\n", ret); | |
393 | return ret; | |
394 | } | |
395 | ||
396 | guc_status = I915_READ(GUC_STATUS); | |
397 | WARN(!(guc_status & GS_MIA_IN_RESET), | |
398 | "GuC status: 0x%x, MIA core expected to be in reset\n", guc_status); | |
399 | ||
400 | return ret; | |
401 | } | |
402 | ||
33a732f4 | 403 | /** |
f09d675f | 404 | * intel_guc_setup() - finish preparing the GuC for activity |
33a732f4 AD |
405 | * @dev: drm device |
406 | * | |
407 | * Called from gem_init_hw() during driver loading and also after a GPU reset. | |
408 | * | |
f09d675f | 409 | * The main action required here it to load the GuC uCode into the device. |
33a732f4 | 410 | * The firmware image should have already been fetched into memory by the |
f09d675f DG |
411 | * earlier call to intel_guc_init(), so here we need only check that worked, |
412 | * and then transfer the image to the h/w. | |
33a732f4 AD |
413 | * |
414 | * Return: non-zero code on error | |
415 | */ | |
f09d675f | 416 | int intel_guc_setup(struct drm_device *dev) |
33a732f4 | 417 | { |
fac5e23e | 418 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 | 419 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
fce91f22 DG |
420 | const char *fw_path = guc_fw->guc_fw_path; |
421 | int retries, ret, err; | |
33a732f4 | 422 | |
fce91f22 DG |
423 | DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n", |
424 | fw_path, | |
33a732f4 AD |
425 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), |
426 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
427 | ||
fce91f22 DG |
428 | /* Loading forbidden, or no firmware to load? */ |
429 | if (!i915.enable_guc_loading) { | |
430 | err = 0; | |
431 | goto fail; | |
e556f7c1 DG |
432 | } else if (fw_path == NULL) { |
433 | /* Device is known to have no uCode (e.g. no GuC) */ | |
434 | err = -ENXIO; | |
435 | goto fail; | |
436 | } else if (*fw_path == '\0') { | |
437 | /* Device has a GuC but we don't know what f/w to load? */ | |
438 | DRM_INFO("No GuC firmware known for this platform\n"); | |
fce91f22 DG |
439 | err = -ENODEV; |
440 | goto fail; | |
441 | } | |
33a732f4 | 442 | |
fce91f22 DG |
443 | /* Fetch failed, or already fetched but failed to load? */ |
444 | if (guc_fw->guc_fw_fetch_status != GUC_FIRMWARE_SUCCESS) { | |
33a732f4 AD |
445 | err = -EIO; |
446 | goto fail; | |
fce91f22 DG |
447 | } else if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL) { |
448 | err = -ENOEXEC; | |
33a732f4 | 449 | goto fail; |
33a732f4 AD |
450 | } |
451 | ||
fce91f22 DG |
452 | direct_interrupts_to_host(dev_priv); |
453 | ||
454 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING; | |
455 | ||
456 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
457 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
458 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
459 | ||
beffa517 | 460 | err = i915_guc_submission_init(dev_priv); |
bac427f8 AD |
461 | if (err) |
462 | goto fail; | |
463 | ||
6b332fa2 AS |
464 | /* |
465 | * WaEnableuKernelHeaderValidFix:skl,bxt | |
466 | * For BXT, this is only upto B0 but below WA is required for later | |
467 | * steppings also so this is extended as well. | |
468 | */ | |
469 | /* WaEnableGuCBootHashCheckNotSet:skl,bxt */ | |
d761701c DG |
470 | for (retries = 3; ; ) { |
471 | /* | |
472 | * Always reset the GuC just before (re)loading, so | |
473 | * that the state and timing are fairly predictable | |
474 | */ | |
475 | err = i915_reset_guc(dev_priv); | |
6b332fa2 | 476 | if (err) { |
fce91f22 | 477 | DRM_ERROR("GuC reset failed: %d\n", err); |
6b332fa2 AS |
478 | goto fail; |
479 | } | |
d761701c DG |
480 | |
481 | err = guc_ucode_xfer(dev_priv); | |
482 | if (!err) | |
483 | break; | |
484 | ||
485 | if (--retries == 0) | |
486 | goto fail; | |
487 | ||
fce91f22 DG |
488 | DRM_INFO("GuC fw load failed: %d; will reset and " |
489 | "retry %d more time(s)\n", err, retries); | |
6b332fa2 | 490 | } |
33a732f4 AD |
491 | |
492 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS; | |
493 | ||
494 | DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n", | |
495 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), | |
496 | intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); | |
497 | ||
44a28b1d | 498 | if (i915.enable_guc_submission) { |
beffa517 | 499 | err = i915_guc_submission_enable(dev_priv); |
44a28b1d DG |
500 | if (err) |
501 | goto fail; | |
4df001d3 | 502 | direct_interrupts_to_guc(dev_priv); |
44a28b1d DG |
503 | } |
504 | ||
33a732f4 AD |
505 | return 0; |
506 | ||
507 | fail: | |
508 | if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING) | |
509 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL; | |
510 | ||
4df001d3 | 511 | direct_interrupts_to_host(dev_priv); |
beffa517 DG |
512 | i915_guc_submission_disable(dev_priv); |
513 | i915_guc_submission_fini(dev_priv); | |
44a28b1d | 514 | |
fce91f22 DG |
515 | /* |
516 | * We've failed to load the firmware :( | |
517 | * | |
518 | * Decide whether to disable GuC submission and fall back to | |
519 | * execlist mode, and whether to hide the error by returning | |
520 | * zero or to return -EIO, which the caller will treat as a | |
521 | * nonfatal error (i.e. it doesn't prevent driver load, but | |
522 | * marks the GPU as wedged until reset). | |
523 | */ | |
524 | if (i915.enable_guc_loading > 1) { | |
525 | ret = -EIO; | |
526 | } else if (i915.enable_guc_submission > 1) { | |
527 | ret = -EIO; | |
528 | } else { | |
529 | ret = 0; | |
530 | } | |
531 | ||
4e50f796 DG |
532 | if (err == 0 && !HAS_GUC_UCODE(dev)) |
533 | ; /* Don't mention the GuC! */ | |
534 | else if (err == 0) | |
fce91f22 | 535 | DRM_INFO("GuC firmware load skipped\n"); |
4e50f796 | 536 | else if (ret != -EIO) |
fce91f22 | 537 | DRM_INFO("GuC firmware load failed: %d\n", err); |
4e50f796 DG |
538 | else |
539 | DRM_ERROR("GuC firmware load failed: %d\n", err); | |
fce91f22 DG |
540 | |
541 | if (i915.enable_guc_submission) { | |
542 | if (fw_path == NULL) | |
543 | DRM_INFO("GuC submission without firmware not supported\n"); | |
544 | if (ret == 0) | |
e556f7c1 | 545 | DRM_INFO("Falling back from GuC submission to execlist mode\n"); |
fce91f22 DG |
546 | else |
547 | DRM_ERROR("GuC init failed: %d\n", ret); | |
548 | } | |
549 | i915.enable_guc_submission = 0; | |
550 | ||
551 | return ret; | |
33a732f4 AD |
552 | } |
553 | ||
554 | static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) | |
555 | { | |
556 | struct drm_i915_gem_object *obj; | |
557 | const struct firmware *fw; | |
feda33ef AD |
558 | struct guc_css_header *css; |
559 | size_t size; | |
33a732f4 AD |
560 | int err; |
561 | ||
562 | DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n", | |
563 | intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); | |
564 | ||
565 | err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev); | |
566 | if (err) | |
567 | goto fail; | |
568 | if (!fw) | |
569 | goto fail; | |
570 | ||
571 | DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n", | |
572 | guc_fw->guc_fw_path, fw); | |
33a732f4 | 573 | |
feda33ef AD |
574 | /* Check the size of the blob before examining buffer contents */ |
575 | if (fw->size < sizeof(struct guc_css_header)) { | |
576 | DRM_ERROR("Firmware header is missing\n"); | |
33a732f4 | 577 | goto fail; |
feda33ef AD |
578 | } |
579 | ||
580 | css = (struct guc_css_header *)fw->data; | |
581 | ||
582 | /* Firmware bits always start from header */ | |
583 | guc_fw->header_offset = 0; | |
584 | guc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - | |
585 | css->key_size_dw - css->exponent_size_dw) * sizeof(u32); | |
586 | ||
587 | if (guc_fw->header_size != sizeof(struct guc_css_header)) { | |
588 | DRM_ERROR("CSS header definition mismatch\n"); | |
589 | goto fail; | |
590 | } | |
591 | ||
592 | /* then, uCode */ | |
593 | guc_fw->ucode_offset = guc_fw->header_offset + guc_fw->header_size; | |
594 | guc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); | |
595 | ||
596 | /* now RSA */ | |
597 | if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { | |
598 | DRM_ERROR("RSA key size is bad\n"); | |
599 | goto fail; | |
600 | } | |
601 | guc_fw->rsa_offset = guc_fw->ucode_offset + guc_fw->ucode_size; | |
602 | guc_fw->rsa_size = css->key_size_dw * sizeof(u32); | |
603 | ||
604 | /* At least, it should have header, uCode and RSA. Size of all three. */ | |
605 | size = guc_fw->header_size + guc_fw->ucode_size + guc_fw->rsa_size; | |
606 | if (fw->size < size) { | |
607 | DRM_ERROR("Missing firmware components\n"); | |
608 | goto fail; | |
609 | } | |
610 | ||
611 | /* Header and uCode will be loaded to WOPCM. Size of the two. */ | |
612 | size = guc_fw->header_size + guc_fw->ucode_size; | |
f19ec8cb | 613 | if (size > guc_wopcm_size(to_i915(dev))) { |
feda33ef AD |
614 | DRM_ERROR("Firmware is too large to fit in WOPCM\n"); |
615 | goto fail; | |
616 | } | |
33a732f4 AD |
617 | |
618 | /* | |
619 | * The GuC firmware image has the version number embedded at a well-known | |
620 | * offset within the firmware blob; note that major / minor version are | |
621 | * TWO bytes each (i.e. u16), although all pointers and offsets are defined | |
622 | * in terms of bytes (u8). | |
623 | */ | |
feda33ef AD |
624 | guc_fw->guc_fw_major_found = css->guc_sw_version >> 16; |
625 | guc_fw->guc_fw_minor_found = css->guc_sw_version & 0xFFFF; | |
33a732f4 AD |
626 | |
627 | if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted || | |
628 | guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) { | |
629 | DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n", | |
630 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, | |
631 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
632 | err = -ENOEXEC; | |
633 | goto fail; | |
634 | } | |
635 | ||
636 | DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", | |
637 | guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, | |
638 | guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); | |
639 | ||
bf248ca1 | 640 | mutex_lock(&dev->struct_mutex); |
33a732f4 | 641 | obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); |
bf248ca1 | 642 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
643 | if (IS_ERR_OR_NULL(obj)) { |
644 | err = obj ? PTR_ERR(obj) : -ENOMEM; | |
645 | goto fail; | |
646 | } | |
647 | ||
648 | guc_fw->guc_fw_obj = obj; | |
649 | guc_fw->guc_fw_size = fw->size; | |
650 | ||
651 | DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n", | |
652 | guc_fw->guc_fw_obj); | |
653 | ||
654 | release_firmware(fw); | |
655 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS; | |
656 | return; | |
657 | ||
658 | fail: | |
659 | DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n", | |
660 | err, fw, guc_fw->guc_fw_obj); | |
661 | DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n", | |
662 | guc_fw->guc_fw_path, err); | |
663 | ||
a9d8adad | 664 | mutex_lock(&dev->struct_mutex); |
33a732f4 AD |
665 | obj = guc_fw->guc_fw_obj; |
666 | if (obj) | |
f8c417cd | 667 | i915_gem_object_put(obj); |
33a732f4 | 668 | guc_fw->guc_fw_obj = NULL; |
a9d8adad | 669 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
670 | |
671 | release_firmware(fw); /* OK even if fw is NULL */ | |
672 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL; | |
673 | } | |
674 | ||
675 | /** | |
f09d675f | 676 | * intel_guc_init() - define parameters and fetch firmware |
33a732f4 AD |
677 | * @dev: drm device |
678 | * | |
679 | * Called early during driver load, but after GEM is initialised. | |
33a732f4 AD |
680 | * |
681 | * The firmware will be transferred to the GuC's memory later, | |
f09d675f | 682 | * when intel_guc_setup() is called. |
33a732f4 | 683 | */ |
f09d675f | 684 | void intel_guc_init(struct drm_device *dev) |
33a732f4 | 685 | { |
fac5e23e | 686 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 AD |
687 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
688 | const char *fw_path; | |
689 | ||
fce91f22 DG |
690 | /* A negative value means "use platform default" */ |
691 | if (i915.enable_guc_loading < 0) | |
692 | i915.enable_guc_loading = HAS_GUC_UCODE(dev); | |
693 | if (i915.enable_guc_submission < 0) | |
694 | i915.enable_guc_submission = HAS_GUC_SCHED(dev); | |
33a732f4 AD |
695 | |
696 | if (!HAS_GUC_UCODE(dev)) { | |
697 | fw_path = NULL; | |
698 | } else if (IS_SKYLAKE(dev)) { | |
699 | fw_path = I915_SKL_GUC_UCODE; | |
ab65cce8 AD |
700 | guc_fw->guc_fw_major_wanted = 6; |
701 | guc_fw->guc_fw_minor_wanted = 1; | |
57bf5c81 NH |
702 | } else if (IS_BROXTON(dev)) { |
703 | fw_path = I915_BXT_GUC_UCODE; | |
704 | guc_fw->guc_fw_major_wanted = 8; | |
705 | guc_fw->guc_fw_minor_wanted = 7; | |
ff64cc16 PA |
706 | } else if (IS_KABYLAKE(dev)) { |
707 | fw_path = I915_KBL_GUC_UCODE; | |
708 | guc_fw->guc_fw_major_wanted = 9; | |
709 | guc_fw->guc_fw_minor_wanted = 14; | |
33a732f4 | 710 | } else { |
33a732f4 AD |
711 | fw_path = ""; /* unknown device */ |
712 | } | |
713 | ||
714 | guc_fw->guc_dev = dev; | |
715 | guc_fw->guc_fw_path = fw_path; | |
716 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
717 | guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; | |
718 | ||
fce91f22 DG |
719 | /* Early (and silent) return if GuC loading is disabled */ |
720 | if (!i915.enable_guc_loading) | |
721 | return; | |
33a732f4 AD |
722 | if (fw_path == NULL) |
723 | return; | |
fce91f22 | 724 | if (*fw_path == '\0') |
33a732f4 | 725 | return; |
33a732f4 AD |
726 | |
727 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING; | |
728 | DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path); | |
729 | guc_fw_fetch(dev, guc_fw); | |
730 | /* status must now be FAIL or SUCCESS */ | |
731 | } | |
732 | ||
733 | /** | |
f09d675f | 734 | * intel_guc_fini() - clean up all allocated resources |
33a732f4 AD |
735 | * @dev: drm device |
736 | */ | |
f09d675f | 737 | void intel_guc_fini(struct drm_device *dev) |
33a732f4 | 738 | { |
fac5e23e | 739 | struct drm_i915_private *dev_priv = to_i915(dev); |
33a732f4 AD |
740 | struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; |
741 | ||
a9d8adad | 742 | mutex_lock(&dev->struct_mutex); |
4df001d3 | 743 | direct_interrupts_to_host(dev_priv); |
beffa517 DG |
744 | i915_guc_submission_disable(dev_priv); |
745 | i915_guc_submission_fini(dev_priv); | |
bac427f8 | 746 | |
33a732f4 | 747 | if (guc_fw->guc_fw_obj) |
f8c417cd | 748 | i915_gem_object_put(guc_fw->guc_fw_obj); |
33a732f4 | 749 | guc_fw->guc_fw_obj = NULL; |
bf248ca1 | 750 | mutex_unlock(&dev->struct_mutex); |
33a732f4 AD |
751 | |
752 | guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; | |
753 | } |