Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 50 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
51 | uint32_t enabled_bits; |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
ffc85dab | 81 | MISSING_CASE(type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
ffc85dab | 96 | MISSING_CASE(type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
ffc85dab | 111 | MISSING_CASE(type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
f0f59a00 VS |
116 | static i915_reg_t |
117 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
118 | enum transcoder cpu_transcoder, | |
119 | enum hdmi_infoframe_type type, | |
120 | int i) | |
2da8af54 | 121 | { |
178f736a DL |
122 | switch (type) { |
123 | case HDMI_INFOFRAME_TYPE_AVI: | |
436c6d4a | 124 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 125 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 126 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 127 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 128 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 129 | default: |
ffc85dab | 130 | MISSING_CASE(type); |
f0f59a00 | 131 | return INVALID_MMIO_REG; |
2da8af54 PZ |
132 | } |
133 | } | |
134 | ||
a3da1df7 | 135 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 136 | enum hdmi_infoframe_type type, |
fff63867 | 137 | const void *frame, ssize_t len) |
45187ace | 138 | { |
fff63867 | 139 | const uint32_t *data = frame; |
3c17fe4b | 140 | struct drm_device *dev = encoder->dev; |
fac5e23e | 141 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 142 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 143 | int i; |
3c17fe4b | 144 | |
822974ae PZ |
145 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
146 | ||
1d4f85ac | 147 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 148 | val |= g4x_infoframe_index(type); |
22509ec8 | 149 | |
178f736a | 150 | val &= ~g4x_infoframe_enable(type); |
45187ace | 151 | |
22509ec8 | 152 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 153 | |
9d9740f0 | 154 | mmiowb(); |
45187ace | 155 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
156 | I915_WRITE(VIDEO_DIP_DATA, *data); |
157 | data++; | |
158 | } | |
adf00b26 PZ |
159 | /* Write every possible data byte to force correct ECC calculation. */ |
160 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
161 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 162 | mmiowb(); |
3c17fe4b | 163 | |
178f736a | 164 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 165 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 166 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 167 | |
22509ec8 | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 169 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
170 | } |
171 | ||
cda0aaaf VS |
172 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
173 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 174 | { |
cda0aaaf | 175 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 176 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
177 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178 | ||
ec1dc603 VS |
179 | if ((val & VIDEO_DIP_ENABLE) == 0) |
180 | return false; | |
89a35ecd | 181 | |
ec1dc603 VS |
182 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
183 | return false; | |
184 | ||
185 | return val & (VIDEO_DIP_ENABLE_AVI | | |
186 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
187 | } |
188 | ||
fdf1250a | 189 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 190 | enum hdmi_infoframe_type type, |
fff63867 | 191 | const void *frame, ssize_t len) |
fdf1250a | 192 | { |
fff63867 | 193 | const uint32_t *data = frame; |
fdf1250a | 194 | struct drm_device *dev = encoder->dev; |
fac5e23e | 195 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed517fbb | 196 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 197 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 198 | u32 val = I915_READ(reg); |
f0f59a00 | 199 | int i; |
fdf1250a | 200 | |
822974ae PZ |
201 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
202 | ||
fdf1250a | 203 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 204 | val |= g4x_infoframe_index(type); |
fdf1250a | 205 | |
178f736a | 206 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
207 | |
208 | I915_WRITE(reg, val); | |
209 | ||
9d9740f0 | 210 | mmiowb(); |
fdf1250a PZ |
211 | for (i = 0; i < len; i += 4) { |
212 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
213 | data++; | |
214 | } | |
adf00b26 PZ |
215 | /* Write every possible data byte to force correct ECC calculation. */ |
216 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
217 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 218 | mmiowb(); |
fdf1250a | 219 | |
178f736a | 220 | val |= g4x_infoframe_enable(type); |
fdf1250a | 221 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 222 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
223 | |
224 | I915_WRITE(reg, val); | |
9d9740f0 | 225 | POSTING_READ(reg); |
fdf1250a PZ |
226 | } |
227 | ||
cda0aaaf VS |
228 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
229 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 230 | { |
cda0aaaf | 231 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 232 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
233 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
234 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
235 | u32 val = I915_READ(reg); |
236 | ||
ec1dc603 VS |
237 | if ((val & VIDEO_DIP_ENABLE) == 0) |
238 | return false; | |
239 | ||
240 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
241 | return false; | |
052f62f7 | 242 | |
ec1dc603 VS |
243 | return val & (VIDEO_DIP_ENABLE_AVI | |
244 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
245 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
246 | } |
247 | ||
fdf1250a | 248 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
b055c8f3 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
b055c8f3 | 253 | struct drm_device *dev = encoder->dev; |
fac5e23e | 254 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 256 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
f0f59a00 | 258 | int i; |
b055c8f3 | 259 | |
822974ae PZ |
260 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
261 | ||
64a8fc01 | 262 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 263 | val |= g4x_infoframe_index(type); |
45187ace | 264 | |
ecb97851 PZ |
265 | /* The DIP control register spec says that we need to update the AVI |
266 | * infoframe without clearing its enable bit */ | |
178f736a DL |
267 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
268 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 269 | |
22509ec8 | 270 | I915_WRITE(reg, val); |
45187ace | 271 | |
9d9740f0 | 272 | mmiowb(); |
45187ace | 273 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
274 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
275 | data++; | |
276 | } | |
adf00b26 PZ |
277 | /* Write every possible data byte to force correct ECC calculation. */ |
278 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
279 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 280 | mmiowb(); |
b055c8f3 | 281 | |
178f736a | 282 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 283 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 284 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 285 | |
22509ec8 | 286 | I915_WRITE(reg, val); |
9d9740f0 | 287 | POSTING_READ(reg); |
45187ace | 288 | } |
90b107c8 | 289 | |
cda0aaaf VS |
290 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
291 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 292 | { |
cda0aaaf VS |
293 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
294 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
295 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 296 | |
ec1dc603 VS |
297 | if ((val & VIDEO_DIP_ENABLE) == 0) |
298 | return false; | |
299 | ||
300 | return val & (VIDEO_DIP_ENABLE_AVI | | |
301 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
302 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
303 | } |
304 | ||
90b107c8 | 305 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 306 | enum hdmi_infoframe_type type, |
fff63867 | 307 | const void *frame, ssize_t len) |
90b107c8 | 308 | { |
fff63867 | 309 | const uint32_t *data = frame; |
90b107c8 | 310 | struct drm_device *dev = encoder->dev; |
fac5e23e | 311 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed517fbb | 312 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 313 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 314 | u32 val = I915_READ(reg); |
f0f59a00 | 315 | int i; |
90b107c8 | 316 | |
822974ae PZ |
317 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
318 | ||
90b107c8 | 319 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 320 | val |= g4x_infoframe_index(type); |
22509ec8 | 321 | |
178f736a | 322 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 323 | |
22509ec8 | 324 | I915_WRITE(reg, val); |
90b107c8 | 325 | |
9d9740f0 | 326 | mmiowb(); |
90b107c8 SK |
327 | for (i = 0; i < len; i += 4) { |
328 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
329 | data++; | |
330 | } | |
adf00b26 PZ |
331 | /* Write every possible data byte to force correct ECC calculation. */ |
332 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
333 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 334 | mmiowb(); |
90b107c8 | 335 | |
178f736a | 336 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 337 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 338 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 339 | |
22509ec8 | 340 | I915_WRITE(reg, val); |
9d9740f0 | 341 | POSTING_READ(reg); |
90b107c8 SK |
342 | } |
343 | ||
cda0aaaf VS |
344 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
345 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 346 | { |
cda0aaaf | 347 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 348 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
349 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
350 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 351 | |
ec1dc603 VS |
352 | if ((val & VIDEO_DIP_ENABLE) == 0) |
353 | return false; | |
354 | ||
355 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
356 | return false; | |
535afa2e | 357 | |
ec1dc603 VS |
358 | return val & (VIDEO_DIP_ENABLE_AVI | |
359 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
360 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
361 | } |
362 | ||
8c5f5f7c | 363 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 364 | enum hdmi_infoframe_type type, |
fff63867 | 365 | const void *frame, ssize_t len) |
8c5f5f7c | 366 | { |
fff63867 | 367 | const uint32_t *data = frame; |
2da8af54 | 368 | struct drm_device *dev = encoder->dev; |
fac5e23e | 369 | struct drm_i915_private *dev_priv = to_i915(dev); |
2da8af54 | 370 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
436c6d4a | 371 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
f0f59a00 VS |
372 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
373 | i915_reg_t data_reg; | |
178f736a | 374 | int i; |
2da8af54 | 375 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 376 | |
436c6d4a | 377 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 378 | |
178f736a | 379 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
380 | I915_WRITE(ctl_reg, val); |
381 | ||
9d9740f0 | 382 | mmiowb(); |
2da8af54 | 383 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
384 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
385 | type, i >> 2), *data); | |
2da8af54 PZ |
386 | data++; |
387 | } | |
adf00b26 PZ |
388 | /* Write every possible data byte to force correct ECC calculation. */ |
389 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
436c6d4a VS |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), 0); | |
9d9740f0 | 392 | mmiowb(); |
8c5f5f7c | 393 | |
178f736a | 394 | val |= hsw_infoframe_enable(type); |
2da8af54 | 395 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 396 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
397 | } |
398 | ||
cda0aaaf VS |
399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
400 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 401 | { |
cda0aaaf VS |
402 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
403 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 404 | |
ec1dc603 VS |
405 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
406 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
407 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
408 | } |
409 | ||
5adaea79 DL |
410 | /* |
411 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
412 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
413 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
414 | * used for both technologies. | |
415 | * | |
416 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
417 | * DW1: DB3 | DB2 | DB1 | DB0 | |
418 | * DW2: DB7 | DB6 | DB5 | DB4 | |
419 | * DW3: ... | |
420 | * | |
421 | * (HB is Header Byte, DB is Data Byte) | |
422 | * | |
423 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
424 | * trick them by giving an offset into the buffer and moving back the header | |
425 | * bytes by one. | |
426 | */ | |
9198ee5b DL |
427 | static void intel_write_infoframe(struct drm_encoder *encoder, |
428 | union hdmi_infoframe *frame) | |
45187ace JB |
429 | { |
430 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
431 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
432 | ssize_t len; | |
45187ace | 433 | |
5adaea79 DL |
434 | /* see comment above for the reason for this offset */ |
435 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
436 | if (len < 0) | |
437 | return; | |
438 | ||
439 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
440 | buffer[0] = buffer[1]; | |
441 | buffer[1] = buffer[2]; | |
442 | buffer[2] = buffer[3]; | |
443 | buffer[3] = 0; | |
444 | len++; | |
45187ace | 445 | |
5adaea79 | 446 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
447 | } |
448 | ||
687f4d06 | 449 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
7c5f93b0 | 450 | const struct drm_display_mode *adjusted_mode) |
45187ace | 451 | { |
abedc077 | 452 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 453 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
454 | union hdmi_infoframe frame; |
455 | int ret; | |
45187ace | 456 | |
5adaea79 DL |
457 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
458 | adjusted_mode); | |
459 | if (ret < 0) { | |
460 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
461 | return; | |
462 | } | |
c846b619 | 463 | |
abedc077 | 464 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 465 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
466 | frame.avi.quantization_range = |
467 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 468 | else |
5adaea79 DL |
469 | frame.avi.quantization_range = |
470 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
471 | } |
472 | ||
9198ee5b | 473 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
474 | } |
475 | ||
687f4d06 | 476 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 477 | { |
5adaea79 DL |
478 | union hdmi_infoframe frame; |
479 | int ret; | |
480 | ||
481 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
482 | if (ret < 0) { | |
483 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
484 | return; | |
485 | } | |
c0864cb3 | 486 | |
5adaea79 | 487 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 488 | |
9198ee5b | 489 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
490 | } |
491 | ||
c8bb75af LD |
492 | static void |
493 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
7c5f93b0 | 494 | const struct drm_display_mode *adjusted_mode) |
c8bb75af LD |
495 | { |
496 | union hdmi_infoframe frame; | |
497 | int ret; | |
498 | ||
499 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
500 | adjusted_mode); | |
501 | if (ret < 0) | |
502 | return; | |
503 | ||
504 | intel_write_infoframe(encoder, &frame); | |
505 | } | |
506 | ||
687f4d06 | 507 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 508 | bool enable, |
7c5f93b0 | 509 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 510 | { |
fac5e23e | 511 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
512 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
513 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 514 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 515 | u32 val = I915_READ(reg); |
822cdc52 | 516 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 517 | |
afba0188 DV |
518 | assert_hdmi_port_disabled(intel_hdmi); |
519 | ||
0c14c7f9 PZ |
520 | /* If the registers were not initialized yet, they might be zeroes, |
521 | * which means we're selecting the AVI DIP and we're setting its | |
522 | * frequency to once. This seems to really confuse the HW and make | |
523 | * things stop working (the register spec says the AVI always needs to | |
524 | * be sent every VSync). So here we avoid writing to the register more | |
525 | * than we need and also explicitly select the AVI DIP and explicitly | |
526 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
527 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
528 | * either. */ | |
529 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
530 | ||
6897b4b5 | 531 | if (!enable) { |
0c14c7f9 PZ |
532 | if (!(val & VIDEO_DIP_ENABLE)) |
533 | return; | |
0be6f0c8 VS |
534 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
535 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
536 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
537 | return; | |
538 | } | |
539 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
540 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 541 | I915_WRITE(reg, val); |
9d9740f0 | 542 | POSTING_READ(reg); |
0c14c7f9 PZ |
543 | return; |
544 | } | |
545 | ||
72b78c9d PZ |
546 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
547 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
548 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
549 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
550 | return; | |
72b78c9d PZ |
551 | } |
552 | val &= ~VIDEO_DIP_PORT_MASK; | |
553 | val |= port; | |
554 | } | |
555 | ||
822974ae | 556 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
557 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
558 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 559 | |
f278d972 | 560 | I915_WRITE(reg, val); |
9d9740f0 | 561 | POSTING_READ(reg); |
f278d972 | 562 | |
687f4d06 PZ |
563 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
564 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 565 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
566 | } |
567 | ||
6d67415f VS |
568 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
569 | { | |
570 | struct drm_device *dev = encoder->dev; | |
571 | struct drm_connector *connector; | |
572 | ||
573 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
574 | ||
575 | /* | |
576 | * HDMI cloning is only supported on g4x which doesn't | |
577 | * support deep color or GCP infoframes anyway so no | |
578 | * need to worry about multiple HDMI sinks here. | |
579 | */ | |
580 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
581 | if (connector->encoder == encoder) | |
582 | return connector->display_info.bpc > 8; | |
583 | ||
584 | return false; | |
585 | } | |
586 | ||
12aa3290 VS |
587 | /* |
588 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
589 | * | |
590 | * From HDMI specification 1.4a: | |
591 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
592 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
593 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
594 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
595 | * phase of 0 | |
596 | */ | |
597 | static bool gcp_default_phase_possible(int pipe_bpp, | |
598 | const struct drm_display_mode *mode) | |
599 | { | |
600 | unsigned int pixels_per_group; | |
601 | ||
602 | switch (pipe_bpp) { | |
603 | case 30: | |
604 | /* 4 pixels in 5 clocks */ | |
605 | pixels_per_group = 4; | |
606 | break; | |
607 | case 36: | |
608 | /* 2 pixels in 3 clocks */ | |
609 | pixels_per_group = 2; | |
610 | break; | |
611 | case 48: | |
612 | /* 1 pixel in 2 clocks */ | |
613 | pixels_per_group = 1; | |
614 | break; | |
615 | default: | |
616 | /* phase information not relevant for 8bpc */ | |
617 | return false; | |
618 | } | |
619 | ||
620 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
621 | mode->crtc_htotal % pixels_per_group == 0 && | |
622 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
623 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
624 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
625 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
626 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
627 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
628 | } | |
629 | ||
6d67415f VS |
630 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
631 | { | |
fac5e23e | 632 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6d67415f | 633 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 VS |
634 | i915_reg_t reg; |
635 | u32 val = 0; | |
6d67415f VS |
636 | |
637 | if (HAS_DDI(dev_priv)) | |
638 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); | |
666a4537 | 639 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 640 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 641 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
642 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
643 | else | |
644 | return false; | |
645 | ||
646 | /* Indicate color depth whenever the sink supports deep color */ | |
647 | if (hdmi_sink_is_deep_color(encoder)) | |
648 | val |= GCP_COLOR_INDICATION; | |
649 | ||
12aa3290 VS |
650 | /* Enable default_phase whenever the display mode is suitably aligned */ |
651 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, | |
652 | &crtc->config->base.adjusted_mode)) | |
653 | val |= GCP_DEFAULT_PHASE_ENABLE; | |
654 | ||
6d67415f VS |
655 | I915_WRITE(reg, val); |
656 | ||
657 | return val != 0; | |
658 | } | |
659 | ||
687f4d06 | 660 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 661 | bool enable, |
7c5f93b0 | 662 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 663 | { |
fac5e23e | 664 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 665 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
69fde0a6 VS |
666 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
667 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 668 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 669 | u32 val = I915_READ(reg); |
822cdc52 | 670 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 671 | |
afba0188 DV |
672 | assert_hdmi_port_disabled(intel_hdmi); |
673 | ||
0c14c7f9 PZ |
674 | /* See the big comment in g4x_set_infoframes() */ |
675 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
676 | ||
6897b4b5 | 677 | if (!enable) { |
0c14c7f9 PZ |
678 | if (!(val & VIDEO_DIP_ENABLE)) |
679 | return; | |
0be6f0c8 VS |
680 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
681 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
682 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 683 | I915_WRITE(reg, val); |
9d9740f0 | 684 | POSTING_READ(reg); |
0c14c7f9 PZ |
685 | return; |
686 | } | |
687 | ||
72b78c9d | 688 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
689 | WARN(val & VIDEO_DIP_ENABLE, |
690 | "DIP already enabled on port %c\n", | |
691 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
692 | val &= ~VIDEO_DIP_PORT_MASK; |
693 | val |= port; | |
694 | } | |
695 | ||
822974ae | 696 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
697 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
698 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
699 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 700 | |
6d67415f VS |
701 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
702 | val |= VIDEO_DIP_ENABLE_GCP; | |
703 | ||
f278d972 | 704 | I915_WRITE(reg, val); |
9d9740f0 | 705 | POSTING_READ(reg); |
f278d972 | 706 | |
687f4d06 PZ |
707 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
708 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 709 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
710 | } |
711 | ||
712 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 713 | bool enable, |
7c5f93b0 | 714 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 715 | { |
fac5e23e | 716 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 PZ |
717 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
718 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 719 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
720 | u32 val = I915_READ(reg); |
721 | ||
afba0188 DV |
722 | assert_hdmi_port_disabled(intel_hdmi); |
723 | ||
0c14c7f9 PZ |
724 | /* See the big comment in g4x_set_infoframes() */ |
725 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
726 | ||
6897b4b5 | 727 | if (!enable) { |
0c14c7f9 PZ |
728 | if (!(val & VIDEO_DIP_ENABLE)) |
729 | return; | |
0be6f0c8 VS |
730 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
731 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
732 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 733 | I915_WRITE(reg, val); |
9d9740f0 | 734 | POSTING_READ(reg); |
0c14c7f9 PZ |
735 | return; |
736 | } | |
737 | ||
822974ae PZ |
738 | /* Set both together, unset both together: see the spec. */ |
739 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 740 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 741 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 742 | |
6d67415f VS |
743 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
744 | val |= VIDEO_DIP_ENABLE_GCP; | |
745 | ||
822974ae | 746 | I915_WRITE(reg, val); |
9d9740f0 | 747 | POSTING_READ(reg); |
822974ae | 748 | |
687f4d06 PZ |
749 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
750 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 751 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
752 | } |
753 | ||
754 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 755 | bool enable, |
7c5f93b0 | 756 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 757 | { |
fac5e23e | 758 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 759 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
760 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
761 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 762 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 763 | u32 val = I915_READ(reg); |
6a2b8021 | 764 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 765 | |
afba0188 DV |
766 | assert_hdmi_port_disabled(intel_hdmi); |
767 | ||
0c14c7f9 PZ |
768 | /* See the big comment in g4x_set_infoframes() */ |
769 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
770 | ||
6897b4b5 | 771 | if (!enable) { |
0c14c7f9 PZ |
772 | if (!(val & VIDEO_DIP_ENABLE)) |
773 | return; | |
0be6f0c8 VS |
774 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
775 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
776 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 777 | I915_WRITE(reg, val); |
9d9740f0 | 778 | POSTING_READ(reg); |
0c14c7f9 PZ |
779 | return; |
780 | } | |
781 | ||
6a2b8021 | 782 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
783 | WARN(val & VIDEO_DIP_ENABLE, |
784 | "DIP already enabled on port %c\n", | |
785 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
786 | val &= ~VIDEO_DIP_PORT_MASK; |
787 | val |= port; | |
788 | } | |
789 | ||
822974ae | 790 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
791 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
792 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
793 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 794 | |
6d67415f VS |
795 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
796 | val |= VIDEO_DIP_ENABLE_GCP; | |
797 | ||
822974ae | 798 | I915_WRITE(reg, val); |
9d9740f0 | 799 | POSTING_READ(reg); |
822974ae | 800 | |
687f4d06 PZ |
801 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
802 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 803 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
804 | } |
805 | ||
806 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 807 | bool enable, |
7c5f93b0 | 808 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 809 | { |
fac5e23e | 810 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 PZ |
811 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
812 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 813 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 814 | u32 val = I915_READ(reg); |
0c14c7f9 | 815 | |
afba0188 DV |
816 | assert_hdmi_port_disabled(intel_hdmi); |
817 | ||
0be6f0c8 VS |
818 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
819 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
820 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
821 | ||
6897b4b5 | 822 | if (!enable) { |
0be6f0c8 | 823 | I915_WRITE(reg, val); |
9d9740f0 | 824 | POSTING_READ(reg); |
0c14c7f9 PZ |
825 | return; |
826 | } | |
827 | ||
6d67415f VS |
828 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
829 | val |= VIDEO_DIP_ENABLE_GCP_HSW; | |
830 | ||
0dd87d20 | 831 | I915_WRITE(reg, val); |
9d9740f0 | 832 | POSTING_READ(reg); |
0dd87d20 | 833 | |
687f4d06 PZ |
834 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
835 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 836 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
837 | } |
838 | ||
b2ccb822 VS |
839 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
840 | { | |
841 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
842 | struct i2c_adapter *adapter = | |
843 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
844 | ||
845 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
846 | return; | |
847 | ||
848 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
849 | enable ? "Enabling" : "Disabling"); | |
850 | ||
851 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
852 | adapter, enable); | |
853 | } | |
854 | ||
4cde8a21 | 855 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 856 | { |
c59423a3 | 857 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 858 | struct drm_i915_private *dev_priv = to_i915(dev); |
c59423a3 DV |
859 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
860 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
7c5f93b0 | 861 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 862 | u32 hdmi_val; |
7d57382e | 863 | |
b2ccb822 VS |
864 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
865 | ||
b242b7f7 | 866 | hdmi_val = SDVO_ENCODING_HDMI; |
0f2a2a75 VS |
867 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
868 | hdmi_val |= HDMI_COLOR_RANGE_16_235; | |
b599c0bc | 869 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 870 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 871 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 872 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 873 | |
6e3c9717 | 874 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 875 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 876 | else |
4f3a8bc7 | 877 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 878 | |
6e3c9717 | 879 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 880 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 881 | |
75770564 | 882 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 883 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
884 | else if (IS_CHERRYVIEW(dev)) |
885 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 886 | else |
c59423a3 | 887 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 888 | |
b242b7f7 PZ |
889 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
890 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
891 | } |
892 | ||
85234cdc DV |
893 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
894 | enum pipe *pipe) | |
7d57382e | 895 | { |
85234cdc | 896 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 897 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc | 898 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 899 | enum intel_display_power_domain power_domain; |
85234cdc | 900 | u32 tmp; |
5b092174 | 901 | bool ret; |
85234cdc | 902 | |
6d129bea | 903 | power_domain = intel_display_port_power_domain(encoder); |
5b092174 | 904 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
905 | return false; |
906 | ||
5b092174 ID |
907 | ret = false; |
908 | ||
b242b7f7 | 909 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
910 | |
911 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 912 | goto out; |
85234cdc DV |
913 | |
914 | if (HAS_PCH_CPT(dev)) | |
915 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
916 | else if (IS_CHERRYVIEW(dev)) |
917 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
918 | else |
919 | *pipe = PORT_TO_PIPE(tmp); | |
920 | ||
5b092174 ID |
921 | ret = true; |
922 | ||
923 | out: | |
924 | intel_display_power_put(dev_priv, power_domain); | |
925 | ||
926 | return ret; | |
85234cdc DV |
927 | } |
928 | ||
045ac3b5 | 929 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 930 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
931 | { |
932 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 933 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 934 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 935 | u32 tmp, flags = 0; |
18442d08 | 936 | int dotclock; |
045ac3b5 JB |
937 | |
938 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
939 | ||
940 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
941 | flags |= DRM_MODE_FLAG_PHSYNC; | |
942 | else | |
943 | flags |= DRM_MODE_FLAG_NHSYNC; | |
944 | ||
945 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
946 | flags |= DRM_MODE_FLAG_PVSYNC; | |
947 | else | |
948 | flags |= DRM_MODE_FLAG_NVSYNC; | |
949 | ||
6897b4b5 DV |
950 | if (tmp & HDMI_MODE_SELECT_HDMI) |
951 | pipe_config->has_hdmi_sink = true; | |
952 | ||
cda0aaaf | 953 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
954 | pipe_config->has_infoframe = true; |
955 | ||
c84db770 | 956 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
957 | pipe_config->has_audio = true; |
958 | ||
8c875fca VS |
959 | if (!HAS_PCH_SPLIT(dev) && |
960 | tmp & HDMI_COLOR_RANGE_16_235) | |
961 | pipe_config->limited_color_range = true; | |
962 | ||
2d112de7 | 963 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
964 | |
965 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
966 | dotclock = pipe_config->port_clock * 2 / 3; | |
967 | else | |
968 | dotclock = pipe_config->port_clock; | |
969 | ||
be69a133 VS |
970 | if (pipe_config->pixel_multiplier) |
971 | dotclock /= pipe_config->pixel_multiplier; | |
972 | ||
2d112de7 | 973 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
974 | |
975 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
976 | } |
977 | ||
d1b1589c VS |
978 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
979 | { | |
980 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
981 | ||
982 | WARN_ON(!crtc->config->has_hdmi_sink); | |
983 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
984 | pipe_name(crtc->pipe)); | |
985 | intel_audio_codec_enable(encoder); | |
986 | } | |
987 | ||
bf868c7d | 988 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 989 | { |
5ab432ef | 990 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 991 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d | 992 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 993 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
994 | u32 temp; |
995 | ||
b242b7f7 | 996 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 997 | |
bf868c7d VS |
998 | temp |= SDVO_ENABLE; |
999 | if (crtc->config->has_audio) | |
1000 | temp |= SDVO_AUDIO_ENABLE; | |
7a87c289 | 1001 | |
bf868c7d VS |
1002 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1003 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1004 | ||
1005 | if (crtc->config->has_audio) | |
1006 | intel_enable_hdmi_audio(encoder); | |
1007 | } | |
1008 | ||
1009 | static void ibx_enable_hdmi(struct intel_encoder *encoder) | |
1010 | { | |
1011 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1012 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1013 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1014 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1015 | u32 temp; | |
1016 | ||
1017 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1018 | |
bf868c7d VS |
1019 | temp |= SDVO_ENABLE; |
1020 | if (crtc->config->has_audio) | |
1021 | temp |= SDVO_AUDIO_ENABLE; | |
5ab432ef | 1022 | |
bf868c7d VS |
1023 | /* |
1024 | * HW workaround, need to write this twice for issue | |
1025 | * that may result in first write getting masked. | |
1026 | */ | |
1027 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1028 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1029 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1030 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1031 | |
bf868c7d VS |
1032 | /* |
1033 | * HW workaround, need to toggle enable bit off and on | |
1034 | * for 12bpc with pixel repeat. | |
1035 | * | |
1036 | * FIXME: BSpec says this should be done at the end of | |
1037 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1038 | */ |
bf868c7d VS |
1039 | if (crtc->config->pipe_bpp > 24 && |
1040 | crtc->config->pixel_multiplier > 1) { | |
1041 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); | |
1042 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1043 | ||
1044 | /* | |
1045 | * HW workaround, need to write this twice for issue | |
1046 | * that may result in first write getting masked. | |
1047 | */ | |
1048 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1049 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1050 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1051 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1052 | } |
c1dec79a | 1053 | |
bf868c7d | 1054 | if (crtc->config->has_audio) |
d1b1589c VS |
1055 | intel_enable_hdmi_audio(encoder); |
1056 | } | |
1057 | ||
1058 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
1059 | { | |
1060 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1061 | struct drm_i915_private *dev_priv = to_i915(dev); |
d1b1589c VS |
1062 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1063 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1064 | enum pipe pipe = crtc->pipe; | |
1065 | u32 temp; | |
1066 | ||
1067 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1068 | ||
1069 | temp |= SDVO_ENABLE; | |
1070 | if (crtc->config->has_audio) | |
1071 | temp |= SDVO_AUDIO_ENABLE; | |
1072 | ||
1073 | /* | |
1074 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1075 | * | |
1076 | * The procedure for 12bpc is as follows: | |
1077 | * 1. disable HDMI clock gating | |
1078 | * 2. enable HDMI with 8bpc | |
1079 | * 3. enable HDMI with 12bpc | |
1080 | * 4. enable HDMI clock gating | |
1081 | */ | |
1082 | ||
1083 | if (crtc->config->pipe_bpp > 24) { | |
1084 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1085 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1086 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1087 | ||
1088 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1089 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1090 | } |
d1b1589c VS |
1091 | |
1092 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1093 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1094 | ||
1095 | if (crtc->config->pipe_bpp > 24) { | |
1096 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1097 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1098 | ||
1099 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1100 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1101 | ||
1102 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1103 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1104 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1105 | } | |
1106 | ||
1107 | if (crtc->config->has_audio) | |
1108 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 1109 | } |
89b667f8 | 1110 | |
b76cf76b JN |
1111 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1112 | { | |
5ab432ef DV |
1113 | } |
1114 | ||
1115 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
1116 | { | |
1117 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1118 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1119 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
495a5bb8 | 1120 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 1121 | u32 temp; |
5ab432ef | 1122 | |
b242b7f7 | 1123 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1124 | |
1612c8bd | 1125 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1126 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1127 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1128 | |
1129 | /* | |
1130 | * HW workaround for IBX, we need to move the port | |
1131 | * to transcoder A after disabling it to allow the | |
1132 | * matching DP port to be enabled on transcoder A. | |
1133 | */ | |
1134 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
0c241d5b VS |
1135 | /* |
1136 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1137 | * doing the workaround. Sweep them under the rug. | |
1138 | */ | |
1139 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1140 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1141 | ||
1612c8bd VS |
1142 | temp &= ~SDVO_PIPE_B_SELECT; |
1143 | temp |= SDVO_ENABLE; | |
1144 | /* | |
1145 | * HW workaround, need to write this twice for issue | |
1146 | * that may result in first write getting masked. | |
1147 | */ | |
1148 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1149 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1150 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1151 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1152 | ||
1153 | temp &= ~SDVO_ENABLE; | |
1154 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1155 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1156 | |
91c8a326 | 1157 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
0c241d5b VS |
1158 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1159 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1160 | } |
6d67415f | 1161 | |
0be6f0c8 | 1162 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
b2ccb822 VS |
1163 | |
1164 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1165 | } |
1166 | ||
a4790cec VS |
1167 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1168 | { | |
1169 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1170 | ||
1171 | if (crtc->config->has_audio) | |
1172 | intel_audio_codec_disable(encoder); | |
1173 | ||
1174 | intel_disable_hdmi(encoder); | |
1175 | } | |
1176 | ||
1177 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
1178 | { | |
1179 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1180 | ||
1181 | if (crtc->config->has_audio) | |
1182 | intel_audio_codec_disable(encoder); | |
1183 | } | |
1184 | ||
1185 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
1186 | { | |
1187 | intel_disable_hdmi(encoder); | |
1188 | } | |
1189 | ||
b1ba124d | 1190 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) |
7d148ef5 | 1191 | { |
b1ba124d | 1192 | if (IS_G4X(dev_priv)) |
7d148ef5 | 1193 | return 165000; |
b1ba124d | 1194 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
7d148ef5 DV |
1195 | return 300000; |
1196 | else | |
1197 | return 225000; | |
1198 | } | |
1199 | ||
b1ba124d VS |
1200 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
1201 | bool respect_downstream_limits) | |
1202 | { | |
1203 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1204 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | |
1205 | ||
1206 | if (respect_downstream_limits) { | |
1207 | if (hdmi->dp_dual_mode.max_tmds_clock) | |
1208 | max_tmds_clock = min(max_tmds_clock, | |
1209 | hdmi->dp_dual_mode.max_tmds_clock); | |
1210 | if (!hdmi->has_hdmi_sink) | |
1211 | max_tmds_clock = min(max_tmds_clock, 165000); | |
1212 | } | |
1213 | ||
1214 | return max_tmds_clock; | |
1215 | } | |
1216 | ||
e64e739e VS |
1217 | static enum drm_mode_status |
1218 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
b1ba124d | 1219 | int clock, bool respect_downstream_limits) |
e64e739e VS |
1220 | { |
1221 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1222 | ||
1223 | if (clock < 25000) | |
1224 | return MODE_CLOCK_LOW; | |
b1ba124d | 1225 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) |
e64e739e VS |
1226 | return MODE_CLOCK_HIGH; |
1227 | ||
5e6ccc0b VS |
1228 | /* BXT DPLL can't generate 223-240 MHz */ |
1229 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) | |
1230 | return MODE_CLOCK_RANGE; | |
1231 | ||
1232 | /* CHV DPLL can't generate 216-240 MHz */ | |
1233 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) | |
e64e739e VS |
1234 | return MODE_CLOCK_RANGE; |
1235 | ||
1236 | return MODE_OK; | |
1237 | } | |
1238 | ||
c19de8eb DL |
1239 | static enum drm_mode_status |
1240 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1241 | struct drm_display_mode *mode) | |
7d57382e | 1242 | { |
e64e739e VS |
1243 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1244 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1245 | enum drm_mode_status status; | |
1246 | int clock; | |
587bf496 | 1247 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
e64e739e VS |
1248 | |
1249 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1250 | return MODE_NO_DBLESCAN; | |
697c4078 | 1251 | |
e64e739e | 1252 | clock = mode->clock; |
587bf496 MK |
1253 | |
1254 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1255 | clock *= 2; | |
1256 | ||
1257 | if (clock > max_dotclk) | |
1258 | return MODE_CLOCK_HIGH; | |
1259 | ||
697c4078 CT |
1260 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1261 | clock *= 2; | |
1262 | ||
e64e739e VS |
1263 | /* check if we can do 8bpc */ |
1264 | status = hdmi_port_clock_valid(hdmi, clock, true); | |
7d57382e | 1265 | |
e64e739e VS |
1266 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1267 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) | |
1268 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); | |
7d57382e | 1269 | |
e64e739e | 1270 | return status; |
7d57382e EA |
1271 | } |
1272 | ||
77f06c86 | 1273 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1274 | { |
77f06c86 | 1275 | struct drm_device *dev = crtc_state->base.crtc->dev; |
71800632 | 1276 | |
f227ae9e | 1277 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1278 | return false; |
1279 | ||
71800632 VS |
1280 | /* |
1281 | * HDMI 12bpc affects the clocks, so it's only possible | |
1282 | * when not cloning with other encoder types. | |
1283 | */ | |
3f1c928f | 1284 | return crtc_state->output_types == 1 << INTEL_OUTPUT_HDMI; |
71800632 VS |
1285 | } |
1286 | ||
5bfe2ac0 | 1287 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1288 | struct intel_crtc_state *pipe_config) |
7d57382e | 1289 | { |
5bfe2ac0 DV |
1290 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1291 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 | 1292 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
e64e739e VS |
1293 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1294 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1295 | int desired_bpp; |
3685a8f3 | 1296 | |
6897b4b5 DV |
1297 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1298 | ||
e43823ec JB |
1299 | if (pipe_config->has_hdmi_sink) |
1300 | pipe_config->has_infoframe = true; | |
1301 | ||
55bc60db VS |
1302 | if (intel_hdmi->color_range_auto) { |
1303 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
0f2a2a75 VS |
1304 | pipe_config->limited_color_range = |
1305 | pipe_config->has_hdmi_sink && | |
1306 | drm_match_cea_mode(adjusted_mode) > 1; | |
1307 | } else { | |
1308 | pipe_config->limited_color_range = | |
1309 | intel_hdmi->limited_color_range; | |
55bc60db VS |
1310 | } |
1311 | ||
697c4078 CT |
1312 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1313 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1314 | clock_8bpc *= 2; |
3320e37f | 1315 | clock_12bpc *= 2; |
697c4078 CT |
1316 | } |
1317 | ||
5bfe2ac0 DV |
1318 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1319 | pipe_config->has_pch_encoder = true; | |
1320 | ||
9ed109a7 DV |
1321 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1322 | pipe_config->has_audio = true; | |
1323 | ||
4e53c2e0 DV |
1324 | /* |
1325 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1326 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1327 | * outputs. We also need to check that the higher clock still fits |
1328 | * within limits. | |
4e53c2e0 | 1329 | */ |
6897b4b5 | 1330 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
b1ba124d | 1331 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true) == MODE_OK && |
7a0baa62 | 1332 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1333 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1334 | desired_bpp = 12*3; | |
325b9d04 DV |
1335 | |
1336 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1337 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1338 | } else { |
e29c22c0 DV |
1339 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1340 | desired_bpp = 8*3; | |
e64e739e VS |
1341 | |
1342 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1343 | } |
1344 | ||
1345 | if (!pipe_config->bw_constrained) { | |
1346 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1347 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1348 | } |
1349 | ||
e64e739e VS |
1350 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1351 | false) != MODE_OK) { | |
1352 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | |
325b9d04 DV |
1353 | return false; |
1354 | } | |
1355 | ||
28b468a0 VS |
1356 | /* Set user selected PAR to incoming mode's member */ |
1357 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
1358 | ||
d4d6279a ACO |
1359 | pipe_config->lane_count = 4; |
1360 | ||
7d57382e EA |
1361 | return true; |
1362 | } | |
1363 | ||
953ece69 CW |
1364 | static void |
1365 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1366 | { |
df0e9248 | 1367 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1368 | |
953ece69 CW |
1369 | intel_hdmi->has_hdmi_sink = false; |
1370 | intel_hdmi->has_audio = false; | |
1371 | intel_hdmi->rgb_quant_range_selectable = false; | |
1372 | ||
b1ba124d VS |
1373 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1374 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1375 | ||
953ece69 CW |
1376 | kfree(to_intel_connector(connector)->detect_edid); |
1377 | to_intel_connector(connector)->detect_edid = NULL; | |
1378 | } | |
1379 | ||
b1ba124d | 1380 | static void |
d6199256 | 1381 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1382 | { |
1383 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1384 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
d6199256 | 1385 | enum port port = hdmi_to_dig_port(hdmi)->port; |
b1ba124d VS |
1386 | struct i2c_adapter *adapter = |
1387 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1388 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1389 | ||
d6199256 VS |
1390 | /* |
1391 | * Type 1 DVI adaptors are not required to implement any | |
1392 | * registers, so we can't always detect their presence. | |
1393 | * Ideally we should be able to check the state of the | |
1394 | * CONFIG1 pin, but no such luck on our hardware. | |
1395 | * | |
1396 | * The only method left to us is to check the VBT to see | |
1397 | * if the port is a dual mode capable DP port. But let's | |
1398 | * only do that when we sucesfully read the EDID, to avoid | |
1399 | * confusing log messages about DP dual mode adaptors when | |
1400 | * there's nothing connected to the port. | |
1401 | */ | |
1402 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
1403 | if (has_edid && | |
1404 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { | |
1405 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1406 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1407 | } else { | |
1408 | type = DRM_DP_DUAL_MODE_NONE; | |
1409 | } | |
1410 | } | |
1411 | ||
1412 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1413 | return; |
1414 | ||
1415 | hdmi->dp_dual_mode.type = type; | |
1416 | hdmi->dp_dual_mode.max_tmds_clock = | |
1417 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1418 | ||
1419 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1420 | drm_dp_get_dual_mode_type_name(type), | |
1421 | hdmi->dp_dual_mode.max_tmds_clock); | |
1422 | } | |
1423 | ||
953ece69 | 1424 | static bool |
237ed86c | 1425 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
953ece69 CW |
1426 | { |
1427 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1428 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
237ed86c | 1429 | struct edid *edid = NULL; |
953ece69 | 1430 | bool connected = false; |
164c8598 | 1431 | |
69172f21 ID |
1432 | if (force) { |
1433 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); | |
671dedd2 | 1434 | |
237ed86c SJ |
1435 | edid = drm_get_edid(connector, |
1436 | intel_gmbus_get_adapter(dev_priv, | |
1437 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1438 | |
d6199256 | 1439 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1440 | |
69172f21 ID |
1441 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1442 | } | |
30ad48b7 | 1443 | |
953ece69 CW |
1444 | to_intel_connector(connector)->detect_edid = edid; |
1445 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1446 | intel_hdmi->rgb_quant_range_selectable = | |
1447 | drm_rgb_quant_range_selectable(edid); | |
1448 | ||
1449 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1450 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1451 | intel_hdmi->has_audio = | |
953ece69 CW |
1452 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1453 | ||
1454 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1455 | intel_hdmi->has_hdmi_sink = | |
1456 | drm_detect_hdmi_monitor(edid); | |
1457 | ||
1458 | connected = true; | |
55b7d6e8 CW |
1459 | } |
1460 | ||
953ece69 CW |
1461 | return connected; |
1462 | } | |
1463 | ||
8166fcea DV |
1464 | static enum drm_connector_status |
1465 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1466 | { |
8166fcea DV |
1467 | enum drm_connector_status status; |
1468 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1469 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
237ed86c | 1470 | bool live_status = false; |
61fb3980 | 1471 | unsigned int try; |
953ece69 | 1472 | |
8166fcea DV |
1473 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1474 | connector->base.id, connector->name); | |
1475 | ||
29bb94bb ID |
1476 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1477 | ||
f8d03ea0 | 1478 | for (try = 0; !live_status && try < 9; try++) { |
61fb3980 GW |
1479 | if (try) |
1480 | msleep(10); | |
237ed86c SJ |
1481 | live_status = intel_digital_port_connected(dev_priv, |
1482 | hdmi_to_dig_port(intel_hdmi)); | |
237ed86c SJ |
1483 | } |
1484 | ||
4f4a8185 SS |
1485 | if (!live_status) { |
1486 | DRM_DEBUG_KMS("HDMI live status down\n"); | |
1487 | /* | |
1488 | * Live status register is not reliable on all intel platforms. | |
1489 | * So consider live_status only for certain platforms, for | |
1490 | * others, read EDID to determine presence of sink. | |
1491 | */ | |
1492 | if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv)) | |
1493 | live_status = true; | |
1494 | } | |
237ed86c | 1495 | |
8166fcea | 1496 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1497 | |
8166fcea | 1498 | if (intel_hdmi_set_edid(connector, live_status)) { |
953ece69 CW |
1499 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1500 | ||
1501 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1502 | status = connector_status_connected; | |
8166fcea | 1503 | } else |
953ece69 | 1504 | status = connector_status_disconnected; |
671dedd2 | 1505 | |
29bb94bb ID |
1506 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1507 | ||
2ded9e27 | 1508 | return status; |
7d57382e EA |
1509 | } |
1510 | ||
953ece69 CW |
1511 | static void |
1512 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1513 | { |
953ece69 | 1514 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1515 | |
953ece69 CW |
1516 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1517 | connector->base.id, connector->name); | |
7d57382e | 1518 | |
953ece69 | 1519 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1520 | |
953ece69 CW |
1521 | if (connector->status != connector_status_connected) |
1522 | return; | |
671dedd2 | 1523 | |
237ed86c | 1524 | intel_hdmi_set_edid(connector, true); |
953ece69 CW |
1525 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1526 | } | |
671dedd2 | 1527 | |
953ece69 CW |
1528 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1529 | { | |
1530 | struct edid *edid; | |
1531 | ||
1532 | edid = to_intel_connector(connector)->detect_edid; | |
1533 | if (edid == NULL) | |
1534 | return 0; | |
671dedd2 | 1535 | |
953ece69 | 1536 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1537 | } |
1538 | ||
1aad7ac0 CW |
1539 | static bool |
1540 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1541 | { | |
1aad7ac0 | 1542 | bool has_audio = false; |
953ece69 | 1543 | struct edid *edid; |
1aad7ac0 | 1544 | |
953ece69 CW |
1545 | edid = to_intel_connector(connector)->detect_edid; |
1546 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1547 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1548 | |
1aad7ac0 CW |
1549 | return has_audio; |
1550 | } | |
1551 | ||
55b7d6e8 CW |
1552 | static int |
1553 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1554 | struct drm_property *property, |
1555 | uint64_t val) | |
55b7d6e8 CW |
1556 | { |
1557 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1558 | struct intel_digital_port *intel_dig_port = |
1559 | hdmi_to_dig_port(intel_hdmi); | |
fac5e23e | 1560 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
55b7d6e8 CW |
1561 | int ret; |
1562 | ||
662595df | 1563 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1564 | if (ret) |
1565 | return ret; | |
1566 | ||
3f43c48d | 1567 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1568 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1569 | bool has_audio; |
1570 | ||
1571 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1572 | return 0; |
1573 | ||
1aad7ac0 | 1574 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1575 | |
b1d7e4b4 | 1576 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1577 | has_audio = intel_hdmi_detect_audio(connector); |
1578 | else | |
b1d7e4b4 | 1579 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1580 | |
b1d7e4b4 WF |
1581 | if (i == HDMI_AUDIO_OFF_DVI) |
1582 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1583 | |
1aad7ac0 | 1584 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1585 | goto done; |
1586 | } | |
1587 | ||
e953fd7b | 1588 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 1589 | bool old_auto = intel_hdmi->color_range_auto; |
0f2a2a75 | 1590 | bool old_range = intel_hdmi->limited_color_range; |
ae4edb80 | 1591 | |
55bc60db VS |
1592 | switch (val) { |
1593 | case INTEL_BROADCAST_RGB_AUTO: | |
1594 | intel_hdmi->color_range_auto = true; | |
1595 | break; | |
1596 | case INTEL_BROADCAST_RGB_FULL: | |
1597 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1598 | intel_hdmi->limited_color_range = false; |
55bc60db VS |
1599 | break; |
1600 | case INTEL_BROADCAST_RGB_LIMITED: | |
1601 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1602 | intel_hdmi->limited_color_range = true; |
55bc60db VS |
1603 | break; |
1604 | default: | |
1605 | return -EINVAL; | |
1606 | } | |
ae4edb80 DV |
1607 | |
1608 | if (old_auto == intel_hdmi->color_range_auto && | |
0f2a2a75 | 1609 | old_range == intel_hdmi->limited_color_range) |
ae4edb80 DV |
1610 | return 0; |
1611 | ||
e953fd7b CW |
1612 | goto done; |
1613 | } | |
1614 | ||
94a11ddc VK |
1615 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1616 | switch (val) { | |
1617 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1618 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1619 | break; | |
1620 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1621 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1622 | break; | |
1623 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1624 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1625 | break; | |
1626 | default: | |
1627 | return -EINVAL; | |
1628 | } | |
1629 | goto done; | |
1630 | } | |
1631 | ||
55b7d6e8 CW |
1632 | return -EINVAL; |
1633 | ||
1634 | done: | |
c0c36b94 CW |
1635 | if (intel_dig_port->base.base.crtc) |
1636 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1637 | |
1638 | return 0; | |
1639 | } | |
1640 | ||
13732ba7 JB |
1641 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1642 | { | |
1643 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1644 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1645 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1646 | |
4cde8a21 DV |
1647 | intel_hdmi_prepare(encoder); |
1648 | ||
6897b4b5 | 1649 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1650 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1651 | adjusted_mode); |
13732ba7 JB |
1652 | } |
1653 | ||
9514ac6e | 1654 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1655 | { |
1656 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1657 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 | 1658 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1659 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
1660 | struct intel_crtc *intel_crtc = |
1661 | to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1662 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
5f68c275 ACO |
1663 | |
1664 | vlv_phy_pre_encoder_enable(encoder); | |
b76cf76b | 1665 | |
53d98725 ACO |
1666 | /* HDMI 1.0V-2dB */ |
1667 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1668 | 0x2b247878); | |
1669 | ||
6897b4b5 | 1670 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1671 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1672 | adjusted_mode); |
13732ba7 | 1673 | |
bf868c7d | 1674 | g4x_enable_hdmi(encoder); |
b76cf76b | 1675 | |
9b6de0a1 | 1676 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1677 | } |
1678 | ||
9514ac6e | 1679 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 | 1680 | { |
4cde8a21 DV |
1681 | intel_hdmi_prepare(encoder); |
1682 | ||
6da2e616 | 1683 | vlv_phy_pre_pll_enable(encoder); |
89b667f8 JB |
1684 | } |
1685 | ||
9197c88b VS |
1686 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1687 | { | |
625695f8 VS |
1688 | intel_hdmi_prepare(encoder); |
1689 | ||
419b1b7a | 1690 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
1691 | } |
1692 | ||
d6db995f VS |
1693 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1694 | { | |
204970b5 | 1695 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
1696 | } |
1697 | ||
9514ac6e | 1698 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 | 1699 | { |
89b667f8 | 1700 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
0f572ebe | 1701 | vlv_phy_reset_lanes(encoder); |
89b667f8 JB |
1702 | } |
1703 | ||
580d3811 VS |
1704 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1705 | { | |
580d3811 | 1706 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1707 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1708 | |
a580516d | 1709 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1710 | |
a8f327fb VS |
1711 | /* Assert data lane reset */ |
1712 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1713 | |
a580516d | 1714 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1715 | } |
1716 | ||
e4a1d846 CML |
1717 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1718 | { | |
1719 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1720 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 | 1721 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1722 | struct drm_i915_private *dev_priv = to_i915(dev); |
e4a1d846 CML |
1723 | struct intel_crtc *intel_crtc = |
1724 | to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1725 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
2e523e98 | 1726 | |
e7d2a717 | 1727 | chv_phy_pre_encoder_enable(encoder); |
a02ef3c7 | 1728 | |
e4a1d846 CML |
1729 | /* FIXME: Program the support xxx V-dB */ |
1730 | /* Use 800mV-0dB */ | |
b7fa22d8 | 1731 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 1732 | |
b4eb1564 | 1733 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1734 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1735 | adjusted_mode); |
1736 | ||
bf868c7d | 1737 | g4x_enable_hdmi(encoder); |
e4a1d846 | 1738 | |
9b6de0a1 | 1739 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1740 | |
1741 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 1742 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
1743 | } |
1744 | ||
7d57382e EA |
1745 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1746 | { | |
10e972d3 | 1747 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1748 | drm_connector_cleanup(connector); |
674e2d08 | 1749 | kfree(connector); |
7d57382e EA |
1750 | } |
1751 | ||
7d57382e | 1752 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
4d688a2a | 1753 | .dpms = drm_atomic_helper_connector_dpms, |
7d57382e | 1754 | .detect = intel_hdmi_detect, |
953ece69 | 1755 | .force = intel_hdmi_force, |
7d57382e | 1756 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1757 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1758 | .atomic_get_property = intel_connector_atomic_get_property, |
1ebaa0b9 | 1759 | .late_register = intel_connector_register, |
c191eca1 | 1760 | .early_unregister = intel_connector_unregister, |
7d57382e | 1761 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1762 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1763 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1764 | }; |
1765 | ||
1766 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1767 | .get_modes = intel_hdmi_get_modes, | |
1768 | .mode_valid = intel_hdmi_mode_valid, | |
7d57382e EA |
1769 | }; |
1770 | ||
7d57382e | 1771 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1772 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1773 | }; |
1774 | ||
55b7d6e8 CW |
1775 | static void |
1776 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1777 | { | |
3f43c48d | 1778 | intel_attach_force_audio_property(connector); |
e953fd7b | 1779 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1780 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1781 | intel_attach_aspect_ratio_property(connector); |
1782 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1783 | } |
1784 | ||
00c09d70 PZ |
1785 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1786 | struct intel_connector *intel_connector) | |
7d57382e | 1787 | { |
b9cb234c PZ |
1788 | struct drm_connector *connector = &intel_connector->base; |
1789 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1790 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1791 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 1792 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 1793 | enum port port = intel_dig_port->port; |
11c1b657 | 1794 | uint8_t alternate_ddc_pin; |
373a3cf7 | 1795 | |
22f35042 VS |
1796 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
1797 | port_name(port)); | |
1798 | ||
ccb1a831 VS |
1799 | if (WARN(intel_dig_port->max_lanes < 4, |
1800 | "Not enough lanes (%d) for HDMI on port %c\n", | |
1801 | intel_dig_port->max_lanes, port_name(port))) | |
1802 | return; | |
1803 | ||
7d57382e | 1804 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1805 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1806 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1807 | ||
c3febcc4 | 1808 | connector->interlace_allowed = 1; |
7d57382e | 1809 | connector->doublescan_allowed = 0; |
573e74ad | 1810 | connector->stereo_allowed = 1; |
66a9278e | 1811 | |
08d644ad DV |
1812 | switch (port) { |
1813 | case PORT_B: | |
4c272834 JN |
1814 | if (IS_BROXTON(dev_priv)) |
1815 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
1816 | else | |
1817 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
cf1d5883 SJ |
1818 | /* |
1819 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
1820 | * interrupts to check the external panel connection. | |
1821 | */ | |
e87a005d | 1822 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 SJ |
1823 | intel_encoder->hpd_pin = HPD_PORT_A; |
1824 | else | |
1825 | intel_encoder->hpd_pin = HPD_PORT_B; | |
08d644ad DV |
1826 | break; |
1827 | case PORT_C: | |
4c272834 JN |
1828 | if (IS_BROXTON(dev_priv)) |
1829 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
1830 | else | |
1831 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 1832 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1833 | break; |
1834 | case PORT_D: | |
4c272834 JN |
1835 | if (WARN_ON(IS_BROXTON(dev_priv))) |
1836 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
1837 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 1838 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 1839 | else |
988c7015 | 1840 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 1841 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad | 1842 | break; |
11c1b657 XZ |
1843 | case PORT_E: |
1844 | /* On SKL PORT E doesn't have seperate GMBUS pin | |
1845 | * We rely on VBT to set a proper alternate GMBUS pin. */ | |
1846 | alternate_ddc_pin = | |
1847 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; | |
1848 | switch (alternate_ddc_pin) { | |
1849 | case DDC_PIN_B: | |
1850 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
1851 | break; | |
1852 | case DDC_PIN_C: | |
1853 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1854 | break; | |
1855 | case DDC_PIN_D: | |
1856 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; | |
1857 | break; | |
1858 | default: | |
1859 | MISSING_CASE(alternate_ddc_pin); | |
1860 | } | |
1861 | intel_encoder->hpd_pin = HPD_PORT_E; | |
1862 | break; | |
08d644ad | 1863 | case PORT_A: |
1d843f9d | 1864 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1865 | /* Internal port only for eDP. */ |
1866 | default: | |
6e4c1677 | 1867 | BUG(); |
f8aed700 | 1868 | } |
7d57382e | 1869 | |
666a4537 | 1870 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
90b107c8 | 1871 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1872 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1873 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1874 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1875 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1876 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1877 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1878 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1879 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1880 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1881 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1882 | } else if (HAS_PCH_IBX(dev)) { |
1883 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1884 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1885 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1886 | } else { |
1887 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1888 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1889 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1890 | } |
45187ace | 1891 | |
affa9354 | 1892 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1893 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1894 | else | |
1895 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1896 | |
1897 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1898 | ||
1899 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
d8b4c43a | 1900 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
1901 | |
1902 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1903 | * 0xd. Failure to do so will result in spurious interrupts being | |
1904 | * generated on the port when a cable is not attached. | |
1905 | */ | |
1906 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1907 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1908 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1909 | } | |
1910 | } | |
1911 | ||
f0f59a00 VS |
1912 | void intel_hdmi_init(struct drm_device *dev, |
1913 | i915_reg_t hdmi_reg, enum port port) | |
b9cb234c PZ |
1914 | { |
1915 | struct intel_digital_port *intel_dig_port; | |
1916 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1917 | struct intel_connector *intel_connector; |
1918 | ||
b14c5679 | 1919 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1920 | if (!intel_dig_port) |
1921 | return; | |
1922 | ||
08d9bc92 | 1923 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
1924 | if (!intel_connector) { |
1925 | kfree(intel_dig_port); | |
1926 | return; | |
1927 | } | |
1928 | ||
1929 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1930 | |
1931 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
580d8ed5 | 1932 | DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port)); |
00c09d70 | 1933 | |
5bfe2ac0 | 1934 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
1935 | if (HAS_PCH_SPLIT(dev)) { |
1936 | intel_encoder->disable = pch_disable_hdmi; | |
1937 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
1938 | } else { | |
1939 | intel_encoder->disable = g4x_disable_hdmi; | |
1940 | } | |
00c09d70 | 1941 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 1942 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1943 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1944 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1945 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1946 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1947 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 1948 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
e4a1d846 | 1949 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1950 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1951 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1952 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1953 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1954 | } else { |
13732ba7 | 1955 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
1956 | if (HAS_PCH_CPT(dev)) |
1957 | intel_encoder->enable = cpt_enable_hdmi; | |
bf868c7d VS |
1958 | else if (HAS_PCH_IBX(dev)) |
1959 | intel_encoder->enable = ibx_enable_hdmi; | |
d1b1589c | 1960 | else |
bf868c7d | 1961 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 1962 | } |
5ab432ef | 1963 | |
b9cb234c | 1964 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1965 | if (IS_CHERRYVIEW(dev)) { |
1966 | if (port == PORT_D) | |
1967 | intel_encoder->crtc_mask = 1 << 2; | |
1968 | else | |
1969 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1970 | } else { | |
1971 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1972 | } | |
301ea74a | 1973 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1974 | /* |
1975 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1976 | * to work on real hardware. And since g4x can send infoframes to | |
1977 | * only one port anyway, nothing is lost by allowing it. | |
1978 | */ | |
1979 | if (IS_G4X(dev)) | |
1980 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1981 | |
174edf1f | 1982 | intel_dig_port->port = port; |
b242b7f7 | 1983 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 1984 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 1985 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 1986 | |
b9cb234c | 1987 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1988 | } |