Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
9dff6af8 | 43 | bool has_hdmi_sink; |
7d57382e EA |
44 | }; |
45 | ||
ea5b213a CW |
46 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
47 | { | |
4ef69c7a | 48 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
49 | } |
50 | ||
df0e9248 CW |
51 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
52 | { | |
53 | return container_of(intel_attached_encoder(connector), | |
54 | struct intel_hdmi, base); | |
55 | } | |
56 | ||
7d57382e EA |
57 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
58 | struct drm_display_mode *mode, | |
59 | struct drm_display_mode *adjusted_mode) | |
60 | { | |
61 | struct drm_device *dev = encoder->dev; | |
62 | struct drm_i915_private *dev_priv = dev->dev_private; | |
63 | struct drm_crtc *crtc = encoder->crtc; | |
64 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 65 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
66 | u32 sdvox; |
67 | ||
b599c0bc AJ |
68 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
69 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
70 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
71 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
72 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 73 | |
ea5b213a | 74 | if (intel_hdmi->has_hdmi_sink) { |
7d57382e | 75 | sdvox |= SDVO_AUDIO_ENABLE; |
467b200d ZW |
76 | if (HAS_PCH_CPT(dev)) |
77 | sdvox |= HDMI_MODE_SELECT; | |
78 | } | |
7d57382e | 79 | |
0f229062 ZW |
80 | if (intel_crtc->pipe == 1) { |
81 | if (HAS_PCH_CPT(dev)) | |
82 | sdvox |= PORT_TRANS_B_SEL_CPT; | |
83 | else | |
84 | sdvox |= SDVO_PIPE_B_SELECT; | |
85 | } | |
7d57382e | 86 | |
ea5b213a CW |
87 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
88 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e EA |
89 | } |
90 | ||
91 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
92 | { | |
93 | struct drm_device *dev = encoder->dev; | |
94 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 95 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
96 | u32 temp; |
97 | ||
ea5b213a | 98 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
99 | |
100 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
101 | * we do this anyway which shows more stable in testing. | |
102 | */ | |
c619eed4 | 103 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
104 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
105 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
106 | } |
107 | ||
108 | if (mode != DRM_MODE_DPMS_ON) { | |
109 | temp &= ~SDVO_ENABLE; | |
7d57382e | 110 | } else { |
d8a2d0e0 | 111 | temp |= SDVO_ENABLE; |
7d57382e | 112 | } |
d8a2d0e0 | 113 | |
ea5b213a CW |
114 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
115 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
116 | |
117 | /* HW workaround, need to write this twice for issue that may result | |
118 | * in first write getting masked. | |
119 | */ | |
c619eed4 | 120 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
121 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
122 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 123 | } |
7d57382e EA |
124 | } |
125 | ||
7d57382e EA |
126 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
127 | struct drm_display_mode *mode) | |
128 | { | |
129 | if (mode->clock > 165000) | |
130 | return MODE_CLOCK_HIGH; | |
131 | if (mode->clock < 20000) | |
132 | return MODE_CLOCK_HIGH; | |
133 | ||
134 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
135 | return MODE_NO_DBLESCAN; | |
136 | ||
137 | return MODE_OK; | |
138 | } | |
139 | ||
140 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
141 | struct drm_display_mode *mode, | |
142 | struct drm_display_mode *adjusted_mode) | |
143 | { | |
144 | return true; | |
145 | } | |
146 | ||
aa93d632 | 147 | static enum drm_connector_status |
2ded9e27 | 148 | intel_hdmi_detect(struct drm_connector *connector) |
9dff6af8 | 149 | { |
df0e9248 | 150 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 151 | struct edid *edid = NULL; |
aa93d632 | 152 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 153 | |
ea5b213a CW |
154 | intel_hdmi->has_hdmi_sink = false; |
155 | edid = drm_get_edid(connector, intel_hdmi->base.ddc_bus); | |
2ded9e27 | 156 | |
aa93d632 | 157 | if (edid) { |
be9f1c4f | 158 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 159 | status = connector_status_connected; |
ea5b213a | 160 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
aa93d632 | 161 | } |
674e2d08 | 162 | connector->display_info.raw_edid = NULL; |
aa93d632 | 163 | kfree(edid); |
9dff6af8 | 164 | } |
30ad48b7 | 165 | |
2ded9e27 | 166 | return status; |
7d57382e EA |
167 | } |
168 | ||
169 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
170 | { | |
df0e9248 | 171 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e EA |
172 | |
173 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
174 | * we can send audio to it. | |
175 | */ | |
176 | ||
ea5b213a | 177 | return intel_ddc_get_modes(connector, intel_hdmi->base.ddc_bus); |
7d57382e EA |
178 | } |
179 | ||
180 | static void intel_hdmi_destroy(struct drm_connector *connector) | |
181 | { | |
7d57382e EA |
182 | drm_sysfs_connector_remove(connector); |
183 | drm_connector_cleanup(connector); | |
674e2d08 | 184 | kfree(connector); |
7d57382e EA |
185 | } |
186 | ||
187 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
188 | .dpms = intel_hdmi_dpms, | |
189 | .mode_fixup = intel_hdmi_mode_fixup, | |
190 | .prepare = intel_encoder_prepare, | |
191 | .mode_set = intel_hdmi_mode_set, | |
192 | .commit = intel_encoder_commit, | |
193 | }; | |
194 | ||
195 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 196 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
197 | .detect = intel_hdmi_detect, |
198 | .fill_modes = drm_helper_probe_single_connector_modes, | |
199 | .destroy = intel_hdmi_destroy, | |
200 | }; | |
201 | ||
202 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
203 | .get_modes = intel_hdmi_get_modes, | |
204 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 205 | .best_encoder = intel_best_encoder, |
7d57382e EA |
206 | }; |
207 | ||
7d57382e | 208 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 209 | .destroy = intel_encoder_destroy, |
7d57382e EA |
210 | }; |
211 | ||
7d57382e EA |
212 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
213 | { | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | struct drm_connector *connector; | |
21d40d37 | 216 | struct intel_encoder *intel_encoder; |
674e2d08 | 217 | struct intel_connector *intel_connector; |
ea5b213a | 218 | struct intel_hdmi *intel_hdmi; |
7d57382e | 219 | |
ea5b213a CW |
220 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
221 | if (!intel_hdmi) | |
7d57382e | 222 | return; |
674e2d08 ZW |
223 | |
224 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
225 | if (!intel_connector) { | |
ea5b213a | 226 | kfree(intel_hdmi); |
674e2d08 ZW |
227 | return; |
228 | } | |
229 | ||
ea5b213a | 230 | intel_encoder = &intel_hdmi->base; |
674e2d08 | 231 | connector = &intel_connector->base; |
7d57382e | 232 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 233 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
234 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
235 | ||
21d40d37 | 236 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 237 | |
eb1f8e4f | 238 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e EA |
239 | connector->interlace_allowed = 0; |
240 | connector->doublescan_allowed = 0; | |
21d40d37 | 241 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
7d57382e EA |
242 | |
243 | /* Set up the DDC bus. */ | |
f8aed700 | 244 | if (sdvox_reg == SDVOB) { |
21d40d37 EA |
245 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
246 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); | |
b01f2c3a | 247 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 248 | } else if (sdvox_reg == SDVOC) { |
21d40d37 EA |
249 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
250 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); | |
b01f2c3a | 251 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 252 | } else if (sdvox_reg == HDMIB) { |
21d40d37 EA |
253 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
254 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, | |
30ad48b7 | 255 | "HDMIB"); |
b01f2c3a | 256 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 257 | } else if (sdvox_reg == HDMIC) { |
21d40d37 EA |
258 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
259 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, | |
30ad48b7 | 260 | "HDMIC"); |
b01f2c3a | 261 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 262 | } else if (sdvox_reg == HDMID) { |
21d40d37 EA |
263 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
264 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, | |
30ad48b7 | 265 | "HDMID"); |
b01f2c3a | 266 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 267 | } |
21d40d37 | 268 | if (!intel_encoder->ddc_bus) |
7d57382e EA |
269 | goto err_connector; |
270 | ||
ea5b213a | 271 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 272 | |
4ef69c7a | 273 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
7d57382e | 274 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 275 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 276 | |
df0e9248 | 277 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
278 | drm_sysfs_connector_add(connector); |
279 | ||
280 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
281 | * 0xd. Failure to do so will result in spurious interrupts being | |
282 | * generated on the port when a cable is not attached. | |
283 | */ | |
284 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
285 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
286 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
287 | } | |
288 | ||
289 | return; | |
290 | ||
291 | err_connector: | |
292 | drm_connector_cleanup(connector); | |
ea5b213a | 293 | kfree(intel_hdmi); |
674e2d08 | 294 | kfree(intel_connector); |
7d57382e EA |
295 | |
296 | return; | |
297 | } |