Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
fdf1250a | 169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 170 | enum hdmi_infoframe_type type, |
fff63867 | 171 | const void *frame, ssize_t len) |
fdf1250a | 172 | { |
fff63867 | 173 | const uint32_t *data = frame; |
fdf1250a PZ |
174 | struct drm_device *dev = encoder->dev; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 176 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 177 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
178 | u32 val = I915_READ(reg); |
179 | ||
822974ae PZ |
180 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
181 | ||
fdf1250a | 182 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 183 | val |= g4x_infoframe_index(type); |
fdf1250a | 184 | |
178f736a | 185 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
186 | |
187 | I915_WRITE(reg, val); | |
188 | ||
9d9740f0 | 189 | mmiowb(); |
fdf1250a PZ |
190 | for (i = 0; i < len; i += 4) { |
191 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
192 | data++; | |
193 | } | |
adf00b26 PZ |
194 | /* Write every possible data byte to force correct ECC calculation. */ |
195 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 197 | mmiowb(); |
fdf1250a | 198 | |
178f736a | 199 | val |= g4x_infoframe_enable(type); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
9d9740f0 | 204 | POSTING_READ(reg); |
fdf1250a PZ |
205 | } |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 208 | enum hdmi_infoframe_type type, |
fff63867 | 209 | const void *frame, ssize_t len) |
b055c8f3 | 210 | { |
fff63867 | 211 | const uint32_t *data = frame; |
b055c8f3 JB |
212 | struct drm_device *dev = encoder->dev; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 214 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 215 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 | 217 | |
822974ae PZ |
218 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 221 | val |= g4x_infoframe_index(type); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
178f736a DL |
225 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
226 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 227 | |
22509ec8 | 228 | I915_WRITE(reg, val); |
45187ace | 229 | |
9d9740f0 | 230 | mmiowb(); |
45187ace | 231 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
233 | data++; | |
234 | } | |
adf00b26 PZ |
235 | /* Write every possible data byte to force correct ECC calculation. */ |
236 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
237 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 238 | mmiowb(); |
b055c8f3 | 239 | |
178f736a | 240 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
9d9740f0 | 245 | POSTING_READ(reg); |
45187ace | 246 | } |
90b107c8 SK |
247 | |
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
90b107c8 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
90b107c8 SK |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 256 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 | 258 | |
822974ae PZ |
259 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 262 | val |= g4x_infoframe_index(type); |
22509ec8 | 263 | |
178f736a | 264 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 | 267 | |
9d9740f0 | 268 | mmiowb(); |
90b107c8 SK |
269 | for (i = 0; i < len; i += 4) { |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
90b107c8 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
90b107c8 SK |
284 | } |
285 | ||
8c5f5f7c | 286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 287 | enum hdmi_infoframe_type type, |
fff63867 | 288 | const void *frame, ssize_t len) |
8c5f5f7c | 289 | { |
fff63867 | 290 | const uint32_t *data = frame; |
2da8af54 PZ |
291 | struct drm_device *dev = encoder->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 294 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
295 | u32 data_reg; |
296 | int i; | |
2da8af54 | 297 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 298 | |
178f736a | 299 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
300 | intel_crtc->config.cpu_transcoder, |
301 | dev_priv); | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
178f736a | 305 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
306 | I915_WRITE(ctl_reg, val); |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
178f736a | 318 | val |= hsw_infoframe_enable(type); |
2da8af54 | 319 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
5adaea79 DL |
323 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
327 | * used for both technologies. | |
328 | * | |
329 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
330 | * DW1: DB3 | DB2 | DB1 | DB0 | |
331 | * DW2: DB7 | DB6 | DB5 | DB4 | |
332 | * DW3: ... | |
333 | * | |
334 | * (HB is Header Byte, DB is Data Byte) | |
335 | * | |
336 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
337 | * trick them by giving an offset into the buffer and moving back the header | |
338 | * bytes by one. | |
339 | */ | |
9198ee5b DL |
340 | static void intel_write_infoframe(struct drm_encoder *encoder, |
341 | union hdmi_infoframe *frame) | |
45187ace JB |
342 | { |
343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
344 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
345 | ssize_t len; | |
45187ace | 346 | |
5adaea79 DL |
347 | /* see comment above for the reason for this offset */ |
348 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
349 | if (len < 0) | |
350 | return; | |
351 | ||
352 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
353 | buffer[0] = buffer[1]; | |
354 | buffer[1] = buffer[2]; | |
355 | buffer[2] = buffer[3]; | |
356 | buffer[3] = 0; | |
357 | len++; | |
45187ace | 358 | |
5adaea79 | 359 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
360 | } |
361 | ||
687f4d06 | 362 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 363 | struct drm_display_mode *adjusted_mode) |
45187ace | 364 | { |
abedc077 | 365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 366 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
367 | union hdmi_infoframe frame; |
368 | int ret; | |
45187ace | 369 | |
94a11ddc VK |
370 | /* Set user selected PAR to incoming mode's member */ |
371 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
372 | ||
5adaea79 DL |
373 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
374 | adjusted_mode); | |
375 | if (ret < 0) { | |
376 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
377 | return; | |
378 | } | |
c846b619 | 379 | |
abedc077 | 380 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 381 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
382 | frame.avi.quantization_range = |
383 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 384 | else |
5adaea79 DL |
385 | frame.avi.quantization_range = |
386 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
387 | } |
388 | ||
9198ee5b | 389 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
390 | } |
391 | ||
687f4d06 | 392 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 393 | { |
5adaea79 DL |
394 | union hdmi_infoframe frame; |
395 | int ret; | |
396 | ||
397 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
398 | if (ret < 0) { | |
399 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
400 | return; | |
401 | } | |
c0864cb3 | 402 | |
5adaea79 | 403 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 404 | |
9198ee5b | 405 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
406 | } |
407 | ||
c8bb75af LD |
408 | static void |
409 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
410 | struct drm_display_mode *adjusted_mode) | |
411 | { | |
412 | union hdmi_infoframe frame; | |
413 | int ret; | |
414 | ||
415 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
416 | adjusted_mode); | |
417 | if (ret < 0) | |
418 | return; | |
419 | ||
420 | intel_write_infoframe(encoder, &frame); | |
421 | } | |
422 | ||
687f4d06 | 423 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 424 | bool enable, |
687f4d06 PZ |
425 | struct drm_display_mode *adjusted_mode) |
426 | { | |
0c14c7f9 | 427 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
428 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
429 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
430 | u32 reg = VIDEO_DIP_CTL; |
431 | u32 val = I915_READ(reg); | |
822cdc52 | 432 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 433 | |
afba0188 DV |
434 | assert_hdmi_port_disabled(intel_hdmi); |
435 | ||
0c14c7f9 PZ |
436 | /* If the registers were not initialized yet, they might be zeroes, |
437 | * which means we're selecting the AVI DIP and we're setting its | |
438 | * frequency to once. This seems to really confuse the HW and make | |
439 | * things stop working (the register spec says the AVI always needs to | |
440 | * be sent every VSync). So here we avoid writing to the register more | |
441 | * than we need and also explicitly select the AVI DIP and explicitly | |
442 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
443 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
444 | * either. */ | |
445 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
446 | ||
6897b4b5 | 447 | if (!enable) { |
0c14c7f9 PZ |
448 | if (!(val & VIDEO_DIP_ENABLE)) |
449 | return; | |
450 | val &= ~VIDEO_DIP_ENABLE; | |
451 | I915_WRITE(reg, val); | |
9d9740f0 | 452 | POSTING_READ(reg); |
0c14c7f9 PZ |
453 | return; |
454 | } | |
455 | ||
72b78c9d PZ |
456 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
457 | if (val & VIDEO_DIP_ENABLE) { | |
458 | val &= ~VIDEO_DIP_ENABLE; | |
459 | I915_WRITE(reg, val); | |
9d9740f0 | 460 | POSTING_READ(reg); |
72b78c9d PZ |
461 | } |
462 | val &= ~VIDEO_DIP_PORT_MASK; | |
463 | val |= port; | |
464 | } | |
465 | ||
822974ae | 466 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 467 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 468 | |
f278d972 | 469 | I915_WRITE(reg, val); |
9d9740f0 | 470 | POSTING_READ(reg); |
f278d972 | 471 | |
687f4d06 PZ |
472 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
473 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 474 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
475 | } |
476 | ||
477 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 478 | bool enable, |
687f4d06 PZ |
479 | struct drm_display_mode *adjusted_mode) |
480 | { | |
0c14c7f9 PZ |
481 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
483 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
484 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
485 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
486 | u32 val = I915_READ(reg); | |
822cdc52 | 487 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 488 | |
afba0188 DV |
489 | assert_hdmi_port_disabled(intel_hdmi); |
490 | ||
0c14c7f9 PZ |
491 | /* See the big comment in g4x_set_infoframes() */ |
492 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
493 | ||
6897b4b5 | 494 | if (!enable) { |
0c14c7f9 PZ |
495 | if (!(val & VIDEO_DIP_ENABLE)) |
496 | return; | |
497 | val &= ~VIDEO_DIP_ENABLE; | |
498 | I915_WRITE(reg, val); | |
9d9740f0 | 499 | POSTING_READ(reg); |
0c14c7f9 PZ |
500 | return; |
501 | } | |
502 | ||
72b78c9d PZ |
503 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
504 | if (val & VIDEO_DIP_ENABLE) { | |
505 | val &= ~VIDEO_DIP_ENABLE; | |
506 | I915_WRITE(reg, val); | |
9d9740f0 | 507 | POSTING_READ(reg); |
72b78c9d PZ |
508 | } |
509 | val &= ~VIDEO_DIP_PORT_MASK; | |
510 | val |= port; | |
511 | } | |
512 | ||
822974ae | 513 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
514 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
515 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 516 | |
f278d972 | 517 | I915_WRITE(reg, val); |
9d9740f0 | 518 | POSTING_READ(reg); |
f278d972 | 519 | |
687f4d06 PZ |
520 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
521 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 522 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
523 | } |
524 | ||
525 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 526 | bool enable, |
687f4d06 PZ |
527 | struct drm_display_mode *adjusted_mode) |
528 | { | |
0c14c7f9 PZ |
529 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
530 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
531 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
532 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
533 | u32 val = I915_READ(reg); | |
534 | ||
afba0188 DV |
535 | assert_hdmi_port_disabled(intel_hdmi); |
536 | ||
0c14c7f9 PZ |
537 | /* See the big comment in g4x_set_infoframes() */ |
538 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
539 | ||
6897b4b5 | 540 | if (!enable) { |
0c14c7f9 PZ |
541 | if (!(val & VIDEO_DIP_ENABLE)) |
542 | return; | |
543 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
544 | I915_WRITE(reg, val); | |
9d9740f0 | 545 | POSTING_READ(reg); |
0c14c7f9 PZ |
546 | return; |
547 | } | |
548 | ||
822974ae PZ |
549 | /* Set both together, unset both together: see the spec. */ |
550 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
551 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
552 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
553 | |
554 | I915_WRITE(reg, val); | |
9d9740f0 | 555 | POSTING_READ(reg); |
822974ae | 556 | |
687f4d06 PZ |
557 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
558 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 559 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
560 | } |
561 | ||
562 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 563 | bool enable, |
687f4d06 PZ |
564 | struct drm_display_mode *adjusted_mode) |
565 | { | |
0c14c7f9 | 566 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 567 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
568 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
569 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
570 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
571 | u32 val = I915_READ(reg); | |
6a2b8021 | 572 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 573 | |
afba0188 DV |
574 | assert_hdmi_port_disabled(intel_hdmi); |
575 | ||
0c14c7f9 PZ |
576 | /* See the big comment in g4x_set_infoframes() */ |
577 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
578 | ||
6897b4b5 | 579 | if (!enable) { |
0c14c7f9 PZ |
580 | if (!(val & VIDEO_DIP_ENABLE)) |
581 | return; | |
582 | val &= ~VIDEO_DIP_ENABLE; | |
583 | I915_WRITE(reg, val); | |
9d9740f0 | 584 | POSTING_READ(reg); |
0c14c7f9 PZ |
585 | return; |
586 | } | |
587 | ||
6a2b8021 JB |
588 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
589 | if (val & VIDEO_DIP_ENABLE) { | |
590 | val &= ~VIDEO_DIP_ENABLE; | |
591 | I915_WRITE(reg, val); | |
592 | POSTING_READ(reg); | |
593 | } | |
594 | val &= ~VIDEO_DIP_PORT_MASK; | |
595 | val |= port; | |
596 | } | |
597 | ||
822974ae | 598 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
599 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
600 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
601 | |
602 | I915_WRITE(reg, val); | |
9d9740f0 | 603 | POSTING_READ(reg); |
822974ae | 604 | |
687f4d06 PZ |
605 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
606 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 607 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
608 | } |
609 | ||
610 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 611 | bool enable, |
687f4d06 PZ |
612 | struct drm_display_mode *adjusted_mode) |
613 | { | |
0c14c7f9 PZ |
614 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
615 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
616 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 617 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 618 | u32 val = I915_READ(reg); |
0c14c7f9 | 619 | |
afba0188 DV |
620 | assert_hdmi_port_disabled(intel_hdmi); |
621 | ||
6897b4b5 | 622 | if (!enable) { |
0c14c7f9 | 623 | I915_WRITE(reg, 0); |
9d9740f0 | 624 | POSTING_READ(reg); |
0c14c7f9 PZ |
625 | return; |
626 | } | |
627 | ||
0dd87d20 PZ |
628 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
629 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
630 | ||
631 | I915_WRITE(reg, val); | |
9d9740f0 | 632 | POSTING_READ(reg); |
0dd87d20 | 633 | |
687f4d06 PZ |
634 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
635 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 636 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
637 | } |
638 | ||
4cde8a21 | 639 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 640 | { |
c59423a3 | 641 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 642 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
643 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
644 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
645 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 646 | u32 hdmi_val; |
7d57382e | 647 | |
b242b7f7 | 648 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 649 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 650 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 651 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 652 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 653 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 654 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 655 | |
c59423a3 | 656 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 657 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 658 | else |
4f3a8bc7 | 659 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 660 | |
6897b4b5 | 661 | if (crtc->config.has_hdmi_sink) |
dc0fa718 | 662 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 663 | |
75770564 | 664 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 665 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
666 | else if (IS_CHERRYVIEW(dev)) |
667 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 668 | else |
c59423a3 | 669 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 670 | |
b242b7f7 PZ |
671 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
672 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
673 | } |
674 | ||
85234cdc DV |
675 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
676 | enum pipe *pipe) | |
7d57382e | 677 | { |
85234cdc | 678 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 679 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 680 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 681 | enum intel_display_power_domain power_domain; |
85234cdc DV |
682 | u32 tmp; |
683 | ||
6d129bea | 684 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 685 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
686 | return false; |
687 | ||
b242b7f7 | 688 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
689 | |
690 | if (!(tmp & SDVO_ENABLE)) | |
691 | return false; | |
692 | ||
693 | if (HAS_PCH_CPT(dev)) | |
694 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
695 | else if (IS_CHERRYVIEW(dev)) |
696 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
697 | else |
698 | *pipe = PORT_TO_PIPE(tmp); | |
699 | ||
700 | return true; | |
701 | } | |
702 | ||
045ac3b5 JB |
703 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
704 | struct intel_crtc_config *pipe_config) | |
705 | { | |
706 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
707 | struct drm_device *dev = encoder->base.dev; |
708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 709 | u32 tmp, flags = 0; |
18442d08 | 710 | int dotclock; |
045ac3b5 JB |
711 | |
712 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
713 | ||
714 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
715 | flags |= DRM_MODE_FLAG_PHSYNC; | |
716 | else | |
717 | flags |= DRM_MODE_FLAG_NHSYNC; | |
718 | ||
719 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
720 | flags |= DRM_MODE_FLAG_PVSYNC; | |
721 | else | |
722 | flags |= DRM_MODE_FLAG_NVSYNC; | |
723 | ||
6897b4b5 DV |
724 | if (tmp & HDMI_MODE_SELECT_HDMI) |
725 | pipe_config->has_hdmi_sink = true; | |
726 | ||
c84db770 | 727 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
728 | pipe_config->has_audio = true; |
729 | ||
8c875fca VS |
730 | if (!HAS_PCH_SPLIT(dev) && |
731 | tmp & HDMI_COLOR_RANGE_16_235) | |
732 | pipe_config->limited_color_range = true; | |
733 | ||
045ac3b5 | 734 | pipe_config->adjusted_mode.flags |= flags; |
18442d08 VS |
735 | |
736 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
737 | dotclock = pipe_config->port_clock * 2 / 3; | |
738 | else | |
739 | dotclock = pipe_config->port_clock; | |
740 | ||
741 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
742 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
743 | ||
241bfc38 | 744 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
745 | } |
746 | ||
5ab432ef | 747 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 748 | { |
5ab432ef | 749 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 750 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 751 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 752 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 753 | u32 temp; |
2deed761 WF |
754 | u32 enable_bits = SDVO_ENABLE; |
755 | ||
9ed109a7 | 756 | if (intel_crtc->config.has_audio) |
2deed761 | 757 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 758 | |
b242b7f7 | 759 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 760 | |
7a87c289 | 761 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
762 | * before disabling it, so restore the transcoder select bit here. */ |
763 | if (HAS_PCH_IBX(dev)) | |
764 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 765 | |
d8a2d0e0 ZW |
766 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
767 | * we do this anyway which shows more stable in testing. | |
768 | */ | |
c619eed4 | 769 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
770 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
771 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
772 | } |
773 | ||
5ab432ef DV |
774 | temp |= enable_bits; |
775 | ||
b242b7f7 PZ |
776 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
777 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
778 | |
779 | /* HW workaround, need to write this twice for issue that may result | |
780 | * in first write getting masked. | |
781 | */ | |
782 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
783 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
784 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 785 | } |
c1dec79a JN |
786 | |
787 | if (intel_crtc->config.has_audio) { | |
788 | WARN_ON(!intel_crtc->config.has_hdmi_sink); | |
789 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
790 | pipe_name(intel_crtc->pipe)); | |
791 | intel_audio_codec_enable(encoder); | |
792 | } | |
b76cf76b | 793 | } |
89b667f8 | 794 | |
b76cf76b JN |
795 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
796 | { | |
5ab432ef DV |
797 | } |
798 | ||
799 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
800 | { | |
801 | struct drm_device *dev = encoder->base.dev; | |
802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
803 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 804 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 805 | u32 temp; |
3cce574f | 806 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 807 | |
495a5bb8 JN |
808 | if (crtc->config.has_audio) |
809 | intel_audio_codec_disable(encoder); | |
810 | ||
b242b7f7 | 811 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
812 | |
813 | /* HW workaround for IBX, we need to move the port to transcoder A | |
814 | * before disabling it. */ | |
815 | if (HAS_PCH_IBX(dev)) { | |
816 | struct drm_crtc *crtc = encoder->base.crtc; | |
817 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
818 | ||
819 | if (temp & SDVO_PIPE_B_SELECT) { | |
820 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
821 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
822 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
823 | |
824 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
825 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
826 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
827 | |
828 | /* Transcoder selection bits only update | |
829 | * effectively on vblank. */ | |
830 | if (crtc) | |
831 | intel_wait_for_vblank(dev, pipe); | |
832 | else | |
833 | msleep(50); | |
834 | } | |
7d57382e | 835 | } |
d8a2d0e0 | 836 | |
5ab432ef DV |
837 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
838 | * we do this anyway which shows more stable in testing. | |
839 | */ | |
840 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
841 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
842 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
843 | } |
844 | ||
845 | temp &= ~enable_bits; | |
d8a2d0e0 | 846 | |
b242b7f7 PZ |
847 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
848 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
849 | |
850 | /* HW workaround, need to write this twice for issue that may result | |
851 | * in first write getting masked. | |
852 | */ | |
c619eed4 | 853 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
854 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
855 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 856 | } |
7d57382e EA |
857 | } |
858 | ||
40478455 | 859 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
860 | { |
861 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
862 | ||
40478455 | 863 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 864 | return 165000; |
e3c33578 | 865 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
866 | return 300000; |
867 | else | |
868 | return 225000; | |
869 | } | |
870 | ||
c19de8eb DL |
871 | static enum drm_mode_status |
872 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
873 | struct drm_display_mode *mode) | |
7d57382e | 874 | { |
697c4078 CT |
875 | int clock = mode->clock; |
876 | ||
877 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
878 | clock *= 2; | |
879 | ||
880 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
881 | true)) | |
7d57382e | 882 | return MODE_CLOCK_HIGH; |
697c4078 | 883 | if (clock < 20000) |
5cbba41d | 884 | return MODE_CLOCK_LOW; |
7d57382e EA |
885 | |
886 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
887 | return MODE_NO_DBLESCAN; | |
888 | ||
889 | return MODE_OK; | |
890 | } | |
891 | ||
71800632 VS |
892 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
893 | { | |
894 | struct drm_device *dev = crtc->base.dev; | |
895 | struct intel_encoder *encoder; | |
896 | int count = 0, count_hdmi = 0; | |
897 | ||
f227ae9e | 898 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
899 | return false; |
900 | ||
b2784e15 | 901 | for_each_intel_encoder(dev, encoder) { |
71800632 VS |
902 | if (encoder->new_crtc != crtc) |
903 | continue; | |
904 | ||
905 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
906 | count++; | |
907 | } | |
908 | ||
909 | /* | |
910 | * HDMI 12bpc affects the clocks, so it's only possible | |
911 | * when not cloning with other encoder types. | |
912 | */ | |
913 | return count_hdmi > 0 && count_hdmi == count; | |
914 | } | |
915 | ||
5bfe2ac0 DV |
916 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
917 | struct intel_crtc_config *pipe_config) | |
7d57382e | 918 | { |
5bfe2ac0 DV |
919 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
920 | struct drm_device *dev = encoder->base.dev; | |
921 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 922 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
40478455 | 923 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 924 | int desired_bpp; |
3685a8f3 | 925 | |
6897b4b5 DV |
926 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
927 | ||
55bc60db VS |
928 | if (intel_hdmi->color_range_auto) { |
929 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 930 | if (pipe_config->has_hdmi_sink && |
18316c8c | 931 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 932 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
933 | else |
934 | intel_hdmi->color_range = 0; | |
935 | } | |
936 | ||
697c4078 CT |
937 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
938 | pipe_config->pixel_multiplier = 2; | |
939 | } | |
940 | ||
3685a8f3 | 941 | if (intel_hdmi->color_range) |
50f3b016 | 942 | pipe_config->limited_color_range = true; |
3685a8f3 | 943 | |
5bfe2ac0 DV |
944 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
945 | pipe_config->has_pch_encoder = true; | |
946 | ||
9ed109a7 DV |
947 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
948 | pipe_config->has_audio = true; | |
949 | ||
4e53c2e0 DV |
950 | /* |
951 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
952 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
953 | * outputs. We also need to check that the higher clock still fits |
954 | * within limits. | |
4e53c2e0 | 955 | */ |
6897b4b5 | 956 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 VS |
957 | clock_12bpc <= portclock_limit && |
958 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
959 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
960 | desired_bpp = 12*3; | |
325b9d04 DV |
961 | |
962 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 963 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 964 | } else { |
e29c22c0 DV |
965 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
966 | desired_bpp = 8*3; | |
967 | } | |
968 | ||
969 | if (!pipe_config->bw_constrained) { | |
970 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
971 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
972 | } |
973 | ||
241bfc38 | 974 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
975 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
976 | return false; | |
977 | } | |
978 | ||
7d57382e EA |
979 | return true; |
980 | } | |
981 | ||
953ece69 CW |
982 | static void |
983 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 984 | { |
df0e9248 | 985 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 986 | |
953ece69 CW |
987 | intel_hdmi->has_hdmi_sink = false; |
988 | intel_hdmi->has_audio = false; | |
989 | intel_hdmi->rgb_quant_range_selectable = false; | |
990 | ||
991 | kfree(to_intel_connector(connector)->detect_edid); | |
992 | to_intel_connector(connector)->detect_edid = NULL; | |
993 | } | |
994 | ||
995 | static bool | |
996 | intel_hdmi_set_edid(struct drm_connector *connector) | |
997 | { | |
998 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
999 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1000 | struct intel_encoder *intel_encoder = | |
1001 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1002 | enum intel_display_power_domain power_domain; | |
1003 | struct edid *edid; | |
1004 | bool connected = false; | |
164c8598 | 1005 | |
671dedd2 ID |
1006 | power_domain = intel_display_port_power_domain(intel_encoder); |
1007 | intel_display_power_get(dev_priv, power_domain); | |
1008 | ||
f899fc64 | 1009 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1010 | intel_gmbus_get_adapter(dev_priv, |
1011 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1012 | |
953ece69 | 1013 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1014 | |
953ece69 CW |
1015 | to_intel_connector(connector)->detect_edid = edid; |
1016 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1017 | intel_hdmi->rgb_quant_range_selectable = | |
1018 | drm_rgb_quant_range_selectable(edid); | |
1019 | ||
1020 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1021 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1022 | intel_hdmi->has_audio = | |
953ece69 CW |
1023 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1024 | ||
1025 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1026 | intel_hdmi->has_hdmi_sink = | |
1027 | drm_detect_hdmi_monitor(edid); | |
1028 | ||
1029 | connected = true; | |
55b7d6e8 CW |
1030 | } |
1031 | ||
953ece69 CW |
1032 | return connected; |
1033 | } | |
1034 | ||
1035 | static enum drm_connector_status | |
1036 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1037 | { | |
1038 | enum drm_connector_status status; | |
1039 | ||
1040 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1041 | connector->base.id, connector->name); | |
1042 | ||
1043 | intel_hdmi_unset_edid(connector); | |
1044 | ||
1045 | if (intel_hdmi_set_edid(connector)) { | |
1046 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1047 | ||
1048 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1049 | status = connector_status_connected; | |
1050 | } else | |
1051 | status = connector_status_disconnected; | |
671dedd2 | 1052 | |
2ded9e27 | 1053 | return status; |
7d57382e EA |
1054 | } |
1055 | ||
953ece69 CW |
1056 | static void |
1057 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1058 | { |
953ece69 | 1059 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1060 | |
953ece69 CW |
1061 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1062 | connector->base.id, connector->name); | |
7d57382e | 1063 | |
953ece69 | 1064 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1065 | |
953ece69 CW |
1066 | if (connector->status != connector_status_connected) |
1067 | return; | |
671dedd2 | 1068 | |
953ece69 CW |
1069 | intel_hdmi_set_edid(connector); |
1070 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1071 | } | |
671dedd2 | 1072 | |
953ece69 CW |
1073 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1074 | { | |
1075 | struct edid *edid; | |
1076 | ||
1077 | edid = to_intel_connector(connector)->detect_edid; | |
1078 | if (edid == NULL) | |
1079 | return 0; | |
671dedd2 | 1080 | |
953ece69 | 1081 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1082 | } |
1083 | ||
1aad7ac0 CW |
1084 | static bool |
1085 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1086 | { | |
1aad7ac0 | 1087 | bool has_audio = false; |
953ece69 | 1088 | struct edid *edid; |
1aad7ac0 | 1089 | |
953ece69 CW |
1090 | edid = to_intel_connector(connector)->detect_edid; |
1091 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1092 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1093 | |
1aad7ac0 CW |
1094 | return has_audio; |
1095 | } | |
1096 | ||
55b7d6e8 CW |
1097 | static int |
1098 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1099 | struct drm_property *property, |
1100 | uint64_t val) | |
55b7d6e8 CW |
1101 | { |
1102 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1103 | struct intel_digital_port *intel_dig_port = |
1104 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1105 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1106 | int ret; |
1107 | ||
662595df | 1108 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1109 | if (ret) |
1110 | return ret; | |
1111 | ||
3f43c48d | 1112 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1113 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1114 | bool has_audio; |
1115 | ||
1116 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1117 | return 0; |
1118 | ||
1aad7ac0 | 1119 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1120 | |
b1d7e4b4 | 1121 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1122 | has_audio = intel_hdmi_detect_audio(connector); |
1123 | else | |
b1d7e4b4 | 1124 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1125 | |
b1d7e4b4 WF |
1126 | if (i == HDMI_AUDIO_OFF_DVI) |
1127 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1128 | |
1aad7ac0 | 1129 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1130 | goto done; |
1131 | } | |
1132 | ||
e953fd7b | 1133 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1134 | bool old_auto = intel_hdmi->color_range_auto; |
1135 | uint32_t old_range = intel_hdmi->color_range; | |
1136 | ||
55bc60db VS |
1137 | switch (val) { |
1138 | case INTEL_BROADCAST_RGB_AUTO: | |
1139 | intel_hdmi->color_range_auto = true; | |
1140 | break; | |
1141 | case INTEL_BROADCAST_RGB_FULL: | |
1142 | intel_hdmi->color_range_auto = false; | |
1143 | intel_hdmi->color_range = 0; | |
1144 | break; | |
1145 | case INTEL_BROADCAST_RGB_LIMITED: | |
1146 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1147 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1148 | break; |
1149 | default: | |
1150 | return -EINVAL; | |
1151 | } | |
ae4edb80 DV |
1152 | |
1153 | if (old_auto == intel_hdmi->color_range_auto && | |
1154 | old_range == intel_hdmi->color_range) | |
1155 | return 0; | |
1156 | ||
e953fd7b CW |
1157 | goto done; |
1158 | } | |
1159 | ||
94a11ddc VK |
1160 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1161 | switch (val) { | |
1162 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1163 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1164 | break; | |
1165 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1166 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1167 | break; | |
1168 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1169 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1170 | break; | |
1171 | default: | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | goto done; | |
1175 | } | |
1176 | ||
55b7d6e8 CW |
1177 | return -EINVAL; |
1178 | ||
1179 | done: | |
c0c36b94 CW |
1180 | if (intel_dig_port->base.base.crtc) |
1181 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1182 | |
1183 | return 0; | |
1184 | } | |
1185 | ||
13732ba7 JB |
1186 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1187 | { | |
1188 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1189 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1190 | struct drm_display_mode *adjusted_mode = | |
1191 | &intel_crtc->config.adjusted_mode; | |
1192 | ||
4cde8a21 DV |
1193 | intel_hdmi_prepare(encoder); |
1194 | ||
6897b4b5 DV |
1195 | intel_hdmi->set_infoframes(&encoder->base, |
1196 | intel_crtc->config.has_hdmi_sink, | |
1197 | adjusted_mode); | |
13732ba7 JB |
1198 | } |
1199 | ||
9514ac6e | 1200 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1201 | { |
1202 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1203 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1204 | struct drm_device *dev = encoder->base.dev; |
1205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1206 | struct intel_crtc *intel_crtc = | |
1207 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 JB |
1208 | struct drm_display_mode *adjusted_mode = |
1209 | &intel_crtc->config.adjusted_mode; | |
e4607fcf | 1210 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1211 | int pipe = intel_crtc->pipe; |
1212 | u32 val; | |
1213 | ||
89b667f8 | 1214 | /* Enable clock channels for this port */ |
0980a60f | 1215 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1216 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1217 | val = 0; |
1218 | if (pipe) | |
1219 | val |= (1<<21); | |
1220 | else | |
1221 | val &= ~(1<<21); | |
1222 | val |= 0x001000c4; | |
ab3c759a | 1223 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1224 | |
1225 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1226 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1227 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1228 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1229 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1230 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1231 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1232 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1233 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1234 | |
1235 | /* Program lane clock */ | |
ab3c759a CML |
1236 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1237 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1238 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1239 | |
6897b4b5 DV |
1240 | intel_hdmi->set_infoframes(&encoder->base, |
1241 | intel_crtc->config.has_hdmi_sink, | |
1242 | adjusted_mode); | |
13732ba7 | 1243 | |
b76cf76b JN |
1244 | intel_enable_hdmi(encoder); |
1245 | ||
e4607fcf | 1246 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1247 | } |
1248 | ||
9514ac6e | 1249 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1250 | { |
1251 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1252 | struct drm_device *dev = encoder->base.dev; | |
1253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1254 | struct intel_crtc *intel_crtc = |
1255 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1256 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1257 | int pipe = intel_crtc->pipe; |
89b667f8 | 1258 | |
4cde8a21 DV |
1259 | intel_hdmi_prepare(encoder); |
1260 | ||
89b667f8 | 1261 | /* Program Tx lane resets to default */ |
0980a60f | 1262 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1263 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1264 | DPIO_PCS_TX_LANE2_RESET | |
1265 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1266 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1267 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1268 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1269 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1270 | DPIO_PCS_CLK_SOFT_RESET); | |
1271 | ||
1272 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1273 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1274 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1275 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1276 | ||
1277 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1278 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1279 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1280 | } |
1281 | ||
9197c88b VS |
1282 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1283 | { | |
1284 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1285 | struct drm_device *dev = encoder->base.dev; | |
1286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1287 | struct intel_crtc *intel_crtc = | |
1288 | to_intel_crtc(encoder->base.crtc); | |
1289 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1290 | enum pipe pipe = intel_crtc->pipe; | |
1291 | u32 val; | |
1292 | ||
625695f8 VS |
1293 | intel_hdmi_prepare(encoder); |
1294 | ||
9197c88b VS |
1295 | mutex_lock(&dev_priv->dpio_lock); |
1296 | ||
b9e5ac3c VS |
1297 | /* program left/right clock distribution */ |
1298 | if (pipe != PIPE_B) { | |
1299 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1300 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1301 | if (ch == DPIO_CH0) | |
1302 | val |= CHV_BUFLEFTENA1_FORCE; | |
1303 | if (ch == DPIO_CH1) | |
1304 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1305 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1306 | } else { | |
1307 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1308 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1309 | if (ch == DPIO_CH0) | |
1310 | val |= CHV_BUFLEFTENA2_FORCE; | |
1311 | if (ch == DPIO_CH1) | |
1312 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1313 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1314 | } | |
1315 | ||
9197c88b VS |
1316 | /* program clock channel usage */ |
1317 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1318 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1319 | if (pipe != PIPE_B) | |
1320 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1321 | else | |
1322 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1323 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1324 | ||
1325 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1326 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1327 | if (pipe != PIPE_B) | |
1328 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1329 | else | |
1330 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1331 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1332 | ||
1333 | /* | |
1334 | * This a a bit weird since generally CL | |
1335 | * matches the pipe, but here we need to | |
1336 | * pick the CL based on the port. | |
1337 | */ | |
1338 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1339 | if (pipe != PIPE_B) | |
1340 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1341 | else | |
1342 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1343 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1344 | ||
1345 | mutex_unlock(&dev_priv->dpio_lock); | |
1346 | } | |
1347 | ||
9514ac6e | 1348 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1349 | { |
1350 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1351 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1352 | struct intel_crtc *intel_crtc = |
1353 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1354 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1355 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1356 | |
1357 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1358 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1359 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1360 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1361 | mutex_unlock(&dev_priv->dpio_lock); |
1362 | } | |
1363 | ||
580d3811 VS |
1364 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1365 | { | |
1366 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1367 | struct drm_device *dev = encoder->base.dev; | |
1368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1369 | struct intel_crtc *intel_crtc = | |
1370 | to_intel_crtc(encoder->base.crtc); | |
1371 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1372 | enum pipe pipe = intel_crtc->pipe; | |
1373 | u32 val; | |
1374 | ||
1375 | mutex_lock(&dev_priv->dpio_lock); | |
1376 | ||
1377 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1378 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1379 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1380 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1381 | |
97fd4d5c VS |
1382 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1383 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1384 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1385 | ||
1386 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1387 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1388 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1389 | ||
1390 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1391 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1392 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1393 | |
1394 | mutex_unlock(&dev_priv->dpio_lock); | |
1395 | } | |
1396 | ||
e4a1d846 CML |
1397 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1398 | { | |
1399 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1400 | struct drm_device *dev = encoder->base.dev; | |
1401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1402 | struct intel_crtc *intel_crtc = | |
1403 | to_intel_crtc(encoder->base.crtc); | |
1404 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1405 | int pipe = intel_crtc->pipe; | |
1406 | int data, i; | |
1407 | u32 val; | |
1408 | ||
e4a1d846 | 1409 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 | 1410 | |
570e2a74 VS |
1411 | /* allow hardware to manage TX FIFO reset source */ |
1412 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1413 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1414 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1415 | ||
1416 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1417 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1418 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1419 | ||
949c1d43 | 1420 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1421 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1422 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1423 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1424 | ||
1425 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1426 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1427 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1428 | ||
1429 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1430 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1431 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1432 | |
97fd4d5c | 1433 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1434 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1435 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1436 | |
1437 | /* Program Tx latency optimal setting */ | |
e4a1d846 CML |
1438 | for (i = 0; i < 4; i++) { |
1439 | /* Set the latency optimal bit */ | |
1440 | data = (i == 1) ? 0x0 : 0x6; | |
1441 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1442 | data << DPIO_FRC_LATENCY_SHFIT); | |
1443 | ||
1444 | /* Set the upar bit */ | |
1445 | data = (i == 1) ? 0x0 : 0x1; | |
1446 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1447 | data << DPIO_UPAR_SHIFT); | |
1448 | } | |
1449 | ||
1450 | /* Data lane stagger programming */ | |
1451 | /* FIXME: Fix up value only after power analysis */ | |
1452 | ||
1453 | /* Clear calc init */ | |
1966e59e VS |
1454 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1455 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1456 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1457 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1458 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1459 | ||
1460 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1461 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1462 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1463 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1464 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1465 | |
a02ef3c7 VS |
1466 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1467 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1468 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1469 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1470 | ||
1471 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1472 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1473 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1474 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1475 | ||
e4a1d846 CML |
1476 | /* FIXME: Program the support xxx V-dB */ |
1477 | /* Use 800mV-0dB */ | |
f72df8db VS |
1478 | for (i = 0; i < 4; i++) { |
1479 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1480 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1481 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1482 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1483 | } | |
e4a1d846 | 1484 | |
f72df8db VS |
1485 | for (i = 0; i < 4; i++) { |
1486 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1487 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1488 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1489 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1490 | } | |
e4a1d846 CML |
1491 | |
1492 | /* Disable unique transition scale */ | |
f72df8db VS |
1493 | for (i = 0; i < 4; i++) { |
1494 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1495 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1496 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1497 | } | |
e4a1d846 CML |
1498 | |
1499 | /* Additional steps for 1200mV-0dB */ | |
1500 | #if 0 | |
1501 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1502 | if (ch) | |
1503 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1504 | else | |
1505 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1506 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1507 | ||
1508 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1509 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1510 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1511 | #endif | |
1512 | /* Start swing calculation */ | |
1966e59e VS |
1513 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1514 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1515 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1516 | ||
1517 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1518 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1519 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1520 | |
1521 | /* LRC Bypass */ | |
1522 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1523 | val |= DPIO_LRC_BYPASS; | |
1524 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1525 | ||
1526 | mutex_unlock(&dev_priv->dpio_lock); | |
1527 | ||
1528 | intel_enable_hdmi(encoder); | |
1529 | ||
1530 | vlv_wait_port_ready(dev_priv, dport); | |
1531 | } | |
1532 | ||
7d57382e EA |
1533 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1534 | { | |
10e972d3 | 1535 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1536 | drm_connector_cleanup(connector); |
674e2d08 | 1537 | kfree(connector); |
7d57382e EA |
1538 | } |
1539 | ||
7d57382e | 1540 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1541 | .dpms = intel_connector_dpms, |
7d57382e | 1542 | .detect = intel_hdmi_detect, |
953ece69 | 1543 | .force = intel_hdmi_force, |
7d57382e | 1544 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1545 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1546 | .destroy = intel_hdmi_destroy, |
1547 | }; | |
1548 | ||
1549 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1550 | .get_modes = intel_hdmi_get_modes, | |
1551 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1552 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1553 | }; |
1554 | ||
7d57382e | 1555 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1556 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1557 | }; |
1558 | ||
94a11ddc VK |
1559 | static void |
1560 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1561 | { | |
1562 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1563 | drm_object_attach_property(&connector->base, | |
1564 | connector->dev->mode_config.aspect_ratio_property, | |
1565 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1566 | } | |
1567 | ||
55b7d6e8 CW |
1568 | static void |
1569 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1570 | { | |
3f43c48d | 1571 | intel_attach_force_audio_property(connector); |
e953fd7b | 1572 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1573 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1574 | intel_attach_aspect_ratio_property(connector); |
1575 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1576 | } |
1577 | ||
00c09d70 PZ |
1578 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1579 | struct intel_connector *intel_connector) | |
7d57382e | 1580 | { |
b9cb234c PZ |
1581 | struct drm_connector *connector = &intel_connector->base; |
1582 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1583 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1584 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1585 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1586 | enum port port = intel_dig_port->port; |
373a3cf7 | 1587 | |
7d57382e | 1588 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1589 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1590 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1591 | ||
c3febcc4 | 1592 | connector->interlace_allowed = 1; |
7d57382e | 1593 | connector->doublescan_allowed = 0; |
573e74ad | 1594 | connector->stereo_allowed = 1; |
66a9278e | 1595 | |
08d644ad DV |
1596 | switch (port) { |
1597 | case PORT_B: | |
f899fc64 | 1598 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1599 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1600 | break; |
1601 | case PORT_C: | |
7ceae0a5 | 1602 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1603 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1604 | break; |
1605 | case PORT_D: | |
c0c35329 VS |
1606 | if (IS_CHERRYVIEW(dev)) |
1607 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; | |
1608 | else | |
1609 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
1d843f9d | 1610 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1611 | break; |
1612 | case PORT_A: | |
1d843f9d | 1613 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1614 | /* Internal port only for eDP. */ |
1615 | default: | |
6e4c1677 | 1616 | BUG(); |
f8aed700 | 1617 | } |
7d57382e | 1618 | |
7637bfdb | 1619 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1620 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1621 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
b98856a8 | 1622 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1623 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1624 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1625 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1626 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1627 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1628 | } else if (HAS_PCH_IBX(dev)) { |
1629 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1630 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1631 | } else { |
1632 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1633 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1634 | } |
45187ace | 1635 | |
affa9354 | 1636 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1637 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1638 | else | |
1639 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1640 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1641 | |
1642 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1643 | ||
1644 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1645 | drm_connector_register(connector); |
b9cb234c PZ |
1646 | |
1647 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1648 | * 0xd. Failure to do so will result in spurious interrupts being | |
1649 | * generated on the port when a cable is not attached. | |
1650 | */ | |
1651 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1652 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1653 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1654 | } | |
1655 | } | |
1656 | ||
b242b7f7 | 1657 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1658 | { |
1659 | struct intel_digital_port *intel_dig_port; | |
1660 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1661 | struct intel_connector *intel_connector; |
1662 | ||
b14c5679 | 1663 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1664 | if (!intel_dig_port) |
1665 | return; | |
1666 | ||
b14c5679 | 1667 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1668 | if (!intel_connector) { |
1669 | kfree(intel_dig_port); | |
1670 | return; | |
1671 | } | |
1672 | ||
1673 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1674 | |
1675 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1676 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1677 | |
5bfe2ac0 | 1678 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1679 | intel_encoder->disable = intel_disable_hdmi; |
1680 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1681 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1682 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1683 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1684 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1685 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1686 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1687 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1688 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1689 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1690 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1691 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1692 | } else { |
13732ba7 | 1693 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1694 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1695 | } |
5ab432ef | 1696 | |
b9cb234c | 1697 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1698 | if (IS_CHERRYVIEW(dev)) { |
1699 | if (port == PORT_D) | |
1700 | intel_encoder->crtc_mask = 1 << 2; | |
1701 | else | |
1702 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1703 | } else { | |
1704 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1705 | } | |
301ea74a | 1706 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1707 | /* |
1708 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1709 | * to work on real hardware. And since g4x can send infoframes to | |
1710 | * only one port anyway, nothing is lost by allowing it. | |
1711 | */ | |
1712 | if (IS_G4X(dev)) | |
1713 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1714 | |
174edf1f | 1715 | intel_dig_port->port = port; |
b242b7f7 | 1716 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1717 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1718 | |
b9cb234c | 1719 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1720 | } |