Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
f5bbfca3 | 40 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 41 | { |
4ef69c7a | 42 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
43 | } |
44 | ||
df0e9248 CW |
45 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
46 | { | |
47 | return container_of(intel_attached_encoder(connector), | |
48 | struct intel_hdmi, base); | |
49 | } | |
50 | ||
45187ace | 51 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 52 | { |
45187ace | 53 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
54 | uint8_t sum = 0; |
55 | unsigned i; | |
56 | ||
45187ace JB |
57 | frame->checksum = 0; |
58 | frame->ecc = 0; | |
3c17fe4b | 59 | |
64a8fc01 | 60 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
61 | sum += data[i]; |
62 | ||
45187ace | 63 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
64 | } |
65 | ||
bc2481f3 | 66 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 67 | { |
45187ace JB |
68 | u32 flags = 0; |
69 | ||
70 | switch (frame->type) { | |
71 | case DIP_TYPE_AVI: | |
72 | flags |= VIDEO_DIP_SELECT_AVI; | |
73 | break; | |
74 | case DIP_TYPE_SPD: | |
75 | flags |= VIDEO_DIP_SELECT_SPD; | |
76 | break; | |
77 | default: | |
78 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
79 | break; | |
80 | } | |
81 | ||
82 | return flags; | |
83 | } | |
84 | ||
bc2481f3 | 85 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace JB |
86 | { |
87 | u32 flags = 0; | |
88 | ||
89 | switch (frame->type) { | |
90 | case DIP_TYPE_AVI: | |
fa193ff7 | 91 | flags |= VIDEO_DIP_ENABLE_AVI; |
45187ace JB |
92 | break; |
93 | case DIP_TYPE_SPD: | |
fa193ff7 PZ |
94 | flags |= VIDEO_DIP_ENABLE_SPD; |
95 | break; | |
96 | default: | |
97 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
98 | break; | |
99 | } | |
100 | ||
101 | return flags; | |
102 | } | |
103 | ||
a3da1df7 DV |
104 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
105 | struct dip_infoframe *frame) | |
45187ace JB |
106 | { |
107 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
108 | struct drm_device *dev = encoder->dev; |
109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
110 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 111 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 112 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 113 | |
3c17fe4b DH |
114 | |
115 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 116 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 117 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 118 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 119 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 120 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
121 | else |
122 | return; | |
123 | ||
1d4f85ac | 124 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 125 | val |= g4x_infoframe_index(frame); |
22509ec8 | 126 | |
bc2481f3 | 127 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 128 | val |= VIDEO_DIP_ENABLE; |
45187ace | 129 | |
22509ec8 | 130 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 131 | |
45187ace | 132 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
133 | I915_WRITE(VIDEO_DIP_DATA, *data); |
134 | data++; | |
135 | } | |
136 | ||
bc2481f3 | 137 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 138 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 139 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 140 | |
22509ec8 | 141 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
142 | } |
143 | ||
fdf1250a PZ |
144 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
145 | struct dip_infoframe *frame) | |
146 | { | |
147 | uint32_t *data = (uint32_t *)frame; | |
148 | struct drm_device *dev = encoder->dev; | |
149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
150 | struct drm_crtc *crtc = encoder->crtc; | |
151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4e89ee17 | 152 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
153 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
154 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
155 | u32 val = I915_READ(reg); | |
156 | ||
4e89ee17 PZ |
157 | val &= ~VIDEO_DIP_PORT_MASK; |
158 | switch (intel_hdmi->sdvox_reg) { | |
159 | case HDMIB: | |
160 | val |= VIDEO_DIP_PORT_B; | |
161 | break; | |
162 | case HDMIC: | |
163 | val |= VIDEO_DIP_PORT_C; | |
164 | break; | |
165 | case HDMID: | |
166 | val |= VIDEO_DIP_PORT_D; | |
167 | break; | |
168 | default: | |
169 | return; | |
170 | } | |
171 | ||
fdf1250a PZ |
172 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
173 | ||
174 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
bc2481f3 | 175 | val |= g4x_infoframe_index(frame); |
fdf1250a | 176 | |
bc2481f3 | 177 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
178 | val |= VIDEO_DIP_ENABLE; |
179 | ||
180 | I915_WRITE(reg, val); | |
181 | ||
182 | for (i = 0; i < len; i += 4) { | |
183 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
184 | data++; | |
185 | } | |
186 | ||
bc2481f3 | 187 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 188 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 189 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
190 | |
191 | I915_WRITE(reg, val); | |
192 | } | |
193 | ||
194 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
195 | struct dip_infoframe *frame) | |
b055c8f3 | 196 | { |
45187ace | 197 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
198 | struct drm_device *dev = encoder->dev; |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
200 | struct drm_crtc *crtc = encoder->crtc; |
201 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
202 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 203 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 204 | u32 val = I915_READ(reg); |
b055c8f3 JB |
205 | |
206 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
207 | ||
64a8fc01 | 208 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 209 | val |= g4x_infoframe_index(frame); |
45187ace | 210 | |
ecb97851 PZ |
211 | /* The DIP control register spec says that we need to update the AVI |
212 | * infoframe without clearing its enable bit */ | |
213 | if (frame->type == DIP_TYPE_AVI) | |
214 | val |= VIDEO_DIP_ENABLE_AVI; | |
215 | else | |
bc2481f3 | 216 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 217 | |
22509ec8 PZ |
218 | val |= VIDEO_DIP_ENABLE; |
219 | ||
220 | I915_WRITE(reg, val); | |
45187ace JB |
221 | |
222 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
223 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
224 | data++; | |
225 | } | |
226 | ||
bc2481f3 | 227 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 228 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 229 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 230 | |
22509ec8 | 231 | I915_WRITE(reg, val); |
45187ace | 232 | } |
90b107c8 SK |
233 | |
234 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
235 | struct dip_infoframe *frame) | |
236 | { | |
237 | uint32_t *data = (uint32_t *)frame; | |
238 | struct drm_device *dev = encoder->dev; | |
239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
240 | struct drm_crtc *crtc = encoder->crtc; | |
241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
242 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
243 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 244 | u32 val = I915_READ(reg); |
90b107c8 SK |
245 | |
246 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
247 | ||
90b107c8 | 248 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 249 | val |= g4x_infoframe_index(frame); |
22509ec8 | 250 | |
bc2481f3 | 251 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 252 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 253 | |
22509ec8 | 254 | I915_WRITE(reg, val); |
90b107c8 SK |
255 | |
256 | for (i = 0; i < len; i += 4) { | |
257 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
258 | data++; | |
259 | } | |
260 | ||
bc2481f3 | 261 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 262 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 263 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 264 | |
22509ec8 | 265 | I915_WRITE(reg, val); |
90b107c8 SK |
266 | } |
267 | ||
8c5f5f7c ED |
268 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
269 | struct dip_infoframe *frame) | |
270 | { | |
271 | /* Not implemented yet, so avoid doing anything at all. | |
272 | * This is the placeholder for Paulo Zanoni's infoframe writing patch | |
273 | */ | |
274 | DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n"); | |
275 | ||
276 | return; | |
277 | ||
278 | } | |
279 | ||
45187ace JB |
280 | static void intel_set_infoframe(struct drm_encoder *encoder, |
281 | struct dip_infoframe *frame) | |
282 | { | |
283 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
284 | ||
285 | if (!intel_hdmi->has_hdmi_sink) | |
286 | return; | |
287 | ||
288 | intel_dip_infoframe_csum(frame); | |
289 | intel_hdmi->write_infoframe(encoder, frame); | |
290 | } | |
291 | ||
f5bbfca3 | 292 | void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 293 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
294 | { |
295 | struct dip_infoframe avi_if = { | |
296 | .type = DIP_TYPE_AVI, | |
297 | .ver = DIP_VERSION_AVI, | |
298 | .len = DIP_LEN_AVI, | |
299 | }; | |
300 | ||
c846b619 PZ |
301 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
302 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
303 | ||
45187ace | 304 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
305 | } |
306 | ||
f5bbfca3 | 307 | void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
308 | { |
309 | struct dip_infoframe spd_if; | |
310 | ||
311 | memset(&spd_if, 0, sizeof(spd_if)); | |
312 | spd_if.type = DIP_TYPE_SPD; | |
313 | spd_if.ver = DIP_VERSION_SPD; | |
314 | spd_if.len = DIP_LEN_SPD; | |
315 | strcpy(spd_if.body.spd.vn, "Intel"); | |
316 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
317 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
318 | ||
319 | intel_set_infoframe(encoder, &spd_if); | |
320 | } | |
321 | ||
7d57382e EA |
322 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
323 | struct drm_display_mode *mode, | |
324 | struct drm_display_mode *adjusted_mode) | |
325 | { | |
326 | struct drm_device *dev = encoder->dev; | |
327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
328 | struct drm_crtc *crtc = encoder->crtc; | |
329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 330 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
331 | u32 sdvox; |
332 | ||
b599c0bc | 333 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
334 | if (!HAS_PCH_SPLIT(dev)) |
335 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
336 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
337 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
338 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
339 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 340 | |
020f6704 JB |
341 | if (intel_crtc->bpp > 24) |
342 | sdvox |= COLOR_FORMAT_12bpc; | |
343 | else | |
344 | sdvox |= COLOR_FORMAT_8bpc; | |
345 | ||
2e3d6006 ZW |
346 | /* Required on CPT */ |
347 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
348 | sdvox |= HDMI_MODE_SELECT; | |
349 | ||
3c17fe4b | 350 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
351 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
352 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 353 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 354 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 355 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 356 | } |
7d57382e | 357 | |
75770564 JB |
358 | if (HAS_PCH_CPT(dev)) |
359 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
360 | else if (intel_crtc->pipe == 1) | |
361 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 362 | |
ea5b213a CW |
363 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
364 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 365 | |
c846b619 | 366 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 367 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
368 | } |
369 | ||
370 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
371 | { | |
372 | struct drm_device *dev = encoder->dev; | |
373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 374 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 375 | u32 temp; |
2deed761 WF |
376 | u32 enable_bits = SDVO_ENABLE; |
377 | ||
378 | if (intel_hdmi->has_audio) | |
379 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 380 | |
ea5b213a | 381 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
382 | |
383 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
384 | * we do this anyway which shows more stable in testing. | |
385 | */ | |
c619eed4 | 386 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
387 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
388 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
389 | } |
390 | ||
391 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 392 | temp &= ~enable_bits; |
7d57382e | 393 | } else { |
2deed761 | 394 | temp |= enable_bits; |
7d57382e | 395 | } |
d8a2d0e0 | 396 | |
ea5b213a CW |
397 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
398 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
399 | |
400 | /* HW workaround, need to write this twice for issue that may result | |
401 | * in first write getting masked. | |
402 | */ | |
c619eed4 | 403 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
404 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
405 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 406 | } |
7d57382e EA |
407 | } |
408 | ||
7d57382e EA |
409 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
410 | struct drm_display_mode *mode) | |
411 | { | |
412 | if (mode->clock > 165000) | |
413 | return MODE_CLOCK_HIGH; | |
414 | if (mode->clock < 20000) | |
5cbba41d | 415 | return MODE_CLOCK_LOW; |
7d57382e EA |
416 | |
417 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
418 | return MODE_NO_DBLESCAN; | |
419 | ||
420 | return MODE_OK; | |
421 | } | |
422 | ||
423 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
424 | struct drm_display_mode *mode, | |
425 | struct drm_display_mode *adjusted_mode) | |
426 | { | |
427 | return true; | |
428 | } | |
429 | ||
aa93d632 | 430 | static enum drm_connector_status |
930a9e28 | 431 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 432 | { |
df0e9248 | 433 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
434 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
435 | struct edid *edid; | |
aa93d632 | 436 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 437 | |
ea5b213a | 438 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 439 | intel_hdmi->has_audio = false; |
f899fc64 | 440 | edid = drm_get_edid(connector, |
3bd7d909 DK |
441 | intel_gmbus_get_adapter(dev_priv, |
442 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 443 | |
aa93d632 | 444 | if (edid) { |
be9f1c4f | 445 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 446 | status = connector_status_connected; |
b1d7e4b4 WF |
447 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
448 | intel_hdmi->has_hdmi_sink = | |
449 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 450 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 451 | } |
674e2d08 | 452 | connector->display_info.raw_edid = NULL; |
aa93d632 | 453 | kfree(edid); |
9dff6af8 | 454 | } |
30ad48b7 | 455 | |
55b7d6e8 | 456 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
457 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
458 | intel_hdmi->has_audio = | |
459 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
460 | } |
461 | ||
2ded9e27 | 462 | return status; |
7d57382e EA |
463 | } |
464 | ||
465 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
466 | { | |
df0e9248 | 467 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 468 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
469 | |
470 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
471 | * we can send audio to it. | |
472 | */ | |
473 | ||
f899fc64 | 474 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
475 | intel_gmbus_get_adapter(dev_priv, |
476 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
477 | } |
478 | ||
1aad7ac0 CW |
479 | static bool |
480 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
481 | { | |
482 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
483 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
484 | struct edid *edid; | |
485 | bool has_audio = false; | |
486 | ||
487 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
488 | intel_gmbus_get_adapter(dev_priv, |
489 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
490 | if (edid) { |
491 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
492 | has_audio = drm_detect_monitor_audio(edid); | |
493 | ||
494 | connector->display_info.raw_edid = NULL; | |
495 | kfree(edid); | |
496 | } | |
497 | ||
498 | return has_audio; | |
499 | } | |
500 | ||
55b7d6e8 CW |
501 | static int |
502 | intel_hdmi_set_property(struct drm_connector *connector, | |
503 | struct drm_property *property, | |
504 | uint64_t val) | |
505 | { | |
506 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 507 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
508 | int ret; |
509 | ||
510 | ret = drm_connector_property_set_value(connector, property, val); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
3f43c48d | 514 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 515 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
516 | bool has_audio; |
517 | ||
518 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
519 | return 0; |
520 | ||
1aad7ac0 | 521 | intel_hdmi->force_audio = i; |
55b7d6e8 | 522 | |
b1d7e4b4 | 523 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
524 | has_audio = intel_hdmi_detect_audio(connector); |
525 | else | |
b1d7e4b4 | 526 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 527 | |
b1d7e4b4 WF |
528 | if (i == HDMI_AUDIO_OFF_DVI) |
529 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 530 | |
1aad7ac0 | 531 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
532 | goto done; |
533 | } | |
534 | ||
e953fd7b CW |
535 | if (property == dev_priv->broadcast_rgb_property) { |
536 | if (val == !!intel_hdmi->color_range) | |
537 | return 0; | |
538 | ||
539 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
540 | goto done; | |
541 | } | |
542 | ||
55b7d6e8 CW |
543 | return -EINVAL; |
544 | ||
545 | done: | |
546 | if (intel_hdmi->base.base.crtc) { | |
547 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
548 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
549 | crtc->x, crtc->y, | |
550 | crtc->fb); | |
551 | } | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
7d57382e EA |
556 | static void intel_hdmi_destroy(struct drm_connector *connector) |
557 | { | |
7d57382e EA |
558 | drm_sysfs_connector_remove(connector); |
559 | drm_connector_cleanup(connector); | |
674e2d08 | 560 | kfree(connector); |
7d57382e EA |
561 | } |
562 | ||
72662e10 ED |
563 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
564 | .dpms = intel_ddi_dpms, | |
565 | .mode_fixup = intel_hdmi_mode_fixup, | |
566 | .prepare = intel_encoder_prepare, | |
567 | .mode_set = intel_ddi_mode_set, | |
568 | .commit = intel_encoder_commit, | |
569 | }; | |
570 | ||
7d57382e EA |
571 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
572 | .dpms = intel_hdmi_dpms, | |
573 | .mode_fixup = intel_hdmi_mode_fixup, | |
574 | .prepare = intel_encoder_prepare, | |
575 | .mode_set = intel_hdmi_mode_set, | |
576 | .commit = intel_encoder_commit, | |
577 | }; | |
578 | ||
579 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 580 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
581 | .detect = intel_hdmi_detect, |
582 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 583 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
584 | .destroy = intel_hdmi_destroy, |
585 | }; | |
586 | ||
587 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
588 | .get_modes = intel_hdmi_get_modes, | |
589 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 590 | .best_encoder = intel_best_encoder, |
7d57382e EA |
591 | }; |
592 | ||
7d57382e | 593 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 594 | .destroy = intel_encoder_destroy, |
7d57382e EA |
595 | }; |
596 | ||
55b7d6e8 CW |
597 | static void |
598 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
599 | { | |
3f43c48d | 600 | intel_attach_force_audio_property(connector); |
e953fd7b | 601 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
602 | } |
603 | ||
7d57382e EA |
604 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
605 | { | |
606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
607 | struct drm_connector *connector; | |
21d40d37 | 608 | struct intel_encoder *intel_encoder; |
674e2d08 | 609 | struct intel_connector *intel_connector; |
ea5b213a | 610 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 611 | int i; |
7d57382e | 612 | |
ea5b213a CW |
613 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
614 | if (!intel_hdmi) | |
7d57382e | 615 | return; |
674e2d08 ZW |
616 | |
617 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
618 | if (!intel_connector) { | |
ea5b213a | 619 | kfree(intel_hdmi); |
674e2d08 ZW |
620 | return; |
621 | } | |
622 | ||
ea5b213a | 623 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
624 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
625 | DRM_MODE_ENCODER_TMDS); | |
626 | ||
674e2d08 | 627 | connector = &intel_connector->base; |
7d57382e | 628 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 629 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
630 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
631 | ||
21d40d37 | 632 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 633 | |
eb1f8e4f | 634 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 635 | connector->interlace_allowed = 1; |
7d57382e | 636 | connector->doublescan_allowed = 0; |
27f8227b | 637 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
638 | |
639 | /* Set up the DDC bus. */ | |
f8aed700 | 640 | if (sdvox_reg == SDVOB) { |
21d40d37 | 641 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 642 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 643 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 644 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 645 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 646 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 647 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 648 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 649 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 650 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 651 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 652 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 653 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 654 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 655 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 656 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 657 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 658 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 659 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
660 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
661 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
662 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
663 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
664 | intel_hdmi->ddi_port = PORT_B; | |
665 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
666 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
667 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
668 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
669 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
670 | intel_hdmi->ddi_port = PORT_C; | |
671 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
672 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
673 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
674 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
675 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
676 | intel_hdmi->ddi_port = PORT_D; | |
677 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
678 | } else { |
679 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
680 | * in a way that we should let the kernel know about it */ | |
681 | BUG(); | |
f8aed700 | 682 | } |
7d57382e | 683 | |
ea5b213a | 684 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 685 | |
64a8fc01 | 686 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 687 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
64a8fc01 | 688 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
689 | } else if (IS_VALLEYVIEW(dev)) { |
690 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
691 | for_each_pipe(i) | |
692 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
693 | } else if (IS_HASWELL(dev)) { |
694 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
695 | * just doing the minimal required for HDMI to work at this stage. | |
696 | */ | |
697 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
698 | for_each_pipe(i) | |
699 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
700 | } else if (HAS_PCH_IBX(dev)) { |
701 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
702 | for_each_pipe(i) | |
703 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
704 | } else { | |
705 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
706 | for_each_pipe(i) |
707 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
708 | } | |
45187ace | 709 | |
72662e10 ED |
710 | if (IS_HASWELL(dev)) |
711 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
712 | else | |
713 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 714 | |
55b7d6e8 CW |
715 | intel_hdmi_add_properties(intel_hdmi, connector); |
716 | ||
df0e9248 | 717 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
718 | drm_sysfs_connector_add(connector); |
719 | ||
720 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
721 | * 0xd. Failure to do so will result in spurious interrupts being | |
722 | * generated on the port when a cable is not attached. | |
723 | */ | |
724 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
725 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
726 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
727 | } | |
7d57382e | 728 | } |