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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
40 | struct intel_hdmi_priv { | |
41 | u32 sdvox_reg; | |
9dff6af8 | 42 | bool has_hdmi_sink; |
7d57382e EA |
43 | }; |
44 | ||
45 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, | |
46 | struct drm_display_mode *mode, | |
47 | struct drm_display_mode *adjusted_mode) | |
48 | { | |
49 | struct drm_device *dev = encoder->dev; | |
50 | struct drm_i915_private *dev_priv = dev->dev_private; | |
51 | struct drm_crtc *crtc = encoder->crtc; | |
52 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
21d40d37 EA |
53 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
54 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | |
7d57382e EA |
55 | u32 sdvox; |
56 | ||
57 | sdvox = SDVO_ENCODING_HDMI | | |
58 | SDVO_BORDER_ENABLE | | |
59 | SDVO_VSYNC_ACTIVE_HIGH | | |
56d21b07 | 60 | SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e EA |
61 | |
62 | if (hdmi_priv->has_hdmi_sink) | |
63 | sdvox |= SDVO_AUDIO_ENABLE; | |
64 | ||
0f229062 ZW |
65 | if (intel_crtc->pipe == 1) { |
66 | if (HAS_PCH_CPT(dev)) | |
67 | sdvox |= PORT_TRANS_B_SEL_CPT; | |
68 | else | |
69 | sdvox |= SDVO_PIPE_B_SELECT; | |
70 | } | |
7d57382e EA |
71 | |
72 | I915_WRITE(hdmi_priv->sdvox_reg, sdvox); | |
73 | POSTING_READ(hdmi_priv->sdvox_reg); | |
74 | } | |
75 | ||
76 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
77 | { | |
78 | struct drm_device *dev = encoder->dev; | |
79 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 EA |
80 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
81 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | |
7d57382e EA |
82 | u32 temp; |
83 | ||
d8a2d0e0 ZW |
84 | temp = I915_READ(hdmi_priv->sdvox_reg); |
85 | ||
86 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
87 | * we do this anyway which shows more stable in testing. | |
88 | */ | |
c619eed4 | 89 | if (HAS_PCH_SPLIT(dev)) { |
7d57382e | 90 | I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); |
d8a2d0e0 ZW |
91 | POSTING_READ(hdmi_priv->sdvox_reg); |
92 | } | |
93 | ||
94 | if (mode != DRM_MODE_DPMS_ON) { | |
95 | temp &= ~SDVO_ENABLE; | |
7d57382e | 96 | } else { |
d8a2d0e0 | 97 | temp |= SDVO_ENABLE; |
7d57382e | 98 | } |
d8a2d0e0 ZW |
99 | |
100 | I915_WRITE(hdmi_priv->sdvox_reg, temp); | |
7d57382e | 101 | POSTING_READ(hdmi_priv->sdvox_reg); |
d8a2d0e0 ZW |
102 | |
103 | /* HW workaround, need to write this twice for issue that may result | |
104 | * in first write getting masked. | |
105 | */ | |
c619eed4 | 106 | if (HAS_PCH_SPLIT(dev)) { |
d8a2d0e0 ZW |
107 | I915_WRITE(hdmi_priv->sdvox_reg, temp); |
108 | POSTING_READ(hdmi_priv->sdvox_reg); | |
109 | } | |
7d57382e EA |
110 | } |
111 | ||
7d57382e EA |
112 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
113 | struct drm_display_mode *mode) | |
114 | { | |
115 | if (mode->clock > 165000) | |
116 | return MODE_CLOCK_HIGH; | |
117 | if (mode->clock < 20000) | |
118 | return MODE_CLOCK_HIGH; | |
119 | ||
120 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
121 | return MODE_NO_DBLESCAN; | |
122 | ||
123 | return MODE_OK; | |
124 | } | |
125 | ||
126 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
127 | struct drm_display_mode *mode, | |
128 | struct drm_display_mode *adjusted_mode) | |
129 | { | |
130 | return true; | |
131 | } | |
132 | ||
aa93d632 | 133 | static enum drm_connector_status |
2ded9e27 | 134 | intel_hdmi_detect(struct drm_connector *connector) |
9dff6af8 | 135 | { |
674e2d08 ZW |
136 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
137 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
21d40d37 | 138 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; |
9dff6af8 | 139 | struct edid *edid = NULL; |
aa93d632 | 140 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 141 | |
2ded9e27 | 142 | hdmi_priv->has_hdmi_sink = false; |
674e2d08 | 143 | edid = drm_get_edid(connector, |
21d40d37 | 144 | intel_encoder->ddc_bus); |
2ded9e27 | 145 | |
aa93d632 | 146 | if (edid) { |
be9f1c4f | 147 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 KP |
148 | status = connector_status_connected; |
149 | hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); | |
150 | } | |
674e2d08 | 151 | connector->display_info.raw_edid = NULL; |
aa93d632 | 152 | kfree(edid); |
9dff6af8 | 153 | } |
30ad48b7 | 154 | |
2ded9e27 | 155 | return status; |
7d57382e EA |
156 | } |
157 | ||
158 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
159 | { | |
674e2d08 ZW |
160 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
161 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
7d57382e EA |
162 | |
163 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
164 | * we can send audio to it. | |
165 | */ | |
166 | ||
335af9a2 | 167 | return intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
7d57382e EA |
168 | } |
169 | ||
170 | static void intel_hdmi_destroy(struct drm_connector *connector) | |
171 | { | |
7d57382e EA |
172 | drm_sysfs_connector_remove(connector); |
173 | drm_connector_cleanup(connector); | |
674e2d08 | 174 | kfree(connector); |
7d57382e EA |
175 | } |
176 | ||
177 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
178 | .dpms = intel_hdmi_dpms, | |
179 | .mode_fixup = intel_hdmi_mode_fixup, | |
180 | .prepare = intel_encoder_prepare, | |
181 | .mode_set = intel_hdmi_mode_set, | |
182 | .commit = intel_encoder_commit, | |
183 | }; | |
184 | ||
185 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 186 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
187 | .detect = intel_hdmi_detect, |
188 | .fill_modes = drm_helper_probe_single_connector_modes, | |
189 | .destroy = intel_hdmi_destroy, | |
190 | }; | |
191 | ||
192 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
193 | .get_modes = intel_hdmi_get_modes, | |
194 | .mode_valid = intel_hdmi_mode_valid, | |
674e2d08 | 195 | .best_encoder = intel_attached_encoder, |
7d57382e EA |
196 | }; |
197 | ||
198 | static void intel_hdmi_enc_destroy(struct drm_encoder *encoder) | |
199 | { | |
674e2d08 ZW |
200 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
201 | ||
202 | if (intel_encoder->i2c_bus) | |
203 | intel_i2c_destroy(intel_encoder->i2c_bus); | |
7d57382e | 204 | drm_encoder_cleanup(encoder); |
674e2d08 | 205 | kfree(intel_encoder); |
7d57382e EA |
206 | } |
207 | ||
208 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { | |
209 | .destroy = intel_hdmi_enc_destroy, | |
210 | }; | |
211 | ||
7d57382e EA |
212 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
213 | { | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | struct drm_connector *connector; | |
21d40d37 | 216 | struct intel_encoder *intel_encoder; |
674e2d08 | 217 | struct intel_connector *intel_connector; |
7d57382e EA |
218 | struct intel_hdmi_priv *hdmi_priv; |
219 | ||
21d40d37 | 220 | intel_encoder = kcalloc(sizeof(struct intel_encoder) + |
7d57382e | 221 | sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); |
21d40d37 | 222 | if (!intel_encoder) |
7d57382e | 223 | return; |
674e2d08 ZW |
224 | |
225 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
226 | if (!intel_connector) { | |
227 | kfree(intel_encoder); | |
228 | return; | |
229 | } | |
230 | ||
21d40d37 | 231 | hdmi_priv = (struct intel_hdmi_priv *)(intel_encoder + 1); |
7d57382e | 232 | |
674e2d08 | 233 | connector = &intel_connector->base; |
7d57382e | 234 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 235 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
236 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
237 | ||
21d40d37 | 238 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 239 | |
eb1f8e4f | 240 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e EA |
241 | connector->interlace_allowed = 0; |
242 | connector->doublescan_allowed = 0; | |
21d40d37 | 243 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
7d57382e EA |
244 | |
245 | /* Set up the DDC bus. */ | |
f8aed700 | 246 | if (sdvox_reg == SDVOB) { |
21d40d37 EA |
247 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
248 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); | |
b01f2c3a | 249 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 250 | } else if (sdvox_reg == SDVOC) { |
21d40d37 EA |
251 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
252 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); | |
b01f2c3a | 253 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 254 | } else if (sdvox_reg == HDMIB) { |
21d40d37 EA |
255 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
256 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, | |
30ad48b7 | 257 | "HDMIB"); |
b01f2c3a | 258 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 259 | } else if (sdvox_reg == HDMIC) { |
21d40d37 EA |
260 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
261 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, | |
30ad48b7 | 262 | "HDMIC"); |
b01f2c3a | 263 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 264 | } else if (sdvox_reg == HDMID) { |
21d40d37 EA |
265 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
266 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, | |
30ad48b7 | 267 | "HDMID"); |
b01f2c3a | 268 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 269 | } |
21d40d37 | 270 | if (!intel_encoder->ddc_bus) |
7d57382e EA |
271 | goto err_connector; |
272 | ||
273 | hdmi_priv->sdvox_reg = sdvox_reg; | |
21d40d37 | 274 | intel_encoder->dev_priv = hdmi_priv; |
7d57382e | 275 | |
21d40d37 | 276 | drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs, |
7d57382e | 277 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 278 | drm_encoder_helper_add(&intel_encoder->enc, &intel_hdmi_helper_funcs); |
7d57382e | 279 | |
674e2d08 | 280 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 281 | &intel_encoder->enc); |
7d57382e EA |
282 | drm_sysfs_connector_add(connector); |
283 | ||
284 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
285 | * 0xd. Failure to do so will result in spurious interrupts being | |
286 | * generated on the port when a cable is not attached. | |
287 | */ | |
288 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
289 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
290 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
291 | } | |
292 | ||
293 | return; | |
294 | ||
295 | err_connector: | |
296 | drm_connector_cleanup(connector); | |
21d40d37 | 297 | kfree(intel_encoder); |
674e2d08 | 298 | kfree(intel_connector); |
7d57382e EA |
299 | |
300 | return; | |
301 | } |