Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
fdf1250a | 169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 170 | enum hdmi_infoframe_type type, |
fff63867 | 171 | const void *frame, ssize_t len) |
fdf1250a | 172 | { |
fff63867 | 173 | const uint32_t *data = frame; |
fdf1250a PZ |
174 | struct drm_device *dev = encoder->dev; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 176 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 177 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
178 | u32 val = I915_READ(reg); |
179 | ||
822974ae PZ |
180 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
181 | ||
fdf1250a | 182 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 183 | val |= g4x_infoframe_index(type); |
fdf1250a | 184 | |
178f736a | 185 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
186 | |
187 | I915_WRITE(reg, val); | |
188 | ||
9d9740f0 | 189 | mmiowb(); |
fdf1250a PZ |
190 | for (i = 0; i < len; i += 4) { |
191 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
192 | data++; | |
193 | } | |
adf00b26 PZ |
194 | /* Write every possible data byte to force correct ECC calculation. */ |
195 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 197 | mmiowb(); |
fdf1250a | 198 | |
178f736a | 199 | val |= g4x_infoframe_enable(type); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
9d9740f0 | 204 | POSTING_READ(reg); |
fdf1250a PZ |
205 | } |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 208 | enum hdmi_infoframe_type type, |
fff63867 | 209 | const void *frame, ssize_t len) |
b055c8f3 | 210 | { |
fff63867 | 211 | const uint32_t *data = frame; |
b055c8f3 JB |
212 | struct drm_device *dev = encoder->dev; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 214 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 215 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 | 217 | |
822974ae PZ |
218 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 221 | val |= g4x_infoframe_index(type); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
178f736a DL |
225 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
226 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 227 | |
22509ec8 | 228 | I915_WRITE(reg, val); |
45187ace | 229 | |
9d9740f0 | 230 | mmiowb(); |
45187ace | 231 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
233 | data++; | |
234 | } | |
adf00b26 PZ |
235 | /* Write every possible data byte to force correct ECC calculation. */ |
236 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
237 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 238 | mmiowb(); |
b055c8f3 | 239 | |
178f736a | 240 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
9d9740f0 | 245 | POSTING_READ(reg); |
45187ace | 246 | } |
90b107c8 SK |
247 | |
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
90b107c8 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
90b107c8 SK |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 256 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 | 258 | |
822974ae PZ |
259 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 262 | val |= g4x_infoframe_index(type); |
22509ec8 | 263 | |
178f736a | 264 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 | 267 | |
9d9740f0 | 268 | mmiowb(); |
90b107c8 SK |
269 | for (i = 0; i < len; i += 4) { |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
90b107c8 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
90b107c8 SK |
284 | } |
285 | ||
8c5f5f7c | 286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 287 | enum hdmi_infoframe_type type, |
fff63867 | 288 | const void *frame, ssize_t len) |
8c5f5f7c | 289 | { |
fff63867 | 290 | const uint32_t *data = frame; |
2da8af54 PZ |
291 | struct drm_device *dev = encoder->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 294 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
295 | u32 data_reg; |
296 | int i; | |
2da8af54 | 297 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 298 | |
178f736a | 299 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
300 | intel_crtc->config.cpu_transcoder, |
301 | dev_priv); | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
178f736a | 305 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
306 | I915_WRITE(ctl_reg, val); |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
178f736a | 318 | val |= hsw_infoframe_enable(type); |
2da8af54 | 319 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
5adaea79 DL |
323 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
327 | * used for both technologies. | |
328 | * | |
329 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
330 | * DW1: DB3 | DB2 | DB1 | DB0 | |
331 | * DW2: DB7 | DB6 | DB5 | DB4 | |
332 | * DW3: ... | |
333 | * | |
334 | * (HB is Header Byte, DB is Data Byte) | |
335 | * | |
336 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
337 | * trick them by giving an offset into the buffer and moving back the header | |
338 | * bytes by one. | |
339 | */ | |
9198ee5b DL |
340 | static void intel_write_infoframe(struct drm_encoder *encoder, |
341 | union hdmi_infoframe *frame) | |
45187ace JB |
342 | { |
343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
344 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
345 | ssize_t len; | |
45187ace | 346 | |
5adaea79 DL |
347 | /* see comment above for the reason for this offset */ |
348 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
349 | if (len < 0) | |
350 | return; | |
351 | ||
352 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
353 | buffer[0] = buffer[1]; | |
354 | buffer[1] = buffer[2]; | |
355 | buffer[2] = buffer[3]; | |
356 | buffer[3] = 0; | |
357 | len++; | |
45187ace | 358 | |
5adaea79 | 359 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
360 | } |
361 | ||
687f4d06 | 362 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 363 | struct drm_display_mode *adjusted_mode) |
45187ace | 364 | { |
abedc077 | 365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 366 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
367 | union hdmi_infoframe frame; |
368 | int ret; | |
45187ace | 369 | |
5adaea79 DL |
370 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
371 | adjusted_mode); | |
372 | if (ret < 0) { | |
373 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
374 | return; | |
375 | } | |
c846b619 | 376 | |
abedc077 | 377 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 378 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
379 | frame.avi.quantization_range = |
380 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 381 | else |
5adaea79 DL |
382 | frame.avi.quantization_range = |
383 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
384 | } |
385 | ||
9198ee5b | 386 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
387 | } |
388 | ||
687f4d06 | 389 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 390 | { |
5adaea79 DL |
391 | union hdmi_infoframe frame; |
392 | int ret; | |
393 | ||
394 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
395 | if (ret < 0) { | |
396 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
397 | return; | |
398 | } | |
c0864cb3 | 399 | |
5adaea79 | 400 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 401 | |
9198ee5b | 402 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
403 | } |
404 | ||
c8bb75af LD |
405 | static void |
406 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
407 | struct drm_display_mode *adjusted_mode) | |
408 | { | |
409 | union hdmi_infoframe frame; | |
410 | int ret; | |
411 | ||
412 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
413 | adjusted_mode); | |
414 | if (ret < 0) | |
415 | return; | |
416 | ||
417 | intel_write_infoframe(encoder, &frame); | |
418 | } | |
419 | ||
687f4d06 | 420 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 421 | bool enable, |
687f4d06 PZ |
422 | struct drm_display_mode *adjusted_mode) |
423 | { | |
0c14c7f9 | 424 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
425 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
426 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
427 | u32 reg = VIDEO_DIP_CTL; |
428 | u32 val = I915_READ(reg); | |
822cdc52 | 429 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 430 | |
afba0188 DV |
431 | assert_hdmi_port_disabled(intel_hdmi); |
432 | ||
0c14c7f9 PZ |
433 | /* If the registers were not initialized yet, they might be zeroes, |
434 | * which means we're selecting the AVI DIP and we're setting its | |
435 | * frequency to once. This seems to really confuse the HW and make | |
436 | * things stop working (the register spec says the AVI always needs to | |
437 | * be sent every VSync). So here we avoid writing to the register more | |
438 | * than we need and also explicitly select the AVI DIP and explicitly | |
439 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
440 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
441 | * either. */ | |
442 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
443 | ||
6897b4b5 | 444 | if (!enable) { |
0c14c7f9 PZ |
445 | if (!(val & VIDEO_DIP_ENABLE)) |
446 | return; | |
447 | val &= ~VIDEO_DIP_ENABLE; | |
448 | I915_WRITE(reg, val); | |
9d9740f0 | 449 | POSTING_READ(reg); |
0c14c7f9 PZ |
450 | return; |
451 | } | |
452 | ||
72b78c9d PZ |
453 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
454 | if (val & VIDEO_DIP_ENABLE) { | |
455 | val &= ~VIDEO_DIP_ENABLE; | |
456 | I915_WRITE(reg, val); | |
9d9740f0 | 457 | POSTING_READ(reg); |
72b78c9d PZ |
458 | } |
459 | val &= ~VIDEO_DIP_PORT_MASK; | |
460 | val |= port; | |
461 | } | |
462 | ||
822974ae | 463 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 464 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 465 | |
f278d972 | 466 | I915_WRITE(reg, val); |
9d9740f0 | 467 | POSTING_READ(reg); |
f278d972 | 468 | |
687f4d06 PZ |
469 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
470 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 471 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
472 | } |
473 | ||
474 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 475 | bool enable, |
687f4d06 PZ |
476 | struct drm_display_mode *adjusted_mode) |
477 | { | |
0c14c7f9 PZ |
478 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
479 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
480 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
481 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
482 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
483 | u32 val = I915_READ(reg); | |
822cdc52 | 484 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 485 | |
afba0188 DV |
486 | assert_hdmi_port_disabled(intel_hdmi); |
487 | ||
0c14c7f9 PZ |
488 | /* See the big comment in g4x_set_infoframes() */ |
489 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
490 | ||
6897b4b5 | 491 | if (!enable) { |
0c14c7f9 PZ |
492 | if (!(val & VIDEO_DIP_ENABLE)) |
493 | return; | |
494 | val &= ~VIDEO_DIP_ENABLE; | |
495 | I915_WRITE(reg, val); | |
9d9740f0 | 496 | POSTING_READ(reg); |
0c14c7f9 PZ |
497 | return; |
498 | } | |
499 | ||
72b78c9d PZ |
500 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
501 | if (val & VIDEO_DIP_ENABLE) { | |
502 | val &= ~VIDEO_DIP_ENABLE; | |
503 | I915_WRITE(reg, val); | |
9d9740f0 | 504 | POSTING_READ(reg); |
72b78c9d PZ |
505 | } |
506 | val &= ~VIDEO_DIP_PORT_MASK; | |
507 | val |= port; | |
508 | } | |
509 | ||
822974ae | 510 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
511 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
512 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 513 | |
f278d972 | 514 | I915_WRITE(reg, val); |
9d9740f0 | 515 | POSTING_READ(reg); |
f278d972 | 516 | |
687f4d06 PZ |
517 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
518 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 519 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
520 | } |
521 | ||
522 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 523 | bool enable, |
687f4d06 PZ |
524 | struct drm_display_mode *adjusted_mode) |
525 | { | |
0c14c7f9 PZ |
526 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
527 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
528 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
529 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
530 | u32 val = I915_READ(reg); | |
531 | ||
afba0188 DV |
532 | assert_hdmi_port_disabled(intel_hdmi); |
533 | ||
0c14c7f9 PZ |
534 | /* See the big comment in g4x_set_infoframes() */ |
535 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
536 | ||
6897b4b5 | 537 | if (!enable) { |
0c14c7f9 PZ |
538 | if (!(val & VIDEO_DIP_ENABLE)) |
539 | return; | |
540 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
541 | I915_WRITE(reg, val); | |
9d9740f0 | 542 | POSTING_READ(reg); |
0c14c7f9 PZ |
543 | return; |
544 | } | |
545 | ||
822974ae PZ |
546 | /* Set both together, unset both together: see the spec. */ |
547 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
548 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
549 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
550 | |
551 | I915_WRITE(reg, val); | |
9d9740f0 | 552 | POSTING_READ(reg); |
822974ae | 553 | |
687f4d06 PZ |
554 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
555 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 556 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
557 | } |
558 | ||
559 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 560 | bool enable, |
687f4d06 PZ |
561 | struct drm_display_mode *adjusted_mode) |
562 | { | |
0c14c7f9 | 563 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 564 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
565 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
566 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
567 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
568 | u32 val = I915_READ(reg); | |
6a2b8021 | 569 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 570 | |
afba0188 DV |
571 | assert_hdmi_port_disabled(intel_hdmi); |
572 | ||
0c14c7f9 PZ |
573 | /* See the big comment in g4x_set_infoframes() */ |
574 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
575 | ||
6897b4b5 | 576 | if (!enable) { |
0c14c7f9 PZ |
577 | if (!(val & VIDEO_DIP_ENABLE)) |
578 | return; | |
579 | val &= ~VIDEO_DIP_ENABLE; | |
580 | I915_WRITE(reg, val); | |
9d9740f0 | 581 | POSTING_READ(reg); |
0c14c7f9 PZ |
582 | return; |
583 | } | |
584 | ||
6a2b8021 JB |
585 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
586 | if (val & VIDEO_DIP_ENABLE) { | |
587 | val &= ~VIDEO_DIP_ENABLE; | |
588 | I915_WRITE(reg, val); | |
589 | POSTING_READ(reg); | |
590 | } | |
591 | val &= ~VIDEO_DIP_PORT_MASK; | |
592 | val |= port; | |
593 | } | |
594 | ||
822974ae | 595 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
596 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
597 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
598 | |
599 | I915_WRITE(reg, val); | |
9d9740f0 | 600 | POSTING_READ(reg); |
822974ae | 601 | |
687f4d06 PZ |
602 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
603 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 604 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
605 | } |
606 | ||
607 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 608 | bool enable, |
687f4d06 PZ |
609 | struct drm_display_mode *adjusted_mode) |
610 | { | |
0c14c7f9 PZ |
611 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
612 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
613 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 614 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 615 | u32 val = I915_READ(reg); |
0c14c7f9 | 616 | |
afba0188 DV |
617 | assert_hdmi_port_disabled(intel_hdmi); |
618 | ||
6897b4b5 | 619 | if (!enable) { |
0c14c7f9 | 620 | I915_WRITE(reg, 0); |
9d9740f0 | 621 | POSTING_READ(reg); |
0c14c7f9 PZ |
622 | return; |
623 | } | |
624 | ||
0dd87d20 PZ |
625 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
626 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
627 | ||
628 | I915_WRITE(reg, val); | |
9d9740f0 | 629 | POSTING_READ(reg); |
0dd87d20 | 630 | |
687f4d06 PZ |
631 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
632 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 633 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
634 | } |
635 | ||
4cde8a21 | 636 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 637 | { |
c59423a3 | 638 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 639 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
640 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
641 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
642 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 643 | u32 hdmi_val; |
7d57382e | 644 | |
b242b7f7 | 645 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 646 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 647 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 648 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 649 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 650 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 651 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 652 | |
c59423a3 | 653 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 654 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 655 | else |
4f3a8bc7 | 656 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 657 | |
6897b4b5 | 658 | if (crtc->config.has_hdmi_sink) |
dc0fa718 | 659 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 660 | |
9ed109a7 | 661 | if (crtc->config.has_audio) { |
6897b4b5 | 662 | WARN_ON(!crtc->config.has_hdmi_sink); |
e0dac65e | 663 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 664 | pipe_name(crtc->pipe)); |
b242b7f7 | 665 | hdmi_val |= SDVO_AUDIO_ENABLE; |
c59423a3 | 666 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 667 | } |
7d57382e | 668 | |
75770564 | 669 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 670 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
671 | else if (IS_CHERRYVIEW(dev)) |
672 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 673 | else |
c59423a3 | 674 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 675 | |
b242b7f7 PZ |
676 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
677 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
678 | } |
679 | ||
85234cdc DV |
680 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
681 | enum pipe *pipe) | |
7d57382e | 682 | { |
85234cdc | 683 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 684 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 685 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 686 | enum intel_display_power_domain power_domain; |
85234cdc DV |
687 | u32 tmp; |
688 | ||
6d129bea ID |
689 | power_domain = intel_display_port_power_domain(encoder); |
690 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
691 | return false; | |
692 | ||
b242b7f7 | 693 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
694 | |
695 | if (!(tmp & SDVO_ENABLE)) | |
696 | return false; | |
697 | ||
698 | if (HAS_PCH_CPT(dev)) | |
699 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
700 | else | |
701 | *pipe = PORT_TO_PIPE(tmp); | |
702 | ||
703 | return true; | |
704 | } | |
705 | ||
045ac3b5 JB |
706 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
707 | struct intel_crtc_config *pipe_config) | |
708 | { | |
709 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
710 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
711 | u32 tmp, flags = 0; | |
18442d08 | 712 | int dotclock; |
045ac3b5 JB |
713 | |
714 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
715 | ||
716 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
717 | flags |= DRM_MODE_FLAG_PHSYNC; | |
718 | else | |
719 | flags |= DRM_MODE_FLAG_NHSYNC; | |
720 | ||
721 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
722 | flags |= DRM_MODE_FLAG_PVSYNC; | |
723 | else | |
724 | flags |= DRM_MODE_FLAG_NVSYNC; | |
725 | ||
6897b4b5 DV |
726 | if (tmp & HDMI_MODE_SELECT_HDMI) |
727 | pipe_config->has_hdmi_sink = true; | |
728 | ||
9ed109a7 DV |
729 | if (tmp & HDMI_MODE_SELECT_HDMI) |
730 | pipe_config->has_audio = true; | |
731 | ||
045ac3b5 | 732 | pipe_config->adjusted_mode.flags |= flags; |
18442d08 VS |
733 | |
734 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
735 | dotclock = pipe_config->port_clock * 2 / 3; | |
736 | else | |
737 | dotclock = pipe_config->port_clock; | |
738 | ||
739 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
740 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
741 | ||
241bfc38 | 742 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
743 | } |
744 | ||
5ab432ef | 745 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 746 | { |
5ab432ef | 747 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 748 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 749 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 750 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 751 | u32 temp; |
2deed761 WF |
752 | u32 enable_bits = SDVO_ENABLE; |
753 | ||
9ed109a7 | 754 | if (intel_crtc->config.has_audio) |
2deed761 | 755 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 756 | |
b242b7f7 | 757 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 758 | |
7a87c289 | 759 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
760 | * before disabling it, so restore the transcoder select bit here. */ |
761 | if (HAS_PCH_IBX(dev)) | |
762 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 763 | |
d8a2d0e0 ZW |
764 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
765 | * we do this anyway which shows more stable in testing. | |
766 | */ | |
c619eed4 | 767 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
768 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
769 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
770 | } |
771 | ||
5ab432ef DV |
772 | temp |= enable_bits; |
773 | ||
b242b7f7 PZ |
774 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
775 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
776 | |
777 | /* HW workaround, need to write this twice for issue that may result | |
778 | * in first write getting masked. | |
779 | */ | |
780 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
781 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
782 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 783 | } |
b76cf76b | 784 | } |
89b667f8 | 785 | |
b76cf76b JN |
786 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
787 | { | |
5ab432ef DV |
788 | } |
789 | ||
790 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
791 | { | |
792 | struct drm_device *dev = encoder->base.dev; | |
793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
794 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
795 | u32 temp; | |
3cce574f | 796 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 797 | |
b242b7f7 | 798 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
799 | |
800 | /* HW workaround for IBX, we need to move the port to transcoder A | |
801 | * before disabling it. */ | |
802 | if (HAS_PCH_IBX(dev)) { | |
803 | struct drm_crtc *crtc = encoder->base.crtc; | |
804 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
805 | ||
806 | if (temp & SDVO_PIPE_B_SELECT) { | |
807 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
808 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
809 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
810 | |
811 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
812 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
813 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
814 | |
815 | /* Transcoder selection bits only update | |
816 | * effectively on vblank. */ | |
817 | if (crtc) | |
818 | intel_wait_for_vblank(dev, pipe); | |
819 | else | |
820 | msleep(50); | |
821 | } | |
7d57382e | 822 | } |
d8a2d0e0 | 823 | |
5ab432ef DV |
824 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
825 | * we do this anyway which shows more stable in testing. | |
826 | */ | |
827 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
828 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
829 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
830 | } |
831 | ||
832 | temp &= ~enable_bits; | |
d8a2d0e0 | 833 | |
b242b7f7 PZ |
834 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
835 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
836 | |
837 | /* HW workaround, need to write this twice for issue that may result | |
838 | * in first write getting masked. | |
839 | */ | |
c619eed4 | 840 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
841 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
842 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 843 | } |
7d57382e EA |
844 | } |
845 | ||
40478455 | 846 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
847 | { |
848 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
849 | ||
40478455 | 850 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 851 | return 165000; |
e3c33578 | 852 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
853 | return 300000; |
854 | else | |
855 | return 225000; | |
856 | } | |
857 | ||
c19de8eb DL |
858 | static enum drm_mode_status |
859 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
860 | struct drm_display_mode *mode) | |
7d57382e | 861 | { |
40478455 VS |
862 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
863 | true)) | |
7d57382e EA |
864 | return MODE_CLOCK_HIGH; |
865 | if (mode->clock < 20000) | |
5cbba41d | 866 | return MODE_CLOCK_LOW; |
7d57382e EA |
867 | |
868 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
869 | return MODE_NO_DBLESCAN; | |
870 | ||
871 | return MODE_OK; | |
872 | } | |
873 | ||
71800632 VS |
874 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
875 | { | |
876 | struct drm_device *dev = crtc->base.dev; | |
877 | struct intel_encoder *encoder; | |
878 | int count = 0, count_hdmi = 0; | |
879 | ||
880 | if (!HAS_PCH_SPLIT(dev)) | |
881 | return false; | |
882 | ||
883 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
884 | if (encoder->new_crtc != crtc) | |
885 | continue; | |
886 | ||
887 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
888 | count++; | |
889 | } | |
890 | ||
891 | /* | |
892 | * HDMI 12bpc affects the clocks, so it's only possible | |
893 | * when not cloning with other encoder types. | |
894 | */ | |
895 | return count_hdmi > 0 && count_hdmi == count; | |
896 | } | |
897 | ||
5bfe2ac0 DV |
898 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
899 | struct intel_crtc_config *pipe_config) | |
7d57382e | 900 | { |
5bfe2ac0 DV |
901 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
902 | struct drm_device *dev = encoder->base.dev; | |
903 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 904 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
40478455 | 905 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 906 | int desired_bpp; |
3685a8f3 | 907 | |
6897b4b5 DV |
908 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
909 | ||
55bc60db VS |
910 | if (intel_hdmi->color_range_auto) { |
911 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 912 | if (pipe_config->has_hdmi_sink && |
18316c8c | 913 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 914 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
915 | else |
916 | intel_hdmi->color_range = 0; | |
917 | } | |
918 | ||
3685a8f3 | 919 | if (intel_hdmi->color_range) |
50f3b016 | 920 | pipe_config->limited_color_range = true; |
3685a8f3 | 921 | |
5bfe2ac0 DV |
922 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
923 | pipe_config->has_pch_encoder = true; | |
924 | ||
9ed109a7 DV |
925 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
926 | pipe_config->has_audio = true; | |
927 | ||
4e53c2e0 DV |
928 | /* |
929 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
930 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
931 | * outputs. We also need to check that the higher clock still fits |
932 | * within limits. | |
4e53c2e0 | 933 | */ |
6897b4b5 | 934 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 VS |
935 | clock_12bpc <= portclock_limit && |
936 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
937 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
938 | desired_bpp = 12*3; | |
325b9d04 DV |
939 | |
940 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 941 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 942 | } else { |
e29c22c0 DV |
943 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
944 | desired_bpp = 8*3; | |
945 | } | |
946 | ||
947 | if (!pipe_config->bw_constrained) { | |
948 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
949 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
950 | } |
951 | ||
241bfc38 | 952 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
953 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
954 | return false; | |
955 | } | |
956 | ||
7d57382e EA |
957 | return true; |
958 | } | |
959 | ||
aa93d632 | 960 | static enum drm_connector_status |
930a9e28 | 961 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 962 | { |
b0ea7d37 | 963 | struct drm_device *dev = connector->dev; |
df0e9248 | 964 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
965 | struct intel_digital_port *intel_dig_port = |
966 | hdmi_to_dig_port(intel_hdmi); | |
967 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 968 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 969 | struct edid *edid; |
671dedd2 | 970 | enum intel_display_power_domain power_domain; |
aa93d632 | 971 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 972 | |
164c8598 CW |
973 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
974 | connector->base.id, drm_get_connector_name(connector)); | |
975 | ||
671dedd2 ID |
976 | power_domain = intel_display_port_power_domain(intel_encoder); |
977 | intel_display_power_get(dev_priv, power_domain); | |
978 | ||
ea5b213a | 979 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 980 | intel_hdmi->has_audio = false; |
abedc077 | 981 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 982 | edid = drm_get_edid(connector, |
3bd7d909 DK |
983 | intel_gmbus_get_adapter(dev_priv, |
984 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 985 | |
aa93d632 | 986 | if (edid) { |
be9f1c4f | 987 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 988 | status = connector_status_connected; |
b1d7e4b4 WF |
989 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
990 | intel_hdmi->has_hdmi_sink = | |
991 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 992 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
993 | intel_hdmi->rgb_quant_range_selectable = |
994 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 995 | } |
aa93d632 | 996 | kfree(edid); |
9dff6af8 | 997 | } |
30ad48b7 | 998 | |
55b7d6e8 | 999 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
1000 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1001 | intel_hdmi->has_audio = | |
1002 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 1003 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
1004 | } |
1005 | ||
671dedd2 ID |
1006 | intel_display_power_put(dev_priv, power_domain); |
1007 | ||
2ded9e27 | 1008 | return status; |
7d57382e EA |
1009 | } |
1010 | ||
1011 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
1012 | { | |
671dedd2 ID |
1013 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1014 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
f899fc64 | 1015 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 ID |
1016 | enum intel_display_power_domain power_domain; |
1017 | int ret; | |
7d57382e EA |
1018 | |
1019 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
1020 | * we can send audio to it. | |
1021 | */ | |
1022 | ||
671dedd2 ID |
1023 | power_domain = intel_display_port_power_domain(intel_encoder); |
1024 | intel_display_power_get(dev_priv, power_domain); | |
1025 | ||
1026 | ret = intel_ddc_get_modes(connector, | |
3bd7d909 DK |
1027 | intel_gmbus_get_adapter(dev_priv, |
1028 | intel_hdmi->ddc_bus)); | |
671dedd2 ID |
1029 | |
1030 | intel_display_power_put(dev_priv, power_domain); | |
1031 | ||
1032 | return ret; | |
7d57382e EA |
1033 | } |
1034 | ||
1aad7ac0 CW |
1035 | static bool |
1036 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1037 | { | |
671dedd2 ID |
1038 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1039 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
1aad7ac0 | 1040 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 | 1041 | enum intel_display_power_domain power_domain; |
1aad7ac0 CW |
1042 | struct edid *edid; |
1043 | bool has_audio = false; | |
1044 | ||
671dedd2 ID |
1045 | power_domain = intel_display_port_power_domain(intel_encoder); |
1046 | intel_display_power_get(dev_priv, power_domain); | |
1047 | ||
1aad7ac0 | 1048 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1049 | intel_gmbus_get_adapter(dev_priv, |
1050 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
1051 | if (edid) { |
1052 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
1053 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
1054 | kfree(edid); |
1055 | } | |
1056 | ||
671dedd2 ID |
1057 | intel_display_power_put(dev_priv, power_domain); |
1058 | ||
1aad7ac0 CW |
1059 | return has_audio; |
1060 | } | |
1061 | ||
55b7d6e8 CW |
1062 | static int |
1063 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1064 | struct drm_property *property, |
1065 | uint64_t val) | |
55b7d6e8 CW |
1066 | { |
1067 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1068 | struct intel_digital_port *intel_dig_port = |
1069 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1070 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1071 | int ret; |
1072 | ||
662595df | 1073 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1074 | if (ret) |
1075 | return ret; | |
1076 | ||
3f43c48d | 1077 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1078 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1079 | bool has_audio; |
1080 | ||
1081 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1082 | return 0; |
1083 | ||
1aad7ac0 | 1084 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1085 | |
b1d7e4b4 | 1086 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1087 | has_audio = intel_hdmi_detect_audio(connector); |
1088 | else | |
b1d7e4b4 | 1089 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1090 | |
b1d7e4b4 WF |
1091 | if (i == HDMI_AUDIO_OFF_DVI) |
1092 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1093 | |
1aad7ac0 | 1094 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1095 | goto done; |
1096 | } | |
1097 | ||
e953fd7b | 1098 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1099 | bool old_auto = intel_hdmi->color_range_auto; |
1100 | uint32_t old_range = intel_hdmi->color_range; | |
1101 | ||
55bc60db VS |
1102 | switch (val) { |
1103 | case INTEL_BROADCAST_RGB_AUTO: | |
1104 | intel_hdmi->color_range_auto = true; | |
1105 | break; | |
1106 | case INTEL_BROADCAST_RGB_FULL: | |
1107 | intel_hdmi->color_range_auto = false; | |
1108 | intel_hdmi->color_range = 0; | |
1109 | break; | |
1110 | case INTEL_BROADCAST_RGB_LIMITED: | |
1111 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1112 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1113 | break; |
1114 | default: | |
1115 | return -EINVAL; | |
1116 | } | |
ae4edb80 DV |
1117 | |
1118 | if (old_auto == intel_hdmi->color_range_auto && | |
1119 | old_range == intel_hdmi->color_range) | |
1120 | return 0; | |
1121 | ||
e953fd7b CW |
1122 | goto done; |
1123 | } | |
1124 | ||
55b7d6e8 CW |
1125 | return -EINVAL; |
1126 | ||
1127 | done: | |
c0c36b94 CW |
1128 | if (intel_dig_port->base.base.crtc) |
1129 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1130 | |
1131 | return 0; | |
1132 | } | |
1133 | ||
13732ba7 JB |
1134 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1135 | { | |
1136 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1137 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1138 | struct drm_display_mode *adjusted_mode = | |
1139 | &intel_crtc->config.adjusted_mode; | |
1140 | ||
4cde8a21 DV |
1141 | intel_hdmi_prepare(encoder); |
1142 | ||
6897b4b5 DV |
1143 | intel_hdmi->set_infoframes(&encoder->base, |
1144 | intel_crtc->config.has_hdmi_sink, | |
1145 | adjusted_mode); | |
13732ba7 JB |
1146 | } |
1147 | ||
9514ac6e | 1148 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1149 | { |
1150 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1151 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1152 | struct drm_device *dev = encoder->base.dev; |
1153 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1154 | struct intel_crtc *intel_crtc = | |
1155 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 JB |
1156 | struct drm_display_mode *adjusted_mode = |
1157 | &intel_crtc->config.adjusted_mode; | |
e4607fcf | 1158 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1159 | int pipe = intel_crtc->pipe; |
1160 | u32 val; | |
1161 | ||
89b667f8 | 1162 | /* Enable clock channels for this port */ |
0980a60f | 1163 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1164 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1165 | val = 0; |
1166 | if (pipe) | |
1167 | val |= (1<<21); | |
1168 | else | |
1169 | val &= ~(1<<21); | |
1170 | val |= 0x001000c4; | |
ab3c759a | 1171 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1172 | |
1173 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1174 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1175 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1176 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1177 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1178 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1179 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1180 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1181 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1182 | |
1183 | /* Program lane clock */ | |
ab3c759a CML |
1184 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1185 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1186 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1187 | |
6897b4b5 DV |
1188 | intel_hdmi->set_infoframes(&encoder->base, |
1189 | intel_crtc->config.has_hdmi_sink, | |
1190 | adjusted_mode); | |
13732ba7 | 1191 | |
b76cf76b JN |
1192 | intel_enable_hdmi(encoder); |
1193 | ||
e4607fcf | 1194 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1195 | } |
1196 | ||
9514ac6e | 1197 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1198 | { |
1199 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1200 | struct drm_device *dev = encoder->base.dev; | |
1201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1202 | struct intel_crtc *intel_crtc = |
1203 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1204 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1205 | int pipe = intel_crtc->pipe; |
89b667f8 | 1206 | |
4cde8a21 DV |
1207 | intel_hdmi_prepare(encoder); |
1208 | ||
89b667f8 | 1209 | /* Program Tx lane resets to default */ |
0980a60f | 1210 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1211 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1212 | DPIO_PCS_TX_LANE2_RESET | |
1213 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1214 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1215 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1216 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1217 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1218 | DPIO_PCS_CLK_SOFT_RESET); | |
1219 | ||
1220 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1221 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1222 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1223 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1224 | ||
1225 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1226 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1227 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1228 | } |
1229 | ||
9514ac6e | 1230 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1231 | { |
1232 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1233 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1234 | struct intel_crtc *intel_crtc = |
1235 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1236 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1237 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1238 | |
1239 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1240 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1241 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1242 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1243 | mutex_unlock(&dev_priv->dpio_lock); |
1244 | } | |
1245 | ||
e4a1d846 CML |
1246 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1247 | { | |
1248 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1249 | struct drm_device *dev = encoder->base.dev; | |
1250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1251 | struct intel_crtc *intel_crtc = | |
1252 | to_intel_crtc(encoder->base.crtc); | |
1253 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1254 | int pipe = intel_crtc->pipe; | |
1255 | int data, i; | |
1256 | u32 val; | |
1257 | ||
1258 | /* Program Tx latency optimal setting */ | |
1259 | mutex_lock(&dev_priv->dpio_lock); | |
1260 | for (i = 0; i < 4; i++) { | |
1261 | /* Set the latency optimal bit */ | |
1262 | data = (i == 1) ? 0x0 : 0x6; | |
1263 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1264 | data << DPIO_FRC_LATENCY_SHFIT); | |
1265 | ||
1266 | /* Set the upar bit */ | |
1267 | data = (i == 1) ? 0x0 : 0x1; | |
1268 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1269 | data << DPIO_UPAR_SHIFT); | |
1270 | } | |
1271 | ||
1272 | /* Data lane stagger programming */ | |
1273 | /* FIXME: Fix up value only after power analysis */ | |
1274 | ||
1275 | /* Clear calc init */ | |
1276 | vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0); | |
1277 | ||
1278 | /* FIXME: Program the support xxx V-dB */ | |
1279 | /* Use 800mV-0dB */ | |
1280 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch)); | |
1281 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1282 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1283 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val); | |
1284 | ||
1285 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)); | |
1286 | val &= ~DPIO_SWING_MARGIN_MASK; | |
1287 | val |= 102 << DPIO_SWING_MARGIN_SHIFT; | |
1288 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), val); | |
1289 | ||
1290 | /* Disable unique transition scale */ | |
1291 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1292 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1293 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1294 | ||
1295 | /* Additional steps for 1200mV-0dB */ | |
1296 | #if 0 | |
1297 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1298 | if (ch) | |
1299 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1300 | else | |
1301 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1302 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1303 | ||
1304 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1305 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1306 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1307 | #endif | |
1308 | /* Start swing calculation */ | |
1309 | vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), | |
1310 | DPIO_PCS_SWING_CALC_TX0_TX2 | | |
1311 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
1312 | ||
1313 | /* LRC Bypass */ | |
1314 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1315 | val |= DPIO_LRC_BYPASS; | |
1316 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1317 | ||
1318 | mutex_unlock(&dev_priv->dpio_lock); | |
1319 | ||
1320 | intel_enable_hdmi(encoder); | |
1321 | ||
1322 | vlv_wait_port_ready(dev_priv, dport); | |
1323 | } | |
1324 | ||
7d57382e EA |
1325 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1326 | { | |
7d57382e | 1327 | drm_connector_cleanup(connector); |
674e2d08 | 1328 | kfree(connector); |
7d57382e EA |
1329 | } |
1330 | ||
7d57382e | 1331 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1332 | .dpms = intel_connector_dpms, |
7d57382e EA |
1333 | .detect = intel_hdmi_detect, |
1334 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1335 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1336 | .destroy = intel_hdmi_destroy, |
1337 | }; | |
1338 | ||
1339 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1340 | .get_modes = intel_hdmi_get_modes, | |
1341 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1342 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1343 | }; |
1344 | ||
7d57382e | 1345 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1346 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1347 | }; |
1348 | ||
55b7d6e8 CW |
1349 | static void |
1350 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1351 | { | |
3f43c48d | 1352 | intel_attach_force_audio_property(connector); |
e953fd7b | 1353 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1354 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1355 | } |
1356 | ||
00c09d70 PZ |
1357 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1358 | struct intel_connector *intel_connector) | |
7d57382e | 1359 | { |
b9cb234c PZ |
1360 | struct drm_connector *connector = &intel_connector->base; |
1361 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1362 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1363 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1364 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1365 | enum port port = intel_dig_port->port; |
373a3cf7 | 1366 | |
7d57382e | 1367 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1368 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1369 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1370 | ||
c3febcc4 | 1371 | connector->interlace_allowed = 1; |
7d57382e | 1372 | connector->doublescan_allowed = 0; |
573e74ad | 1373 | connector->stereo_allowed = 1; |
66a9278e | 1374 | |
08d644ad DV |
1375 | switch (port) { |
1376 | case PORT_B: | |
f899fc64 | 1377 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1378 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1379 | break; |
1380 | case PORT_C: | |
7ceae0a5 | 1381 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1382 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1383 | break; |
1384 | case PORT_D: | |
7ceae0a5 | 1385 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1386 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1387 | break; |
1388 | case PORT_A: | |
1d843f9d | 1389 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1390 | /* Internal port only for eDP. */ |
1391 | default: | |
6e4c1677 | 1392 | BUG(); |
f8aed700 | 1393 | } |
7d57382e | 1394 | |
7637bfdb | 1395 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1396 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1397 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1398 | } else if (!HAS_PCH_SPLIT(dev)) { |
1399 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1400 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1401 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1402 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1403 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1404 | } else if (HAS_PCH_IBX(dev)) { |
1405 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1406 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1407 | } else { |
1408 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1409 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1410 | } |
45187ace | 1411 | |
affa9354 | 1412 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1413 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1414 | else | |
1415 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1416 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1417 | |
1418 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1419 | ||
1420 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1421 | drm_sysfs_connector_add(connector); | |
1422 | ||
1423 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1424 | * 0xd. Failure to do so will result in spurious interrupts being | |
1425 | * generated on the port when a cable is not attached. | |
1426 | */ | |
1427 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1428 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1429 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1430 | } | |
1431 | } | |
1432 | ||
b242b7f7 | 1433 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1434 | { |
1435 | struct intel_digital_port *intel_dig_port; | |
1436 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1437 | struct intel_connector *intel_connector; |
1438 | ||
b14c5679 | 1439 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1440 | if (!intel_dig_port) |
1441 | return; | |
1442 | ||
b14c5679 | 1443 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1444 | if (!intel_connector) { |
1445 | kfree(intel_dig_port); | |
1446 | return; | |
1447 | } | |
1448 | ||
1449 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1450 | |
1451 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1452 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1453 | |
5bfe2ac0 | 1454 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1455 | intel_encoder->disable = intel_disable_hdmi; |
1456 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1457 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 CML |
1458 | if (IS_CHERRYVIEW(dev)) { |
1459 | intel_encoder->pre_enable = chv_hdmi_pre_enable; | |
1460 | intel_encoder->enable = vlv_enable_hdmi; | |
1461 | } else if (IS_VALLEYVIEW(dev)) { | |
9514ac6e CML |
1462 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1463 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1464 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1465 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1466 | } else { |
13732ba7 | 1467 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1468 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1469 | } |
5ab432ef | 1470 | |
b9cb234c | 1471 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1472 | if (IS_CHERRYVIEW(dev)) { |
1473 | if (port == PORT_D) | |
1474 | intel_encoder->crtc_mask = 1 << 2; | |
1475 | else | |
1476 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1477 | } else { | |
1478 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1479 | } | |
301ea74a | 1480 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1481 | /* |
1482 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1483 | * to work on real hardware. And since g4x can send infoframes to | |
1484 | * only one port anyway, nothing is lost by allowing it. | |
1485 | */ | |
1486 | if (IS_G4X(dev)) | |
1487 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1488 | |
174edf1f | 1489 | intel_dig_port->port = port; |
b242b7f7 | 1490 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1491 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1492 | |
b9cb234c | 1493 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1494 | } |