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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
178f736a | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
178f736a | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
178f736a | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
178f736a | 116 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
117 | enum transcoder cpu_transcoder, |
118 | struct drm_i915_private *dev_priv) | |
2da8af54 | 119 | { |
178f736a DL |
120 | switch (type) { |
121 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 123 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 124 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
125 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 127 | default: |
178f736a | 128 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
129 | return 0; |
130 | } | |
131 | } | |
132 | ||
a3da1df7 | 133 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 134 | enum hdmi_infoframe_type type, |
fff63867 | 135 | const void *frame, ssize_t len) |
45187ace | 136 | { |
fff63867 | 137 | const uint32_t *data = frame; |
3c17fe4b DH |
138 | struct drm_device *dev = encoder->dev; |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 141 | int i; |
3c17fe4b | 142 | |
822974ae PZ |
143 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | ||
1d4f85ac | 145 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 146 | val |= g4x_infoframe_index(type); |
22509ec8 | 147 | |
178f736a | 148 | val &= ~g4x_infoframe_enable(type); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 151 | |
9d9740f0 | 152 | mmiowb(); |
45187ace | 153 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
154 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | data++; | |
156 | } | |
adf00b26 PZ |
157 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
159 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 160 | mmiowb(); |
3c17fe4b | 161 | |
178f736a | 162 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 163 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 164 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 165 | |
22509ec8 | 166 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 167 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
168 | } |
169 | ||
e43823ec JB |
170 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | { | |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 174 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
175 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | ||
89a35ecd JB |
177 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
178 | return val & VIDEO_DIP_ENABLE; | |
179 | ||
180 | return false; | |
e43823ec JB |
181 | } |
182 | ||
fdf1250a | 183 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 184 | enum hdmi_infoframe_type type, |
fff63867 | 185 | const void *frame, ssize_t len) |
fdf1250a | 186 | { |
fff63867 | 187 | const uint32_t *data = frame; |
fdf1250a PZ |
188 | struct drm_device *dev = encoder->dev; |
189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 190 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 191 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
192 | u32 val = I915_READ(reg); |
193 | ||
822974ae PZ |
194 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
195 | ||
fdf1250a | 196 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 197 | val |= g4x_infoframe_index(type); |
fdf1250a | 198 | |
178f736a | 199 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
200 | |
201 | I915_WRITE(reg, val); | |
202 | ||
9d9740f0 | 203 | mmiowb(); |
fdf1250a PZ |
204 | for (i = 0; i < len; i += 4) { |
205 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
206 | data++; | |
207 | } | |
adf00b26 PZ |
208 | /* Write every possible data byte to force correct ECC calculation. */ |
209 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 211 | mmiowb(); |
fdf1250a | 212 | |
178f736a | 213 | val |= g4x_infoframe_enable(type); |
fdf1250a | 214 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 215 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
216 | |
217 | I915_WRITE(reg, val); | |
9d9740f0 | 218 | POSTING_READ(reg); |
fdf1250a PZ |
219 | } |
220 | ||
e43823ec JB |
221 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
222 | { | |
223 | struct drm_device *dev = encoder->dev; | |
224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
225 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
052f62f7 | 226 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
227 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
228 | u32 val = I915_READ(reg); | |
229 | ||
052f62f7 JN |
230 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
231 | return val & VIDEO_DIP_ENABLE; | |
232 | ||
233 | return false; | |
e43823ec JB |
234 | } |
235 | ||
fdf1250a | 236 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 237 | enum hdmi_infoframe_type type, |
fff63867 | 238 | const void *frame, ssize_t len) |
b055c8f3 | 239 | { |
fff63867 | 240 | const uint32_t *data = frame; |
b055c8f3 JB |
241 | struct drm_device *dev = encoder->dev; |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 243 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 244 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 245 | u32 val = I915_READ(reg); |
b055c8f3 | 246 | |
822974ae PZ |
247 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
248 | ||
64a8fc01 | 249 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 250 | val |= g4x_infoframe_index(type); |
45187ace | 251 | |
ecb97851 PZ |
252 | /* The DIP control register spec says that we need to update the AVI |
253 | * infoframe without clearing its enable bit */ | |
178f736a DL |
254 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
255 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 256 | |
22509ec8 | 257 | I915_WRITE(reg, val); |
45187ace | 258 | |
9d9740f0 | 259 | mmiowb(); |
45187ace | 260 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
261 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
262 | data++; | |
263 | } | |
adf00b26 PZ |
264 | /* Write every possible data byte to force correct ECC calculation. */ |
265 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
266 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 267 | mmiowb(); |
b055c8f3 | 268 | |
178f736a | 269 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 270 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 271 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 272 | |
22509ec8 | 273 | I915_WRITE(reg, val); |
9d9740f0 | 274 | POSTING_READ(reg); |
45187ace | 275 | } |
90b107c8 | 276 | |
e43823ec JB |
277 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
278 | { | |
279 | struct drm_device *dev = encoder->dev; | |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
282 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
283 | u32 val = I915_READ(reg); | |
284 | ||
285 | return val & VIDEO_DIP_ENABLE; | |
286 | } | |
287 | ||
90b107c8 | 288 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 289 | enum hdmi_infoframe_type type, |
fff63867 | 290 | const void *frame, ssize_t len) |
90b107c8 | 291 | { |
fff63867 | 292 | const uint32_t *data = frame; |
90b107c8 SK |
293 | struct drm_device *dev = encoder->dev; |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 296 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 297 | u32 val = I915_READ(reg); |
90b107c8 | 298 | |
822974ae PZ |
299 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
300 | ||
90b107c8 | 301 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 302 | val |= g4x_infoframe_index(type); |
22509ec8 | 303 | |
178f736a | 304 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 305 | |
22509ec8 | 306 | I915_WRITE(reg, val); |
90b107c8 | 307 | |
9d9740f0 | 308 | mmiowb(); |
90b107c8 SK |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 316 | mmiowb(); |
90b107c8 | 317 | |
178f736a | 318 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 319 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 320 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 321 | |
22509ec8 | 322 | I915_WRITE(reg, val); |
9d9740f0 | 323 | POSTING_READ(reg); |
90b107c8 SK |
324 | } |
325 | ||
e43823ec JB |
326 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
327 | { | |
328 | struct drm_device *dev = encoder->dev; | |
329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
330 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
535afa2e | 331 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
332 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
333 | u32 val = I915_READ(reg); | |
334 | ||
eeea3e67 | 335 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
535afa2e JB |
336 | return val & VIDEO_DIP_ENABLE; |
337 | ||
338 | return false; | |
e43823ec JB |
339 | } |
340 | ||
8c5f5f7c | 341 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 342 | enum hdmi_infoframe_type type, |
fff63867 | 343 | const void *frame, ssize_t len) |
8c5f5f7c | 344 | { |
fff63867 | 345 | const uint32_t *data = frame; |
2da8af54 PZ |
346 | struct drm_device *dev = encoder->dev; |
347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
348 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 349 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
350 | u32 data_reg; |
351 | int i; | |
2da8af54 | 352 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 353 | |
178f736a | 354 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 355 | intel_crtc->config->cpu_transcoder, |
a57c774a | 356 | dev_priv); |
2da8af54 PZ |
357 | if (data_reg == 0) |
358 | return; | |
359 | ||
178f736a | 360 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
361 | I915_WRITE(ctl_reg, val); |
362 | ||
9d9740f0 | 363 | mmiowb(); |
2da8af54 PZ |
364 | for (i = 0; i < len; i += 4) { |
365 | I915_WRITE(data_reg + i, *data); | |
366 | data++; | |
367 | } | |
adf00b26 PZ |
368 | /* Write every possible data byte to force correct ECC calculation. */ |
369 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
370 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 371 | mmiowb(); |
8c5f5f7c | 372 | |
178f736a | 373 | val |= hsw_infoframe_enable(type); |
2da8af54 | 374 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 375 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
376 | } |
377 | ||
e43823ec JB |
378 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
379 | { | |
380 | struct drm_device *dev = encoder->dev; | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 383 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
384 | u32 val = I915_READ(ctl_reg); |
385 | ||
386 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | | |
387 | VIDEO_DIP_ENABLE_VS_HSW); | |
388 | } | |
389 | ||
5adaea79 DL |
390 | /* |
391 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
392 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
393 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
394 | * used for both technologies. | |
395 | * | |
396 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
397 | * DW1: DB3 | DB2 | DB1 | DB0 | |
398 | * DW2: DB7 | DB6 | DB5 | DB4 | |
399 | * DW3: ... | |
400 | * | |
401 | * (HB is Header Byte, DB is Data Byte) | |
402 | * | |
403 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
404 | * trick them by giving an offset into the buffer and moving back the header | |
405 | * bytes by one. | |
406 | */ | |
9198ee5b DL |
407 | static void intel_write_infoframe(struct drm_encoder *encoder, |
408 | union hdmi_infoframe *frame) | |
45187ace JB |
409 | { |
410 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
411 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
412 | ssize_t len; | |
45187ace | 413 | |
5adaea79 DL |
414 | /* see comment above for the reason for this offset */ |
415 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
416 | if (len < 0) | |
417 | return; | |
418 | ||
419 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
420 | buffer[0] = buffer[1]; | |
421 | buffer[1] = buffer[2]; | |
422 | buffer[2] = buffer[3]; | |
423 | buffer[3] = 0; | |
424 | len++; | |
45187ace | 425 | |
5adaea79 | 426 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
427 | } |
428 | ||
687f4d06 | 429 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 430 | struct drm_display_mode *adjusted_mode) |
45187ace | 431 | { |
abedc077 | 432 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 433 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
434 | union hdmi_infoframe frame; |
435 | int ret; | |
45187ace | 436 | |
94a11ddc VK |
437 | /* Set user selected PAR to incoming mode's member */ |
438 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
439 | ||
5adaea79 DL |
440 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
441 | adjusted_mode); | |
442 | if (ret < 0) { | |
443 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
444 | return; | |
445 | } | |
c846b619 | 446 | |
abedc077 | 447 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 448 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
449 | frame.avi.quantization_range = |
450 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 451 | else |
5adaea79 DL |
452 | frame.avi.quantization_range = |
453 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
454 | } |
455 | ||
9198ee5b | 456 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
457 | } |
458 | ||
687f4d06 | 459 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 460 | { |
5adaea79 DL |
461 | union hdmi_infoframe frame; |
462 | int ret; | |
463 | ||
464 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
465 | if (ret < 0) { | |
466 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
467 | return; | |
468 | } | |
c0864cb3 | 469 | |
5adaea79 | 470 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 471 | |
9198ee5b | 472 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
473 | } |
474 | ||
c8bb75af LD |
475 | static void |
476 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
477 | struct drm_display_mode *adjusted_mode) | |
478 | { | |
479 | union hdmi_infoframe frame; | |
480 | int ret; | |
481 | ||
482 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
483 | adjusted_mode); | |
484 | if (ret < 0) | |
485 | return; | |
486 | ||
487 | intel_write_infoframe(encoder, &frame); | |
488 | } | |
489 | ||
687f4d06 | 490 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 491 | bool enable, |
687f4d06 PZ |
492 | struct drm_display_mode *adjusted_mode) |
493 | { | |
0c14c7f9 | 494 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
495 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
496 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
497 | u32 reg = VIDEO_DIP_CTL; |
498 | u32 val = I915_READ(reg); | |
822cdc52 | 499 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 500 | |
afba0188 DV |
501 | assert_hdmi_port_disabled(intel_hdmi); |
502 | ||
0c14c7f9 PZ |
503 | /* If the registers were not initialized yet, they might be zeroes, |
504 | * which means we're selecting the AVI DIP and we're setting its | |
505 | * frequency to once. This seems to really confuse the HW and make | |
506 | * things stop working (the register spec says the AVI always needs to | |
507 | * be sent every VSync). So here we avoid writing to the register more | |
508 | * than we need and also explicitly select the AVI DIP and explicitly | |
509 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
510 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
511 | * either. */ | |
512 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
513 | ||
6897b4b5 | 514 | if (!enable) { |
0c14c7f9 PZ |
515 | if (!(val & VIDEO_DIP_ENABLE)) |
516 | return; | |
517 | val &= ~VIDEO_DIP_ENABLE; | |
518 | I915_WRITE(reg, val); | |
9d9740f0 | 519 | POSTING_READ(reg); |
0c14c7f9 PZ |
520 | return; |
521 | } | |
522 | ||
72b78c9d PZ |
523 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
524 | if (val & VIDEO_DIP_ENABLE) { | |
525 | val &= ~VIDEO_DIP_ENABLE; | |
526 | I915_WRITE(reg, val); | |
9d9740f0 | 527 | POSTING_READ(reg); |
72b78c9d PZ |
528 | } |
529 | val &= ~VIDEO_DIP_PORT_MASK; | |
530 | val |= port; | |
531 | } | |
532 | ||
822974ae | 533 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 534 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 535 | |
f278d972 | 536 | I915_WRITE(reg, val); |
9d9740f0 | 537 | POSTING_READ(reg); |
f278d972 | 538 | |
687f4d06 PZ |
539 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
540 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 541 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
542 | } |
543 | ||
6d67415f VS |
544 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
545 | { | |
546 | struct drm_device *dev = encoder->dev; | |
547 | struct drm_connector *connector; | |
548 | ||
549 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
550 | ||
551 | /* | |
552 | * HDMI cloning is only supported on g4x which doesn't | |
553 | * support deep color or GCP infoframes anyway so no | |
554 | * need to worry about multiple HDMI sinks here. | |
555 | */ | |
556 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
557 | if (connector->encoder == encoder) | |
558 | return connector->display_info.bpc > 8; | |
559 | ||
560 | return false; | |
561 | } | |
562 | ||
12aa3290 VS |
563 | /* |
564 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
565 | * | |
566 | * From HDMI specification 1.4a: | |
567 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
568 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
569 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
570 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
571 | * phase of 0 | |
572 | */ | |
573 | static bool gcp_default_phase_possible(int pipe_bpp, | |
574 | const struct drm_display_mode *mode) | |
575 | { | |
576 | unsigned int pixels_per_group; | |
577 | ||
578 | switch (pipe_bpp) { | |
579 | case 30: | |
580 | /* 4 pixels in 5 clocks */ | |
581 | pixels_per_group = 4; | |
582 | break; | |
583 | case 36: | |
584 | /* 2 pixels in 3 clocks */ | |
585 | pixels_per_group = 2; | |
586 | break; | |
587 | case 48: | |
588 | /* 1 pixel in 2 clocks */ | |
589 | pixels_per_group = 1; | |
590 | break; | |
591 | default: | |
592 | /* phase information not relevant for 8bpc */ | |
593 | return false; | |
594 | } | |
595 | ||
596 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
597 | mode->crtc_htotal % pixels_per_group == 0 && | |
598 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
599 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
600 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
601 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
602 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
603 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
604 | } | |
605 | ||
6d67415f VS |
606 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
607 | { | |
608 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
609 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
610 | u32 reg, val = 0; | |
611 | ||
612 | if (HAS_DDI(dev_priv)) | |
613 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); | |
614 | else if (IS_VALLEYVIEW(dev_priv)) | |
615 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
616 | else if (HAS_PCH_SPLIT(dev_priv->dev)) | |
617 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
618 | else | |
619 | return false; | |
620 | ||
621 | /* Indicate color depth whenever the sink supports deep color */ | |
622 | if (hdmi_sink_is_deep_color(encoder)) | |
623 | val |= GCP_COLOR_INDICATION; | |
624 | ||
12aa3290 VS |
625 | /* Enable default_phase whenever the display mode is suitably aligned */ |
626 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, | |
627 | &crtc->config->base.adjusted_mode)) | |
628 | val |= GCP_DEFAULT_PHASE_ENABLE; | |
629 | ||
6d67415f VS |
630 | I915_WRITE(reg, val); |
631 | ||
632 | return val != 0; | |
633 | } | |
634 | ||
635 | static void intel_disable_gcp_infoframe(struct intel_crtc *crtc) | |
636 | { | |
637 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
638 | u32 reg; | |
639 | ||
640 | if (HAS_DDI(dev_priv)) | |
641 | reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); | |
642 | else if (IS_VALLEYVIEW(dev_priv)) | |
643 | reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); | |
644 | else if (HAS_PCH_SPLIT(dev_priv->dev)) | |
645 | reg = TVIDEO_DIP_CTL(crtc->pipe); | |
646 | else | |
647 | return; | |
648 | ||
649 | I915_WRITE(reg, I915_READ(reg) & ~VIDEO_DIP_ENABLE_GCP); | |
650 | } | |
651 | ||
687f4d06 | 652 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 653 | bool enable, |
687f4d06 PZ |
654 | struct drm_display_mode *adjusted_mode) |
655 | { | |
0c14c7f9 PZ |
656 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
657 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
658 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
659 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
660 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
661 | u32 val = I915_READ(reg); | |
822cdc52 | 662 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 663 | |
afba0188 DV |
664 | assert_hdmi_port_disabled(intel_hdmi); |
665 | ||
0c14c7f9 PZ |
666 | /* See the big comment in g4x_set_infoframes() */ |
667 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
668 | ||
6897b4b5 | 669 | if (!enable) { |
0c14c7f9 PZ |
670 | if (!(val & VIDEO_DIP_ENABLE)) |
671 | return; | |
672 | val &= ~VIDEO_DIP_ENABLE; | |
673 | I915_WRITE(reg, val); | |
9d9740f0 | 674 | POSTING_READ(reg); |
0c14c7f9 PZ |
675 | return; |
676 | } | |
677 | ||
72b78c9d PZ |
678 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
679 | if (val & VIDEO_DIP_ENABLE) { | |
680 | val &= ~VIDEO_DIP_ENABLE; | |
681 | I915_WRITE(reg, val); | |
9d9740f0 | 682 | POSTING_READ(reg); |
72b78c9d PZ |
683 | } |
684 | val &= ~VIDEO_DIP_PORT_MASK; | |
685 | val |= port; | |
686 | } | |
687 | ||
822974ae | 688 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
689 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
690 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 691 | |
6d67415f VS |
692 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
693 | val |= VIDEO_DIP_ENABLE_GCP; | |
694 | ||
f278d972 | 695 | I915_WRITE(reg, val); |
9d9740f0 | 696 | POSTING_READ(reg); |
f278d972 | 697 | |
687f4d06 PZ |
698 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
699 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 700 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
701 | } |
702 | ||
703 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 704 | bool enable, |
687f4d06 PZ |
705 | struct drm_display_mode *adjusted_mode) |
706 | { | |
0c14c7f9 PZ |
707 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
708 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
709 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
710 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
711 | u32 val = I915_READ(reg); | |
712 | ||
afba0188 DV |
713 | assert_hdmi_port_disabled(intel_hdmi); |
714 | ||
0c14c7f9 PZ |
715 | /* See the big comment in g4x_set_infoframes() */ |
716 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
717 | ||
6897b4b5 | 718 | if (!enable) { |
0c14c7f9 PZ |
719 | if (!(val & VIDEO_DIP_ENABLE)) |
720 | return; | |
721 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
722 | I915_WRITE(reg, val); | |
9d9740f0 | 723 | POSTING_READ(reg); |
0c14c7f9 PZ |
724 | return; |
725 | } | |
726 | ||
822974ae PZ |
727 | /* Set both together, unset both together: see the spec. */ |
728 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
729 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
730 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 731 | |
6d67415f VS |
732 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
733 | val |= VIDEO_DIP_ENABLE_GCP; | |
734 | ||
822974ae | 735 | I915_WRITE(reg, val); |
9d9740f0 | 736 | POSTING_READ(reg); |
822974ae | 737 | |
687f4d06 PZ |
738 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
739 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 740 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
741 | } |
742 | ||
743 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 744 | bool enable, |
687f4d06 PZ |
745 | struct drm_display_mode *adjusted_mode) |
746 | { | |
0c14c7f9 | 747 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 748 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
749 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
750 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
751 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
752 | u32 val = I915_READ(reg); | |
6a2b8021 | 753 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 754 | |
afba0188 DV |
755 | assert_hdmi_port_disabled(intel_hdmi); |
756 | ||
0c14c7f9 PZ |
757 | /* See the big comment in g4x_set_infoframes() */ |
758 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
759 | ||
6897b4b5 | 760 | if (!enable) { |
0c14c7f9 PZ |
761 | if (!(val & VIDEO_DIP_ENABLE)) |
762 | return; | |
763 | val &= ~VIDEO_DIP_ENABLE; | |
764 | I915_WRITE(reg, val); | |
9d9740f0 | 765 | POSTING_READ(reg); |
0c14c7f9 PZ |
766 | return; |
767 | } | |
768 | ||
6a2b8021 JB |
769 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
770 | if (val & VIDEO_DIP_ENABLE) { | |
771 | val &= ~VIDEO_DIP_ENABLE; | |
772 | I915_WRITE(reg, val); | |
773 | POSTING_READ(reg); | |
774 | } | |
775 | val &= ~VIDEO_DIP_PORT_MASK; | |
776 | val |= port; | |
777 | } | |
778 | ||
822974ae | 779 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
780 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
781 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 782 | |
6d67415f VS |
783 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
784 | val |= VIDEO_DIP_ENABLE_GCP; | |
785 | ||
822974ae | 786 | I915_WRITE(reg, val); |
9d9740f0 | 787 | POSTING_READ(reg); |
822974ae | 788 | |
687f4d06 PZ |
789 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
790 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 791 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
792 | } |
793 | ||
794 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 795 | bool enable, |
687f4d06 PZ |
796 | struct drm_display_mode *adjusted_mode) |
797 | { | |
0c14c7f9 PZ |
798 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
799 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
800 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 801 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 802 | u32 val = I915_READ(reg); |
0c14c7f9 | 803 | |
afba0188 DV |
804 | assert_hdmi_port_disabled(intel_hdmi); |
805 | ||
6897b4b5 | 806 | if (!enable) { |
0c14c7f9 | 807 | I915_WRITE(reg, 0); |
9d9740f0 | 808 | POSTING_READ(reg); |
0c14c7f9 PZ |
809 | return; |
810 | } | |
811 | ||
0dd87d20 PZ |
812 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
813 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
814 | ||
6d67415f VS |
815 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
816 | val |= VIDEO_DIP_ENABLE_GCP_HSW; | |
817 | ||
0dd87d20 | 818 | I915_WRITE(reg, val); |
9d9740f0 | 819 | POSTING_READ(reg); |
0dd87d20 | 820 | |
687f4d06 PZ |
821 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
822 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 823 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
824 | } |
825 | ||
4cde8a21 | 826 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 827 | { |
c59423a3 | 828 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 829 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
830 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
831 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 832 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 833 | u32 hdmi_val; |
7d57382e | 834 | |
b242b7f7 | 835 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 836 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 837 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 838 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 839 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 840 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 841 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 842 | |
6e3c9717 | 843 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 844 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 845 | else |
4f3a8bc7 | 846 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 847 | |
6e3c9717 | 848 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 849 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 850 | |
75770564 | 851 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 852 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
853 | else if (IS_CHERRYVIEW(dev)) |
854 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 855 | else |
c59423a3 | 856 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 857 | |
b242b7f7 PZ |
858 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
859 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
860 | } |
861 | ||
85234cdc DV |
862 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
863 | enum pipe *pipe) | |
7d57382e | 864 | { |
85234cdc | 865 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 866 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 867 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 868 | enum intel_display_power_domain power_domain; |
85234cdc DV |
869 | u32 tmp; |
870 | ||
6d129bea | 871 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 872 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
873 | return false; |
874 | ||
b242b7f7 | 875 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
876 | |
877 | if (!(tmp & SDVO_ENABLE)) | |
878 | return false; | |
879 | ||
880 | if (HAS_PCH_CPT(dev)) | |
881 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
882 | else if (IS_CHERRYVIEW(dev)) |
883 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
884 | else |
885 | *pipe = PORT_TO_PIPE(tmp); | |
886 | ||
887 | return true; | |
888 | } | |
889 | ||
045ac3b5 | 890 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 891 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
892 | { |
893 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
894 | struct drm_device *dev = encoder->base.dev; |
895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 896 | u32 tmp, flags = 0; |
18442d08 | 897 | int dotclock; |
045ac3b5 JB |
898 | |
899 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
900 | ||
901 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
902 | flags |= DRM_MODE_FLAG_PHSYNC; | |
903 | else | |
904 | flags |= DRM_MODE_FLAG_NHSYNC; | |
905 | ||
906 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
907 | flags |= DRM_MODE_FLAG_PVSYNC; | |
908 | else | |
909 | flags |= DRM_MODE_FLAG_NVSYNC; | |
910 | ||
6897b4b5 DV |
911 | if (tmp & HDMI_MODE_SELECT_HDMI) |
912 | pipe_config->has_hdmi_sink = true; | |
913 | ||
e43823ec JB |
914 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
915 | pipe_config->has_infoframe = true; | |
916 | ||
c84db770 | 917 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
918 | pipe_config->has_audio = true; |
919 | ||
8c875fca VS |
920 | if (!HAS_PCH_SPLIT(dev) && |
921 | tmp & HDMI_COLOR_RANGE_16_235) | |
922 | pipe_config->limited_color_range = true; | |
923 | ||
2d112de7 | 924 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
925 | |
926 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
927 | dotclock = pipe_config->port_clock * 2 / 3; | |
928 | else | |
929 | dotclock = pipe_config->port_clock; | |
930 | ||
931 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
932 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
933 | ||
2d112de7 | 934 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
935 | } |
936 | ||
d1b1589c VS |
937 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
938 | { | |
939 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
940 | ||
941 | WARN_ON(!crtc->config->has_hdmi_sink); | |
942 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
943 | pipe_name(crtc->pipe)); | |
944 | intel_audio_codec_enable(encoder); | |
945 | } | |
946 | ||
bf868c7d | 947 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 948 | { |
5ab432ef | 949 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
bf868c7d | 951 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 952 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
953 | u32 temp; |
954 | ||
b242b7f7 | 955 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 956 | |
bf868c7d VS |
957 | temp |= SDVO_ENABLE; |
958 | if (crtc->config->has_audio) | |
959 | temp |= SDVO_AUDIO_ENABLE; | |
7a87c289 | 960 | |
bf868c7d VS |
961 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
962 | POSTING_READ(intel_hdmi->hdmi_reg); | |
963 | ||
964 | if (crtc->config->has_audio) | |
965 | intel_enable_hdmi_audio(encoder); | |
966 | } | |
967 | ||
968 | static void ibx_enable_hdmi(struct intel_encoder *encoder) | |
969 | { | |
970 | struct drm_device *dev = encoder->base.dev; | |
971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
972 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
973 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
974 | u32 temp; | |
975 | ||
976 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 977 | |
bf868c7d VS |
978 | temp |= SDVO_ENABLE; |
979 | if (crtc->config->has_audio) | |
980 | temp |= SDVO_AUDIO_ENABLE; | |
5ab432ef | 981 | |
bf868c7d VS |
982 | /* |
983 | * HW workaround, need to write this twice for issue | |
984 | * that may result in first write getting masked. | |
985 | */ | |
986 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
987 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
988 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
989 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 990 | |
bf868c7d VS |
991 | /* |
992 | * HW workaround, need to toggle enable bit off and on | |
993 | * for 12bpc with pixel repeat. | |
994 | * | |
995 | * FIXME: BSpec says this should be done at the end of | |
996 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 997 | */ |
bf868c7d VS |
998 | if (crtc->config->pipe_bpp > 24 && |
999 | crtc->config->pixel_multiplier > 1) { | |
1000 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); | |
1001 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1002 | ||
1003 | /* | |
1004 | * HW workaround, need to write this twice for issue | |
1005 | * that may result in first write getting masked. | |
1006 | */ | |
1007 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1008 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1009 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1010 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1011 | } |
c1dec79a | 1012 | |
bf868c7d | 1013 | if (crtc->config->has_audio) |
d1b1589c VS |
1014 | intel_enable_hdmi_audio(encoder); |
1015 | } | |
1016 | ||
1017 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
1018 | { | |
1019 | struct drm_device *dev = encoder->base.dev; | |
1020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1021 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1022 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1023 | enum pipe pipe = crtc->pipe; | |
1024 | u32 temp; | |
1025 | ||
1026 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1027 | ||
1028 | temp |= SDVO_ENABLE; | |
1029 | if (crtc->config->has_audio) | |
1030 | temp |= SDVO_AUDIO_ENABLE; | |
1031 | ||
1032 | /* | |
1033 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1034 | * | |
1035 | * The procedure for 12bpc is as follows: | |
1036 | * 1. disable HDMI clock gating | |
1037 | * 2. enable HDMI with 8bpc | |
1038 | * 3. enable HDMI with 12bpc | |
1039 | * 4. enable HDMI clock gating | |
1040 | */ | |
1041 | ||
1042 | if (crtc->config->pipe_bpp > 24) { | |
1043 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1044 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1045 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1046 | ||
1047 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1048 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1049 | } |
d1b1589c VS |
1050 | |
1051 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1052 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1053 | ||
1054 | if (crtc->config->pipe_bpp > 24) { | |
1055 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1056 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1057 | ||
1058 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1059 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1060 | ||
1061 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1062 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1063 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1064 | } | |
1065 | ||
1066 | if (crtc->config->has_audio) | |
1067 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 1068 | } |
89b667f8 | 1069 | |
b76cf76b JN |
1070 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1071 | { | |
5ab432ef DV |
1072 | } |
1073 | ||
1074 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
1075 | { | |
1076 | struct drm_device *dev = encoder->base.dev; | |
1077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1078 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 1079 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 1080 | u32 temp; |
5ab432ef | 1081 | |
b242b7f7 | 1082 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1083 | |
1612c8bd | 1084 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1085 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1086 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1087 | |
1088 | /* | |
1089 | * HW workaround for IBX, we need to move the port | |
1090 | * to transcoder A after disabling it to allow the | |
1091 | * matching DP port to be enabled on transcoder A. | |
1092 | */ | |
1093 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
1094 | temp &= ~SDVO_PIPE_B_SELECT; | |
1095 | temp |= SDVO_ENABLE; | |
1096 | /* | |
1097 | * HW workaround, need to write this twice for issue | |
1098 | * that may result in first write getting masked. | |
1099 | */ | |
1100 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1101 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1102 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1103 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1104 | ||
1105 | temp &= ~SDVO_ENABLE; | |
1106 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1107 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1108 | } | |
6d67415f VS |
1109 | |
1110 | intel_disable_gcp_infoframe(to_intel_crtc(encoder->base.crtc)); | |
7d57382e EA |
1111 | } |
1112 | ||
a4790cec VS |
1113 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1114 | { | |
1115 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1116 | ||
1117 | if (crtc->config->has_audio) | |
1118 | intel_audio_codec_disable(encoder); | |
1119 | ||
1120 | intel_disable_hdmi(encoder); | |
1121 | } | |
1122 | ||
1123 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
1124 | { | |
1125 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1126 | ||
1127 | if (crtc->config->has_audio) | |
1128 | intel_audio_codec_disable(encoder); | |
1129 | } | |
1130 | ||
1131 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
1132 | { | |
1133 | intel_disable_hdmi(encoder); | |
1134 | } | |
1135 | ||
40478455 | 1136 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
1137 | { |
1138 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1139 | ||
40478455 | 1140 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 1141 | return 165000; |
e3c33578 | 1142 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
1143 | return 300000; |
1144 | else | |
1145 | return 225000; | |
1146 | } | |
1147 | ||
c19de8eb DL |
1148 | static enum drm_mode_status |
1149 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1150 | struct drm_display_mode *mode) | |
7d57382e | 1151 | { |
697c4078 CT |
1152 | int clock = mode->clock; |
1153 | ||
1154 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
1155 | clock *= 2; | |
1156 | ||
1157 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
1158 | true)) | |
7d57382e | 1159 | return MODE_CLOCK_HIGH; |
697c4078 | 1160 | if (clock < 20000) |
5cbba41d | 1161 | return MODE_CLOCK_LOW; |
7d57382e EA |
1162 | |
1163 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1164 | return MODE_NO_DBLESCAN; | |
1165 | ||
1166 | return MODE_OK; | |
1167 | } | |
1168 | ||
77f06c86 | 1169 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1170 | { |
77f06c86 ACO |
1171 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1172 | struct drm_atomic_state *state; | |
71800632 | 1173 | struct intel_encoder *encoder; |
da3ced29 | 1174 | struct drm_connector *connector; |
77f06c86 | 1175 | struct drm_connector_state *connector_state; |
71800632 | 1176 | int count = 0, count_hdmi = 0; |
77f06c86 | 1177 | int i; |
71800632 | 1178 | |
f227ae9e | 1179 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1180 | return false; |
1181 | ||
77f06c86 ACO |
1182 | state = crtc_state->base.state; |
1183 | ||
da3ced29 | 1184 | for_each_connector_in_state(state, connector, connector_state, i) { |
77f06c86 ACO |
1185 | if (connector_state->crtc != crtc_state->base.crtc) |
1186 | continue; | |
1187 | ||
1188 | encoder = to_intel_encoder(connector_state->best_encoder); | |
1189 | ||
71800632 VS |
1190 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1191 | count++; | |
1192 | } | |
1193 | ||
1194 | /* | |
1195 | * HDMI 12bpc affects the clocks, so it's only possible | |
1196 | * when not cloning with other encoder types. | |
1197 | */ | |
1198 | return count_hdmi > 0 && count_hdmi == count; | |
1199 | } | |
1200 | ||
5bfe2ac0 | 1201 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1202 | struct intel_crtc_state *pipe_config) |
7d57382e | 1203 | { |
5bfe2ac0 DV |
1204 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1205 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 ACO |
1206 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1207 | int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2; | |
40478455 | 1208 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 1209 | int desired_bpp; |
3685a8f3 | 1210 | |
6897b4b5 DV |
1211 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1212 | ||
e43823ec JB |
1213 | if (pipe_config->has_hdmi_sink) |
1214 | pipe_config->has_infoframe = true; | |
1215 | ||
55bc60db VS |
1216 | if (intel_hdmi->color_range_auto) { |
1217 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 1218 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1219 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1220 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1221 | else |
1222 | intel_hdmi->color_range = 0; | |
1223 | } | |
1224 | ||
697c4078 CT |
1225 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1226 | pipe_config->pixel_multiplier = 2; | |
1227 | } | |
1228 | ||
3685a8f3 | 1229 | if (intel_hdmi->color_range) |
50f3b016 | 1230 | pipe_config->limited_color_range = true; |
3685a8f3 | 1231 | |
5bfe2ac0 DV |
1232 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1233 | pipe_config->has_pch_encoder = true; | |
1234 | ||
9ed109a7 DV |
1235 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1236 | pipe_config->has_audio = true; | |
1237 | ||
4e53c2e0 DV |
1238 | /* |
1239 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1240 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1241 | * outputs. We also need to check that the higher clock still fits |
1242 | * within limits. | |
4e53c2e0 | 1243 | */ |
6897b4b5 | 1244 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 | 1245 | clock_12bpc <= portclock_limit && |
5e3daaca DV |
1246 | hdmi_12bpc_possible(pipe_config) && |
1247 | 0 /* FIXME 12bpc support totally broken */) { | |
e29c22c0 DV |
1248 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1249 | desired_bpp = 12*3; | |
325b9d04 DV |
1250 | |
1251 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1252 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1253 | } else { |
e29c22c0 DV |
1254 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1255 | desired_bpp = 8*3; | |
1256 | } | |
1257 | ||
1258 | if (!pipe_config->bw_constrained) { | |
1259 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1260 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1261 | } |
1262 | ||
241bfc38 | 1263 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
1264 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
1265 | return false; | |
1266 | } | |
1267 | ||
7d57382e EA |
1268 | return true; |
1269 | } | |
1270 | ||
953ece69 CW |
1271 | static void |
1272 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1273 | { |
df0e9248 | 1274 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1275 | |
953ece69 CW |
1276 | intel_hdmi->has_hdmi_sink = false; |
1277 | intel_hdmi->has_audio = false; | |
1278 | intel_hdmi->rgb_quant_range_selectable = false; | |
1279 | ||
1280 | kfree(to_intel_connector(connector)->detect_edid); | |
1281 | to_intel_connector(connector)->detect_edid = NULL; | |
1282 | } | |
1283 | ||
1284 | static bool | |
1285 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1286 | { | |
1287 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1288 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1289 | struct intel_encoder *intel_encoder = | |
1290 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1291 | enum intel_display_power_domain power_domain; | |
1292 | struct edid *edid; | |
1293 | bool connected = false; | |
164c8598 | 1294 | |
671dedd2 ID |
1295 | power_domain = intel_display_port_power_domain(intel_encoder); |
1296 | intel_display_power_get(dev_priv, power_domain); | |
1297 | ||
f899fc64 | 1298 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1299 | intel_gmbus_get_adapter(dev_priv, |
1300 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1301 | |
953ece69 | 1302 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1303 | |
953ece69 CW |
1304 | to_intel_connector(connector)->detect_edid = edid; |
1305 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1306 | intel_hdmi->rgb_quant_range_selectable = | |
1307 | drm_rgb_quant_range_selectable(edid); | |
1308 | ||
1309 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1310 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1311 | intel_hdmi->has_audio = | |
953ece69 CW |
1312 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1313 | ||
1314 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1315 | intel_hdmi->has_hdmi_sink = | |
1316 | drm_detect_hdmi_monitor(edid); | |
1317 | ||
1318 | connected = true; | |
55b7d6e8 CW |
1319 | } |
1320 | ||
953ece69 CW |
1321 | return connected; |
1322 | } | |
1323 | ||
1324 | static enum drm_connector_status | |
1325 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1326 | { | |
1327 | enum drm_connector_status status; | |
1328 | ||
1329 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1330 | connector->base.id, connector->name); | |
1331 | ||
1332 | intel_hdmi_unset_edid(connector); | |
1333 | ||
1334 | if (intel_hdmi_set_edid(connector)) { | |
1335 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1336 | ||
1337 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1338 | status = connector_status_connected; | |
1339 | } else | |
1340 | status = connector_status_disconnected; | |
671dedd2 | 1341 | |
2ded9e27 | 1342 | return status; |
7d57382e EA |
1343 | } |
1344 | ||
953ece69 CW |
1345 | static void |
1346 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1347 | { |
953ece69 | 1348 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1349 | |
953ece69 CW |
1350 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1351 | connector->base.id, connector->name); | |
7d57382e | 1352 | |
953ece69 | 1353 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1354 | |
953ece69 CW |
1355 | if (connector->status != connector_status_connected) |
1356 | return; | |
671dedd2 | 1357 | |
953ece69 CW |
1358 | intel_hdmi_set_edid(connector); |
1359 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1360 | } | |
671dedd2 | 1361 | |
953ece69 CW |
1362 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1363 | { | |
1364 | struct edid *edid; | |
1365 | ||
1366 | edid = to_intel_connector(connector)->detect_edid; | |
1367 | if (edid == NULL) | |
1368 | return 0; | |
671dedd2 | 1369 | |
953ece69 | 1370 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1371 | } |
1372 | ||
1aad7ac0 CW |
1373 | static bool |
1374 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1375 | { | |
1aad7ac0 | 1376 | bool has_audio = false; |
953ece69 | 1377 | struct edid *edid; |
1aad7ac0 | 1378 | |
953ece69 CW |
1379 | edid = to_intel_connector(connector)->detect_edid; |
1380 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1381 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1382 | |
1aad7ac0 CW |
1383 | return has_audio; |
1384 | } | |
1385 | ||
55b7d6e8 CW |
1386 | static int |
1387 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1388 | struct drm_property *property, |
1389 | uint64_t val) | |
55b7d6e8 CW |
1390 | { |
1391 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1392 | struct intel_digital_port *intel_dig_port = |
1393 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1394 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1395 | int ret; |
1396 | ||
662595df | 1397 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1398 | if (ret) |
1399 | return ret; | |
1400 | ||
3f43c48d | 1401 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1402 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1403 | bool has_audio; |
1404 | ||
1405 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1406 | return 0; |
1407 | ||
1aad7ac0 | 1408 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1409 | |
b1d7e4b4 | 1410 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1411 | has_audio = intel_hdmi_detect_audio(connector); |
1412 | else | |
b1d7e4b4 | 1413 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1414 | |
b1d7e4b4 WF |
1415 | if (i == HDMI_AUDIO_OFF_DVI) |
1416 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1417 | |
1aad7ac0 | 1418 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1419 | goto done; |
1420 | } | |
1421 | ||
e953fd7b | 1422 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1423 | bool old_auto = intel_hdmi->color_range_auto; |
1424 | uint32_t old_range = intel_hdmi->color_range; | |
1425 | ||
55bc60db VS |
1426 | switch (val) { |
1427 | case INTEL_BROADCAST_RGB_AUTO: | |
1428 | intel_hdmi->color_range_auto = true; | |
1429 | break; | |
1430 | case INTEL_BROADCAST_RGB_FULL: | |
1431 | intel_hdmi->color_range_auto = false; | |
1432 | intel_hdmi->color_range = 0; | |
1433 | break; | |
1434 | case INTEL_BROADCAST_RGB_LIMITED: | |
1435 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1436 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1437 | break; |
1438 | default: | |
1439 | return -EINVAL; | |
1440 | } | |
ae4edb80 DV |
1441 | |
1442 | if (old_auto == intel_hdmi->color_range_auto && | |
1443 | old_range == intel_hdmi->color_range) | |
1444 | return 0; | |
1445 | ||
e953fd7b CW |
1446 | goto done; |
1447 | } | |
1448 | ||
94a11ddc VK |
1449 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1450 | switch (val) { | |
1451 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1452 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1453 | break; | |
1454 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1455 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1456 | break; | |
1457 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1458 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1459 | break; | |
1460 | default: | |
1461 | return -EINVAL; | |
1462 | } | |
1463 | goto done; | |
1464 | } | |
1465 | ||
55b7d6e8 CW |
1466 | return -EINVAL; |
1467 | ||
1468 | done: | |
c0c36b94 CW |
1469 | if (intel_dig_port->base.base.crtc) |
1470 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1471 | |
1472 | return 0; | |
1473 | } | |
1474 | ||
13732ba7 JB |
1475 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1476 | { | |
1477 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1478 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1479 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 1480 | &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1481 | |
4cde8a21 DV |
1482 | intel_hdmi_prepare(encoder); |
1483 | ||
6897b4b5 | 1484 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1485 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1486 | adjusted_mode); |
13732ba7 JB |
1487 | } |
1488 | ||
9514ac6e | 1489 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1490 | { |
1491 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1492 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1493 | struct drm_device *dev = encoder->base.dev; |
1494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1495 | struct intel_crtc *intel_crtc = | |
1496 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 | 1497 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1498 | &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1499 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1500 | int pipe = intel_crtc->pipe; |
1501 | u32 val; | |
1502 | ||
89b667f8 | 1503 | /* Enable clock channels for this port */ |
a580516d | 1504 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1505 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1506 | val = 0; |
1507 | if (pipe) | |
1508 | val |= (1<<21); | |
1509 | else | |
1510 | val &= ~(1<<21); | |
1511 | val |= 0x001000c4; | |
ab3c759a | 1512 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1513 | |
1514 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1515 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1516 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1517 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1518 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1519 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1520 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1521 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1522 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1523 | |
1524 | /* Program lane clock */ | |
ab3c759a CML |
1525 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1526 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
a580516d | 1527 | mutex_unlock(&dev_priv->sb_lock); |
b76cf76b | 1528 | |
6897b4b5 | 1529 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1530 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1531 | adjusted_mode); |
13732ba7 | 1532 | |
bf868c7d | 1533 | g4x_enable_hdmi(encoder); |
b76cf76b | 1534 | |
9b6de0a1 | 1535 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1536 | } |
1537 | ||
9514ac6e | 1538 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1539 | { |
1540 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1541 | struct drm_device *dev = encoder->base.dev; | |
1542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1543 | struct intel_crtc *intel_crtc = |
1544 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1545 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1546 | int pipe = intel_crtc->pipe; |
89b667f8 | 1547 | |
4cde8a21 DV |
1548 | intel_hdmi_prepare(encoder); |
1549 | ||
89b667f8 | 1550 | /* Program Tx lane resets to default */ |
a580516d | 1551 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1552 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1553 | DPIO_PCS_TX_LANE2_RESET | |
1554 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1555 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1556 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1557 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1558 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1559 | DPIO_PCS_CLK_SOFT_RESET); | |
1560 | ||
1561 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1562 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1563 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1564 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1565 | ||
1566 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1567 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
a580516d | 1568 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1569 | } |
1570 | ||
9197c88b VS |
1571 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1572 | { | |
1573 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1574 | struct drm_device *dev = encoder->base.dev; | |
1575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1576 | struct intel_crtc *intel_crtc = | |
1577 | to_intel_crtc(encoder->base.crtc); | |
1578 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1579 | enum pipe pipe = intel_crtc->pipe; | |
1580 | u32 val; | |
1581 | ||
625695f8 VS |
1582 | intel_hdmi_prepare(encoder); |
1583 | ||
a580516d | 1584 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 1585 | |
b9e5ac3c VS |
1586 | /* program left/right clock distribution */ |
1587 | if (pipe != PIPE_B) { | |
1588 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1589 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1590 | if (ch == DPIO_CH0) | |
1591 | val |= CHV_BUFLEFTENA1_FORCE; | |
1592 | if (ch == DPIO_CH1) | |
1593 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1594 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1595 | } else { | |
1596 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1597 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1598 | if (ch == DPIO_CH0) | |
1599 | val |= CHV_BUFLEFTENA2_FORCE; | |
1600 | if (ch == DPIO_CH1) | |
1601 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1602 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1603 | } | |
1604 | ||
9197c88b VS |
1605 | /* program clock channel usage */ |
1606 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1607 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1608 | if (pipe != PIPE_B) | |
1609 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1610 | else | |
1611 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1612 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1613 | ||
1614 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1615 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1616 | if (pipe != PIPE_B) | |
1617 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1618 | else | |
1619 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1620 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1621 | ||
1622 | /* | |
1623 | * This a a bit weird since generally CL | |
1624 | * matches the pipe, but here we need to | |
1625 | * pick the CL based on the port. | |
1626 | */ | |
1627 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1628 | if (pipe != PIPE_B) | |
1629 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1630 | else | |
1631 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1632 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1633 | ||
a580516d | 1634 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
1635 | } |
1636 | ||
9514ac6e | 1637 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1638 | { |
1639 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1640 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1641 | struct intel_crtc *intel_crtc = |
1642 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1643 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1644 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1645 | |
1646 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
a580516d | 1647 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
1648 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1649 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
a580516d | 1650 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1651 | } |
1652 | ||
580d3811 VS |
1653 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1654 | { | |
1655 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1656 | struct drm_device *dev = encoder->base.dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | struct intel_crtc *intel_crtc = | |
1659 | to_intel_crtc(encoder->base.crtc); | |
1660 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1661 | enum pipe pipe = intel_crtc->pipe; | |
1662 | u32 val; | |
1663 | ||
a580516d | 1664 | mutex_lock(&dev_priv->sb_lock); |
580d3811 VS |
1665 | |
1666 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1667 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1668 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1669 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1670 | |
97fd4d5c VS |
1671 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1672 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1673 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1674 | ||
1675 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1676 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1677 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1678 | ||
1679 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1680 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1681 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 | 1682 | |
a580516d | 1683 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1684 | } |
1685 | ||
e4a1d846 CML |
1686 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1687 | { | |
1688 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1689 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1690 | struct drm_device *dev = encoder->base.dev; |
1691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1692 | struct intel_crtc *intel_crtc = | |
1693 | to_intel_crtc(encoder->base.crtc); | |
b4eb1564 | 1694 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1695 | &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1696 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1697 | int pipe = intel_crtc->pipe; | |
2e523e98 | 1698 | int data, i, stagger; |
e4a1d846 CML |
1699 | u32 val; |
1700 | ||
a580516d | 1701 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 1702 | |
570e2a74 VS |
1703 | /* allow hardware to manage TX FIFO reset source */ |
1704 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1705 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1706 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1707 | ||
1708 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1709 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1710 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1711 | ||
949c1d43 | 1712 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1713 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1714 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1715 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1716 | ||
1717 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1718 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1719 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1720 | ||
1721 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1722 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1723 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1724 | |
97fd4d5c | 1725 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1726 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1727 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1728 | |
1729 | /* Program Tx latency optimal setting */ | |
e4a1d846 | 1730 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
1731 | /* Set the upar bit */ |
1732 | data = (i == 1) ? 0x0 : 0x1; | |
1733 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1734 | data << DPIO_UPAR_SHIFT); | |
1735 | } | |
1736 | ||
1737 | /* Data lane stagger programming */ | |
2e523e98 VS |
1738 | if (intel_crtc->config->port_clock > 270000) |
1739 | stagger = 0x18; | |
1740 | else if (intel_crtc->config->port_clock > 135000) | |
1741 | stagger = 0xd; | |
1742 | else if (intel_crtc->config->port_clock > 67500) | |
1743 | stagger = 0x7; | |
1744 | else if (intel_crtc->config->port_clock > 33750) | |
1745 | stagger = 0x4; | |
1746 | else | |
1747 | stagger = 0x2; | |
1748 | ||
1749 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1750 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1751 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1752 | ||
1753 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1754 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1755 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1756 | ||
1757 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
1758 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1759 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1760 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1761 | DPIO_TX1_STAGGER_MULT(6) | | |
1762 | DPIO_TX2_STAGGER_MULT(0)); | |
1763 | ||
1764 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
1765 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1766 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1767 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1768 | DPIO_TX1_STAGGER_MULT(7) | | |
1769 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 CML |
1770 | |
1771 | /* Clear calc init */ | |
1966e59e VS |
1772 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1773 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1774 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1775 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1776 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1777 | ||
1778 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1779 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1780 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1781 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1782 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1783 | |
a02ef3c7 VS |
1784 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1785 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1786 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1787 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1788 | ||
1789 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1790 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1791 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1792 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1793 | ||
e4a1d846 CML |
1794 | /* FIXME: Program the support xxx V-dB */ |
1795 | /* Use 800mV-0dB */ | |
f72df8db VS |
1796 | for (i = 0; i < 4; i++) { |
1797 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1798 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1799 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1800 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1801 | } | |
e4a1d846 | 1802 | |
f72df8db VS |
1803 | for (i = 0; i < 4; i++) { |
1804 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1805 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1806 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1807 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1808 | } | |
e4a1d846 CML |
1809 | |
1810 | /* Disable unique transition scale */ | |
f72df8db VS |
1811 | for (i = 0; i < 4; i++) { |
1812 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1813 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1814 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1815 | } | |
e4a1d846 CML |
1816 | |
1817 | /* Additional steps for 1200mV-0dB */ | |
1818 | #if 0 | |
1819 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1820 | if (ch) | |
1821 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1822 | else | |
1823 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1824 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1825 | ||
1826 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1827 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1828 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1829 | #endif | |
1830 | /* Start swing calculation */ | |
1966e59e VS |
1831 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1832 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1833 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1834 | ||
1835 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1836 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1837 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1838 | |
1839 | /* LRC Bypass */ | |
1840 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1841 | val |= DPIO_LRC_BYPASS; | |
1842 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1843 | ||
a580516d | 1844 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 1845 | |
b4eb1564 | 1846 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1847 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1848 | adjusted_mode); |
1849 | ||
bf868c7d | 1850 | g4x_enable_hdmi(encoder); |
e4a1d846 | 1851 | |
9b6de0a1 | 1852 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
e4a1d846 CML |
1853 | } |
1854 | ||
7d57382e EA |
1855 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1856 | { | |
10e972d3 | 1857 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1858 | drm_connector_cleanup(connector); |
674e2d08 | 1859 | kfree(connector); |
7d57382e EA |
1860 | } |
1861 | ||
7d57382e | 1862 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1863 | .dpms = intel_connector_dpms, |
7d57382e | 1864 | .detect = intel_hdmi_detect, |
953ece69 | 1865 | .force = intel_hdmi_force, |
7d57382e | 1866 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1867 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1868 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 1869 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1870 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1871 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1872 | }; |
1873 | ||
1874 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1875 | .get_modes = intel_hdmi_get_modes, | |
1876 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1877 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1878 | }; |
1879 | ||
7d57382e | 1880 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1881 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1882 | }; |
1883 | ||
94a11ddc VK |
1884 | static void |
1885 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1886 | { | |
1887 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1888 | drm_object_attach_property(&connector->base, | |
1889 | connector->dev->mode_config.aspect_ratio_property, | |
1890 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1891 | } | |
1892 | ||
55b7d6e8 CW |
1893 | static void |
1894 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1895 | { | |
3f43c48d | 1896 | intel_attach_force_audio_property(connector); |
e953fd7b | 1897 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1898 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1899 | intel_attach_aspect_ratio_property(connector); |
1900 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1901 | } |
1902 | ||
00c09d70 PZ |
1903 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1904 | struct intel_connector *intel_connector) | |
7d57382e | 1905 | { |
b9cb234c PZ |
1906 | struct drm_connector *connector = &intel_connector->base; |
1907 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1908 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1909 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1910 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1911 | enum port port = intel_dig_port->port; |
373a3cf7 | 1912 | |
7d57382e | 1913 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1914 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1915 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1916 | ||
c3febcc4 | 1917 | connector->interlace_allowed = 1; |
7d57382e | 1918 | connector->doublescan_allowed = 0; |
573e74ad | 1919 | connector->stereo_allowed = 1; |
66a9278e | 1920 | |
08d644ad DV |
1921 | switch (port) { |
1922 | case PORT_B: | |
4c272834 JN |
1923 | if (IS_BROXTON(dev_priv)) |
1924 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
1925 | else | |
1926 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
1d843f9d | 1927 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1928 | break; |
1929 | case PORT_C: | |
4c272834 JN |
1930 | if (IS_BROXTON(dev_priv)) |
1931 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
1932 | else | |
1933 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 1934 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1935 | break; |
1936 | case PORT_D: | |
4c272834 JN |
1937 | if (WARN_ON(IS_BROXTON(dev_priv))) |
1938 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
1939 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 1940 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 1941 | else |
988c7015 | 1942 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 1943 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1944 | break; |
1945 | case PORT_A: | |
1d843f9d | 1946 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1947 | /* Internal port only for eDP. */ |
1948 | default: | |
6e4c1677 | 1949 | BUG(); |
f8aed700 | 1950 | } |
7d57382e | 1951 | |
7637bfdb | 1952 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1953 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1954 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1955 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1956 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1957 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1958 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1959 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1960 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1961 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1962 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1963 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1964 | } else if (HAS_PCH_IBX(dev)) { |
1965 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1966 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1967 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1968 | } else { |
1969 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1970 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1971 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1972 | } |
45187ace | 1973 | |
affa9354 | 1974 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1975 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1976 | else | |
1977 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1978 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1979 | |
1980 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1981 | ||
1982 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1983 | drm_connector_register(connector); |
b9cb234c PZ |
1984 | |
1985 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1986 | * 0xd. Failure to do so will result in spurious interrupts being | |
1987 | * generated on the port when a cable is not attached. | |
1988 | */ | |
1989 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1990 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1991 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1992 | } | |
1993 | } | |
1994 | ||
b242b7f7 | 1995 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1996 | { |
1997 | struct intel_digital_port *intel_dig_port; | |
1998 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1999 | struct intel_connector *intel_connector; |
2000 | ||
b14c5679 | 2001 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2002 | if (!intel_dig_port) |
2003 | return; | |
2004 | ||
08d9bc92 | 2005 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2006 | if (!intel_connector) { |
2007 | kfree(intel_dig_port); | |
2008 | return; | |
2009 | } | |
2010 | ||
2011 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
2012 | |
2013 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
2014 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 2015 | |
5bfe2ac0 | 2016 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
2017 | if (HAS_PCH_SPLIT(dev)) { |
2018 | intel_encoder->disable = pch_disable_hdmi; | |
2019 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2020 | } else { | |
2021 | intel_encoder->disable = g4x_disable_hdmi; | |
2022 | } | |
00c09d70 | 2023 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2024 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 2025 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 2026 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2027 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2028 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2029 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 2030 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
2031 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2032 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2033 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2034 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2035 | } else { |
13732ba7 | 2036 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
2037 | if (HAS_PCH_CPT(dev)) |
2038 | intel_encoder->enable = cpt_enable_hdmi; | |
bf868c7d VS |
2039 | else if (HAS_PCH_IBX(dev)) |
2040 | intel_encoder->enable = ibx_enable_hdmi; | |
d1b1589c | 2041 | else |
bf868c7d | 2042 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2043 | } |
5ab432ef | 2044 | |
b9cb234c | 2045 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
2046 | if (IS_CHERRYVIEW(dev)) { |
2047 | if (port == PORT_D) | |
2048 | intel_encoder->crtc_mask = 1 << 2; | |
2049 | else | |
2050 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2051 | } else { | |
2052 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2053 | } | |
301ea74a | 2054 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2055 | /* |
2056 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2057 | * to work on real hardware. And since g4x can send infoframes to | |
2058 | * only one port anyway, nothing is lost by allowing it. | |
2059 | */ | |
2060 | if (IS_G4X(dev)) | |
2061 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 2062 | |
174edf1f | 2063 | intel_dig_port->port = port; |
b242b7f7 | 2064 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 2065 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 2066 | |
b9cb234c | 2067 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2068 | } |