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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
178f736a | 81 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
178f736a | 96 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
178f736a | 111 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
178f736a | 116 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
117 | enum transcoder cpu_transcoder, |
118 | struct drm_i915_private *dev_priv) | |
2da8af54 | 119 | { |
178f736a DL |
120 | switch (type) { |
121 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 122 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 123 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 124 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
125 | case HDMI_INFOFRAME_TYPE_VENDOR: |
126 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 127 | default: |
178f736a | 128 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
129 | return 0; |
130 | } | |
131 | } | |
132 | ||
a3da1df7 | 133 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 134 | enum hdmi_infoframe_type type, |
fff63867 | 135 | const void *frame, ssize_t len) |
45187ace | 136 | { |
fff63867 | 137 | const uint32_t *data = frame; |
3c17fe4b DH |
138 | struct drm_device *dev = encoder->dev; |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 141 | int i; |
3c17fe4b | 142 | |
822974ae PZ |
143 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
144 | ||
1d4f85ac | 145 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 146 | val |= g4x_infoframe_index(type); |
22509ec8 | 147 | |
178f736a | 148 | val &= ~g4x_infoframe_enable(type); |
45187ace | 149 | |
22509ec8 | 150 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 151 | |
9d9740f0 | 152 | mmiowb(); |
45187ace | 153 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
154 | I915_WRITE(VIDEO_DIP_DATA, *data); |
155 | data++; | |
156 | } | |
adf00b26 PZ |
157 | /* Write every possible data byte to force correct ECC calculation. */ |
158 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
159 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 160 | mmiowb(); |
3c17fe4b | 161 | |
178f736a | 162 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 163 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 164 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 165 | |
22509ec8 | 166 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 167 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
168 | } |
169 | ||
e43823ec JB |
170 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder) |
171 | { | |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
89a35ecd | 174 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
175 | u32 val = I915_READ(VIDEO_DIP_CTL); |
176 | ||
89a35ecd JB |
177 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
178 | return val & VIDEO_DIP_ENABLE; | |
179 | ||
180 | return false; | |
e43823ec JB |
181 | } |
182 | ||
fdf1250a | 183 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 184 | enum hdmi_infoframe_type type, |
fff63867 | 185 | const void *frame, ssize_t len) |
fdf1250a | 186 | { |
fff63867 | 187 | const uint32_t *data = frame; |
fdf1250a PZ |
188 | struct drm_device *dev = encoder->dev; |
189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 190 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 191 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
192 | u32 val = I915_READ(reg); |
193 | ||
822974ae PZ |
194 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
195 | ||
fdf1250a | 196 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 197 | val |= g4x_infoframe_index(type); |
fdf1250a | 198 | |
178f736a | 199 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
200 | |
201 | I915_WRITE(reg, val); | |
202 | ||
9d9740f0 | 203 | mmiowb(); |
fdf1250a PZ |
204 | for (i = 0; i < len; i += 4) { |
205 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
206 | data++; | |
207 | } | |
adf00b26 PZ |
208 | /* Write every possible data byte to force correct ECC calculation. */ |
209 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
210 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 211 | mmiowb(); |
fdf1250a | 212 | |
178f736a | 213 | val |= g4x_infoframe_enable(type); |
fdf1250a | 214 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 215 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
216 | |
217 | I915_WRITE(reg, val); | |
9d9740f0 | 218 | POSTING_READ(reg); |
fdf1250a PZ |
219 | } |
220 | ||
e43823ec JB |
221 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder) |
222 | { | |
223 | struct drm_device *dev = encoder->dev; | |
224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
225 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
052f62f7 | 226 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
227 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
228 | u32 val = I915_READ(reg); | |
229 | ||
052f62f7 JN |
230 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
231 | return val & VIDEO_DIP_ENABLE; | |
232 | ||
233 | return false; | |
e43823ec JB |
234 | } |
235 | ||
fdf1250a | 236 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 237 | enum hdmi_infoframe_type type, |
fff63867 | 238 | const void *frame, ssize_t len) |
b055c8f3 | 239 | { |
fff63867 | 240 | const uint32_t *data = frame; |
b055c8f3 JB |
241 | struct drm_device *dev = encoder->dev; |
242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 243 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 244 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 245 | u32 val = I915_READ(reg); |
b055c8f3 | 246 | |
822974ae PZ |
247 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
248 | ||
64a8fc01 | 249 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 250 | val |= g4x_infoframe_index(type); |
45187ace | 251 | |
ecb97851 PZ |
252 | /* The DIP control register spec says that we need to update the AVI |
253 | * infoframe without clearing its enable bit */ | |
178f736a DL |
254 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
255 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 256 | |
22509ec8 | 257 | I915_WRITE(reg, val); |
45187ace | 258 | |
9d9740f0 | 259 | mmiowb(); |
45187ace | 260 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
261 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
262 | data++; | |
263 | } | |
adf00b26 PZ |
264 | /* Write every possible data byte to force correct ECC calculation. */ |
265 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
266 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 267 | mmiowb(); |
b055c8f3 | 268 | |
178f736a | 269 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 270 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 271 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 272 | |
22509ec8 | 273 | I915_WRITE(reg, val); |
9d9740f0 | 274 | POSTING_READ(reg); |
45187ace | 275 | } |
90b107c8 | 276 | |
e43823ec JB |
277 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder) |
278 | { | |
279 | struct drm_device *dev = encoder->dev; | |
280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
281 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
282 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
283 | u32 val = I915_READ(reg); | |
284 | ||
285 | return val & VIDEO_DIP_ENABLE; | |
286 | } | |
287 | ||
90b107c8 | 288 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 289 | enum hdmi_infoframe_type type, |
fff63867 | 290 | const void *frame, ssize_t len) |
90b107c8 | 291 | { |
fff63867 | 292 | const uint32_t *data = frame; |
90b107c8 SK |
293 | struct drm_device *dev = encoder->dev; |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 296 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 297 | u32 val = I915_READ(reg); |
90b107c8 | 298 | |
822974ae PZ |
299 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
300 | ||
90b107c8 | 301 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 302 | val |= g4x_infoframe_index(type); |
22509ec8 | 303 | |
178f736a | 304 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 305 | |
22509ec8 | 306 | I915_WRITE(reg, val); |
90b107c8 | 307 | |
9d9740f0 | 308 | mmiowb(); |
90b107c8 SK |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 316 | mmiowb(); |
90b107c8 | 317 | |
178f736a | 318 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 319 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 320 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 321 | |
22509ec8 | 322 | I915_WRITE(reg, val); |
9d9740f0 | 323 | POSTING_READ(reg); |
90b107c8 SK |
324 | } |
325 | ||
e43823ec JB |
326 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder) |
327 | { | |
328 | struct drm_device *dev = encoder->dev; | |
329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
330 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
535afa2e | 331 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
332 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
333 | u32 val = I915_READ(reg); | |
334 | ||
eeea3e67 | 335 | if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK)) |
535afa2e JB |
336 | return val & VIDEO_DIP_ENABLE; |
337 | ||
338 | return false; | |
e43823ec JB |
339 | } |
340 | ||
8c5f5f7c | 341 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 342 | enum hdmi_infoframe_type type, |
fff63867 | 343 | const void *frame, ssize_t len) |
8c5f5f7c | 344 | { |
fff63867 | 345 | const uint32_t *data = frame; |
2da8af54 PZ |
346 | struct drm_device *dev = encoder->dev; |
347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
348 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 349 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
178f736a DL |
350 | u32 data_reg; |
351 | int i; | |
2da8af54 | 352 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 353 | |
178f736a | 354 | data_reg = hsw_infoframe_data_reg(type, |
6e3c9717 | 355 | intel_crtc->config->cpu_transcoder, |
a57c774a | 356 | dev_priv); |
2da8af54 PZ |
357 | if (data_reg == 0) |
358 | return; | |
359 | ||
178f736a | 360 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
361 | I915_WRITE(ctl_reg, val); |
362 | ||
9d9740f0 | 363 | mmiowb(); |
2da8af54 PZ |
364 | for (i = 0; i < len; i += 4) { |
365 | I915_WRITE(data_reg + i, *data); | |
366 | data++; | |
367 | } | |
adf00b26 PZ |
368 | /* Write every possible data byte to force correct ECC calculation. */ |
369 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
370 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 371 | mmiowb(); |
8c5f5f7c | 372 | |
178f736a | 373 | val |= hsw_infoframe_enable(type); |
2da8af54 | 374 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 375 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
376 | } |
377 | ||
e43823ec JB |
378 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder) |
379 | { | |
380 | struct drm_device *dev = encoder->dev; | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
6e3c9717 | 383 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
e43823ec JB |
384 | u32 val = I915_READ(ctl_reg); |
385 | ||
386 | return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | | |
387 | VIDEO_DIP_ENABLE_VS_HSW); | |
388 | } | |
389 | ||
5adaea79 DL |
390 | /* |
391 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
392 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
393 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
394 | * used for both technologies. | |
395 | * | |
396 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
397 | * DW1: DB3 | DB2 | DB1 | DB0 | |
398 | * DW2: DB7 | DB6 | DB5 | DB4 | |
399 | * DW3: ... | |
400 | * | |
401 | * (HB is Header Byte, DB is Data Byte) | |
402 | * | |
403 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
404 | * trick them by giving an offset into the buffer and moving back the header | |
405 | * bytes by one. | |
406 | */ | |
9198ee5b DL |
407 | static void intel_write_infoframe(struct drm_encoder *encoder, |
408 | union hdmi_infoframe *frame) | |
45187ace JB |
409 | { |
410 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
411 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
412 | ssize_t len; | |
45187ace | 413 | |
5adaea79 DL |
414 | /* see comment above for the reason for this offset */ |
415 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
416 | if (len < 0) | |
417 | return; | |
418 | ||
419 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
420 | buffer[0] = buffer[1]; | |
421 | buffer[1] = buffer[2]; | |
422 | buffer[2] = buffer[3]; | |
423 | buffer[3] = 0; | |
424 | len++; | |
45187ace | 425 | |
5adaea79 | 426 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
427 | } |
428 | ||
687f4d06 | 429 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 430 | struct drm_display_mode *adjusted_mode) |
45187ace | 431 | { |
abedc077 | 432 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 433 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
434 | union hdmi_infoframe frame; |
435 | int ret; | |
45187ace | 436 | |
94a11ddc VK |
437 | /* Set user selected PAR to incoming mode's member */ |
438 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
439 | ||
5adaea79 DL |
440 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
441 | adjusted_mode); | |
442 | if (ret < 0) { | |
443 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
444 | return; | |
445 | } | |
c846b619 | 446 | |
abedc077 | 447 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 448 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
449 | frame.avi.quantization_range = |
450 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 451 | else |
5adaea79 DL |
452 | frame.avi.quantization_range = |
453 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
454 | } |
455 | ||
9198ee5b | 456 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
457 | } |
458 | ||
687f4d06 | 459 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 460 | { |
5adaea79 DL |
461 | union hdmi_infoframe frame; |
462 | int ret; | |
463 | ||
464 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
465 | if (ret < 0) { | |
466 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
467 | return; | |
468 | } | |
c0864cb3 | 469 | |
5adaea79 | 470 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 471 | |
9198ee5b | 472 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
473 | } |
474 | ||
c8bb75af LD |
475 | static void |
476 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
477 | struct drm_display_mode *adjusted_mode) | |
478 | { | |
479 | union hdmi_infoframe frame; | |
480 | int ret; | |
481 | ||
482 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
483 | adjusted_mode); | |
484 | if (ret < 0) | |
485 | return; | |
486 | ||
487 | intel_write_infoframe(encoder, &frame); | |
488 | } | |
489 | ||
687f4d06 | 490 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 491 | bool enable, |
687f4d06 PZ |
492 | struct drm_display_mode *adjusted_mode) |
493 | { | |
0c14c7f9 | 494 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
495 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
496 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
497 | u32 reg = VIDEO_DIP_CTL; |
498 | u32 val = I915_READ(reg); | |
822cdc52 | 499 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 500 | |
afba0188 DV |
501 | assert_hdmi_port_disabled(intel_hdmi); |
502 | ||
0c14c7f9 PZ |
503 | /* If the registers were not initialized yet, they might be zeroes, |
504 | * which means we're selecting the AVI DIP and we're setting its | |
505 | * frequency to once. This seems to really confuse the HW and make | |
506 | * things stop working (the register spec says the AVI always needs to | |
507 | * be sent every VSync). So here we avoid writing to the register more | |
508 | * than we need and also explicitly select the AVI DIP and explicitly | |
509 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
510 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
511 | * either. */ | |
512 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
513 | ||
6897b4b5 | 514 | if (!enable) { |
0c14c7f9 PZ |
515 | if (!(val & VIDEO_DIP_ENABLE)) |
516 | return; | |
517 | val &= ~VIDEO_DIP_ENABLE; | |
518 | I915_WRITE(reg, val); | |
9d9740f0 | 519 | POSTING_READ(reg); |
0c14c7f9 PZ |
520 | return; |
521 | } | |
522 | ||
72b78c9d PZ |
523 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
524 | if (val & VIDEO_DIP_ENABLE) { | |
525 | val &= ~VIDEO_DIP_ENABLE; | |
526 | I915_WRITE(reg, val); | |
9d9740f0 | 527 | POSTING_READ(reg); |
72b78c9d PZ |
528 | } |
529 | val &= ~VIDEO_DIP_PORT_MASK; | |
530 | val |= port; | |
531 | } | |
532 | ||
822974ae | 533 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 534 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 535 | |
f278d972 | 536 | I915_WRITE(reg, val); |
9d9740f0 | 537 | POSTING_READ(reg); |
f278d972 | 538 | |
687f4d06 PZ |
539 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
540 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 541 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
542 | } |
543 | ||
544 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 545 | bool enable, |
687f4d06 PZ |
546 | struct drm_display_mode *adjusted_mode) |
547 | { | |
0c14c7f9 PZ |
548 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
549 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
550 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
551 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
552 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
553 | u32 val = I915_READ(reg); | |
822cdc52 | 554 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 555 | |
afba0188 DV |
556 | assert_hdmi_port_disabled(intel_hdmi); |
557 | ||
0c14c7f9 PZ |
558 | /* See the big comment in g4x_set_infoframes() */ |
559 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
560 | ||
6897b4b5 | 561 | if (!enable) { |
0c14c7f9 PZ |
562 | if (!(val & VIDEO_DIP_ENABLE)) |
563 | return; | |
564 | val &= ~VIDEO_DIP_ENABLE; | |
565 | I915_WRITE(reg, val); | |
9d9740f0 | 566 | POSTING_READ(reg); |
0c14c7f9 PZ |
567 | return; |
568 | } | |
569 | ||
72b78c9d PZ |
570 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
571 | if (val & VIDEO_DIP_ENABLE) { | |
572 | val &= ~VIDEO_DIP_ENABLE; | |
573 | I915_WRITE(reg, val); | |
9d9740f0 | 574 | POSTING_READ(reg); |
72b78c9d PZ |
575 | } |
576 | val &= ~VIDEO_DIP_PORT_MASK; | |
577 | val |= port; | |
578 | } | |
579 | ||
822974ae | 580 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
581 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
582 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 583 | |
f278d972 | 584 | I915_WRITE(reg, val); |
9d9740f0 | 585 | POSTING_READ(reg); |
f278d972 | 586 | |
687f4d06 PZ |
587 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
588 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 589 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
590 | } |
591 | ||
592 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 593 | bool enable, |
687f4d06 PZ |
594 | struct drm_display_mode *adjusted_mode) |
595 | { | |
0c14c7f9 PZ |
596 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
597 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
598 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
599 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
600 | u32 val = I915_READ(reg); | |
601 | ||
afba0188 DV |
602 | assert_hdmi_port_disabled(intel_hdmi); |
603 | ||
0c14c7f9 PZ |
604 | /* See the big comment in g4x_set_infoframes() */ |
605 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
606 | ||
6897b4b5 | 607 | if (!enable) { |
0c14c7f9 PZ |
608 | if (!(val & VIDEO_DIP_ENABLE)) |
609 | return; | |
610 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
611 | I915_WRITE(reg, val); | |
9d9740f0 | 612 | POSTING_READ(reg); |
0c14c7f9 PZ |
613 | return; |
614 | } | |
615 | ||
822974ae PZ |
616 | /* Set both together, unset both together: see the spec. */ |
617 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
618 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
619 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
620 | |
621 | I915_WRITE(reg, val); | |
9d9740f0 | 622 | POSTING_READ(reg); |
822974ae | 623 | |
687f4d06 PZ |
624 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
625 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 626 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
627 | } |
628 | ||
629 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 630 | bool enable, |
687f4d06 PZ |
631 | struct drm_display_mode *adjusted_mode) |
632 | { | |
0c14c7f9 | 633 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 634 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
635 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
636 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
637 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
638 | u32 val = I915_READ(reg); | |
6a2b8021 | 639 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 640 | |
afba0188 DV |
641 | assert_hdmi_port_disabled(intel_hdmi); |
642 | ||
0c14c7f9 PZ |
643 | /* See the big comment in g4x_set_infoframes() */ |
644 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
645 | ||
6897b4b5 | 646 | if (!enable) { |
0c14c7f9 PZ |
647 | if (!(val & VIDEO_DIP_ENABLE)) |
648 | return; | |
649 | val &= ~VIDEO_DIP_ENABLE; | |
650 | I915_WRITE(reg, val); | |
9d9740f0 | 651 | POSTING_READ(reg); |
0c14c7f9 PZ |
652 | return; |
653 | } | |
654 | ||
6a2b8021 JB |
655 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
656 | if (val & VIDEO_DIP_ENABLE) { | |
657 | val &= ~VIDEO_DIP_ENABLE; | |
658 | I915_WRITE(reg, val); | |
659 | POSTING_READ(reg); | |
660 | } | |
661 | val &= ~VIDEO_DIP_PORT_MASK; | |
662 | val |= port; | |
663 | } | |
664 | ||
822974ae | 665 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
666 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
667 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
668 | |
669 | I915_WRITE(reg, val); | |
9d9740f0 | 670 | POSTING_READ(reg); |
822974ae | 671 | |
687f4d06 PZ |
672 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
673 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 674 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
675 | } |
676 | ||
677 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 678 | bool enable, |
687f4d06 PZ |
679 | struct drm_display_mode *adjusted_mode) |
680 | { | |
0c14c7f9 PZ |
681 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
682 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
683 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
6e3c9717 | 684 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 685 | u32 val = I915_READ(reg); |
0c14c7f9 | 686 | |
afba0188 DV |
687 | assert_hdmi_port_disabled(intel_hdmi); |
688 | ||
6897b4b5 | 689 | if (!enable) { |
0c14c7f9 | 690 | I915_WRITE(reg, 0); |
9d9740f0 | 691 | POSTING_READ(reg); |
0c14c7f9 PZ |
692 | return; |
693 | } | |
694 | ||
0dd87d20 PZ |
695 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
696 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
697 | ||
698 | I915_WRITE(reg, val); | |
9d9740f0 | 699 | POSTING_READ(reg); |
0dd87d20 | 700 | |
687f4d06 PZ |
701 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
702 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 703 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
704 | } |
705 | ||
4cde8a21 | 706 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 707 | { |
c59423a3 | 708 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 709 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
710 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
711 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
6e3c9717 | 712 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 713 | u32 hdmi_val; |
7d57382e | 714 | |
b242b7f7 | 715 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 716 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 717 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 718 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 719 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 720 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 721 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 722 | |
6e3c9717 | 723 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 724 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 725 | else |
4f3a8bc7 | 726 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 727 | |
6e3c9717 | 728 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 729 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 730 | |
75770564 | 731 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 732 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
733 | else if (IS_CHERRYVIEW(dev)) |
734 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 735 | else |
c59423a3 | 736 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 737 | |
b242b7f7 PZ |
738 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
739 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
740 | } |
741 | ||
85234cdc DV |
742 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
743 | enum pipe *pipe) | |
7d57382e | 744 | { |
85234cdc | 745 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 746 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 747 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 748 | enum intel_display_power_domain power_domain; |
85234cdc DV |
749 | u32 tmp; |
750 | ||
6d129bea | 751 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 752 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
753 | return false; |
754 | ||
b242b7f7 | 755 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
756 | |
757 | if (!(tmp & SDVO_ENABLE)) | |
758 | return false; | |
759 | ||
760 | if (HAS_PCH_CPT(dev)) | |
761 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
762 | else if (IS_CHERRYVIEW(dev)) |
763 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
764 | else |
765 | *pipe = PORT_TO_PIPE(tmp); | |
766 | ||
767 | return true; | |
768 | } | |
769 | ||
045ac3b5 | 770 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 771 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
772 | { |
773 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
774 | struct drm_device *dev = encoder->base.dev; |
775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 776 | u32 tmp, flags = 0; |
18442d08 | 777 | int dotclock; |
045ac3b5 JB |
778 | |
779 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
780 | ||
781 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
782 | flags |= DRM_MODE_FLAG_PHSYNC; | |
783 | else | |
784 | flags |= DRM_MODE_FLAG_NHSYNC; | |
785 | ||
786 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
787 | flags |= DRM_MODE_FLAG_PVSYNC; | |
788 | else | |
789 | flags |= DRM_MODE_FLAG_NVSYNC; | |
790 | ||
6897b4b5 DV |
791 | if (tmp & HDMI_MODE_SELECT_HDMI) |
792 | pipe_config->has_hdmi_sink = true; | |
793 | ||
e43823ec JB |
794 | if (intel_hdmi->infoframe_enabled(&encoder->base)) |
795 | pipe_config->has_infoframe = true; | |
796 | ||
c84db770 | 797 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
798 | pipe_config->has_audio = true; |
799 | ||
8c875fca VS |
800 | if (!HAS_PCH_SPLIT(dev) && |
801 | tmp & HDMI_COLOR_RANGE_16_235) | |
802 | pipe_config->limited_color_range = true; | |
803 | ||
2d112de7 | 804 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
805 | |
806 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
807 | dotclock = pipe_config->port_clock * 2 / 3; | |
808 | else | |
809 | dotclock = pipe_config->port_clock; | |
810 | ||
811 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
812 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
813 | ||
2d112de7 | 814 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
815 | } |
816 | ||
d1b1589c VS |
817 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
818 | { | |
819 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
820 | ||
821 | WARN_ON(!crtc->config->has_hdmi_sink); | |
822 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
823 | pipe_name(crtc->pipe)); | |
824 | intel_audio_codec_enable(encoder); | |
825 | } | |
826 | ||
5ab432ef | 827 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 828 | { |
5ab432ef | 829 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 830 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 831 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 832 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 833 | u32 temp; |
2deed761 WF |
834 | u32 enable_bits = SDVO_ENABLE; |
835 | ||
6e3c9717 | 836 | if (intel_crtc->config->has_audio) |
2deed761 | 837 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 838 | |
b242b7f7 | 839 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 840 | |
7a87c289 | 841 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
842 | * before disabling it, so restore the transcoder select bit here. */ |
843 | if (HAS_PCH_IBX(dev)) | |
844 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 845 | |
d8a2d0e0 ZW |
846 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
847 | * we do this anyway which shows more stable in testing. | |
848 | */ | |
c619eed4 | 849 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
850 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
851 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
852 | } |
853 | ||
5ab432ef DV |
854 | temp |= enable_bits; |
855 | ||
b242b7f7 PZ |
856 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
857 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
858 | |
859 | /* HW workaround, need to write this twice for issue that may result | |
860 | * in first write getting masked. | |
861 | */ | |
862 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
863 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
864 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 865 | } |
c1dec79a | 866 | |
d1b1589c VS |
867 | if (intel_crtc->config->has_audio) |
868 | intel_enable_hdmi_audio(encoder); | |
869 | } | |
870 | ||
871 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
872 | { | |
873 | struct drm_device *dev = encoder->base.dev; | |
874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
875 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
876 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
877 | enum pipe pipe = crtc->pipe; | |
878 | u32 temp; | |
879 | ||
880 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
881 | ||
882 | temp |= SDVO_ENABLE; | |
883 | if (crtc->config->has_audio) | |
884 | temp |= SDVO_AUDIO_ENABLE; | |
885 | ||
886 | /* | |
887 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
888 | * | |
889 | * The procedure for 12bpc is as follows: | |
890 | * 1. disable HDMI clock gating | |
891 | * 2. enable HDMI with 8bpc | |
892 | * 3. enable HDMI with 12bpc | |
893 | * 4. enable HDMI clock gating | |
894 | */ | |
895 | ||
896 | if (crtc->config->pipe_bpp > 24) { | |
897 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
898 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
899 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
900 | ||
901 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
902 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 903 | } |
d1b1589c VS |
904 | |
905 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
906 | POSTING_READ(intel_hdmi->hdmi_reg); | |
907 | ||
908 | if (crtc->config->pipe_bpp > 24) { | |
909 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
910 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
911 | ||
912 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
913 | POSTING_READ(intel_hdmi->hdmi_reg); | |
914 | ||
915 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
916 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
917 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
918 | } | |
919 | ||
920 | if (crtc->config->has_audio) | |
921 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 922 | } |
89b667f8 | 923 | |
b76cf76b JN |
924 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
925 | { | |
5ab432ef DV |
926 | } |
927 | ||
928 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
929 | { | |
930 | struct drm_device *dev = encoder->base.dev; | |
931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
932 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 933 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 934 | u32 temp; |
5ab432ef | 935 | |
b242b7f7 | 936 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 937 | |
1612c8bd | 938 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
939 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
940 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
941 | |
942 | /* | |
943 | * HW workaround for IBX, we need to move the port | |
944 | * to transcoder A after disabling it to allow the | |
945 | * matching DP port to be enabled on transcoder A. | |
946 | */ | |
947 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
948 | temp &= ~SDVO_PIPE_B_SELECT; | |
949 | temp |= SDVO_ENABLE; | |
950 | /* | |
951 | * HW workaround, need to write this twice for issue | |
952 | * that may result in first write getting masked. | |
953 | */ | |
954 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
955 | POSTING_READ(intel_hdmi->hdmi_reg); | |
956 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
957 | POSTING_READ(intel_hdmi->hdmi_reg); | |
958 | ||
959 | temp &= ~SDVO_ENABLE; | |
960 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
961 | POSTING_READ(intel_hdmi->hdmi_reg); | |
962 | } | |
7d57382e EA |
963 | } |
964 | ||
a4790cec VS |
965 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
966 | { | |
967 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
968 | ||
969 | if (crtc->config->has_audio) | |
970 | intel_audio_codec_disable(encoder); | |
971 | ||
972 | intel_disable_hdmi(encoder); | |
973 | } | |
974 | ||
975 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
976 | { | |
977 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
978 | ||
979 | if (crtc->config->has_audio) | |
980 | intel_audio_codec_disable(encoder); | |
981 | } | |
982 | ||
983 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
984 | { | |
985 | intel_disable_hdmi(encoder); | |
986 | } | |
987 | ||
40478455 | 988 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
989 | { |
990 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
991 | ||
40478455 | 992 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 993 | return 165000; |
e3c33578 | 994 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
995 | return 300000; |
996 | else | |
997 | return 225000; | |
998 | } | |
999 | ||
c19de8eb DL |
1000 | static enum drm_mode_status |
1001 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1002 | struct drm_display_mode *mode) | |
7d57382e | 1003 | { |
697c4078 CT |
1004 | int clock = mode->clock; |
1005 | ||
1006 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
1007 | clock *= 2; | |
1008 | ||
1009 | if (clock > hdmi_portclock_limit(intel_attached_hdmi(connector), | |
1010 | true)) | |
7d57382e | 1011 | return MODE_CLOCK_HIGH; |
697c4078 | 1012 | if (clock < 20000) |
5cbba41d | 1013 | return MODE_CLOCK_LOW; |
7d57382e EA |
1014 | |
1015 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1016 | return MODE_NO_DBLESCAN; | |
1017 | ||
1018 | return MODE_OK; | |
1019 | } | |
1020 | ||
77f06c86 | 1021 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1022 | { |
77f06c86 ACO |
1023 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1024 | struct drm_atomic_state *state; | |
71800632 | 1025 | struct intel_encoder *encoder; |
da3ced29 | 1026 | struct drm_connector *connector; |
77f06c86 | 1027 | struct drm_connector_state *connector_state; |
71800632 | 1028 | int count = 0, count_hdmi = 0; |
77f06c86 | 1029 | int i; |
71800632 | 1030 | |
f227ae9e | 1031 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1032 | return false; |
1033 | ||
77f06c86 ACO |
1034 | state = crtc_state->base.state; |
1035 | ||
da3ced29 | 1036 | for_each_connector_in_state(state, connector, connector_state, i) { |
77f06c86 ACO |
1037 | if (connector_state->crtc != crtc_state->base.crtc) |
1038 | continue; | |
1039 | ||
1040 | encoder = to_intel_encoder(connector_state->best_encoder); | |
1041 | ||
71800632 VS |
1042 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1043 | count++; | |
1044 | } | |
1045 | ||
1046 | /* | |
1047 | * HDMI 12bpc affects the clocks, so it's only possible | |
1048 | * when not cloning with other encoder types. | |
1049 | */ | |
1050 | return count_hdmi > 0 && count_hdmi == count; | |
1051 | } | |
1052 | ||
5bfe2ac0 | 1053 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1054 | struct intel_crtc_state *pipe_config) |
7d57382e | 1055 | { |
5bfe2ac0 DV |
1056 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1057 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 ACO |
1058 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1059 | int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2; | |
40478455 | 1060 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 1061 | int desired_bpp; |
3685a8f3 | 1062 | |
6897b4b5 DV |
1063 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1064 | ||
e43823ec JB |
1065 | if (pipe_config->has_hdmi_sink) |
1066 | pipe_config->has_infoframe = true; | |
1067 | ||
55bc60db VS |
1068 | if (intel_hdmi->color_range_auto) { |
1069 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 1070 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1071 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1072 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1073 | else |
1074 | intel_hdmi->color_range = 0; | |
1075 | } | |
1076 | ||
697c4078 CT |
1077 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1078 | pipe_config->pixel_multiplier = 2; | |
1079 | } | |
1080 | ||
3685a8f3 | 1081 | if (intel_hdmi->color_range) |
50f3b016 | 1082 | pipe_config->limited_color_range = true; |
3685a8f3 | 1083 | |
5bfe2ac0 DV |
1084 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1085 | pipe_config->has_pch_encoder = true; | |
1086 | ||
9ed109a7 DV |
1087 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1088 | pipe_config->has_audio = true; | |
1089 | ||
4e53c2e0 DV |
1090 | /* |
1091 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1092 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1093 | * outputs. We also need to check that the higher clock still fits |
1094 | * within limits. | |
4e53c2e0 | 1095 | */ |
6897b4b5 | 1096 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 | 1097 | clock_12bpc <= portclock_limit && |
5e3daaca DV |
1098 | hdmi_12bpc_possible(pipe_config) && |
1099 | 0 /* FIXME 12bpc support totally broken */) { | |
e29c22c0 DV |
1100 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1101 | desired_bpp = 12*3; | |
325b9d04 DV |
1102 | |
1103 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1104 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1105 | } else { |
e29c22c0 DV |
1106 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1107 | desired_bpp = 8*3; | |
1108 | } | |
1109 | ||
1110 | if (!pipe_config->bw_constrained) { | |
1111 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1112 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1113 | } |
1114 | ||
241bfc38 | 1115 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
1116 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
1117 | return false; | |
1118 | } | |
1119 | ||
7d57382e EA |
1120 | return true; |
1121 | } | |
1122 | ||
953ece69 CW |
1123 | static void |
1124 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1125 | { |
df0e9248 | 1126 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1127 | |
953ece69 CW |
1128 | intel_hdmi->has_hdmi_sink = false; |
1129 | intel_hdmi->has_audio = false; | |
1130 | intel_hdmi->rgb_quant_range_selectable = false; | |
1131 | ||
1132 | kfree(to_intel_connector(connector)->detect_edid); | |
1133 | to_intel_connector(connector)->detect_edid = NULL; | |
1134 | } | |
1135 | ||
1136 | static bool | |
1137 | intel_hdmi_set_edid(struct drm_connector *connector) | |
1138 | { | |
1139 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1140 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1141 | struct intel_encoder *intel_encoder = | |
1142 | &hdmi_to_dig_port(intel_hdmi)->base; | |
1143 | enum intel_display_power_domain power_domain; | |
1144 | struct edid *edid; | |
1145 | bool connected = false; | |
164c8598 | 1146 | |
671dedd2 ID |
1147 | power_domain = intel_display_port_power_domain(intel_encoder); |
1148 | intel_display_power_get(dev_priv, power_domain); | |
1149 | ||
f899fc64 | 1150 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1151 | intel_gmbus_get_adapter(dev_priv, |
1152 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1153 | |
953ece69 | 1154 | intel_display_power_put(dev_priv, power_domain); |
30ad48b7 | 1155 | |
953ece69 CW |
1156 | to_intel_connector(connector)->detect_edid = edid; |
1157 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1158 | intel_hdmi->rgb_quant_range_selectable = | |
1159 | drm_rgb_quant_range_selectable(edid); | |
1160 | ||
1161 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1162 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1163 | intel_hdmi->has_audio = | |
953ece69 CW |
1164 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1165 | ||
1166 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1167 | intel_hdmi->has_hdmi_sink = | |
1168 | drm_detect_hdmi_monitor(edid); | |
1169 | ||
1170 | connected = true; | |
55b7d6e8 CW |
1171 | } |
1172 | ||
953ece69 CW |
1173 | return connected; |
1174 | } | |
1175 | ||
1176 | static enum drm_connector_status | |
1177 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
1178 | { | |
1179 | enum drm_connector_status status; | |
1180 | ||
1181 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
1182 | connector->base.id, connector->name); | |
1183 | ||
1184 | intel_hdmi_unset_edid(connector); | |
1185 | ||
1186 | if (intel_hdmi_set_edid(connector)) { | |
1187 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1188 | ||
1189 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1190 | status = connector_status_connected; | |
1191 | } else | |
1192 | status = connector_status_disconnected; | |
671dedd2 | 1193 | |
2ded9e27 | 1194 | return status; |
7d57382e EA |
1195 | } |
1196 | ||
953ece69 CW |
1197 | static void |
1198 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1199 | { |
953ece69 | 1200 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1201 | |
953ece69 CW |
1202 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1203 | connector->base.id, connector->name); | |
7d57382e | 1204 | |
953ece69 | 1205 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1206 | |
953ece69 CW |
1207 | if (connector->status != connector_status_connected) |
1208 | return; | |
671dedd2 | 1209 | |
953ece69 CW |
1210 | intel_hdmi_set_edid(connector); |
1211 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1212 | } | |
671dedd2 | 1213 | |
953ece69 CW |
1214 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1215 | { | |
1216 | struct edid *edid; | |
1217 | ||
1218 | edid = to_intel_connector(connector)->detect_edid; | |
1219 | if (edid == NULL) | |
1220 | return 0; | |
671dedd2 | 1221 | |
953ece69 | 1222 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1223 | } |
1224 | ||
1aad7ac0 CW |
1225 | static bool |
1226 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1227 | { | |
1aad7ac0 | 1228 | bool has_audio = false; |
953ece69 | 1229 | struct edid *edid; |
1aad7ac0 | 1230 | |
953ece69 CW |
1231 | edid = to_intel_connector(connector)->detect_edid; |
1232 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1233 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1234 | |
1aad7ac0 CW |
1235 | return has_audio; |
1236 | } | |
1237 | ||
55b7d6e8 CW |
1238 | static int |
1239 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1240 | struct drm_property *property, |
1241 | uint64_t val) | |
55b7d6e8 CW |
1242 | { |
1243 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1244 | struct intel_digital_port *intel_dig_port = |
1245 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1246 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1247 | int ret; |
1248 | ||
662595df | 1249 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1250 | if (ret) |
1251 | return ret; | |
1252 | ||
3f43c48d | 1253 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1254 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1255 | bool has_audio; |
1256 | ||
1257 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1258 | return 0; |
1259 | ||
1aad7ac0 | 1260 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1261 | |
b1d7e4b4 | 1262 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1263 | has_audio = intel_hdmi_detect_audio(connector); |
1264 | else | |
b1d7e4b4 | 1265 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1266 | |
b1d7e4b4 WF |
1267 | if (i == HDMI_AUDIO_OFF_DVI) |
1268 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1269 | |
1aad7ac0 | 1270 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1271 | goto done; |
1272 | } | |
1273 | ||
e953fd7b | 1274 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1275 | bool old_auto = intel_hdmi->color_range_auto; |
1276 | uint32_t old_range = intel_hdmi->color_range; | |
1277 | ||
55bc60db VS |
1278 | switch (val) { |
1279 | case INTEL_BROADCAST_RGB_AUTO: | |
1280 | intel_hdmi->color_range_auto = true; | |
1281 | break; | |
1282 | case INTEL_BROADCAST_RGB_FULL: | |
1283 | intel_hdmi->color_range_auto = false; | |
1284 | intel_hdmi->color_range = 0; | |
1285 | break; | |
1286 | case INTEL_BROADCAST_RGB_LIMITED: | |
1287 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1288 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1289 | break; |
1290 | default: | |
1291 | return -EINVAL; | |
1292 | } | |
ae4edb80 DV |
1293 | |
1294 | if (old_auto == intel_hdmi->color_range_auto && | |
1295 | old_range == intel_hdmi->color_range) | |
1296 | return 0; | |
1297 | ||
e953fd7b CW |
1298 | goto done; |
1299 | } | |
1300 | ||
94a11ddc VK |
1301 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1302 | switch (val) { | |
1303 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1304 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1305 | break; | |
1306 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1307 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1308 | break; | |
1309 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1310 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1311 | break; | |
1312 | default: | |
1313 | return -EINVAL; | |
1314 | } | |
1315 | goto done; | |
1316 | } | |
1317 | ||
55b7d6e8 CW |
1318 | return -EINVAL; |
1319 | ||
1320 | done: | |
c0c36b94 CW |
1321 | if (intel_dig_port->base.base.crtc) |
1322 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1323 | |
1324 | return 0; | |
1325 | } | |
1326 | ||
13732ba7 JB |
1327 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1328 | { | |
1329 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1330 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1331 | struct drm_display_mode *adjusted_mode = | |
6e3c9717 | 1332 | &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1333 | |
4cde8a21 DV |
1334 | intel_hdmi_prepare(encoder); |
1335 | ||
6897b4b5 | 1336 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1337 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1338 | adjusted_mode); |
13732ba7 JB |
1339 | } |
1340 | ||
9514ac6e | 1341 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1342 | { |
1343 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1344 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1345 | struct drm_device *dev = encoder->base.dev; |
1346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1347 | struct intel_crtc *intel_crtc = | |
1348 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 | 1349 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1350 | &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1351 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1352 | int pipe = intel_crtc->pipe; |
1353 | u32 val; | |
1354 | ||
89b667f8 | 1355 | /* Enable clock channels for this port */ |
a580516d | 1356 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1357 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1358 | val = 0; |
1359 | if (pipe) | |
1360 | val |= (1<<21); | |
1361 | else | |
1362 | val &= ~(1<<21); | |
1363 | val |= 0x001000c4; | |
ab3c759a | 1364 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1365 | |
1366 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1367 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1368 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1369 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1370 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1371 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1372 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1373 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1374 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1375 | |
1376 | /* Program lane clock */ | |
ab3c759a CML |
1377 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1378 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
a580516d | 1379 | mutex_unlock(&dev_priv->sb_lock); |
b76cf76b | 1380 | |
6897b4b5 | 1381 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1382 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1383 | adjusted_mode); |
13732ba7 | 1384 | |
b76cf76b JN |
1385 | intel_enable_hdmi(encoder); |
1386 | ||
9b6de0a1 | 1387 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1388 | } |
1389 | ||
9514ac6e | 1390 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1391 | { |
1392 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1393 | struct drm_device *dev = encoder->base.dev; | |
1394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1395 | struct intel_crtc *intel_crtc = |
1396 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1397 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1398 | int pipe = intel_crtc->pipe; |
89b667f8 | 1399 | |
4cde8a21 DV |
1400 | intel_hdmi_prepare(encoder); |
1401 | ||
89b667f8 | 1402 | /* Program Tx lane resets to default */ |
a580516d | 1403 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1404 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1405 | DPIO_PCS_TX_LANE2_RESET | |
1406 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1407 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1408 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1409 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1410 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1411 | DPIO_PCS_CLK_SOFT_RESET); | |
1412 | ||
1413 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1414 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1415 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1416 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1417 | ||
1418 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1419 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
a580516d | 1420 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1421 | } |
1422 | ||
9197c88b VS |
1423 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1424 | { | |
1425 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1426 | struct drm_device *dev = encoder->base.dev; | |
1427 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1428 | struct intel_crtc *intel_crtc = | |
1429 | to_intel_crtc(encoder->base.crtc); | |
1430 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1431 | enum pipe pipe = intel_crtc->pipe; | |
1432 | u32 val; | |
1433 | ||
625695f8 VS |
1434 | intel_hdmi_prepare(encoder); |
1435 | ||
a580516d | 1436 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 1437 | |
b9e5ac3c VS |
1438 | /* program left/right clock distribution */ |
1439 | if (pipe != PIPE_B) { | |
1440 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1441 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1442 | if (ch == DPIO_CH0) | |
1443 | val |= CHV_BUFLEFTENA1_FORCE; | |
1444 | if (ch == DPIO_CH1) | |
1445 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1446 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1447 | } else { | |
1448 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1449 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1450 | if (ch == DPIO_CH0) | |
1451 | val |= CHV_BUFLEFTENA2_FORCE; | |
1452 | if (ch == DPIO_CH1) | |
1453 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1454 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1455 | } | |
1456 | ||
9197c88b VS |
1457 | /* program clock channel usage */ |
1458 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1459 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1460 | if (pipe != PIPE_B) | |
1461 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1462 | else | |
1463 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1464 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1465 | ||
1466 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1467 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1468 | if (pipe != PIPE_B) | |
1469 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1470 | else | |
1471 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1472 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1473 | ||
1474 | /* | |
1475 | * This a a bit weird since generally CL | |
1476 | * matches the pipe, but here we need to | |
1477 | * pick the CL based on the port. | |
1478 | */ | |
1479 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1480 | if (pipe != PIPE_B) | |
1481 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1482 | else | |
1483 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1484 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1485 | ||
a580516d | 1486 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
1487 | } |
1488 | ||
9514ac6e | 1489 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1490 | { |
1491 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1492 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1493 | struct intel_crtc *intel_crtc = |
1494 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1495 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1496 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1497 | |
1498 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
a580516d | 1499 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
1500 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1501 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
a580516d | 1502 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1503 | } |
1504 | ||
580d3811 VS |
1505 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1506 | { | |
1507 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1508 | struct drm_device *dev = encoder->base.dev; | |
1509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1510 | struct intel_crtc *intel_crtc = | |
1511 | to_intel_crtc(encoder->base.crtc); | |
1512 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1513 | enum pipe pipe = intel_crtc->pipe; | |
1514 | u32 val; | |
1515 | ||
a580516d | 1516 | mutex_lock(&dev_priv->sb_lock); |
580d3811 VS |
1517 | |
1518 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1519 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1520 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1521 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1522 | |
97fd4d5c VS |
1523 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1524 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1525 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1526 | ||
1527 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1528 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1530 | ||
1531 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1532 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1533 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 | 1534 | |
a580516d | 1535 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1536 | } |
1537 | ||
e4a1d846 CML |
1538 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1539 | { | |
1540 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1541 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1542 | struct drm_device *dev = encoder->base.dev; |
1543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1544 | struct intel_crtc *intel_crtc = | |
1545 | to_intel_crtc(encoder->base.crtc); | |
b4eb1564 | 1546 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1547 | &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1548 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1549 | int pipe = intel_crtc->pipe; | |
2e523e98 | 1550 | int data, i, stagger; |
e4a1d846 CML |
1551 | u32 val; |
1552 | ||
a580516d | 1553 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 1554 | |
570e2a74 VS |
1555 | /* allow hardware to manage TX FIFO reset source */ |
1556 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1557 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1558 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1559 | ||
1560 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1561 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1562 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1563 | ||
949c1d43 | 1564 | /* Deassert soft data lane reset*/ |
97fd4d5c | 1565 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1566 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1567 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1568 | ||
1569 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1570 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1571 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1572 | ||
1573 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1574 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1575 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1576 | |
97fd4d5c | 1577 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1578 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1579 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1580 | |
1581 | /* Program Tx latency optimal setting */ | |
e4a1d846 | 1582 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
1583 | /* Set the upar bit */ |
1584 | data = (i == 1) ? 0x0 : 0x1; | |
1585 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1586 | data << DPIO_UPAR_SHIFT); | |
1587 | } | |
1588 | ||
1589 | /* Data lane stagger programming */ | |
2e523e98 VS |
1590 | if (intel_crtc->config->port_clock > 270000) |
1591 | stagger = 0x18; | |
1592 | else if (intel_crtc->config->port_clock > 135000) | |
1593 | stagger = 0xd; | |
1594 | else if (intel_crtc->config->port_clock > 67500) | |
1595 | stagger = 0x7; | |
1596 | else if (intel_crtc->config->port_clock > 33750) | |
1597 | stagger = 0x4; | |
1598 | else | |
1599 | stagger = 0x2; | |
1600 | ||
1601 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1602 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1604 | ||
1605 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1606 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1607 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1608 | ||
1609 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
1610 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1611 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1612 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1613 | DPIO_TX1_STAGGER_MULT(6) | | |
1614 | DPIO_TX2_STAGGER_MULT(0)); | |
1615 | ||
1616 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
1617 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1618 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1619 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1620 | DPIO_TX1_STAGGER_MULT(7) | | |
1621 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 CML |
1622 | |
1623 | /* Clear calc init */ | |
1966e59e VS |
1624 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1625 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1626 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1627 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1628 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1629 | ||
1630 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1631 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1632 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1633 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1634 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1635 | |
a02ef3c7 VS |
1636 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1637 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1638 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1639 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1640 | ||
1641 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1642 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1643 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1644 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1645 | ||
e4a1d846 CML |
1646 | /* FIXME: Program the support xxx V-dB */ |
1647 | /* Use 800mV-0dB */ | |
f72df8db VS |
1648 | for (i = 0; i < 4; i++) { |
1649 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1650 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1651 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1652 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1653 | } | |
e4a1d846 | 1654 | |
f72df8db VS |
1655 | for (i = 0; i < 4; i++) { |
1656 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
1657 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1658 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
1659 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1660 | } | |
e4a1d846 CML |
1661 | |
1662 | /* Disable unique transition scale */ | |
f72df8db VS |
1663 | for (i = 0; i < 4; i++) { |
1664 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1665 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1666 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1667 | } | |
e4a1d846 CML |
1668 | |
1669 | /* Additional steps for 1200mV-0dB */ | |
1670 | #if 0 | |
1671 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1672 | if (ch) | |
1673 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1674 | else | |
1675 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1676 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1677 | ||
1678 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1679 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1680 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1681 | #endif | |
1682 | /* Start swing calculation */ | |
1966e59e VS |
1683 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1684 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1685 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1686 | ||
1687 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1688 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1689 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1690 | |
1691 | /* LRC Bypass */ | |
1692 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1693 | val |= DPIO_LRC_BYPASS; | |
1694 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1695 | ||
a580516d | 1696 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 1697 | |
b4eb1564 | 1698 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1699 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1700 | adjusted_mode); |
1701 | ||
e4a1d846 CML |
1702 | intel_enable_hdmi(encoder); |
1703 | ||
9b6de0a1 | 1704 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
e4a1d846 CML |
1705 | } |
1706 | ||
7d57382e EA |
1707 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1708 | { | |
10e972d3 | 1709 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1710 | drm_connector_cleanup(connector); |
674e2d08 | 1711 | kfree(connector); |
7d57382e EA |
1712 | } |
1713 | ||
7d57382e | 1714 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1715 | .dpms = intel_connector_dpms, |
7d57382e | 1716 | .detect = intel_hdmi_detect, |
953ece69 | 1717 | .force = intel_hdmi_force, |
7d57382e | 1718 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 1719 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 1720 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 1721 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1722 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1723 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
1724 | }; |
1725 | ||
1726 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1727 | .get_modes = intel_hdmi_get_modes, | |
1728 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1729 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1730 | }; |
1731 | ||
7d57382e | 1732 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1733 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1734 | }; |
1735 | ||
94a11ddc VK |
1736 | static void |
1737 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1738 | { | |
1739 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1740 | drm_object_attach_property(&connector->base, | |
1741 | connector->dev->mode_config.aspect_ratio_property, | |
1742 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1743 | } | |
1744 | ||
55b7d6e8 CW |
1745 | static void |
1746 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1747 | { | |
3f43c48d | 1748 | intel_attach_force_audio_property(connector); |
e953fd7b | 1749 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1750 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1751 | intel_attach_aspect_ratio_property(connector); |
1752 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1753 | } |
1754 | ||
00c09d70 PZ |
1755 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1756 | struct intel_connector *intel_connector) | |
7d57382e | 1757 | { |
b9cb234c PZ |
1758 | struct drm_connector *connector = &intel_connector->base; |
1759 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1760 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1761 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1762 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1763 | enum port port = intel_dig_port->port; |
373a3cf7 | 1764 | |
7d57382e | 1765 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1766 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1767 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1768 | ||
c3febcc4 | 1769 | connector->interlace_allowed = 1; |
7d57382e | 1770 | connector->doublescan_allowed = 0; |
573e74ad | 1771 | connector->stereo_allowed = 1; |
66a9278e | 1772 | |
08d644ad DV |
1773 | switch (port) { |
1774 | case PORT_B: | |
4c272834 JN |
1775 | if (IS_BROXTON(dev_priv)) |
1776 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
1777 | else | |
1778 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
1d843f9d | 1779 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1780 | break; |
1781 | case PORT_C: | |
4c272834 JN |
1782 | if (IS_BROXTON(dev_priv)) |
1783 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
1784 | else | |
1785 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 1786 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1787 | break; |
1788 | case PORT_D: | |
4c272834 JN |
1789 | if (WARN_ON(IS_BROXTON(dev_priv))) |
1790 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
1791 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 1792 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 1793 | else |
988c7015 | 1794 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 1795 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1796 | break; |
1797 | case PORT_A: | |
1d843f9d | 1798 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1799 | /* Internal port only for eDP. */ |
1800 | default: | |
6e4c1677 | 1801 | BUG(); |
f8aed700 | 1802 | } |
7d57382e | 1803 | |
7637bfdb | 1804 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1805 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1806 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 1807 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 1808 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1809 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1810 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 1811 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 1812 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1813 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1814 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 1815 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
1816 | } else if (HAS_PCH_IBX(dev)) { |
1817 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1818 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 1819 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
1820 | } else { |
1821 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1822 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 1823 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 1824 | } |
45187ace | 1825 | |
affa9354 | 1826 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1827 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1828 | else | |
1829 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1830 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1831 | |
1832 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1833 | ||
1834 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1835 | drm_connector_register(connector); |
b9cb234c PZ |
1836 | |
1837 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1838 | * 0xd. Failure to do so will result in spurious interrupts being | |
1839 | * generated on the port when a cable is not attached. | |
1840 | */ | |
1841 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1842 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1843 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1844 | } | |
1845 | } | |
1846 | ||
b242b7f7 | 1847 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1848 | { |
1849 | struct intel_digital_port *intel_dig_port; | |
1850 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1851 | struct intel_connector *intel_connector; |
1852 | ||
b14c5679 | 1853 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1854 | if (!intel_dig_port) |
1855 | return; | |
1856 | ||
08d9bc92 | 1857 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
1858 | if (!intel_connector) { |
1859 | kfree(intel_dig_port); | |
1860 | return; | |
1861 | } | |
1862 | ||
1863 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1864 | |
1865 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1866 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1867 | |
5bfe2ac0 | 1868 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
1869 | if (HAS_PCH_SPLIT(dev)) { |
1870 | intel_encoder->disable = pch_disable_hdmi; | |
1871 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
1872 | } else { | |
1873 | intel_encoder->disable = g4x_disable_hdmi; | |
1874 | } | |
00c09d70 | 1875 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 1876 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1877 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1878 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1879 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1880 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1881 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1882 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1883 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1884 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1885 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1886 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1887 | } else { |
13732ba7 | 1888 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
1889 | if (HAS_PCH_CPT(dev)) |
1890 | intel_encoder->enable = cpt_enable_hdmi; | |
1891 | else | |
1892 | intel_encoder->enable = intel_enable_hdmi; | |
89b667f8 | 1893 | } |
5ab432ef | 1894 | |
b9cb234c | 1895 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1896 | if (IS_CHERRYVIEW(dev)) { |
1897 | if (port == PORT_D) | |
1898 | intel_encoder->crtc_mask = 1 << 2; | |
1899 | else | |
1900 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1901 | } else { | |
1902 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1903 | } | |
301ea74a | 1904 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1905 | /* |
1906 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1907 | * to work on real hardware. And since g4x can send infoframes to | |
1908 | * only one port anyway, nothing is lost by allowing it. | |
1909 | */ | |
1910 | if (IS_G4X(dev)) | |
1911 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1912 | |
174edf1f | 1913 | intel_dig_port->port = port; |
b242b7f7 | 1914 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1915 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1916 | |
b9cb234c | 1917 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1918 | } |