[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_i2c.c

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2008,2010 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Chris Wilson <chris@chris-wilson.co.uk>
 */
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/export.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"

struct gmbus_pin {
	const char *name;
	int reg;
};

/* Map gmbus pin pairs to names and registers. */
static const struct gmbus_pin gmbus_pins[] = {
	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
};

bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
			      unsigned int pin)
{
	return pin < ARRAY_SIZE(gmbus_pins) && gmbus_pins[pin].reg;
}

/* Intel GPIO access functions */

#define I2C_RISEFALL_TIME 10

static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter *i2c)
{
	return container_of(i2c, struct intel_gmbus, adapter);
}

void
intel_i2c_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
}

static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
{
	u32 val;

	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	if (!IS_PINEVIEW(dev_priv->dev))
		return;

	val = I915_READ(DSPCLK_GATE_D);
	if (enable)
		val |= DPCUNIT_CLOCK_GATE_DISABLE;
	else
		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, val);
}

static u32 get_reserved(struct intel_gmbus *bus)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = 0;

	/* On most chips, these bits must be preserved in software. */
	if (!IS_I830(dev) && !IS_845G(dev))
		reserved = I915_READ_NOTRACE(bus->gpio_reg) &
					     (GPIO_DATA_PULLUP_DISABLE |
					      GPIO_CLOCK_PULLUP_DISABLE);

	return reserved;
}

static int get_clock(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
}

static int get_data(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
}

static void set_clock(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 clock_bits;

	if (state_high)
		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
	else
		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
			GPIO_CLOCK_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
	POSTING_READ(bus->gpio_reg);
}

static void set_data(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 data_bits;

	if (state_high)
		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
	else
		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
			GPIO_DATA_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
	POSTING_READ(bus->gpio_reg);
}

static int
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;

	intel_i2c_reset(dev_priv->dev);
	intel_i2c_quirk_set(dev_priv, true);
	set_data(bus, 1);
	set_clock(bus, 1);
	udelay(I2C_RISEFALL_TIME);
	return 0;
}

static void
intel_gpio_post_xfer(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;

	set_data(bus, 1);
	set_clock(bus, 1);
	intel_i2c_quirk_set(dev_priv, false);
}

static void
intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	struct i2c_algo_bit_data *algo;

	algo = &bus->bit_algo;

	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_pins[pin].reg;

	bus->adapter.algo_data = algo;
	algo->setsda = set_data;
	algo->setscl = set_clock;
	algo->getsda = get_data;
	algo->getscl = get_clock;
	algo->pre_xfer = intel_gpio_pre_xfer;
	algo->post_xfer = intel_gpio_post_xfer;
	algo->udelay = I2C_RISEFALL_TIME;
	algo->timeout = usecs_to_jiffies(2200);
	algo->data = bus;
}

static int
gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
		     u32 gmbus2_status,
		     u32 gmbus4_irq_en)
{
	int i;
	int reg_offset = dev_priv->gpio_mmio_base;
	u32 gmbus2 = 0;
	DEFINE_WAIT(wait);

	if (!HAS_GMBUS_IRQ(dev_priv->dev))
		gmbus4_irq_en = 0;

	/* Important: The hw handles only the first bit, so set only one! Since
	 * we also need to check for NAKs besides the hw ready/idle signal, we
	 * need to wake up periodically and check that ourselves. */
	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);

	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
		prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
				TASK_UNINTERRUPTIBLE);

		gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
		if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
			break;

		schedule_timeout(1);
	}
	finish_wait(&dev_priv->gmbus_wait_queue, &wait);

	I915_WRITE(GMBUS4 + reg_offset, 0);

	if (gmbus2 & GMBUS_SATOER)
		return -ENXIO;
	if (gmbus2 & gmbus2_status)
		return 0;
	return -ETIMEDOUT;
}

static int
gmbus_wait_idle(struct drm_i915_private *dev_priv)
{
	int ret;
	int reg_offset = dev_priv->gpio_mmio_base;

#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)

	if (!HAS_GMBUS_IRQ(dev_priv->dev))
		return wait_for(C, 10);

	/* Important: The hw handles only the first bit, so set only one! */
	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);

	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
				 msecs_to_jiffies_timeout(10));

	I915_WRITE(GMBUS4 + reg_offset, 0);

	if (ret)
		return 0;
	else
		return -ETIMEDOUT;
#undef C
}

static int
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
		u32 gmbus1_index)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u16 len = msg->len;
	u8 *buf = msg->buf;

	I915_WRITE(GMBUS1 + reg_offset,
		   gmbus1_index |
		   GMBUS_CYCLE_WAIT |
		   (len << GMBUS_BYTE_COUNT_SHIFT) |
		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
		   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
	while (len) {
		int ret;
		u32 val, loop = 0;

		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
					   GMBUS_HW_RDY_EN);
		if (ret)
			return ret;

		val = I915_READ(GMBUS3 + reg_offset);
		do {
			*buf++ = val & 0xff;
			val >>= 8;
		} while (--len && ++loop < 4);
	}

	return 0;
}

static int
gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u16 len = msg->len;
	u8 *buf = msg->buf;
	u32 val, loop;

	val = loop = 0;
	while (len && loop < 4) {
		val |= *buf++ << (8 * loop++);
		len -= 1;
	}

	I915_WRITE(GMBUS3 + reg_offset, val);
	I915_WRITE(GMBUS1 + reg_offset,
		   GMBUS_CYCLE_WAIT |
		   (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
	while (len) {
		int ret;

		val = loop = 0;
		do {
			val |= *buf++ << (8 * loop);
		} while (--len && ++loop < 4);

		I915_WRITE(GMBUS3 + reg_offset, val);

		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
					   GMBUS_HW_RDY_EN);
		if (ret)
			return ret;
	}
	return 0;
}

/*
 * The gmbus controller can combine a 1 or 2 byte write with a read that
 * immediately follows it by using an "INDEX" cycle.
 */
static bool
gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
{
	return (i + 1 < num &&
		!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
		(msgs[i + 1].flags & I2C_M_RD));
}

static int
gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u32 gmbus1_index = 0;
	u32 gmbus5 = 0;
	int ret;

	if (msgs[0].len == 2)
		gmbus5 = GMBUS_2BYTE_INDEX_EN |
			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
	if (msgs[0].len == 1)
		gmbus1_index = GMBUS_CYCLE_INDEX |
			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);

	/* GMBUS5 holds 16-bit index */
	if (gmbus5)
		I915_WRITE(GMBUS5 + reg_offset, gmbus5);

	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);

	/* Clear GMBUS5 after each index transfer */
	if (gmbus5)
		I915_WRITE(GMBUS5 + reg_offset, 0);

	return ret;
}

static int
gmbus_xfer(struct i2c_adapter *adapter,
	   struct i2c_msg *msgs,
	   int num)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;
	int i, reg_offset;
	int ret = 0;

	intel_aux_display_runtime_get(dev_priv);
	mutex_lock(&dev_priv->gmbus_mutex);

	if (bus->force_bit) {
		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
		goto out;
	}

	reg_offset = dev_priv->gpio_mmio_base;

	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);

	for (i = 0; i < num; i++) {
		if (gmbus_is_index_read(msgs, i, num)) {
			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
			i += 1;  /* set i to the index of the read xfer */
		} else if (msgs[i].flags & I2C_M_RD) {
			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
		} else {
			ret = gmbus_xfer_write(dev_priv, &msgs[i]);
		}

		if (ret == -ETIMEDOUT)
			goto timeout;
		if (ret == -ENXIO)
			goto clear_err;

		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
					   GMBUS_HW_WAIT_EN);
		if (ret == -ENXIO)
			goto clear_err;
		if (ret)
			goto timeout;
	}

	/* Generate a STOP condition on the bus. Note that gmbus can't generata
	 * a STOP on the very first cycle. To simplify the code we
	 * unconditionally generate the STOP condition with an additional gmbus
	 * cycle. */
	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);

	/* Mark the GMBUS interface as disabled after waiting for idle.
	 * We will re-enable it at the start of the next xfer,
	 * till then let it sleep.
	 */
	if (gmbus_wait_idle(dev_priv)) {
		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
			 adapter->name);
		ret = -ETIMEDOUT;
	}
	I915_WRITE(GMBUS0 + reg_offset, 0);
	ret = ret ?: i;
	goto out;

clear_err:
	/*
	 * Wait for bus to IDLE before clearing NAK.
	 * If we clear the NAK while bus is still active, then it will stay
	 * active and the next transaction may fail.
	 *
	 * If no ACK is received during the address phase of a transaction, the
	 * adapter must report -ENXIO. It is not clear what to return if no ACK
	 * is received at other times. But we have to be careful to not return
	 * spurious -ENXIO because that will prevent i2c and drm edid functions
	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
	 * timing out seems to happen when there _is_ a ddc chip present, but
	 * it's slow responding and only answers on the 2nd retry.
	 */
	ret = -ENXIO;
	if (gmbus_wait_idle(dev_priv)) {
		DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
			      adapter->name);
		ret = -ETIMEDOUT;
	}

	/* Toggle the Software Clear Interrupt bit. This has the effect
	 * of resetting the GMBUS controller and so clearing the
	 * BUS_ERROR raised by the slave's NAK.
	 */
	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	I915_WRITE(GMBUS1 + reg_offset, 0);
	I915_WRITE(GMBUS0 + reg_offset, 0);

	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
			 adapter->name, msgs[i].addr,
			 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);

	goto out;

timeout:
	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
		 bus->adapter.name, bus->reg0 & 0xff);
	I915_WRITE(GMBUS0 + reg_offset, 0);

	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	bus->force_bit = 1;
	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);

out:
	mutex_unlock(&dev_priv->gmbus_mutex);
	intel_aux_display_runtime_put(dev_priv);
	return ret;
}

static u32 gmbus_func(struct i2c_adapter *adapter)
{
	return i2c_bit_algo.functionality(adapter) &
		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
		/* I2C_FUNC_10BIT_ADDR | */
		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
}

static const struct i2c_algorithm gmbus_algorithm = {
	.master_xfer	= gmbus_xfer,
	.functionality	= gmbus_func
};

/**
 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 * @dev: DRM device
 */
int intel_setup_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_gmbus *bus;
	unsigned int pin;
	int ret;

	if (HAS_PCH_NOP(dev))
		return 0;
	else if (HAS_PCH_SPLIT(dev))
		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
	else if (IS_VALLEYVIEW(dev))
		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
	else
		dev_priv->gpio_mmio_base = 0;

	mutex_init(&dev_priv->gmbus_mutex);
	init_waitqueue_head(&dev_priv->gmbus_wait_queue);

	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
			continue;

		bus = &dev_priv->gmbus[pin];

		bus->adapter.owner = THIS_MODULE;
		bus->adapter.class = I2C_CLASS_DDC;
		snprintf(bus->adapter.name,
			 sizeof(bus->adapter.name),
			 "i915 gmbus %s",
			 gmbus_pins[pin].name);

		bus->adapter.dev.parent = &dev->pdev->dev;
		bus->dev_priv = dev_priv;

		bus->adapter.algo = &gmbus_algorithm;

		/* By default use a conservative clock rate */
		bus->reg0 = pin | GMBUS_RATE_100KHZ;

		/* gmbus seems to be broken on i830 */
		if (IS_I830(dev))
			bus->force_bit = 1;

		intel_gpio_setup(bus, pin);

		ret = i2c_add_adapter(&bus->adapter);
		if (ret)
			goto err;
	}

	intel_i2c_reset(dev_priv->dev);

	return 0;

err:
	while (--pin) {
		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
			continue;

		bus = &dev_priv->gmbus[pin];
		i2c_del_adapter(&bus->adapter);
	}
	return ret;
}

struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
					    unsigned int pin)
{
	if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
		return NULL;

	return &dev_priv->gmbus[pin].adapter;
}

void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
}

void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	bus->force_bit += force_bit ? 1 : -1;
	DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
		      force_bit ? "en" : "dis", adapter->name,
		      bus->force_bit);
}

void intel_teardown_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_gmbus *bus;
	unsigned int pin;

	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
		if (!intel_gmbus_is_valid_pin(dev_priv, pin))
			continue;

		bus = &dev_priv->gmbus[pin];
		i2c_del_adapter(&bus->adapter);
	}
}
Commit	Line	Data
79e53945 JB	1	/*
79e53945 JB	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
f899fc64	3	* Copyright © 2006-2008,2010 Intel Corporation
79e53945 JB	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	23	* DEALINGS IN THE SOFTWARE.
	24	*
	25	* Authors:
	26	* Eric Anholt <eric@anholt.net>
f899fc64	27	* Chris Wilson <chris@chris-wilson.co.uk>
79e53945 JB	28	*/
79e53945 JB	29	#include <linux/i2c.h>
79e53945	30	#include <linux/i2c-algo-bit.h>
2d1a8a48	31	#include <linux/export.h>
760285e7	32	#include <drm/drmP.h>
79e53945	33	#include "intel_drv.h"
760285e7	34	#include <drm/i915_drm.h>
79e53945 JB	35	#include "i915_drv.h"
79e53945 JB	36
5ea6e5e3	37	struct gmbus_pin {
2ed06c93 DK	38	const char *name;
	39	int reg;
	40	};
	41
5ea6e5e3 JN	42	/* Map gmbus pin pairs to names and registers. */
	43	static const struct gmbus_pin gmbus_pins[] = {
	44	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
	45	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
	46	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
	47	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
	48	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
	49	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
2ed06c93 DK	50	};
2ed06c93 DK	51
88ac7939 JN	52	bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
	53	unsigned int pin)
	54	{
	55	return pin < ARRAY_SIZE(gmbus_pins) && gmbus_pins[pin].reg;
	56	}
	57
f899fc64 CW	58	/* Intel GPIO access functions */
f899fc64 CW	59
1849ecb2	60	#define I2C_RISEFALL_TIME 10
f899fc64	61
e957d772 CW	62	static inline struct intel_gmbus *
	63	to_intel_gmbus(struct i2c_adapter *i2c)
	64	{
	65	return container_of(i2c, struct intel_gmbus, adapter);
	66	}
	67
f899fc64 CW	68	void
f899fc64 CW	69	intel_i2c_reset(struct drm_device *dev)
0ba0e9e1 SL	70	{
0ba0e9e1 SL	71	struct drm_i915_private *dev_priv = dev->dev_private;
24eb2d59	72
110447fc	73	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
28c70f16	74	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
f899fc64 CW	75	}
	76
	77	static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
	78	{
b222f267	79	u32 val;
0ba0e9e1 SL	80
0ba0e9e1 SL	81	/* When using bit bashing for I2C, this bit needs to be set to 1 */
f899fc64	82	if (!IS_PINEVIEW(dev_priv->dev))
0ba0e9e1	83	return;
b222f267 CW	84
b222f267 CW	85	val = I915_READ(DSPCLK_GATE_D);
0ba0e9e1	86	if (enable)
b222f267	87	val \|= DPCUNIT_CLOCK_GATE_DISABLE;
0ba0e9e1	88	else
b222f267 CW	89	val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
b222f267 CW	90	I915_WRITE(DSPCLK_GATE_D, val);
0ba0e9e1 SL	91	}
0ba0e9e1 SL	92
36c785f0	93	static u32 get_reserved(struct intel_gmbus *bus)
e957d772	94	{
36c785f0	95	struct drm_i915_private *dev_priv = bus->dev_priv;
e957d772 CW	96	struct drm_device *dev = dev_priv->dev;
	97	u32 reserved = 0;
	98
	99	/* On most chips, these bits must be preserved in software. */
	100	if (!IS_I830(dev) && !IS_845G(dev))
36c785f0	101	reserved = I915_READ_NOTRACE(bus->gpio_reg) &
db5e4172 YL	102	(GPIO_DATA_PULLUP_DISABLE \|
db5e4172 YL	103	GPIO_CLOCK_PULLUP_DISABLE);
e957d772 CW	104
	105	return reserved;
	106	}
	107
79e53945 JB	108	static int get_clock(void *data)
79e53945 JB	109	{
36c785f0 DV	110	struct intel_gmbus *bus = data;
	111	struct drm_i915_private *dev_priv = bus->dev_priv;
	112	u32 reserved = get_reserved(bus);
	113	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_CLOCK_DIR_MASK);
	114	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	115	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
79e53945 JB	116	}
	117
	118	static int get_data(void *data)
	119	{
36c785f0 DV	120	struct intel_gmbus *bus = data;
	121	struct drm_i915_private *dev_priv = bus->dev_priv;
	122	u32 reserved = get_reserved(bus);
	123	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_DATA_DIR_MASK);
	124	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	125	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
79e53945 JB	126	}
	127
	128	static void set_clock(void *data, int state_high)
	129	{
36c785f0 DV	130	struct intel_gmbus *bus = data;
	131	struct drm_i915_private *dev_priv = bus->dev_priv;
	132	u32 reserved = get_reserved(bus);
e957d772	133	u32 clock_bits;
79e53945 JB	134
	135	if (state_high)
	136	clock_bits = GPIO_CLOCK_DIR_IN \| GPIO_CLOCK_DIR_MASK;
	137	else
	138	clock_bits = GPIO_CLOCK_DIR_OUT \| GPIO_CLOCK_DIR_MASK \|
	139	GPIO_CLOCK_VAL_MASK;
f899fc64	140
36c785f0 DV	141	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| clock_bits);
36c785f0 DV	142	POSTING_READ(bus->gpio_reg);
79e53945 JB	143	}
	144
	145	static void set_data(void *data, int state_high)
	146	{
36c785f0 DV	147	struct intel_gmbus *bus = data;
	148	struct drm_i915_private *dev_priv = bus->dev_priv;
	149	u32 reserved = get_reserved(bus);
e957d772	150	u32 data_bits;
79e53945 JB	151
	152	if (state_high)
	153	data_bits = GPIO_DATA_DIR_IN \| GPIO_DATA_DIR_MASK;
	154	else
	155	data_bits = GPIO_DATA_DIR_OUT \| GPIO_DATA_DIR_MASK \|
	156	GPIO_DATA_VAL_MASK;
	157
36c785f0 DV	158	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| data_bits);
36c785f0 DV	159	POSTING_READ(bus->gpio_reg);
79e53945 JB	160	}
79e53945 JB	161
489fbc10 DK	162	static int
	163	intel_gpio_pre_xfer(struct i2c_adapter *adapter)
	164	{
	165	struct intel_gmbus *bus = container_of(adapter,
	166	struct intel_gmbus,
	167	adapter);
	168	struct drm_i915_private *dev_priv = bus->dev_priv;
	169
	170	intel_i2c_reset(dev_priv->dev);
	171	intel_i2c_quirk_set(dev_priv, true);
	172	set_data(bus, 1);
	173	set_clock(bus, 1);
	174	udelay(I2C_RISEFALL_TIME);
	175	return 0;
	176	}
	177
	178	static void
	179	intel_gpio_post_xfer(struct i2c_adapter *adapter)
	180	{
	181	struct intel_gmbus *bus = container_of(adapter,
	182	struct intel_gmbus,
	183	adapter);
	184	struct drm_i915_private *dev_priv = bus->dev_priv;
	185
	186	set_data(bus, 1);
	187	set_clock(bus, 1);
	188	intel_i2c_quirk_set(dev_priv, false);
	189	}
	190
2ed06c93	191	static void
5ea6e5e3	192	intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
f0217c42	193	{
36c785f0	194	struct drm_i915_private *dev_priv = bus->dev_priv;
36c785f0	195	struct i2c_algo_bit_data *algo;
f0217c42	196
c167a6fc	197	algo = &bus->bit_algo;
36c785f0	198
5ea6e5e3	199	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_pins[pin].reg;
79e53945	200
c167a6fc	201	bus->adapter.algo_data = algo;
36c785f0 DV	202	algo->setsda = set_data;
	203	algo->setscl = set_clock;
	204	algo->getsda = get_data;
	205	algo->getscl = get_clock;
489fbc10 DK	206	algo->pre_xfer = intel_gpio_pre_xfer;
489fbc10 DK	207	algo->post_xfer = intel_gpio_post_xfer;
36c785f0 DV	208	algo->udelay = I2C_RISEFALL_TIME;
	209	algo->timeout = usecs_to_jiffies(2200);
	210	algo->data = bus;
79e53945 JB	211	}
79e53945 JB	212
61168c53 DV	213	static int
61168c53 DV	214	gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
28c70f16 DV	215	u32 gmbus2_status,
28c70f16 DV	216	u32 gmbus4_irq_en)
61168c53	217	{
28c70f16	218	int i;
61168c53	219	int reg_offset = dev_priv->gpio_mmio_base;
28c70f16 DV	220	u32 gmbus2 = 0;
	221	DEFINE_WAIT(wait);
	222
c12aba5a JK	223	if (!HAS_GMBUS_IRQ(dev_priv->dev))
	224	gmbus4_irq_en = 0;
	225
28c70f16 DV	226	/* Important: The hw handles only the first bit, so set only one! Since
	227	* we also need to check for NAKs besides the hw ready/idle signal, we
	228	* need to wake up periodically and check that ourselves. */
	229	I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
	230
2554fc1f	231	for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
28c70f16 DV	232	prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
	233	TASK_UNINTERRUPTIBLE);
	234
ef04f00d	235	gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
28c70f16 DV	236	if (gmbus2 & (GMBUS_SATOER \| gmbus2_status))
28c70f16 DV	237	break;
61168c53	238
28c70f16 DV	239	schedule_timeout(1);
	240	}
	241	finish_wait(&dev_priv->gmbus_wait_queue, &wait);
	242
	243	I915_WRITE(GMBUS4 + reg_offset, 0);
61168c53 DV	244
	245	if (gmbus2 & GMBUS_SATOER)
	246	return -ENXIO;
28c70f16 DV	247	if (gmbus2 & gmbus2_status)
	248	return 0;
	249	return -ETIMEDOUT;
61168c53 DV	250	}
61168c53 DV	251
2c438c02 DV	252	static int
	253	gmbus_wait_idle(struct drm_i915_private *dev_priv)
	254	{
	255	int ret;
	256	int reg_offset = dev_priv->gpio_mmio_base;
	257
ef04f00d	258	#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
2c438c02 DV	259
	260	if (!HAS_GMBUS_IRQ(dev_priv->dev))
	261	return wait_for(C, 10);
	262
	263	/* Important: The hw handles only the first bit, so set only one! */
	264	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
	265
3598706b ID	266	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b ID	267	msecs_to_jiffies_timeout(10));
2c438c02 DV	268
	269	I915_WRITE(GMBUS4 + reg_offset, 0);
	270
	271	if (ret)
	272	return 0;
	273	else
	274	return -ETIMEDOUT;
	275	#undef C
	276	}
	277
924a93ed	278	static int
56f9eac0 DK	279	gmbus_xfer_read(struct drm_i915_private dev_priv, struct i2c_msg msg,
56f9eac0 DK	280	u32 gmbus1_index)
924a93ed DK	281	{
	282	int reg_offset = dev_priv->gpio_mmio_base;
	283	u16 len = msg->len;
	284	u8 *buf = msg->buf;
	285
	286	I915_WRITE(GMBUS1 + reg_offset,
56f9eac0	287	gmbus1_index \|
924a93ed	288	GMBUS_CYCLE_WAIT \|
924a93ed DK	289	(len << GMBUS_BYTE_COUNT_SHIFT) \|
	290	(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	291	GMBUS_SLAVE_READ \| GMBUS_SW_RDY);
79985eee	292	while (len) {
90e6b26d	293	int ret;
924a93ed DK	294	u32 val, loop = 0;
924a93ed DK	295
28c70f16 DV	296	ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
28c70f16 DV	297	GMBUS_HW_RDY_EN);
90e6b26d	298	if (ret)
61168c53	299	return ret;
924a93ed DK	300
	301	val = I915_READ(GMBUS3 + reg_offset);
	302	do {
	303	*buf++ = val & 0xff;
	304	val >>= 8;
	305	} while (--len && ++loop < 4);
79985eee	306	}
924a93ed DK	307
	308	return 0;
	309	}
	310
	311	static int
72d66afd	312	gmbus_xfer_write(struct drm_i915_private dev_priv, struct i2c_msg msg)
924a93ed DK	313	{
	314	int reg_offset = dev_priv->gpio_mmio_base;
	315	u16 len = msg->len;
	316	u8 *buf = msg->buf;
	317	u32 val, loop;
	318
	319	val = loop = 0;
26883c31 DK	320	while (len && loop < 4) {
	321	val \|= buf++ << (8 loop++);
	322	len -= 1;
	323	}
924a93ed DK	324
	325	I915_WRITE(GMBUS3 + reg_offset, val);
	326	I915_WRITE(GMBUS1 + reg_offset,
	327	GMBUS_CYCLE_WAIT \|
924a93ed DK	328	(msg->len << GMBUS_BYTE_COUNT_SHIFT) \|
	329	(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	330	GMBUS_SLAVE_WRITE \| GMBUS_SW_RDY);
924a93ed	331	while (len) {
90e6b26d	332	int ret;
90e6b26d	333
924a93ed DK	334	val = loop = 0;
	335	do {
	336	val \|= buf++ << (8 loop);
	337	} while (--len && ++loop < 4);
	338
	339	I915_WRITE(GMBUS3 + reg_offset, val);
7a39a9d4	340
28c70f16 DV	341	ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
28c70f16 DV	342	GMBUS_HW_RDY_EN);
90e6b26d	343	if (ret)
61168c53	344	return ret;
924a93ed DK	345	}
	346	return 0;
	347	}
	348
56f9eac0 DK	349	/*
	350	* The gmbus controller can combine a 1 or 2 byte write with a read that
	351	* immediately follows it by using an "INDEX" cycle.
	352	*/
	353	static bool
	354	gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
	355	{
	356	return (i + 1 < num &&
	357	!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
	358	(msgs[i + 1].flags & I2C_M_RD));
	359	}
	360
	361	static int
	362	gmbus_xfer_index_read(struct drm_i915_private dev_priv, struct i2c_msg msgs)
	363	{
	364	int reg_offset = dev_priv->gpio_mmio_base;
	365	u32 gmbus1_index = 0;
	366	u32 gmbus5 = 0;
	367	int ret;
	368
	369	if (msgs[0].len == 2)
	370	gmbus5 = GMBUS_2BYTE_INDEX_EN \|
	371	msgs[0].buf[1] \| (msgs[0].buf[0] << 8);
	372	if (msgs[0].len == 1)
	373	gmbus1_index = GMBUS_CYCLE_INDEX \|
	374	(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
	375
	376	/* GMBUS5 holds 16-bit index */
	377	if (gmbus5)
	378	I915_WRITE(GMBUS5 + reg_offset, gmbus5);
	379
	380	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
	381
	382	/* Clear GMBUS5 after each index transfer */
	383	if (gmbus5)
	384	I915_WRITE(GMBUS5 + reg_offset, 0);
	385
	386	return ret;
	387	}
	388
f899fc64 CW	389	static int
	390	gmbus_xfer(struct i2c_adapter *adapter,
	391	struct i2c_msg *msgs,
	392	int num)
	393	{
	394	struct intel_gmbus *bus = container_of(adapter,
	395	struct intel_gmbus,
	396	adapter);
c2b9152f	397	struct drm_i915_private *dev_priv = bus->dev_priv;
72d66afd DK	398	int i, reg_offset;
72d66afd DK	399	int ret = 0;
f899fc64	400
c67a470b	401	intel_aux_display_runtime_get(dev_priv);
8a8ed1f5 YS	402	mutex_lock(&dev_priv->gmbus_mutex);
	403
	404	if (bus->force_bit) {
489fbc10	405	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
8a8ed1f5 YS	406	goto out;
8a8ed1f5 YS	407	}
f899fc64	408
110447fc	409	reg_offset = dev_priv->gpio_mmio_base;
f899fc64	410
e957d772	411	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
f899fc64 CW	412
f899fc64 CW	413	for (i = 0; i < num; i++) {
56f9eac0 DK	414	if (gmbus_is_index_read(msgs, i, num)) {
	415	ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
	416	i += 1; /* set i to the index of the read xfer */
	417	} else if (msgs[i].flags & I2C_M_RD) {
	418	ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
	419	} else {
72d66afd	420	ret = gmbus_xfer_write(dev_priv, &msgs[i]);
56f9eac0	421	}
924a93ed DK	422
	423	if (ret == -ETIMEDOUT)
	424	goto timeout;
	425	if (ret == -ENXIO)
	426	goto clear_err;
	427
28c70f16 DV	428	ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
28c70f16 DV	429	GMBUS_HW_WAIT_EN);
61168c53 DV	430	if (ret == -ENXIO)
61168c53 DV	431	goto clear_err;
90e6b26d	432	if (ret)
f899fc64	433	goto timeout;
f899fc64 CW	434	}
f899fc64 CW	435
72d66afd DK	436	/* Generate a STOP condition on the bus. Note that gmbus can't generata
	437	* a STOP on the very first cycle. To simplify the code we
	438	* unconditionally generate the STOP condition with an additional gmbus
	439	* cycle. */
	440	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP \| GMBUS_SW_RDY);
	441
e646d577 DK	442	/* Mark the GMBUS interface as disabled after waiting for idle.
	443	* We will re-enable it at the start of the next xfer,
	444	* till then let it sleep.
	445	*/
2c438c02	446	if (gmbus_wait_idle(dev_priv)) {
56fa6d6f	447	DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
e646d577	448	adapter->name);
72d66afd DK	449	ret = -ETIMEDOUT;
72d66afd DK	450	}
e646d577	451	I915_WRITE(GMBUS0 + reg_offset, 0);
72d66afd	452	ret = ret ?: i;
e646d577	453	goto out;
7f58aabc CW	454
7f58aabc CW	455	clear_err:
e646d577 DK	456	/*
	457	* Wait for bus to IDLE before clearing NAK.
	458	* If we clear the NAK while bus is still active, then it will stay
	459	* active and the next transaction may fail.
65e81866 DV	460	*
	461	* If no ACK is received during the address phase of a transaction, the
	462	* adapter must report -ENXIO. It is not clear what to return if no ACK
	463	* is received at other times. But we have to be careful to not return
	464	* spurious -ENXIO because that will prevent i2c and drm edid functions
	465	* from retrying. So return -ENXIO only when gmbus properly quiescents -
	466	* timing out seems to happen when there _is_ a ddc chip present, but
	467	* it's slow responding and only answers on the 2nd retry.
e646d577	468	*/
65e81866	469	ret = -ENXIO;
2c438c02	470	if (gmbus_wait_idle(dev_priv)) {
56fa6d6f DK	471	DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
56fa6d6f DK	472	adapter->name);
65e81866 DV	473	ret = -ETIMEDOUT;
65e81866 DV	474	}
e646d577	475
7f58aabc CW	476	/* Toggle the Software Clear Interrupt bit. This has the effect
	477	* of resetting the GMBUS controller and so clearing the
	478	* BUS_ERROR raised by the slave's NAK.
	479	*/
	480	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	481	I915_WRITE(GMBUS1 + reg_offset, 0);
e646d577	482	I915_WRITE(GMBUS0 + reg_offset, 0);
7f58aabc	483
56fa6d6f	484	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
e646d577 DK	485	adapter->name, msgs[i].addr,
	486	(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
	487
8a8ed1f5	488	goto out;
f899fc64 CW	489
f899fc64 CW	490	timeout:
874e3cc9 DK	491	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
874e3cc9 DK	492	bus->adapter.name, bus->reg0 & 0xff);
7f58aabc CW	493	I915_WRITE(GMBUS0 + reg_offset, 0);
7f58aabc CW	494
2ed06c93	495	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
f2ce9faf	496	bus->force_bit = 1;
2ed06c93	497	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
489fbc10	498
8a8ed1f5 YS	499	out:
8a8ed1f5 YS	500	mutex_unlock(&dev_priv->gmbus_mutex);
c67a470b	501	intel_aux_display_runtime_put(dev_priv);
8a8ed1f5	502	return ret;
f899fc64 CW	503	}
	504
	505	static u32 gmbus_func(struct i2c_adapter *adapter)
	506	{
f6f808c8 DV	507	return i2c_bit_algo.functionality(adapter) &
f6f808c8 DV	508	(I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
f899fc64 CW	509	/* I2C_FUNC_10BIT_ADDR \| */
	510	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
	511	I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
	512	}
	513
	514	static const struct i2c_algorithm gmbus_algorithm = {
	515	.master_xfer = gmbus_xfer,
	516	.functionality = gmbus_func
	517	};
	518
79e53945	519	/**
f899fc64 CW	520	* intel_gmbus_setup - instantiate all Intel i2c GMBuses
f899fc64 CW	521	* @dev: DRM device
79e53945	522	*/
f899fc64 CW	523	int intel_setup_gmbus(struct drm_device *dev)
f899fc64 CW	524	{
f899fc64	525	struct drm_i915_private *dev_priv = dev->dev_private;
5ea6e5e3 JN	526	struct intel_gmbus *bus;
	527	unsigned int pin;
	528	int ret;
f899fc64	529
ab5c608b BW	530	if (HAS_PCH_NOP(dev))
	531	return 0;
	532	else if (HAS_PCH_SPLIT(dev))
110447fc	533	dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
d8112150 VS	534	else if (IS_VALLEYVIEW(dev))
d8112150 VS	535	dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
110447fc DV	536	else
	537	dev_priv->gpio_mmio_base = 0;
	538
8a8ed1f5	539	mutex_init(&dev_priv->gmbus_mutex);
28c70f16	540	init_waitqueue_head(&dev_priv->gmbus_wait_queue);
8a8ed1f5	541
5ea6e5e3	542	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
88ac7939	543	if (!intel_gmbus_is_valid_pin(dev_priv, pin))
5ea6e5e3 JN	544	continue;
	545
	546	bus = &dev_priv->gmbus[pin];
f899fc64 CW	547
	548	bus->adapter.owner = THIS_MODULE;
	549	bus->adapter.class = I2C_CLASS_DDC;
	550	snprintf(bus->adapter.name,
69669455 JD	551	sizeof(bus->adapter.name),
69669455 JD	552	"i915 gmbus %s",
5ea6e5e3	553	gmbus_pins[pin].name);
f899fc64 CW	554
f899fc64 CW	555	bus->adapter.dev.parent = &dev->pdev->dev;
c2b9152f	556	bus->dev_priv = dev_priv;
f899fc64 CW	557
f899fc64 CW	558	bus->adapter.algo = &gmbus_algorithm;
f899fc64	559
e957d772	560	/* By default use a conservative clock rate */
5ea6e5e3	561	bus->reg0 = pin \| GMBUS_RATE_100KHZ;
cb8ea752	562
83ee9e64 DV	563	/* gmbus seems to be broken on i830 */
83ee9e64 DV	564	if (IS_I830(dev))
f2ce9faf	565	bus->force_bit = 1;
83ee9e64	566
5ea6e5e3	567	intel_gpio_setup(bus, pin);
cee25168 JN	568
	569	ret = i2c_add_adapter(&bus->adapter);
	570	if (ret)
	571	goto err;
f899fc64 CW	572	}
	573
	574	intel_i2c_reset(dev_priv->dev);
	575
	576	return 0;
	577
	578	err:
5ea6e5e3	579	while (--pin) {
88ac7939	580	if (!intel_gmbus_is_valid_pin(dev_priv, pin))
5ea6e5e3 JN	581	continue;
	582
	583	bus = &dev_priv->gmbus[pin];
f899fc64 CW	584	i2c_del_adapter(&bus->adapter);
f899fc64 CW	585	}
f899fc64 CW	586	return ret;
	587	}
	588
3bd7d909	589	struct i2c_adapter intel_gmbus_get_adapter(struct drm_i915_private dev_priv,
0184df46	590	unsigned int pin)
3bd7d909	591	{
88ac7939	592	if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
5ea6e5e3 JN	593	return NULL;
	594
	595	return &dev_priv->gmbus[pin].adapter;
3bd7d909 DK	596	}
3bd7d909 DK	597
e957d772 CW	598	void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
	599	{
	600	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	601
d5090b96	602	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) \| speed;
e957d772 CW	603	}
	604
	605	void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
	606	{
	607	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	608
f2ce9faf CW	609	bus->force_bit += force_bit ? 1 : -1;
	610	DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
	611	force_bit ? "en" : "dis", adapter->name,
	612	bus->force_bit);
e957d772 CW	613	}
e957d772 CW	614
f899fc64	615	void intel_teardown_gmbus(struct drm_device *dev)
79e53945	616	{
f899fc64	617	struct drm_i915_private *dev_priv = dev->dev_private;
5ea6e5e3 JN	618	struct intel_gmbus *bus;
	619	unsigned int pin;
	620
	621	for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
88ac7939	622	if (!intel_gmbus_is_valid_pin(dev_priv, pin))
5ea6e5e3	623	continue;
f9c10a9b	624
5ea6e5e3	625	bus = &dev_priv->gmbus[pin];
f899fc64 CW	626	i2c_del_adapter(&bus->adapter);
f899fc64 CW	627	}
79e53945	628	}