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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 193 | |
0d925ea0 | 194 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 195 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
196 | (reg_state)[(pos)+1] = (val); \ |
197 | } while (0) | |
198 | ||
199 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 200 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
201 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
202 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 203 | } while (0) |
e5815a2e | 204 | |
9244a817 | 205 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
206 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
207 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 208 | } while (0) |
2dba3239 | 209 | |
84b790f8 BW |
210 | enum { |
211 | FAULT_AND_HANG = 0, | |
212 | FAULT_AND_HALT, /* Debug only */ | |
213 | FAULT_AND_STREAM, | |
214 | FAULT_AND_CONTINUE /* Unsupported */ | |
215 | }; | |
216 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 217 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
218 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
219 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 220 | |
0e93cdd4 CW |
221 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
222 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
223 | ||
e2efd130 | 224 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 225 | struct intel_engine_cs *engine); |
e2efd130 | 226 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
e5292823 | 227 | struct intel_engine_cs *engine); |
7ba717cf | 228 | |
73e4d07f OM |
229 | /** |
230 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 231 | * @dev_priv: i915 device private |
73e4d07f OM |
232 | * @enable_execlists: value of i915.enable_execlists module parameter. |
233 | * | |
234 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 235 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
236 | * |
237 | * Return: 1 if Execlists is supported and has to be enabled. | |
238 | */ | |
c033666a | 239 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 240 | { |
a0bd6c31 ZL |
241 | /* On platforms with execlist available, vGPU will only |
242 | * support execlist mode, no ring buffer mode. | |
243 | */ | |
c033666a | 244 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
245 | return 1; |
246 | ||
c033666a | 247 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
248 | return 1; |
249 | ||
127f1003 OM |
250 | if (enable_execlists == 0) |
251 | return 0; | |
252 | ||
5a21b665 DV |
253 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
254 | USES_PPGTT(dev_priv) && | |
255 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
256 | return 1; |
257 | ||
258 | return 0; | |
259 | } | |
ede7d42b | 260 | |
ca82580c | 261 | static void |
0bc40be8 | 262 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 263 | { |
c033666a | 264 | struct drm_i915_private *dev_priv = engine->i915; |
ca82580c | 265 | |
c033666a | 266 | if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) |
0bc40be8 | 267 | engine->idle_lite_restore_wa = ~0; |
c6a2ac71 | 268 | |
c033666a CW |
269 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || |
270 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) && | |
0bc40be8 | 271 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 272 | |
0bc40be8 | 273 | engine->ctx_desc_template = GEN8_CTX_VALID; |
c033666a | 274 | if (IS_GEN8(dev_priv)) |
0bc40be8 TU |
275 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
276 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
277 | |
278 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
279 | * signalling between Command Streamers */ | |
280 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
281 | ||
282 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
283 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
284 | if (engine->disable_lite_restore_wa) |
285 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
286 | } |
287 | ||
73e4d07f | 288 | /** |
ca82580c TU |
289 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
290 | * descriptor for a pinned context | |
ca82580c | 291 | * @ctx: Context to work on |
9021ad03 | 292 | * @engine: Engine the descriptor will be used with |
73e4d07f | 293 | * |
ca82580c TU |
294 | * The context descriptor encodes various attributes of a context, |
295 | * including its GTT address and some flags. Because it's fairly | |
296 | * expensive to calculate, we'll just do it once and cache the result, | |
297 | * which remains valid until the context is unpinned. | |
298 | * | |
6e5248b5 DV |
299 | * This is what a descriptor looks like, from LSB to MSB:: |
300 | * | |
301 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
302 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
303 | * bits 32-52: ctx ID, a globally unique tag | |
304 | * bits 53-54: mbz, reserved for use by hardware | |
305 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 306 | */ |
ca82580c | 307 | static void |
e2efd130 | 308 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 309 | struct intel_engine_cs *engine) |
84b790f8 | 310 | { |
9021ad03 | 311 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 312 | u64 desc; |
84b790f8 | 313 | |
7069b144 | 314 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 315 | |
c01fc532 ZW |
316 | desc = ctx->desc_template; /* bits 3-4 */ |
317 | desc |= engine->ctx_desc_template; /* bits 0-11 */ | |
bde13ebd | 318 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 319 | /* bits 12-31 */ |
7069b144 | 320 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 321 | |
9021ad03 | 322 | ce->lrc_desc = desc; |
5af05fef MT |
323 | } |
324 | ||
e2efd130 | 325 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 326 | struct intel_engine_cs *engine) |
84b790f8 | 327 | { |
0bc40be8 | 328 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 329 | } |
203a571b | 330 | |
cc3c4253 MK |
331 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
332 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 333 | { |
cc3c4253 | 334 | |
4a570db5 | 335 | struct intel_engine_cs *engine = rq0->engine; |
c033666a | 336 | struct drm_i915_private *dev_priv = rq0->i915; |
1cff8cc3 | 337 | uint64_t desc[2]; |
84b790f8 | 338 | |
1cff8cc3 | 339 | if (rq1) { |
4a570db5 | 340 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
1cff8cc3 MK |
341 | rq1->elsp_submitted++; |
342 | } else { | |
343 | desc[1] = 0; | |
344 | } | |
84b790f8 | 345 | |
4a570db5 | 346 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
1cff8cc3 | 347 | rq0->elsp_submitted++; |
84b790f8 | 348 | |
1cff8cc3 | 349 | /* You must always write both descriptors in the order below. */ |
e2f80391 TU |
350 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
351 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); | |
6daccb0b | 352 | |
e2f80391 | 353 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
84b790f8 | 354 | /* The context is automatically loaded after the following */ |
e2f80391 | 355 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
84b790f8 | 356 | |
1cff8cc3 | 357 | /* ELSP is a wo register, use another nearby reg for posting */ |
e2f80391 | 358 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
84b790f8 BW |
359 | } |
360 | ||
c6a2ac71 TU |
361 | static void |
362 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
363 | { | |
364 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
365 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
366 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
367 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
368 | } | |
369 | ||
370 | static void execlists_update_context(struct drm_i915_gem_request *rq) | |
ae1250b9 | 371 | { |
4a570db5 | 372 | struct intel_engine_cs *engine = rq->engine; |
05d9824b | 373 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
e2f80391 | 374 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
ae1250b9 | 375 | |
8f942018 | 376 | reg_state[CTX_RING_TAIL+1] = intel_ring_offset(rq->ring, rq->tail); |
ae1250b9 | 377 | |
c6a2ac71 TU |
378 | /* True 32b PPGTT with dynamic page allocation: update PDP |
379 | * registers and point the unallocated PDPs to scratch page. | |
380 | * PML4 is allocated during ppgtt init, so this is not needed | |
381 | * in 48-bit mode. | |
382 | */ | |
383 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
384 | execlists_update_context_pdps(ppgtt, reg_state); | |
ae1250b9 OM |
385 | } |
386 | ||
f4ea6bdd CW |
387 | static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0, |
388 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 389 | { |
26720ab9 | 390 | struct drm_i915_private *dev_priv = rq0->i915; |
3756685a | 391 | unsigned int fw_domains = rq0->engine->fw_domains; |
26720ab9 | 392 | |
05d9824b | 393 | execlists_update_context(rq0); |
d8cb8875 | 394 | |
cc3c4253 | 395 | if (rq1) |
05d9824b | 396 | execlists_update_context(rq1); |
84b790f8 | 397 | |
27af5eea | 398 | spin_lock_irq(&dev_priv->uncore.lock); |
3756685a | 399 | intel_uncore_forcewake_get__locked(dev_priv, fw_domains); |
26720ab9 | 400 | |
cc3c4253 | 401 | execlists_elsp_write(rq0, rq1); |
26720ab9 | 402 | |
3756685a | 403 | intel_uncore_forcewake_put__locked(dev_priv, fw_domains); |
27af5eea | 404 | spin_unlock_irq(&dev_priv->uncore.lock); |
84b790f8 BW |
405 | } |
406 | ||
3c7ba635 ZW |
407 | static inline void execlists_context_status_change( |
408 | struct drm_i915_gem_request *rq, | |
409 | unsigned long status) | |
410 | { | |
411 | /* | |
412 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
413 | * The compiler should eliminate this function as dead-code. | |
414 | */ | |
415 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
416 | return; | |
417 | ||
418 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); | |
419 | } | |
420 | ||
f4ea6bdd | 421 | static void execlists_unqueue(struct intel_engine_cs *engine) |
acdd884a | 422 | { |
6d3d8274 | 423 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
c6a2ac71 | 424 | struct drm_i915_gem_request *cursor, *tmp; |
e981e7b1 | 425 | |
0bc40be8 | 426 | assert_spin_locked(&engine->execlist_lock); |
acdd884a | 427 | |
779949f4 PA |
428 | /* |
429 | * If irqs are not active generate a warning as batches that finish | |
430 | * without the irqs may get lost and a GPU Hang may occur. | |
431 | */ | |
c033666a | 432 | WARN_ON(!intel_irqs_enabled(engine->i915)); |
779949f4 | 433 | |
acdd884a | 434 | /* Try to read in pairs */ |
0bc40be8 | 435 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
acdd884a MT |
436 | execlist_link) { |
437 | if (!req0) { | |
438 | req0 = cursor; | |
6d3d8274 | 439 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
440 | /* Same ctx: ignore first request, as second request |
441 | * will update tail past first request's workload */ | |
e1fee72c | 442 | cursor->elsp_submitted = req0->elsp_submitted; |
e39d42fa | 443 | list_del(&req0->execlist_link); |
e8a261ea | 444 | i915_gem_request_put(req0); |
acdd884a MT |
445 | req0 = cursor; |
446 | } else { | |
80a9a8db ZW |
447 | if (IS_ENABLED(CONFIG_DRM_I915_GVT)) { |
448 | /* | |
449 | * req0 (after merged) ctx requires single | |
450 | * submission, stop picking | |
451 | */ | |
452 | if (req0->ctx->execlists_force_single_submission) | |
453 | break; | |
454 | /* | |
455 | * req0 ctx doesn't require single submission, | |
456 | * but next req ctx requires, stop picking | |
457 | */ | |
458 | if (cursor->ctx->execlists_force_single_submission) | |
459 | break; | |
460 | } | |
acdd884a | 461 | req1 = cursor; |
c6a2ac71 | 462 | WARN_ON(req1->elsp_submitted); |
acdd884a MT |
463 | break; |
464 | } | |
465 | } | |
466 | ||
c6a2ac71 TU |
467 | if (unlikely(!req0)) |
468 | return; | |
469 | ||
3c7ba635 ZW |
470 | execlists_context_status_change(req0, INTEL_CONTEXT_SCHEDULE_IN); |
471 | ||
472 | if (req1) | |
473 | execlists_context_status_change(req1, | |
474 | INTEL_CONTEXT_SCHEDULE_IN); | |
475 | ||
0bc40be8 | 476 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
53292cdb | 477 | /* |
c6a2ac71 TU |
478 | * WaIdleLiteRestore: make sure we never cause a lite restore |
479 | * with HEAD==TAIL. | |
480 | * | |
481 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we | |
482 | * resubmit the request. See gen8_emit_request() for where we | |
483 | * prepare the padding after the end of the request. | |
53292cdb | 484 | */ |
c6a2ac71 | 485 | req0->tail += 8; |
dca33ecc | 486 | req0->tail &= req0->ring->size - 1; |
53292cdb MT |
487 | } |
488 | ||
f4ea6bdd | 489 | execlists_elsp_submit_contexts(req0, req1); |
acdd884a MT |
490 | } |
491 | ||
c6a2ac71 | 492 | static unsigned int |
e39d42fa | 493 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id) |
e981e7b1 | 494 | { |
6d3d8274 | 495 | struct drm_i915_gem_request *head_req; |
e981e7b1 | 496 | |
0bc40be8 | 497 | assert_spin_locked(&engine->execlist_lock); |
e981e7b1 | 498 | |
0bc40be8 | 499 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
6d3d8274 | 500 | struct drm_i915_gem_request, |
e981e7b1 TD |
501 | execlist_link); |
502 | ||
e39d42fa TU |
503 | if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id))) |
504 | return 0; | |
c6a2ac71 TU |
505 | |
506 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); | |
507 | ||
508 | if (--head_req->elsp_submitted > 0) | |
509 | return 0; | |
510 | ||
3c7ba635 ZW |
511 | execlists_context_status_change(head_req, INTEL_CONTEXT_SCHEDULE_OUT); |
512 | ||
e39d42fa | 513 | list_del(&head_req->execlist_link); |
e8a261ea | 514 | i915_gem_request_put(head_req); |
e981e7b1 | 515 | |
c6a2ac71 | 516 | return 1; |
e981e7b1 TD |
517 | } |
518 | ||
c6a2ac71 | 519 | static u32 |
0bc40be8 | 520 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
c6a2ac71 | 521 | u32 *context_id) |
91a41032 | 522 | { |
c033666a | 523 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 524 | u32 status; |
91a41032 | 525 | |
c6a2ac71 TU |
526 | read_pointer %= GEN8_CSB_ENTRIES; |
527 | ||
0bc40be8 | 528 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
c6a2ac71 TU |
529 | |
530 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) | |
531 | return 0; | |
91a41032 | 532 | |
0bc40be8 | 533 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
c6a2ac71 TU |
534 | read_pointer)); |
535 | ||
536 | return status; | |
91a41032 BW |
537 | } |
538 | ||
6e5248b5 | 539 | /* |
73e4d07f OM |
540 | * Check the unread Context Status Buffers and manage the submission of new |
541 | * contexts to the ELSP accordingly. | |
542 | */ | |
27af5eea | 543 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 544 | { |
27af5eea | 545 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
c033666a | 546 | struct drm_i915_private *dev_priv = engine->i915; |
e981e7b1 | 547 | u32 status_pointer; |
c6a2ac71 | 548 | unsigned int read_pointer, write_pointer; |
26720ab9 TU |
549 | u32 csb[GEN8_CSB_ENTRIES][2]; |
550 | unsigned int csb_read = 0, i; | |
c6a2ac71 TU |
551 | unsigned int submit_contexts = 0; |
552 | ||
3756685a | 553 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 554 | |
0bc40be8 | 555 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
e981e7b1 | 556 | |
0bc40be8 | 557 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 558 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
e981e7b1 | 559 | if (read_pointer > write_pointer) |
dfc53c5e | 560 | write_pointer += GEN8_CSB_ENTRIES; |
e981e7b1 | 561 | |
e981e7b1 | 562 | while (read_pointer < write_pointer) { |
26720ab9 TU |
563 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
564 | break; | |
565 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, | |
566 | &csb[csb_read][1]); | |
567 | csb_read++; | |
568 | } | |
91a41032 | 569 | |
26720ab9 TU |
570 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
571 | ||
572 | /* Update the read pointer to the old write pointer. Manual ringbuffer | |
573 | * management ftw </sarcasm> */ | |
574 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), | |
575 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, | |
576 | engine->next_context_status_buffer << 8)); | |
577 | ||
3756685a | 578 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
26720ab9 TU |
579 | |
580 | spin_lock(&engine->execlist_lock); | |
581 | ||
582 | for (i = 0; i < csb_read; i++) { | |
583 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { | |
584 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { | |
585 | if (execlists_check_remove_request(engine, csb[i][1])) | |
e1fee72c OM |
586 | WARN(1, "Lite Restored request removed from queue\n"); |
587 | } else | |
588 | WARN(1, "Preemption without Lite Restore\n"); | |
589 | } | |
590 | ||
26720ab9 | 591 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
c6a2ac71 TU |
592 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
593 | submit_contexts += | |
26720ab9 | 594 | execlists_check_remove_request(engine, csb[i][1]); |
e981e7b1 TD |
595 | } |
596 | ||
c6a2ac71 | 597 | if (submit_contexts) { |
0bc40be8 | 598 | if (!engine->disable_lite_restore_wa || |
26720ab9 | 599 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
f4ea6bdd | 600 | execlists_unqueue(engine); |
5af05fef | 601 | } |
e981e7b1 | 602 | |
0bc40be8 | 603 | spin_unlock(&engine->execlist_lock); |
c6a2ac71 TU |
604 | |
605 | if (unlikely(submit_contexts > 2)) | |
606 | DRM_ERROR("More than two context complete events?\n"); | |
e981e7b1 TD |
607 | } |
608 | ||
f4ea6bdd | 609 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 610 | { |
4a570db5 | 611 | struct intel_engine_cs *engine = request->engine; |
6d3d8274 | 612 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 613 | int num_elements = 0; |
acdd884a | 614 | |
27af5eea | 615 | spin_lock_bh(&engine->execlist_lock); |
acdd884a | 616 | |
e2f80391 | 617 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
f1ad5a1f OM |
618 | if (++num_elements > 2) |
619 | break; | |
620 | ||
621 | if (num_elements > 2) { | |
6d3d8274 | 622 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f | 623 | |
e2f80391 | 624 | tail_req = list_last_entry(&engine->execlist_queue, |
6d3d8274 | 625 | struct drm_i915_gem_request, |
f1ad5a1f OM |
626 | execlist_link); |
627 | ||
ae70797d | 628 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 629 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 630 | "More than 2 already-submitted reqs queued\n"); |
e39d42fa | 631 | list_del(&tail_req->execlist_link); |
e8a261ea | 632 | i915_gem_request_put(tail_req); |
f1ad5a1f OM |
633 | } |
634 | } | |
635 | ||
e8a261ea | 636 | i915_gem_request_get(request); |
e2f80391 | 637 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
a3d12761 | 638 | request->ctx_hw_id = request->ctx->hw_id; |
f1ad5a1f | 639 | if (num_elements == 0) |
f4ea6bdd | 640 | execlists_unqueue(engine); |
acdd884a | 641 | |
27af5eea | 642 | spin_unlock_bh(&engine->execlist_lock); |
acdd884a MT |
643 | } |
644 | ||
40e895ce | 645 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 646 | { |
24f1d3cc | 647 | struct intel_engine_cs *engine = request->engine; |
9021ad03 | 648 | struct intel_context *ce = &request->ctx->engine[engine->id]; |
bfa01200 | 649 | int ret; |
bc0dce3f | 650 | |
6310346e CW |
651 | /* Flush enough space to reduce the likelihood of waiting after |
652 | * we start building the request - in which case we will just | |
653 | * have to repeat work. | |
654 | */ | |
0e93cdd4 | 655 | request->reserved_space += EXECLISTS_REQUEST_SIZE; |
6310346e | 656 | |
9021ad03 | 657 | if (!ce->state) { |
978f1e09 CW |
658 | ret = execlists_context_deferred_alloc(request->ctx, engine); |
659 | if (ret) | |
660 | return ret; | |
661 | } | |
662 | ||
dca33ecc | 663 | request->ring = ce->ring; |
f3cc01f0 | 664 | |
a7e02199 AD |
665 | if (i915.enable_guc_submission) { |
666 | /* | |
667 | * Check that the GuC has space for the request before | |
668 | * going any further, as the i915_add_request() call | |
669 | * later on mustn't fail ... | |
670 | */ | |
7c2c270d | 671 | ret = i915_guc_wq_check_space(request); |
a7e02199 AD |
672 | if (ret) |
673 | return ret; | |
674 | } | |
675 | ||
24f1d3cc CW |
676 | ret = intel_lr_context_pin(request->ctx, engine); |
677 | if (ret) | |
678 | return ret; | |
e28e404c | 679 | |
bfa01200 CW |
680 | ret = intel_ring_begin(request, 0); |
681 | if (ret) | |
682 | goto err_unpin; | |
683 | ||
9021ad03 | 684 | if (!ce->initialised) { |
24f1d3cc CW |
685 | ret = engine->init_context(request); |
686 | if (ret) | |
687 | goto err_unpin; | |
688 | ||
9021ad03 | 689 | ce->initialised = true; |
24f1d3cc CW |
690 | } |
691 | ||
692 | /* Note that after this point, we have committed to using | |
693 | * this request as it is being used to both track the | |
694 | * state of engine initialisation and liveness of the | |
695 | * golden renderstate above. Think twice before you try | |
696 | * to cancel/unwind this request now. | |
697 | */ | |
698 | ||
0e93cdd4 | 699 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; |
bfa01200 CW |
700 | return 0; |
701 | ||
702 | err_unpin: | |
24f1d3cc | 703 | intel_lr_context_unpin(request->ctx, engine); |
e28e404c | 704 | return ret; |
bc0dce3f JH |
705 | } |
706 | ||
bc0dce3f | 707 | /* |
ddd66c51 | 708 | * intel_logical_ring_advance() - advance the tail and prepare for submission |
ae70797d | 709 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
710 | * |
711 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
712 | * really happens during submission is that the context and current tail will be placed | |
713 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
714 | * point, the tail *inside* the context is updated and the ELSP written to. | |
715 | */ | |
7c17d377 | 716 | static int |
ddd66c51 | 717 | intel_logical_ring_advance(struct drm_i915_gem_request *request) |
bc0dce3f | 718 | { |
7e37f889 | 719 | struct intel_ring *ring = request->ring; |
4a570db5 | 720 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 721 | |
1dae2dfb CW |
722 | intel_ring_advance(ring); |
723 | request->tail = ring->tail; | |
bc0dce3f | 724 | |
7c17d377 CW |
725 | /* |
726 | * Here we add two extra NOOPs as padding to avoid | |
727 | * lite restore of a context with HEAD==TAIL. | |
728 | * | |
729 | * Caller must reserve WA_TAIL_DWORDS for us! | |
730 | */ | |
1dae2dfb CW |
731 | intel_ring_emit(ring, MI_NOOP); |
732 | intel_ring_emit(ring, MI_NOOP); | |
733 | intel_ring_advance(ring); | |
d1675198 | 734 | |
a16a4052 CW |
735 | /* We keep the previous context alive until we retire the following |
736 | * request. This ensures that any the context object is still pinned | |
737 | * for any residual writes the HW makes into it on the context switch | |
738 | * into the next object following the breadcrumb. Otherwise, we may | |
739 | * retire the context too early. | |
740 | */ | |
741 | request->previous_context = engine->last_context; | |
742 | engine->last_context = request->ctx; | |
7c17d377 | 743 | return 0; |
bc0dce3f JH |
744 | } |
745 | ||
e39d42fa | 746 | void intel_execlists_cancel_requests(struct intel_engine_cs *engine) |
c86ee3a9 | 747 | { |
6d3d8274 | 748 | struct drm_i915_gem_request *req, *tmp; |
e39d42fa | 749 | LIST_HEAD(cancel_list); |
c86ee3a9 | 750 | |
91c8a326 | 751 | WARN_ON(!mutex_is_locked(&engine->i915->drm.struct_mutex)); |
c86ee3a9 | 752 | |
27af5eea | 753 | spin_lock_bh(&engine->execlist_lock); |
e39d42fa | 754 | list_replace_init(&engine->execlist_queue, &cancel_list); |
27af5eea | 755 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 | 756 | |
e39d42fa | 757 | list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) { |
c86ee3a9 | 758 | list_del(&req->execlist_link); |
e8a261ea | 759 | i915_gem_request_put(req); |
c86ee3a9 TD |
760 | } |
761 | } | |
762 | ||
e2efd130 | 763 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
24f1d3cc | 764 | struct intel_engine_cs *engine) |
dcb4c12a | 765 | { |
9021ad03 | 766 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac TU |
767 | void *vaddr; |
768 | u32 *lrc_reg_state; | |
ca82580c | 769 | int ret; |
dcb4c12a | 770 | |
91c8a326 | 771 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 772 | |
9021ad03 | 773 | if (ce->pin_count++) |
24f1d3cc CW |
774 | return 0; |
775 | ||
bf3783e5 CW |
776 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, |
777 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL); | |
e84fe803 | 778 | if (ret) |
24f1d3cc | 779 | goto err; |
7ba717cf | 780 | |
bf3783e5 | 781 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
782 | if (IS_ERR(vaddr)) { |
783 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 784 | goto unpin_vma; |
82352e90 TU |
785 | } |
786 | ||
7d774cac TU |
787 | lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
788 | ||
aad29fbb | 789 | ret = intel_ring_pin(ce->ring); |
e84fe803 | 790 | if (ret) |
7d774cac | 791 | goto unpin_map; |
d1675198 | 792 | |
0bc40be8 | 793 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 794 | |
bde13ebd CW |
795 | lrc_reg_state[CTX_RING_BUFFER_START+1] = |
796 | i915_ggtt_offset(ce->ring->vma); | |
9021ad03 | 797 | ce->lrc_reg_state = lrc_reg_state; |
bf3783e5 | 798 | ce->state->obj->dirty = true; |
e93c28f3 | 799 | |
e84fe803 | 800 | /* Invalidate GuC TLB. */ |
bf3783e5 CW |
801 | if (i915.enable_guc_submission) { |
802 | struct drm_i915_private *dev_priv = ctx->i915; | |
e84fe803 | 803 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
bf3783e5 | 804 | } |
dcb4c12a | 805 | |
9a6feaf0 | 806 | i915_gem_context_get(ctx); |
24f1d3cc | 807 | return 0; |
7ba717cf | 808 | |
7d774cac | 809 | unpin_map: |
bf3783e5 CW |
810 | i915_gem_object_unpin_map(ce->state->obj); |
811 | unpin_vma: | |
812 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 813 | err: |
9021ad03 | 814 | ce->pin_count = 0; |
e84fe803 NH |
815 | return ret; |
816 | } | |
817 | ||
e2efd130 | 818 | void intel_lr_context_unpin(struct i915_gem_context *ctx, |
24f1d3cc | 819 | struct intel_engine_cs *engine) |
e84fe803 | 820 | { |
9021ad03 | 821 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 822 | |
91c8a326 | 823 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 824 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 825 | |
9021ad03 | 826 | if (--ce->pin_count) |
24f1d3cc | 827 | return; |
e84fe803 | 828 | |
aad29fbb | 829 | intel_ring_unpin(ce->ring); |
dcb4c12a | 830 | |
bf3783e5 CW |
831 | i915_gem_object_unpin_map(ce->state->obj); |
832 | i915_vma_unpin(ce->state); | |
321fe304 | 833 | |
9a6feaf0 | 834 | i915_gem_context_put(ctx); |
dcb4c12a OM |
835 | } |
836 | ||
e2be4faf | 837 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
838 | { |
839 | int ret, i; | |
7e37f889 | 840 | struct intel_ring *ring = req->ring; |
c033666a | 841 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 842 | |
cd7feaaa | 843 | if (w->count == 0) |
771b9a53 MT |
844 | return 0; |
845 | ||
7c9cf4e3 | 846 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
847 | if (ret) |
848 | return ret; | |
849 | ||
987046ad | 850 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
851 | if (ret) |
852 | return ret; | |
853 | ||
1dae2dfb | 854 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
771b9a53 | 855 | for (i = 0; i < w->count; i++) { |
1dae2dfb CW |
856 | intel_ring_emit_reg(ring, w->reg[i].addr); |
857 | intel_ring_emit(ring, w->reg[i].value); | |
771b9a53 | 858 | } |
1dae2dfb | 859 | intel_ring_emit(ring, MI_NOOP); |
771b9a53 | 860 | |
1dae2dfb | 861 | intel_ring_advance(ring); |
771b9a53 | 862 | |
7c9cf4e3 | 863 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
864 | if (ret) |
865 | return ret; | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
83b8a982 | 870 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 871 | do { \ |
83b8a982 AS |
872 | int __index = (index)++; \ |
873 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
874 | return -ENOSPC; \ |
875 | } \ | |
83b8a982 | 876 | batch[__index] = (cmd); \ |
17ee950d AS |
877 | } while (0) |
878 | ||
8f40db77 | 879 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 880 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
881 | |
882 | /* | |
883 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
884 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
885 | * but there is a slight complication as this is applied in WA batch where the | |
886 | * values are only initialized once so we cannot take register value at the | |
887 | * beginning and reuse it further; hence we save its value to memory, upload a | |
888 | * constant value with bit21 set and then we restore it back with the saved value. | |
889 | * To simplify the WA, a constant value is formed by using the default value | |
890 | * of this register. This shouldn't be a problem because we are only modifying | |
891 | * it for a short period and this batch in non-premptible. We can ofcourse | |
892 | * use additional instructions that read the actual value of the register | |
893 | * at that time and set our bit of interest but it makes the WA complicated. | |
894 | * | |
895 | * This WA is also required for Gen9 so extracting as a function avoids | |
896 | * code duplication. | |
897 | */ | |
0bc40be8 | 898 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
6e5248b5 | 899 | uint32_t *batch, |
9e000847 AS |
900 | uint32_t index) |
901 | { | |
5e580523 | 902 | struct drm_i915_private *dev_priv = engine->i915; |
9e000847 AS |
903 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
904 | ||
a4106a78 | 905 | /* |
fe905819 | 906 | * WaDisableLSQCROPERFforOCL:skl,kbl |
a4106a78 AS |
907 | * This WA is implemented in skl_init_clock_gating() but since |
908 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
909 | * set this bit here to retain the WA during flush. | |
910 | */ | |
738fa1b3 MK |
911 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) || |
912 | IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
a4106a78 AS |
913 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
914 | ||
f1afe24f | 915 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 916 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 917 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 918 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 AS |
919 | wa_ctx_emit(batch, index, 0); |
920 | ||
921 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 922 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
923 | wa_ctx_emit(batch, index, l3sqc4_flush); |
924 | ||
925 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
926 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
927 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
928 | wa_ctx_emit(batch, index, 0); | |
929 | wa_ctx_emit(batch, index, 0); | |
930 | wa_ctx_emit(batch, index, 0); | |
931 | wa_ctx_emit(batch, index, 0); | |
932 | ||
f1afe24f | 933 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 934 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 935 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 936 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 | 937 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
938 | |
939 | return index; | |
940 | } | |
941 | ||
17ee950d AS |
942 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
943 | uint32_t offset, | |
944 | uint32_t start_alignment) | |
945 | { | |
946 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
947 | } | |
948 | ||
949 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
950 | uint32_t offset, | |
951 | uint32_t size_alignment) | |
952 | { | |
953 | wa_ctx->size = offset - wa_ctx->offset; | |
954 | ||
955 | WARN(wa_ctx->size % size_alignment, | |
956 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
957 | wa_ctx->size, size_alignment); | |
958 | return 0; | |
959 | } | |
960 | ||
6e5248b5 DV |
961 | /* |
962 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
963 | * initialized at the beginning and shared across all contexts but this field | |
964 | * helps us to have multiple batches at different offsets and select them based | |
965 | * on a criteria. At the moment this batch always start at the beginning of the page | |
966 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 967 | * |
6e5248b5 DV |
968 | * The number of WA applied are not known at the beginning; we use this field |
969 | * to return the no of DWORDS written. | |
17ee950d | 970 | * |
6e5248b5 DV |
971 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
972 | * so it adds NOOPs as padding to make it cacheline aligned. | |
973 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
974 | * makes a complete batch buffer. | |
17ee950d | 975 | */ |
0bc40be8 | 976 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d | 977 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 978 | uint32_t *batch, |
17ee950d AS |
979 | uint32_t *offset) |
980 | { | |
0160f055 | 981 | uint32_t scratch_addr; |
17ee950d AS |
982 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
983 | ||
7ad00d1a | 984 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 985 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 986 | |
c82435bb | 987 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 988 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 989 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
990 | if (rc < 0) |
991 | return rc; | |
992 | index = rc; | |
c82435bb AS |
993 | } |
994 | ||
0160f055 AS |
995 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
996 | /* Actual scratch location is at 128 bytes offset */ | |
bde13ebd | 997 | scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
0160f055 | 998 | |
83b8a982 AS |
999 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1000 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1001 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1002 | PIPE_CONTROL_CS_STALL | | |
1003 | PIPE_CONTROL_QW_WRITE)); | |
1004 | wa_ctx_emit(batch, index, scratch_addr); | |
1005 | wa_ctx_emit(batch, index, 0); | |
1006 | wa_ctx_emit(batch, index, 0); | |
1007 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1008 | |
17ee950d AS |
1009 | /* Pad to end of cacheline */ |
1010 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1011 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1012 | |
1013 | /* | |
1014 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1015 | * execution depends on the length specified in terms of cache lines | |
1016 | * in the register CTX_RCS_INDIRECT_CTX | |
1017 | */ | |
1018 | ||
1019 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1020 | } | |
1021 | ||
6e5248b5 DV |
1022 | /* |
1023 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1024 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1025 | * |
6e5248b5 | 1026 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1027 | * |
1028 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1029 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1030 | */ | |
0bc40be8 | 1031 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d | 1032 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1033 | uint32_t *batch, |
17ee950d AS |
1034 | uint32_t *offset) |
1035 | { | |
1036 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1037 | ||
7ad00d1a | 1038 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1039 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1040 | |
83b8a982 | 1041 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1042 | |
1043 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1044 | } | |
1045 | ||
0bc40be8 | 1046 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1047 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1048 | uint32_t *batch, |
0504cffc AS |
1049 | uint32_t *offset) |
1050 | { | |
a4106a78 | 1051 | int ret; |
5e580523 | 1052 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
1053 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1054 | ||
0907c8f7 | 1055 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
5e580523 DA |
1056 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) || |
1057 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
0907c8f7 | 1058 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1059 | |
a4106a78 | 1060 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1061 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1062 | if (ret < 0) |
1063 | return ret; | |
1064 | index = ret; | |
1065 | ||
873e8171 MK |
1066 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ |
1067 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1068 | wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); | |
1069 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( | |
1070 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); | |
1071 | wa_ctx_emit(batch, index, MI_NOOP); | |
1072 | ||
066d4628 MK |
1073 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1074 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1075 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
56c0f1a7 | 1076 | u32 scratch_addr = |
bde13ebd | 1077 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
066d4628 MK |
1078 | |
1079 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1080 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1081 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1082 | PIPE_CONTROL_CS_STALL | | |
1083 | PIPE_CONTROL_QW_WRITE)); | |
1084 | wa_ctx_emit(batch, index, scratch_addr); | |
1085 | wa_ctx_emit(batch, index, 0); | |
1086 | wa_ctx_emit(batch, index, 0); | |
1087 | wa_ctx_emit(batch, index, 0); | |
1088 | } | |
3485d99e TG |
1089 | |
1090 | /* WaMediaPoolStateCmdInWABB:bxt */ | |
1091 | if (HAS_POOLED_EU(engine->i915)) { | |
1092 | /* | |
1093 | * EU pool configuration is setup along with golden context | |
1094 | * during context initialization. This value depends on | |
1095 | * device type (2x6 or 3x6) and needs to be updated based | |
1096 | * on which subslice is disabled especially for 2x6 | |
1097 | * devices, however it is safe to load default | |
1098 | * configuration of 3x6 device instead of masking off | |
1099 | * corresponding bits because HW ignores bits of a disabled | |
1100 | * subslice and drops down to appropriate config. Please | |
1101 | * see render_state_setup() in i915_gem_render_state.c for | |
1102 | * possible configurations, to avoid duplication they are | |
1103 | * not shown here again. | |
1104 | */ | |
1105 | u32 eu_pool_config = 0x00777000; | |
1106 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1107 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1108 | wa_ctx_emit(batch, index, eu_pool_config); | |
1109 | wa_ctx_emit(batch, index, 0); | |
1110 | wa_ctx_emit(batch, index, 0); | |
1111 | wa_ctx_emit(batch, index, 0); | |
1112 | } | |
1113 | ||
0504cffc AS |
1114 | /* Pad to end of cacheline */ |
1115 | while (index % CACHELINE_DWORDS) | |
1116 | wa_ctx_emit(batch, index, MI_NOOP); | |
1117 | ||
1118 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1119 | } | |
1120 | ||
0bc40be8 | 1121 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1122 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1123 | uint32_t *batch, |
0504cffc AS |
1124 | uint32_t *offset) |
1125 | { | |
1126 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1127 | ||
9b01435d | 1128 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
1129 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) || |
1130 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { | |
9b01435d | 1131 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1132 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1133 | wa_ctx_emit(batch, index, |
1134 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1135 | wa_ctx_emit(batch, index, MI_NOOP); | |
1136 | } | |
1137 | ||
b1e429fe | 1138 | /* WaClearTdlStateAckDirtyBits:bxt */ |
c033666a | 1139 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) { |
b1e429fe TG |
1140 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
1141 | ||
1142 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1143 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1144 | ||
1145 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1146 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1147 | ||
1148 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1149 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1150 | ||
1151 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1152 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1153 | wa_ctx_emit(batch, index, 0x0); | |
1154 | wa_ctx_emit(batch, index, MI_NOOP); | |
1155 | } | |
1156 | ||
0907c8f7 | 1157 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
c033666a CW |
1158 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) || |
1159 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) | |
0907c8f7 AS |
1160 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1161 | ||
0504cffc AS |
1162 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1163 | ||
1164 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1165 | } | |
1166 | ||
0bc40be8 | 1167 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d | 1168 | { |
48bb74e4 CW |
1169 | struct drm_i915_gem_object *obj; |
1170 | struct i915_vma *vma; | |
1171 | int err; | |
17ee950d | 1172 | |
48bb74e4 CW |
1173 | obj = i915_gem_object_create(&engine->i915->drm, PAGE_ALIGN(size)); |
1174 | if (IS_ERR(obj)) | |
1175 | return PTR_ERR(obj); | |
17ee950d | 1176 | |
48bb74e4 CW |
1177 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1178 | if (IS_ERR(vma)) { | |
1179 | err = PTR_ERR(vma); | |
1180 | goto err; | |
17ee950d AS |
1181 | } |
1182 | ||
48bb74e4 CW |
1183 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1184 | if (err) | |
1185 | goto err; | |
1186 | ||
1187 | engine->wa_ctx.vma = vma; | |
17ee950d | 1188 | return 0; |
48bb74e4 CW |
1189 | |
1190 | err: | |
1191 | i915_gem_object_put(obj); | |
1192 | return err; | |
17ee950d AS |
1193 | } |
1194 | ||
0bc40be8 | 1195 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1196 | { |
19880c4a | 1197 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1198 | } |
1199 | ||
0bc40be8 | 1200 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1201 | { |
48bb74e4 | 1202 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d AS |
1203 | uint32_t *batch; |
1204 | uint32_t offset; | |
1205 | struct page *page; | |
48bb74e4 | 1206 | int ret; |
17ee950d | 1207 | |
0bc40be8 | 1208 | WARN_ON(engine->id != RCS); |
17ee950d | 1209 | |
5e60d790 | 1210 | /* update this when WA for higher Gen are added */ |
c033666a | 1211 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1212 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1213 | INTEL_GEN(engine->i915)); |
5e60d790 | 1214 | return 0; |
0504cffc | 1215 | } |
5e60d790 | 1216 | |
c4db7599 | 1217 | /* some WA perform writes to scratch page, ensure it is valid */ |
56c0f1a7 | 1218 | if (!engine->scratch) { |
0bc40be8 | 1219 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
c4db7599 AS |
1220 | return -EINVAL; |
1221 | } | |
1222 | ||
0bc40be8 | 1223 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1224 | if (ret) { |
1225 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1226 | return ret; | |
1227 | } | |
1228 | ||
48bb74e4 | 1229 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
17ee950d AS |
1230 | batch = kmap_atomic(page); |
1231 | offset = 0; | |
1232 | ||
c033666a | 1233 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1234 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1235 | &wa_ctx->indirect_ctx, |
1236 | batch, | |
1237 | &offset); | |
1238 | if (ret) | |
1239 | goto out; | |
1240 | ||
0bc40be8 | 1241 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1242 | &wa_ctx->per_ctx, |
1243 | batch, | |
1244 | &offset); | |
1245 | if (ret) | |
1246 | goto out; | |
c033666a | 1247 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1248 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1249 | &wa_ctx->indirect_ctx, |
1250 | batch, | |
1251 | &offset); | |
1252 | if (ret) | |
1253 | goto out; | |
1254 | ||
0bc40be8 | 1255 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1256 | &wa_ctx->per_ctx, |
1257 | batch, | |
1258 | &offset); | |
1259 | if (ret) | |
1260 | goto out; | |
17ee950d AS |
1261 | } |
1262 | ||
1263 | out: | |
1264 | kunmap_atomic(batch); | |
1265 | if (ret) | |
0bc40be8 | 1266 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1267 | |
1268 | return ret; | |
1269 | } | |
1270 | ||
04794adb TU |
1271 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1272 | { | |
c033666a | 1273 | struct drm_i915_private *dev_priv = engine->i915; |
04794adb TU |
1274 | |
1275 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
57e88531 | 1276 | engine->status_page.ggtt_offset); |
04794adb TU |
1277 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
1278 | } | |
1279 | ||
0bc40be8 | 1280 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1281 | { |
c033666a | 1282 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 1283 | unsigned int next_context_status_buffer_hw; |
9b1136d5 | 1284 | |
04794adb | 1285 | lrc_init_hws(engine); |
e84fe803 | 1286 | |
0bc40be8 TU |
1287 | I915_WRITE_IMR(engine, |
1288 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1289 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
73d477f6 | 1290 | |
0bc40be8 | 1291 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1292 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1293 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
0bc40be8 | 1294 | POSTING_READ(RING_MODE_GEN7(engine)); |
dfc53c5e MT |
1295 | |
1296 | /* | |
1297 | * Instead of resetting the Context Status Buffer (CSB) read pointer to | |
1298 | * zero, we need to read the write pointer from hardware and use its | |
1299 | * value because "this register is power context save restored". | |
1300 | * Effectively, these states have been observed: | |
1301 | * | |
1302 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | | |
1303 | * BDW | CSB regs not reset | CSB regs reset | | |
1304 | * CHT | CSB regs not reset | CSB regs not reset | | |
5590a5f0 BW |
1305 | * SKL | ? | ? | |
1306 | * BXT | ? | ? | | |
dfc53c5e | 1307 | */ |
5590a5f0 | 1308 | next_context_status_buffer_hw = |
0bc40be8 | 1309 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
dfc53c5e MT |
1310 | |
1311 | /* | |
1312 | * When the CSB registers are reset (also after power-up / gpu reset), | |
1313 | * CSB write pointer is set to all 1's, which is not valid, use '5' in | |
1314 | * this special case, so the first element read is CSB[0]. | |
1315 | */ | |
1316 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) | |
1317 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); | |
1318 | ||
0bc40be8 TU |
1319 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
1320 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); | |
9b1136d5 | 1321 | |
fc0768ce | 1322 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1323 | |
0ccdacf6 | 1324 | return intel_mocs_init_engine(engine); |
9b1136d5 OM |
1325 | } |
1326 | ||
0bc40be8 | 1327 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1328 | { |
c033666a | 1329 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1330 | int ret; |
1331 | ||
0bc40be8 | 1332 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1333 | if (ret) |
1334 | return ret; | |
1335 | ||
1336 | /* We need to disable the AsyncFlip performance optimisations in order | |
1337 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1338 | * programmed to '1' on all products. | |
1339 | * | |
1340 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1341 | */ | |
1342 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1343 | ||
9b1136d5 OM |
1344 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1345 | ||
0bc40be8 | 1346 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1347 | } |
1348 | ||
0bc40be8 | 1349 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1350 | { |
1351 | int ret; | |
1352 | ||
0bc40be8 | 1353 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1354 | if (ret) |
1355 | return ret; | |
1356 | ||
0bc40be8 | 1357 | return init_workarounds_ring(engine); |
82ef822e DL |
1358 | } |
1359 | ||
7a01a0a2 MT |
1360 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1361 | { | |
1362 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
7e37f889 | 1363 | struct intel_ring *ring = req->ring; |
4a570db5 | 1364 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1365 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
1366 | int i, ret; | |
1367 | ||
987046ad | 1368 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1369 | if (ret) |
1370 | return ret; | |
1371 | ||
b5321f30 | 1372 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
7a01a0a2 MT |
1373 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
1374 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1375 | ||
b5321f30 CW |
1376 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i)); |
1377 | intel_ring_emit(ring, upper_32_bits(pd_daddr)); | |
1378 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i)); | |
1379 | intel_ring_emit(ring, lower_32_bits(pd_daddr)); | |
7a01a0a2 MT |
1380 | } |
1381 | ||
b5321f30 CW |
1382 | intel_ring_emit(ring, MI_NOOP); |
1383 | intel_ring_advance(ring); | |
7a01a0a2 MT |
1384 | |
1385 | return 0; | |
1386 | } | |
1387 | ||
be795fc1 | 1388 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba CW |
1389 | u64 offset, u32 len, |
1390 | unsigned int dispatch_flags) | |
15648585 | 1391 | { |
7e37f889 | 1392 | struct intel_ring *ring = req->ring; |
8e004efc | 1393 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1394 | int ret; |
1395 | ||
7a01a0a2 MT |
1396 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1397 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1398 | * but we can't. Force Restore would be a second option, but | |
1399 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1400 | * not idle). PML4 is allocated during ppgtt init so this is |
1401 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1402 | if (req->ctx->ppgtt && |
666796da | 1403 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1404 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1405 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1406 | ret = intel_logical_ring_emit_pdps(req); |
1407 | if (ret) | |
1408 | return ret; | |
1409 | } | |
7a01a0a2 | 1410 | |
666796da | 1411 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1412 | } |
1413 | ||
987046ad | 1414 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1415 | if (ret) |
1416 | return ret; | |
1417 | ||
1418 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 CW |
1419 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | |
1420 | (ppgtt<<8) | | |
1421 | (dispatch_flags & I915_DISPATCH_RS ? | |
1422 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
1423 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1424 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1425 | intel_ring_emit(ring, MI_NOOP); | |
1426 | intel_ring_advance(ring); | |
15648585 OM |
1427 | |
1428 | return 0; | |
1429 | } | |
1430 | ||
31bb59cc | 1431 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1432 | { |
c033666a | 1433 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1434 | I915_WRITE_IMR(engine, |
1435 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1436 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1437 | } |
1438 | ||
31bb59cc | 1439 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1440 | { |
c033666a | 1441 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1442 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1443 | } |
1444 | ||
7c9cf4e3 | 1445 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1446 | { |
7e37f889 CW |
1447 | struct intel_ring *ring = request->ring; |
1448 | u32 cmd; | |
4712274c OM |
1449 | int ret; |
1450 | ||
987046ad | 1451 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1452 | if (ret) |
1453 | return ret; | |
1454 | ||
1455 | cmd = MI_FLUSH_DW + 1; | |
1456 | ||
f0a1fb10 CW |
1457 | /* We always require a command barrier so that subsequent |
1458 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1459 | * wrt the contents of the write cache being flushed to memory | |
1460 | * (and thus being coherent from the CPU). | |
1461 | */ | |
1462 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1463 | ||
7c9cf4e3 | 1464 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1465 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1466 | if (request->engine->id == VCS) |
f0a1fb10 | 1467 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1468 | } |
1469 | ||
b5321f30 CW |
1470 | intel_ring_emit(ring, cmd); |
1471 | intel_ring_emit(ring, | |
1472 | I915_GEM_HWS_SCRATCH_ADDR | | |
1473 | MI_FLUSH_DW_USE_GTT); | |
1474 | intel_ring_emit(ring, 0); /* upper addr */ | |
1475 | intel_ring_emit(ring, 0); /* value */ | |
1476 | intel_ring_advance(ring); | |
4712274c OM |
1477 | |
1478 | return 0; | |
1479 | } | |
1480 | ||
7deb4d39 | 1481 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1482 | u32 mode) |
4712274c | 1483 | { |
7e37f889 | 1484 | struct intel_ring *ring = request->ring; |
b5321f30 | 1485 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1486 | u32 scratch_addr = |
1487 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1488 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1489 | u32 flags = 0; |
1490 | int ret; | |
0b2d0934 | 1491 | int len; |
4712274c OM |
1492 | |
1493 | flags |= PIPE_CONTROL_CS_STALL; | |
1494 | ||
7c9cf4e3 | 1495 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1496 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1497 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1498 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1499 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1500 | } |
1501 | ||
7c9cf4e3 | 1502 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1503 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1504 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1505 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1506 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1507 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1508 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1509 | flags |= PIPE_CONTROL_QW_WRITE; | |
1510 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1511 | |
1a5a9ce7 BW |
1512 | /* |
1513 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1514 | * pipe control. | |
1515 | */ | |
c033666a | 1516 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1517 | vf_flush_wa = true; |
0b2d0934 MK |
1518 | |
1519 | /* WaForGAMHang:kbl */ | |
1520 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1521 | dc_flush_wa = true; | |
1a5a9ce7 | 1522 | } |
9647ff36 | 1523 | |
0b2d0934 MK |
1524 | len = 6; |
1525 | ||
1526 | if (vf_flush_wa) | |
1527 | len += 6; | |
1528 | ||
1529 | if (dc_flush_wa) | |
1530 | len += 12; | |
1531 | ||
1532 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1533 | if (ret) |
1534 | return ret; | |
1535 | ||
9647ff36 | 1536 | if (vf_flush_wa) { |
b5321f30 CW |
1537 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1538 | intel_ring_emit(ring, 0); | |
1539 | intel_ring_emit(ring, 0); | |
1540 | intel_ring_emit(ring, 0); | |
1541 | intel_ring_emit(ring, 0); | |
1542 | intel_ring_emit(ring, 0); | |
9647ff36 ID |
1543 | } |
1544 | ||
0b2d0934 | 1545 | if (dc_flush_wa) { |
b5321f30 CW |
1546 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1547 | intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1548 | intel_ring_emit(ring, 0); | |
1549 | intel_ring_emit(ring, 0); | |
1550 | intel_ring_emit(ring, 0); | |
1551 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1552 | } |
1553 | ||
b5321f30 CW |
1554 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1555 | intel_ring_emit(ring, flags); | |
1556 | intel_ring_emit(ring, scratch_addr); | |
1557 | intel_ring_emit(ring, 0); | |
1558 | intel_ring_emit(ring, 0); | |
1559 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1560 | |
1561 | if (dc_flush_wa) { | |
b5321f30 CW |
1562 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1563 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); | |
1564 | intel_ring_emit(ring, 0); | |
1565 | intel_ring_emit(ring, 0); | |
1566 | intel_ring_emit(ring, 0); | |
1567 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1568 | } |
1569 | ||
b5321f30 | 1570 | intel_ring_advance(ring); |
4712274c OM |
1571 | |
1572 | return 0; | |
1573 | } | |
1574 | ||
c04e0f3b | 1575 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1576 | { |
319404df ID |
1577 | /* |
1578 | * On BXT A steppings there is a HW coherency issue whereby the | |
1579 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1580 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1581 | * clflushing the corresponding cacheline whenever the caller wants | |
1582 | * the coherency to be guaranteed. Note that this cacheline is known | |
1583 | * to be clean at this point, since we only write it in | |
1584 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1585 | * this clflush in practice becomes an invalidate operation. | |
1586 | */ | |
c04e0f3b | 1587 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1588 | } |
1589 | ||
7c17d377 CW |
1590 | /* |
1591 | * Reserve space for 2 NOOPs at the end of each request to be | |
1592 | * used as a workaround for not being allowed to do lite | |
1593 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1594 | */ | |
1595 | #define WA_TAIL_DWORDS 2 | |
1596 | ||
c4e76638 | 1597 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1598 | { |
7e37f889 | 1599 | struct intel_ring *ring = request->ring; |
4da46e1e OM |
1600 | int ret; |
1601 | ||
987046ad | 1602 | ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1603 | if (ret) |
1604 | return ret; | |
1605 | ||
7c17d377 CW |
1606 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1607 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1608 | |
b5321f30 CW |
1609 | intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1610 | intel_ring_emit(ring, | |
1611 | intel_hws_seqno_address(request->engine) | | |
1612 | MI_FLUSH_DW_USE_GTT); | |
1613 | intel_ring_emit(ring, 0); | |
1614 | intel_ring_emit(ring, request->fence.seqno); | |
1615 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1616 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1617 | return intel_logical_ring_advance(request); |
7c17d377 | 1618 | } |
4da46e1e | 1619 | |
7c17d377 CW |
1620 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1621 | { | |
7e37f889 | 1622 | struct intel_ring *ring = request->ring; |
7c17d377 | 1623 | int ret; |
53292cdb | 1624 | |
987046ad | 1625 | ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS); |
7c17d377 CW |
1626 | if (ret) |
1627 | return ret; | |
1628 | ||
ce81a65c MW |
1629 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1630 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1631 | ||
7c17d377 CW |
1632 | /* w/a for post sync ops following a GPGPU operation we |
1633 | * need a prior CS_STALL, which is emitted by the flush | |
1634 | * following the batch. | |
1635 | */ | |
b5321f30 CW |
1636 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1637 | intel_ring_emit(ring, | |
1638 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1639 | PIPE_CONTROL_CS_STALL | | |
1640 | PIPE_CONTROL_QW_WRITE)); | |
1641 | intel_ring_emit(ring, intel_hws_seqno_address(request->engine)); | |
1642 | intel_ring_emit(ring, 0); | |
1643 | intel_ring_emit(ring, i915_gem_request_get_seqno(request)); | |
ce81a65c | 1644 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1645 | intel_ring_emit(ring, 0); |
1646 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1647 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1648 | return intel_logical_ring_advance(request); |
4da46e1e OM |
1649 | } |
1650 | ||
8753181e | 1651 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1652 | { |
1653 | int ret; | |
1654 | ||
e2be4faf | 1655 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1656 | if (ret) |
1657 | return ret; | |
1658 | ||
3bbaba0c PA |
1659 | ret = intel_rcs_context_init_mocs(req); |
1660 | /* | |
1661 | * Failing to program the MOCS is non-fatal.The system will not | |
1662 | * run at peak performance. So generate an error and carry on. | |
1663 | */ | |
1664 | if (ret) | |
1665 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1666 | ||
e40f9ee6 | 1667 | return i915_gem_render_state_init(req); |
e7778be1 TD |
1668 | } |
1669 | ||
73e4d07f OM |
1670 | /** |
1671 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1672 | * @engine: Engine Command Streamer. |
73e4d07f | 1673 | */ |
0bc40be8 | 1674 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1675 | { |
6402c330 | 1676 | struct drm_i915_private *dev_priv; |
9832b9da | 1677 | |
117897f4 | 1678 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
1679 | return; |
1680 | ||
27af5eea TU |
1681 | /* |
1682 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1683 | * so this is just for documentation. | |
1684 | */ | |
1685 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1686 | tasklet_kill(&engine->irq_tasklet); | |
1687 | ||
c033666a | 1688 | dev_priv = engine->i915; |
6402c330 | 1689 | |
0bc40be8 | 1690 | if (engine->buffer) { |
0bc40be8 | 1691 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1692 | } |
48d82387 | 1693 | |
0bc40be8 TU |
1694 | if (engine->cleanup) |
1695 | engine->cleanup(engine); | |
48d82387 | 1696 | |
96a945aa | 1697 | intel_engine_cleanup_common(engine); |
688e6c72 | 1698 | |
57e88531 CW |
1699 | if (engine->status_page.vma) { |
1700 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1701 | engine->status_page.vma = NULL; | |
48d82387 | 1702 | } |
24f1d3cc | 1703 | intel_lr_context_unpin(dev_priv->kernel_context, engine); |
17ee950d | 1704 | |
0bc40be8 TU |
1705 | engine->idle_lite_restore_wa = 0; |
1706 | engine->disable_lite_restore_wa = false; | |
1707 | engine->ctx_desc_template = 0; | |
ca82580c | 1708 | |
0bc40be8 | 1709 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1710 | engine->i915 = NULL; |
454afebd OM |
1711 | } |
1712 | ||
ddd66c51 CW |
1713 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) |
1714 | { | |
1715 | struct intel_engine_cs *engine; | |
1716 | ||
1717 | for_each_engine(engine, dev_priv) | |
f4ea6bdd | 1718 | engine->submit_request = execlists_submit_request; |
ddd66c51 CW |
1719 | } |
1720 | ||
c9cacf93 | 1721 | static void |
e1382efb | 1722 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1723 | { |
1724 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1725 | engine->init_hw = gen8_init_common_ring; |
0bc40be8 | 1726 | engine->emit_flush = gen8_emit_flush; |
ddd66c51 | 1727 | engine->emit_request = gen8_emit_request; |
f4ea6bdd | 1728 | engine->submit_request = execlists_submit_request; |
ddd66c51 | 1729 | |
31bb59cc CW |
1730 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1731 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1732 | engine->emit_bb_start = gen8_emit_bb_start; |
1b7744e7 | 1733 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) |
c04e0f3b | 1734 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
c9cacf93 TU |
1735 | } |
1736 | ||
d9f3af96 | 1737 | static inline void |
c2c7f240 | 1738 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1739 | { |
c2c7f240 | 1740 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1741 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1742 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1743 | } |
1744 | ||
7d774cac | 1745 | static int |
bf3783e5 | 1746 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1747 | { |
57e88531 | 1748 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1749 | void *hws; |
04794adb TU |
1750 | |
1751 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1752 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1753 | if (IS_ERR(hws)) |
1754 | return PTR_ERR(hws); | |
57e88531 CW |
1755 | |
1756 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1757 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1758 | engine->status_page.vma = vma; |
7d774cac TU |
1759 | |
1760 | return 0; | |
04794adb TU |
1761 | } |
1762 | ||
bb45438f TU |
1763 | static void |
1764 | logical_ring_setup(struct intel_engine_cs *engine) | |
1765 | { | |
1766 | struct drm_i915_private *dev_priv = engine->i915; | |
1767 | enum forcewake_domains fw_domains; | |
1768 | ||
019bf277 TU |
1769 | intel_engine_setup_common(engine); |
1770 | ||
bb45438f TU |
1771 | /* Intentionally left blank. */ |
1772 | engine->buffer = NULL; | |
1773 | ||
1774 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1775 | RING_ELSP(engine), | |
1776 | FW_REG_WRITE); | |
1777 | ||
1778 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1779 | RING_CONTEXT_STATUS_PTR(engine), | |
1780 | FW_REG_READ | FW_REG_WRITE); | |
1781 | ||
1782 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1783 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1784 | FW_REG_READ); | |
1785 | ||
1786 | engine->fw_domains = fw_domains; | |
1787 | ||
bb45438f TU |
1788 | tasklet_init(&engine->irq_tasklet, |
1789 | intel_lrc_irq_handler, (unsigned long)engine); | |
1790 | ||
1791 | logical_ring_init_platform_invariants(engine); | |
1792 | logical_ring_default_vfuncs(engine); | |
1793 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1794 | } |
1795 | ||
a19d6ff2 TU |
1796 | static int |
1797 | logical_ring_init(struct intel_engine_cs *engine) | |
1798 | { | |
1799 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1800 | int ret; | |
1801 | ||
019bf277 | 1802 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1803 | if (ret) |
1804 | goto error; | |
1805 | ||
1806 | ret = execlists_context_deferred_alloc(dctx, engine); | |
1807 | if (ret) | |
1808 | goto error; | |
1809 | ||
1810 | /* As this is the default context, always pin it */ | |
1811 | ret = intel_lr_context_pin(dctx, engine); | |
1812 | if (ret) { | |
1813 | DRM_ERROR("Failed to pin context for %s: %d\n", | |
1814 | engine->name, ret); | |
1815 | goto error; | |
1816 | } | |
1817 | ||
1818 | /* And setup the hardware status page. */ | |
1819 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1820 | if (ret) { | |
1821 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1822 | goto error; | |
1823 | } | |
1824 | ||
1825 | return 0; | |
1826 | ||
1827 | error: | |
1828 | intel_logical_ring_cleanup(engine); | |
1829 | return ret; | |
1830 | } | |
1831 | ||
88d2ba2e | 1832 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1833 | { |
1834 | struct drm_i915_private *dev_priv = engine->i915; | |
1835 | int ret; | |
1836 | ||
bb45438f TU |
1837 | logical_ring_setup(engine); |
1838 | ||
a19d6ff2 TU |
1839 | if (HAS_L3_DPF(dev_priv)) |
1840 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1841 | ||
1842 | /* Override some for render ring. */ | |
1843 | if (INTEL_GEN(dev_priv) >= 9) | |
1844 | engine->init_hw = gen9_init_render_ring; | |
1845 | else | |
1846 | engine->init_hw = gen8_init_render_ring; | |
1847 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 TU |
1848 | engine->emit_flush = gen8_emit_flush_render; |
1849 | engine->emit_request = gen8_emit_request_render; | |
1850 | ||
56c0f1a7 | 1851 | ret = intel_engine_create_scratch(engine, 4096); |
a19d6ff2 TU |
1852 | if (ret) |
1853 | return ret; | |
1854 | ||
1855 | ret = intel_init_workaround_bb(engine); | |
1856 | if (ret) { | |
1857 | /* | |
1858 | * We continue even if we fail to initialize WA batch | |
1859 | * because we only expect rare glitches but nothing | |
1860 | * critical to prevent us from using GPU | |
1861 | */ | |
1862 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1863 | ret); | |
1864 | } | |
1865 | ||
1866 | ret = logical_ring_init(engine); | |
1867 | if (ret) { | |
1868 | lrc_destroy_wa_ctx_obj(engine); | |
1869 | } | |
1870 | ||
1871 | return ret; | |
1872 | } | |
1873 | ||
88d2ba2e | 1874 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1875 | { |
1876 | logical_ring_setup(engine); | |
1877 | ||
1878 | return logical_ring_init(engine); | |
454afebd OM |
1879 | } |
1880 | ||
0cea6502 | 1881 | static u32 |
c033666a | 1882 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1883 | { |
1884 | u32 rpcs = 0; | |
1885 | ||
1886 | /* | |
1887 | * No explicit RPCS request is needed to ensure full | |
1888 | * slice/subslice/EU enablement prior to Gen9. | |
1889 | */ | |
c033666a | 1890 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1891 | return 0; |
1892 | ||
1893 | /* | |
1894 | * Starting in Gen9, render power gating can leave | |
1895 | * slice/subslice/EU in a partially enabled state. We | |
1896 | * must make an explicit request through RPCS for full | |
1897 | * enablement. | |
1898 | */ | |
c033666a | 1899 | if (INTEL_INFO(dev_priv)->has_slice_pg) { |
0cea6502 | 1900 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
c033666a | 1901 | rpcs |= INTEL_INFO(dev_priv)->slice_total << |
0cea6502 JM |
1902 | GEN8_RPCS_S_CNT_SHIFT; |
1903 | rpcs |= GEN8_RPCS_ENABLE; | |
1904 | } | |
1905 | ||
c033666a | 1906 | if (INTEL_INFO(dev_priv)->has_subslice_pg) { |
0cea6502 | 1907 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
c033666a | 1908 | rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice << |
0cea6502 JM |
1909 | GEN8_RPCS_SS_CNT_SHIFT; |
1910 | rpcs |= GEN8_RPCS_ENABLE; | |
1911 | } | |
1912 | ||
c033666a CW |
1913 | if (INTEL_INFO(dev_priv)->has_eu_pg) { |
1914 | rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice << | |
0cea6502 | 1915 | GEN8_RPCS_EU_MIN_SHIFT; |
c033666a | 1916 | rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice << |
0cea6502 JM |
1917 | GEN8_RPCS_EU_MAX_SHIFT; |
1918 | rpcs |= GEN8_RPCS_ENABLE; | |
1919 | } | |
1920 | ||
1921 | return rpcs; | |
1922 | } | |
1923 | ||
0bc40be8 | 1924 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1925 | { |
1926 | u32 indirect_ctx_offset; | |
1927 | ||
c033666a | 1928 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1929 | default: |
c033666a | 1930 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1931 | /* fall through */ |
1932 | case 9: | |
1933 | indirect_ctx_offset = | |
1934 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1935 | break; | |
1936 | case 8: | |
1937 | indirect_ctx_offset = | |
1938 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1939 | break; | |
1940 | } | |
1941 | ||
1942 | return indirect_ctx_offset; | |
1943 | } | |
1944 | ||
8670d6f9 | 1945 | static int |
e2efd130 | 1946 | populate_lr_context(struct i915_gem_context *ctx, |
7d774cac | 1947 | struct drm_i915_gem_object *ctx_obj, |
0bc40be8 | 1948 | struct intel_engine_cs *engine, |
7e37f889 | 1949 | struct intel_ring *ring) |
8670d6f9 | 1950 | { |
c033666a | 1951 | struct drm_i915_private *dev_priv = ctx->i915; |
ae6c4806 | 1952 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
7d774cac TU |
1953 | void *vaddr; |
1954 | u32 *reg_state; | |
8670d6f9 OM |
1955 | int ret; |
1956 | ||
2d965536 TD |
1957 | if (!ppgtt) |
1958 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1959 | ||
8670d6f9 OM |
1960 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1961 | if (ret) { | |
1962 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1963 | return ret; | |
1964 | } | |
1965 | ||
d31d7cb1 | 1966 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); |
7d774cac TU |
1967 | if (IS_ERR(vaddr)) { |
1968 | ret = PTR_ERR(vaddr); | |
1969 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
8670d6f9 OM |
1970 | return ret; |
1971 | } | |
7d774cac | 1972 | ctx_obj->dirty = true; |
8670d6f9 OM |
1973 | |
1974 | /* The second page of the context object contains some fields which must | |
1975 | * be set up prior to the first execution. */ | |
7d774cac | 1976 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
8670d6f9 OM |
1977 | |
1978 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1979 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1980 | * only for the first context restore: on a subsequent save, the GPU will | |
1981 | * recreate this batchbuffer with new values (including all the missing | |
1982 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 1983 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
1984 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
1985 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
1986 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
1987 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1988 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 1989 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
99cf8ea1 | 1990 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
1991 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
1992 | 0); | |
1993 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
1994 | 0); | |
7ba717cf TD |
1995 | /* Ring buffer start address is not known until the buffer is pinned. |
1996 | * It is written to the context image in execlists_update_context() | |
1997 | */ | |
0bc40be8 TU |
1998 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
1999 | RING_START(engine->mmio_base), 0); | |
2000 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2001 | RING_CTL(engine->mmio_base), | |
7e37f889 | 2002 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
2003 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2004 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2005 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2006 | RING_BBADDR(engine->mmio_base), 0); | |
2007 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2008 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2009 | RING_BB_PPGTT); |
0bc40be8 TU |
2010 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2011 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2012 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2013 | RING_SBBADDR(engine->mmio_base), 0); | |
2014 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2015 | RING_SBBSTATE(engine->mmio_base), 0); | |
2016 | if (engine->id == RCS) { | |
2017 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2018 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2019 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2020 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2021 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2022 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
48bb74e4 | 2023 | if (engine->wa_ctx.vma) { |
0bc40be8 | 2024 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 2025 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d AS |
2026 | |
2027 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2028 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2029 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2030 | ||
2031 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2032 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2033 | |
2034 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2035 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2036 | 0x01; | |
2037 | } | |
8670d6f9 | 2038 | } |
0d925ea0 | 2039 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2040 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2041 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2042 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2043 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2044 | 0); | |
2045 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2046 | 0); | |
2047 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2048 | 0); | |
2049 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2050 | 0); | |
2051 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2052 | 0); | |
2053 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2054 | 0); | |
2055 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2056 | 0); | |
2057 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2058 | 0); | |
d7b2633d | 2059 | |
2dba3239 MT |
2060 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2061 | /* 64b PPGTT (48bit canonical) | |
2062 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2063 | * other PDP Descriptors are ignored. | |
2064 | */ | |
2065 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2066 | } else { | |
2067 | /* 32b PPGTT | |
2068 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2069 | * With dynamic page allocation, PDPs may not be allocated at | |
2070 | * this point. Point the unallocated PDPs to the scratch page | |
2071 | */ | |
c6a2ac71 | 2072 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2073 | } |
2074 | ||
0bc40be8 | 2075 | if (engine->id == RCS) { |
8670d6f9 | 2076 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2077 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2078 | make_rpcs(dev_priv)); |
8670d6f9 OM |
2079 | } |
2080 | ||
7d774cac | 2081 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2082 | |
2083 | return 0; | |
2084 | } | |
2085 | ||
c5d46ee2 DG |
2086 | /** |
2087 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2088 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2089 | * |
2090 | * Each engine may require a different amount of space for a context image, | |
2091 | * so when allocating (or copying) an image, this function can be used to | |
2092 | * find the right size for the specific engine. | |
2093 | * | |
2094 | * Return: size (in bytes) of an engine-specific context image | |
2095 | * | |
2096 | * Note: this size includes the HWSP, which is part of the context image | |
2097 | * in LRC mode, but does not include the "shared data page" used with | |
2098 | * GuC submission. The caller should account for this if using the GuC. | |
2099 | */ | |
0bc40be8 | 2100 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2101 | { |
2102 | int ret = 0; | |
2103 | ||
c033666a | 2104 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2105 | |
0bc40be8 | 2106 | switch (engine->id) { |
8c857917 | 2107 | case RCS: |
c033666a | 2108 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2109 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2110 | else | |
2111 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2112 | break; |
2113 | case VCS: | |
2114 | case BCS: | |
2115 | case VECS: | |
2116 | case VCS2: | |
2117 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2118 | break; | |
2119 | } | |
2120 | ||
2121 | return ret; | |
ede7d42b OM |
2122 | } |
2123 | ||
e2efd130 | 2124 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2125 | struct intel_engine_cs *engine) |
ede7d42b | 2126 | { |
8c857917 | 2127 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2128 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2129 | struct i915_vma *vma; |
8c857917 | 2130 | uint32_t context_size; |
7e37f889 | 2131 | struct intel_ring *ring; |
8c857917 OM |
2132 | int ret; |
2133 | ||
9021ad03 | 2134 | WARN_ON(ce->state); |
ede7d42b | 2135 | |
0bc40be8 | 2136 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2137 | |
d1675198 AD |
2138 | /* One extra page as the sharing data between driver and GuC */ |
2139 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2140 | ||
91c8a326 | 2141 | ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size); |
fe3db79b | 2142 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2143 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2144 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2145 | } |
2146 | ||
bf3783e5 CW |
2147 | vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL); |
2148 | if (IS_ERR(vma)) { | |
2149 | ret = PTR_ERR(vma); | |
2150 | goto error_deref_obj; | |
2151 | } | |
2152 | ||
7e37f889 | 2153 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2154 | if (IS_ERR(ring)) { |
2155 | ret = PTR_ERR(ring); | |
e84fe803 | 2156 | goto error_deref_obj; |
8670d6f9 OM |
2157 | } |
2158 | ||
dca33ecc | 2159 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2160 | if (ret) { |
2161 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2162 | goto error_ring_free; |
84c2377f OM |
2163 | } |
2164 | ||
dca33ecc | 2165 | ce->ring = ring; |
bf3783e5 | 2166 | ce->state = vma; |
9021ad03 | 2167 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2168 | |
2169 | return 0; | |
8670d6f9 | 2170 | |
dca33ecc | 2171 | error_ring_free: |
7e37f889 | 2172 | intel_ring_free(ring); |
e84fe803 | 2173 | error_deref_obj: |
f8c417cd | 2174 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2175 | return ret; |
ede7d42b | 2176 | } |
3e5b6f05 | 2177 | |
7d774cac | 2178 | void intel_lr_context_reset(struct drm_i915_private *dev_priv, |
e2efd130 | 2179 | struct i915_gem_context *ctx) |
3e5b6f05 | 2180 | { |
e2f80391 | 2181 | struct intel_engine_cs *engine; |
3e5b6f05 | 2182 | |
b4ac5afc | 2183 | for_each_engine(engine, dev_priv) { |
9021ad03 | 2184 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac | 2185 | void *vaddr; |
3e5b6f05 | 2186 | uint32_t *reg_state; |
3e5b6f05 | 2187 | |
bf3783e5 | 2188 | if (!ce->state) |
3e5b6f05 TD |
2189 | continue; |
2190 | ||
bf3783e5 | 2191 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac | 2192 | if (WARN_ON(IS_ERR(vaddr))) |
3e5b6f05 | 2193 | continue; |
7d774cac TU |
2194 | |
2195 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; | |
3e5b6f05 TD |
2196 | |
2197 | reg_state[CTX_RING_HEAD+1] = 0; | |
2198 | reg_state[CTX_RING_TAIL+1] = 0; | |
2199 | ||
bf3783e5 CW |
2200 | ce->state->obj->dirty = true; |
2201 | i915_gem_object_unpin_map(ce->state->obj); | |
3e5b6f05 | 2202 | |
dca33ecc CW |
2203 | ce->ring->head = 0; |
2204 | ce->ring->tail = 0; | |
3e5b6f05 TD |
2205 | } |
2206 | } |