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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
158 | |
159 | #define CTX_LRI_HEADER_0 0x01 | |
160 | #define CTX_CONTEXT_CONTROL 0x02 | |
161 | #define CTX_RING_HEAD 0x04 | |
162 | #define CTX_RING_TAIL 0x06 | |
163 | #define CTX_RING_BUFFER_START 0x08 | |
164 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
165 | #define CTX_BB_HEAD_U 0x0c | |
166 | #define CTX_BB_HEAD_L 0x0e | |
167 | #define CTX_BB_STATE 0x10 | |
168 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
169 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
170 | #define CTX_SECOND_BB_STATE 0x16 | |
171 | #define CTX_BB_PER_CTX_PTR 0x18 | |
172 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
173 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
174 | #define CTX_LRI_HEADER_1 0x21 | |
175 | #define CTX_CTX_TIMESTAMP 0x22 | |
176 | #define CTX_PDP3_UDW 0x24 | |
177 | #define CTX_PDP3_LDW 0x26 | |
178 | #define CTX_PDP2_UDW 0x28 | |
179 | #define CTX_PDP2_LDW 0x2a | |
180 | #define CTX_PDP1_UDW 0x2c | |
181 | #define CTX_PDP1_LDW 0x2e | |
182 | #define CTX_PDP0_UDW 0x30 | |
183 | #define CTX_PDP0_LDW 0x32 | |
184 | #define CTX_LRI_HEADER_2 0x41 | |
185 | #define CTX_R_PWR_CLK_STATE 0x42 | |
186 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
187 | ||
84b790f8 BW |
188 | #define GEN8_CTX_VALID (1<<0) |
189 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
190 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
191 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
192 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 193 | |
0d925ea0 | 194 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 195 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
196 | (reg_state)[(pos)+1] = (val); \ |
197 | } while (0) | |
198 | ||
199 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 200 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
201 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
202 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 203 | } while (0) |
e5815a2e | 204 | |
9244a817 | 205 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
206 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
207 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 208 | } while (0) |
2dba3239 | 209 | |
84b790f8 BW |
210 | enum { |
211 | ADVANCED_CONTEXT = 0, | |
2dba3239 | 212 | LEGACY_32B_CONTEXT, |
84b790f8 BW |
213 | ADVANCED_AD_CONTEXT, |
214 | LEGACY_64B_CONTEXT | |
215 | }; | |
2dba3239 MT |
216 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
217 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ | |
218 | LEGACY_64B_CONTEXT :\ | |
219 | LEGACY_32B_CONTEXT) | |
84b790f8 BW |
220 | enum { |
221 | FAULT_AND_HANG = 0, | |
222 | FAULT_AND_HALT, /* Debug only */ | |
223 | FAULT_AND_STREAM, | |
224 | FAULT_AND_CONTINUE /* Unsupported */ | |
225 | }; | |
226 | #define GEN8_CTX_ID_SHIFT 32 | |
71562919 MT |
227 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
228 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 229 | |
e5292823 TU |
230 | static int intel_lr_context_pin(struct intel_context *ctx, |
231 | struct intel_engine_cs *engine); | |
0bc40be8 TU |
232 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, |
233 | struct drm_i915_gem_object *default_ctx_obj); | |
e84fe803 | 234 | |
7ba717cf | 235 | |
73e4d07f OM |
236 | /** |
237 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
238 | * @dev: DRM device. | |
239 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
240 | * | |
241 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 242 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
243 | * |
244 | * Return: 1 if Execlists is supported and has to be enabled. | |
245 | */ | |
127f1003 OM |
246 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
247 | { | |
bd84b1e9 DV |
248 | WARN_ON(i915.enable_ppgtt == -1); |
249 | ||
a0bd6c31 ZL |
250 | /* On platforms with execlist available, vGPU will only |
251 | * support execlist mode, no ring buffer mode. | |
252 | */ | |
253 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) | |
254 | return 1; | |
255 | ||
70ee45e1 DL |
256 | if (INTEL_INFO(dev)->gen >= 9) |
257 | return 1; | |
258 | ||
127f1003 OM |
259 | if (enable_execlists == 0) |
260 | return 0; | |
261 | ||
14bf993e OM |
262 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
263 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
264 | return 1; |
265 | ||
266 | return 0; | |
267 | } | |
ede7d42b | 268 | |
ca82580c | 269 | static void |
0bc40be8 | 270 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 271 | { |
0bc40be8 | 272 | struct drm_device *dev = engine->dev; |
ca82580c | 273 | |
c6a2ac71 | 274 | if (IS_GEN8(dev) || IS_GEN9(dev)) |
0bc40be8 | 275 | engine->idle_lite_restore_wa = ~0; |
c6a2ac71 | 276 | |
0bc40be8 | 277 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
ca82580c | 278 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) && |
0bc40be8 | 279 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 280 | |
0bc40be8 TU |
281 | engine->ctx_desc_template = GEN8_CTX_VALID; |
282 | engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) << | |
ca82580c TU |
283 | GEN8_CTX_ADDRESSING_MODE_SHIFT; |
284 | if (IS_GEN8(dev)) | |
0bc40be8 TU |
285 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
286 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
287 | |
288 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
289 | * signalling between Command Streamers */ | |
290 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
291 | ||
292 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
293 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
294 | if (engine->disable_lite_restore_wa) |
295 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
296 | } |
297 | ||
73e4d07f | 298 | /** |
ca82580c TU |
299 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
300 | * descriptor for a pinned context | |
73e4d07f | 301 | * |
ca82580c TU |
302 | * @ctx: Context to work on |
303 | * @ring: Engine the descriptor will be used with | |
73e4d07f | 304 | * |
ca82580c TU |
305 | * The context descriptor encodes various attributes of a context, |
306 | * including its GTT address and some flags. Because it's fairly | |
307 | * expensive to calculate, we'll just do it once and cache the result, | |
308 | * which remains valid until the context is unpinned. | |
309 | * | |
310 | * This is what a descriptor looks like, from LSB to MSB: | |
311 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
312 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
313 | * bits 32-51: ctx ID, a globally unique tag (the LRCA again!) | |
314 | * bits 52-63: reserved, may encode the engine ID (for GuC) | |
73e4d07f | 315 | */ |
ca82580c TU |
316 | static void |
317 | intel_lr_context_descriptor_update(struct intel_context *ctx, | |
0bc40be8 | 318 | struct intel_engine_cs *engine) |
84b790f8 | 319 | { |
ca82580c | 320 | uint64_t lrca, desc; |
84b790f8 | 321 | |
0bc40be8 | 322 | lrca = ctx->engine[engine->id].lrc_vma->node.start + |
ca82580c | 323 | LRC_PPHWSP_PN * PAGE_SIZE; |
84b790f8 | 324 | |
0bc40be8 | 325 | desc = engine->ctx_desc_template; /* bits 0-11 */ |
ca82580c TU |
326 | desc |= lrca; /* bits 12-31 */ |
327 | desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */ | |
5af05fef | 328 | |
0bc40be8 | 329 | ctx->engine[engine->id].lrc_desc = desc; |
5af05fef MT |
330 | } |
331 | ||
919f1f55 | 332 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
0bc40be8 | 333 | struct intel_engine_cs *engine) |
84b790f8 | 334 | { |
0bc40be8 | 335 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 336 | } |
203a571b | 337 | |
ca82580c TU |
338 | /** |
339 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
340 | * @ctx: Context to get the ID for | |
341 | * @ring: Engine to get the ID for | |
342 | * | |
343 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
344 | * here: the old context ID we pass to userspace as a handler so that | |
345 | * they can refer to a context, and the new context ID we pass to the | |
346 | * ELSP so that the GPU can inform us of the context status via | |
347 | * interrupts. | |
348 | * | |
349 | * The context ID is a portion of the context descriptor, so we can | |
350 | * just extract the required part from the cached descriptor. | |
351 | * | |
352 | * Return: 20-bits globally unique context ID. | |
353 | */ | |
354 | u32 intel_execlists_ctx_id(struct intel_context *ctx, | |
0bc40be8 | 355 | struct intel_engine_cs *engine) |
ca82580c | 356 | { |
0bc40be8 | 357 | return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT; |
84b790f8 BW |
358 | } |
359 | ||
cc3c4253 MK |
360 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
361 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 362 | { |
cc3c4253 | 363 | |
4a570db5 | 364 | struct intel_engine_cs *engine = rq0->engine; |
e2f80391 | 365 | struct drm_device *dev = engine->dev; |
6e7cc470 | 366 | struct drm_i915_private *dev_priv = dev->dev_private; |
1cff8cc3 | 367 | uint64_t desc[2]; |
84b790f8 | 368 | |
1cff8cc3 | 369 | if (rq1) { |
4a570db5 | 370 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
1cff8cc3 MK |
371 | rq1->elsp_submitted++; |
372 | } else { | |
373 | desc[1] = 0; | |
374 | } | |
84b790f8 | 375 | |
4a570db5 | 376 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
1cff8cc3 | 377 | rq0->elsp_submitted++; |
84b790f8 | 378 | |
1cff8cc3 | 379 | /* You must always write both descriptors in the order below. */ |
e2f80391 TU |
380 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
381 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); | |
6daccb0b | 382 | |
e2f80391 | 383 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
84b790f8 | 384 | /* The context is automatically loaded after the following */ |
e2f80391 | 385 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
84b790f8 | 386 | |
1cff8cc3 | 387 | /* ELSP is a wo register, use another nearby reg for posting */ |
e2f80391 | 388 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
84b790f8 BW |
389 | } |
390 | ||
c6a2ac71 TU |
391 | static void |
392 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
393 | { | |
394 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
395 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
396 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
397 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
398 | } | |
399 | ||
400 | static void execlists_update_context(struct drm_i915_gem_request *rq) | |
ae1250b9 | 401 | { |
4a570db5 | 402 | struct intel_engine_cs *engine = rq->engine; |
05d9824b | 403 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
e2f80391 | 404 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
ae1250b9 | 405 | |
05d9824b | 406 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 407 | |
c6a2ac71 TU |
408 | /* True 32b PPGTT with dynamic page allocation: update PDP |
409 | * registers and point the unallocated PDPs to scratch page. | |
410 | * PML4 is allocated during ppgtt init, so this is not needed | |
411 | * in 48-bit mode. | |
412 | */ | |
413 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
414 | execlists_update_context_pdps(ppgtt, reg_state); | |
ae1250b9 OM |
415 | } |
416 | ||
d8cb8875 MK |
417 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
418 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 419 | { |
26720ab9 TU |
420 | struct drm_i915_private *dev_priv = rq0->i915; |
421 | ||
05d9824b | 422 | execlists_update_context(rq0); |
d8cb8875 | 423 | |
cc3c4253 | 424 | if (rq1) |
05d9824b | 425 | execlists_update_context(rq1); |
84b790f8 | 426 | |
27af5eea | 427 | spin_lock_irq(&dev_priv->uncore.lock); |
26720ab9 TU |
428 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); |
429 | ||
cc3c4253 | 430 | execlists_elsp_write(rq0, rq1); |
26720ab9 TU |
431 | |
432 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
27af5eea | 433 | spin_unlock_irq(&dev_priv->uncore.lock); |
84b790f8 BW |
434 | } |
435 | ||
26720ab9 | 436 | static void execlists_context_unqueue(struct intel_engine_cs *engine) |
acdd884a | 437 | { |
6d3d8274 | 438 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
c6a2ac71 | 439 | struct drm_i915_gem_request *cursor, *tmp; |
e981e7b1 | 440 | |
0bc40be8 | 441 | assert_spin_locked(&engine->execlist_lock); |
acdd884a | 442 | |
779949f4 PA |
443 | /* |
444 | * If irqs are not active generate a warning as batches that finish | |
445 | * without the irqs may get lost and a GPU Hang may occur. | |
446 | */ | |
0bc40be8 | 447 | WARN_ON(!intel_irqs_enabled(engine->dev->dev_private)); |
779949f4 | 448 | |
acdd884a | 449 | /* Try to read in pairs */ |
0bc40be8 | 450 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
acdd884a MT |
451 | execlist_link) { |
452 | if (!req0) { | |
453 | req0 = cursor; | |
6d3d8274 | 454 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
455 | /* Same ctx: ignore first request, as second request |
456 | * will update tail past first request's workload */ | |
e1fee72c | 457 | cursor->elsp_submitted = req0->elsp_submitted; |
7eb08a25 | 458 | list_move_tail(&req0->execlist_link, |
0bc40be8 | 459 | &engine->execlist_retired_req_list); |
acdd884a MT |
460 | req0 = cursor; |
461 | } else { | |
462 | req1 = cursor; | |
c6a2ac71 | 463 | WARN_ON(req1->elsp_submitted); |
acdd884a MT |
464 | break; |
465 | } | |
466 | } | |
467 | ||
c6a2ac71 TU |
468 | if (unlikely(!req0)) |
469 | return; | |
470 | ||
0bc40be8 | 471 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
53292cdb | 472 | /* |
c6a2ac71 TU |
473 | * WaIdleLiteRestore: make sure we never cause a lite restore |
474 | * with HEAD==TAIL. | |
475 | * | |
476 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we | |
477 | * resubmit the request. See gen8_emit_request() for where we | |
478 | * prepare the padding after the end of the request. | |
53292cdb | 479 | */ |
c6a2ac71 | 480 | struct intel_ringbuffer *ringbuf; |
53292cdb | 481 | |
0bc40be8 | 482 | ringbuf = req0->ctx->engine[engine->id].ringbuf; |
c6a2ac71 TU |
483 | req0->tail += 8; |
484 | req0->tail &= ringbuf->size - 1; | |
53292cdb MT |
485 | } |
486 | ||
d8cb8875 | 487 | execlists_submit_requests(req0, req1); |
acdd884a MT |
488 | } |
489 | ||
c6a2ac71 | 490 | static unsigned int |
0bc40be8 | 491 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id) |
e981e7b1 | 492 | { |
6d3d8274 | 493 | struct drm_i915_gem_request *head_req; |
e981e7b1 | 494 | |
0bc40be8 | 495 | assert_spin_locked(&engine->execlist_lock); |
e981e7b1 | 496 | |
0bc40be8 | 497 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
6d3d8274 | 498 | struct drm_i915_gem_request, |
e981e7b1 TD |
499 | execlist_link); |
500 | ||
c6a2ac71 TU |
501 | if (!head_req) |
502 | return 0; | |
e1fee72c | 503 | |
0bc40be8 | 504 | if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id)) |
c6a2ac71 TU |
505 | return 0; |
506 | ||
507 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); | |
508 | ||
509 | if (--head_req->elsp_submitted > 0) | |
510 | return 0; | |
511 | ||
512 | list_move_tail(&head_req->execlist_link, | |
0bc40be8 | 513 | &engine->execlist_retired_req_list); |
e981e7b1 | 514 | |
c6a2ac71 | 515 | return 1; |
e981e7b1 TD |
516 | } |
517 | ||
c6a2ac71 | 518 | static u32 |
0bc40be8 | 519 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
c6a2ac71 | 520 | u32 *context_id) |
91a41032 | 521 | { |
0bc40be8 | 522 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
c6a2ac71 | 523 | u32 status; |
91a41032 | 524 | |
c6a2ac71 TU |
525 | read_pointer %= GEN8_CSB_ENTRIES; |
526 | ||
0bc40be8 | 527 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
c6a2ac71 TU |
528 | |
529 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) | |
530 | return 0; | |
91a41032 | 531 | |
0bc40be8 | 532 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
c6a2ac71 TU |
533 | read_pointer)); |
534 | ||
535 | return status; | |
91a41032 BW |
536 | } |
537 | ||
73e4d07f | 538 | /** |
3f7531c3 | 539 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
27af5eea | 540 | * @engine: Engine Command Streamer to handle. |
73e4d07f OM |
541 | * |
542 | * Check the unread Context Status Buffers and manage the submission of new | |
543 | * contexts to the ELSP accordingly. | |
544 | */ | |
27af5eea | 545 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 546 | { |
27af5eea | 547 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
0bc40be8 | 548 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
e981e7b1 | 549 | u32 status_pointer; |
c6a2ac71 | 550 | unsigned int read_pointer, write_pointer; |
26720ab9 TU |
551 | u32 csb[GEN8_CSB_ENTRIES][2]; |
552 | unsigned int csb_read = 0, i; | |
c6a2ac71 TU |
553 | unsigned int submit_contexts = 0; |
554 | ||
27af5eea | 555 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
c6a2ac71 | 556 | |
0bc40be8 | 557 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
e981e7b1 | 558 | |
0bc40be8 | 559 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 560 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
e981e7b1 | 561 | if (read_pointer > write_pointer) |
dfc53c5e | 562 | write_pointer += GEN8_CSB_ENTRIES; |
e981e7b1 | 563 | |
e981e7b1 | 564 | while (read_pointer < write_pointer) { |
26720ab9 TU |
565 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
566 | break; | |
567 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, | |
568 | &csb[csb_read][1]); | |
569 | csb_read++; | |
570 | } | |
91a41032 | 571 | |
26720ab9 TU |
572 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
573 | ||
574 | /* Update the read pointer to the old write pointer. Manual ringbuffer | |
575 | * management ftw </sarcasm> */ | |
576 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), | |
577 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, | |
578 | engine->next_context_status_buffer << 8)); | |
579 | ||
27af5eea | 580 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
26720ab9 TU |
581 | |
582 | spin_lock(&engine->execlist_lock); | |
583 | ||
584 | for (i = 0; i < csb_read; i++) { | |
585 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { | |
586 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { | |
587 | if (execlists_check_remove_request(engine, csb[i][1])) | |
e1fee72c OM |
588 | WARN(1, "Lite Restored request removed from queue\n"); |
589 | } else | |
590 | WARN(1, "Preemption without Lite Restore\n"); | |
591 | } | |
592 | ||
26720ab9 | 593 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
c6a2ac71 TU |
594 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
595 | submit_contexts += | |
26720ab9 | 596 | execlists_check_remove_request(engine, csb[i][1]); |
e981e7b1 TD |
597 | } |
598 | ||
c6a2ac71 | 599 | if (submit_contexts) { |
0bc40be8 | 600 | if (!engine->disable_lite_restore_wa || |
26720ab9 TU |
601 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
602 | execlists_context_unqueue(engine); | |
5af05fef | 603 | } |
e981e7b1 | 604 | |
0bc40be8 | 605 | spin_unlock(&engine->execlist_lock); |
c6a2ac71 TU |
606 | |
607 | if (unlikely(submit_contexts > 2)) | |
608 | DRM_ERROR("More than two context complete events?\n"); | |
e981e7b1 TD |
609 | } |
610 | ||
c6a2ac71 | 611 | static void execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 612 | { |
4a570db5 | 613 | struct intel_engine_cs *engine = request->engine; |
6d3d8274 | 614 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 615 | int num_elements = 0; |
acdd884a | 616 | |
ed54c1a1 | 617 | if (request->ctx != request->i915->kernel_context) |
e2f80391 | 618 | intel_lr_context_pin(request->ctx, engine); |
af3302b9 | 619 | |
9bb1af44 JH |
620 | i915_gem_request_reference(request); |
621 | ||
27af5eea | 622 | spin_lock_bh(&engine->execlist_lock); |
acdd884a | 623 | |
e2f80391 | 624 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
f1ad5a1f OM |
625 | if (++num_elements > 2) |
626 | break; | |
627 | ||
628 | if (num_elements > 2) { | |
6d3d8274 | 629 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f | 630 | |
e2f80391 | 631 | tail_req = list_last_entry(&engine->execlist_queue, |
6d3d8274 | 632 | struct drm_i915_gem_request, |
f1ad5a1f OM |
633 | execlist_link); |
634 | ||
ae70797d | 635 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 636 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 637 | "More than 2 already-submitted reqs queued\n"); |
7eb08a25 | 638 | list_move_tail(&tail_req->execlist_link, |
e2f80391 | 639 | &engine->execlist_retired_req_list); |
f1ad5a1f OM |
640 | } |
641 | } | |
642 | ||
e2f80391 | 643 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
f1ad5a1f | 644 | if (num_elements == 0) |
e2f80391 | 645 | execlists_context_unqueue(engine); |
acdd884a | 646 | |
27af5eea | 647 | spin_unlock_bh(&engine->execlist_lock); |
acdd884a MT |
648 | } |
649 | ||
2f20055d | 650 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 651 | { |
4a570db5 | 652 | struct intel_engine_cs *engine = req->engine; |
ba8b7ccb OM |
653 | uint32_t flush_domains; |
654 | int ret; | |
655 | ||
656 | flush_domains = 0; | |
e2f80391 | 657 | if (engine->gpu_caches_dirty) |
ba8b7ccb OM |
658 | flush_domains = I915_GEM_GPU_DOMAINS; |
659 | ||
e2f80391 | 660 | ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
661 | if (ret) |
662 | return ret; | |
663 | ||
e2f80391 | 664 | engine->gpu_caches_dirty = false; |
ba8b7ccb OM |
665 | return 0; |
666 | } | |
667 | ||
535fbe82 | 668 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
669 | struct list_head *vmas) |
670 | { | |
666796da | 671 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
ba8b7ccb OM |
672 | struct i915_vma *vma; |
673 | uint32_t flush_domains = 0; | |
674 | bool flush_chipset = false; | |
675 | int ret; | |
676 | ||
677 | list_for_each_entry(vma, vmas, exec_list) { | |
678 | struct drm_i915_gem_object *obj = vma->obj; | |
679 | ||
03ade511 | 680 | if (obj->active & other_rings) { |
4a570db5 | 681 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
682 | if (ret) |
683 | return ret; | |
684 | } | |
ba8b7ccb OM |
685 | |
686 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
687 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
688 | ||
689 | flush_domains |= obj->base.write_domain; | |
690 | } | |
691 | ||
692 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
693 | wmb(); | |
694 | ||
695 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
696 | * any residual writes from the previous batch. | |
697 | */ | |
2f20055d | 698 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
699 | } |
700 | ||
40e895ce | 701 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 702 | { |
e28e404c | 703 | int ret = 0; |
bc0dce3f | 704 | |
4a570db5 | 705 | request->ringbuf = request->ctx->engine[request->engine->id].ringbuf; |
f3cc01f0 | 706 | |
a7e02199 AD |
707 | if (i915.enable_guc_submission) { |
708 | /* | |
709 | * Check that the GuC has space for the request before | |
710 | * going any further, as the i915_add_request() call | |
711 | * later on mustn't fail ... | |
712 | */ | |
713 | struct intel_guc *guc = &request->i915->guc; | |
714 | ||
715 | ret = i915_guc_wq_check_space(guc->execbuf_client); | |
716 | if (ret) | |
717 | return ret; | |
718 | } | |
719 | ||
e28e404c | 720 | if (request->ctx != request->i915->kernel_context) |
4a570db5 | 721 | ret = intel_lr_context_pin(request->ctx, request->engine); |
e28e404c DG |
722 | |
723 | return ret; | |
bc0dce3f JH |
724 | } |
725 | ||
ae70797d | 726 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 727 | int bytes) |
bc0dce3f | 728 | { |
ae70797d | 729 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
4a570db5 | 730 | struct intel_engine_cs *engine = req->engine; |
ae70797d | 731 | struct drm_i915_gem_request *target; |
b4716185 CW |
732 | unsigned space; |
733 | int ret; | |
bc0dce3f JH |
734 | |
735 | if (intel_ring_space(ringbuf) >= bytes) | |
736 | return 0; | |
737 | ||
79bbcc29 JH |
738 | /* The whole point of reserving space is to not wait! */ |
739 | WARN_ON(ringbuf->reserved_in_use); | |
740 | ||
e2f80391 | 741 | list_for_each_entry(target, &engine->request_list, list) { |
bc0dce3f JH |
742 | /* |
743 | * The request queue is per-engine, so can contain requests | |
744 | * from multiple ringbuffers. Here, we must ignore any that | |
745 | * aren't from the ringbuffer we're considering. | |
746 | */ | |
ae70797d | 747 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
748 | continue; |
749 | ||
750 | /* Would completion of this request free enough space? */ | |
ae70797d | 751 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
752 | ringbuf->size); |
753 | if (space >= bytes) | |
bc0dce3f | 754 | break; |
bc0dce3f JH |
755 | } |
756 | ||
e2f80391 | 757 | if (WARN_ON(&target->list == &engine->request_list)) |
bc0dce3f JH |
758 | return -ENOSPC; |
759 | ||
ae70797d | 760 | ret = i915_wait_request(target); |
bc0dce3f JH |
761 | if (ret) |
762 | return ret; | |
763 | ||
b4716185 CW |
764 | ringbuf->space = space; |
765 | return 0; | |
bc0dce3f JH |
766 | } |
767 | ||
768 | /* | |
769 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 770 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
771 | * |
772 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
773 | * really happens during submission is that the context and current tail will be placed | |
774 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
775 | * point, the tail *inside* the context is updated and the ELSP written to. | |
776 | */ | |
7c17d377 | 777 | static int |
ae70797d | 778 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 779 | { |
7c17d377 | 780 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
d1675198 | 781 | struct drm_i915_private *dev_priv = request->i915; |
4a570db5 | 782 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 783 | |
7c17d377 CW |
784 | intel_logical_ring_advance(ringbuf); |
785 | request->tail = ringbuf->tail; | |
bc0dce3f | 786 | |
7c17d377 CW |
787 | /* |
788 | * Here we add two extra NOOPs as padding to avoid | |
789 | * lite restore of a context with HEAD==TAIL. | |
790 | * | |
791 | * Caller must reserve WA_TAIL_DWORDS for us! | |
792 | */ | |
793 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
794 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
795 | intel_logical_ring_advance(ringbuf); | |
d1675198 | 796 | |
117897f4 | 797 | if (intel_engine_stopped(engine)) |
7c17d377 | 798 | return 0; |
bc0dce3f | 799 | |
f4e2dece TU |
800 | if (engine->last_context != request->ctx) { |
801 | if (engine->last_context) | |
802 | intel_lr_context_unpin(engine->last_context, engine); | |
803 | if (request->ctx != request->i915->kernel_context) { | |
804 | intel_lr_context_pin(request->ctx, engine); | |
805 | engine->last_context = request->ctx; | |
806 | } else { | |
807 | engine->last_context = NULL; | |
808 | } | |
809 | } | |
810 | ||
d1675198 AD |
811 | if (dev_priv->guc.execbuf_client) |
812 | i915_guc_submit(dev_priv->guc.execbuf_client, request); | |
813 | else | |
814 | execlists_context_queue(request); | |
7c17d377 CW |
815 | |
816 | return 0; | |
bc0dce3f JH |
817 | } |
818 | ||
79bbcc29 | 819 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
820 | { |
821 | uint32_t __iomem *virt; | |
822 | int rem = ringbuf->size - ringbuf->tail; | |
823 | ||
bc0dce3f JH |
824 | virt = ringbuf->virtual_start + ringbuf->tail; |
825 | rem /= 4; | |
826 | while (rem--) | |
827 | iowrite32(MI_NOOP, virt++); | |
828 | ||
829 | ringbuf->tail = 0; | |
830 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
831 | } |
832 | ||
ae70797d | 833 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 834 | { |
ae70797d | 835 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
836 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
837 | int remain_actual = ringbuf->size - ringbuf->tail; | |
838 | int ret, total_bytes, wait_bytes = 0; | |
839 | bool need_wrap = false; | |
29b1b415 | 840 | |
79bbcc29 JH |
841 | if (ringbuf->reserved_in_use) |
842 | total_bytes = bytes; | |
843 | else | |
844 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 845 | |
79bbcc29 JH |
846 | if (unlikely(bytes > remain_usable)) { |
847 | /* | |
848 | * Not enough space for the basic request. So need to flush | |
849 | * out the remainder and then wait for base + reserved. | |
850 | */ | |
851 | wait_bytes = remain_actual + total_bytes; | |
852 | need_wrap = true; | |
853 | } else { | |
854 | if (unlikely(total_bytes > remain_usable)) { | |
855 | /* | |
856 | * The base request will fit but the reserved space | |
782f6bc0 AG |
857 | * falls off the end. So don't need an immediate wrap |
858 | * and only need to effectively wait for the reserved | |
859 | * size space from the start of ringbuffer. | |
79bbcc29 JH |
860 | */ |
861 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
79bbcc29 JH |
862 | } else if (total_bytes > ringbuf->space) { |
863 | /* No wrapping required, just waiting. */ | |
864 | wait_bytes = total_bytes; | |
29b1b415 | 865 | } |
bc0dce3f JH |
866 | } |
867 | ||
79bbcc29 JH |
868 | if (wait_bytes) { |
869 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
870 | if (unlikely(ret)) |
871 | return ret; | |
79bbcc29 JH |
872 | |
873 | if (need_wrap) | |
874 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
875 | } |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | /** | |
881 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
882 | * | |
374887ba | 883 | * @req: The request to start some new work for |
bc0dce3f JH |
884 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
885 | * | |
886 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
887 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
888 | * and also preallocates a request (every workload submission is still mediated through | |
889 | * requests, same as it did with legacy ringbuffer submission). | |
890 | * | |
891 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
892 | */ | |
3bbaba0c | 893 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
bc0dce3f | 894 | { |
4d616a29 | 895 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
896 | int ret; |
897 | ||
4d616a29 | 898 | WARN_ON(req == NULL); |
39dabecd | 899 | dev_priv = req->i915; |
4d616a29 | 900 | |
bc0dce3f JH |
901 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
902 | dev_priv->mm.interruptible); | |
903 | if (ret) | |
904 | return ret; | |
905 | ||
ae70797d | 906 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
907 | if (ret) |
908 | return ret; | |
909 | ||
4d616a29 | 910 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
911 | return 0; |
912 | } | |
913 | ||
ccd98fe4 JH |
914 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
915 | { | |
916 | /* | |
917 | * The first call merely notes the reserve request and is common for | |
918 | * all back ends. The subsequent localised _begin() call actually | |
919 | * ensures that the reservation is available. Without the begin, if | |
920 | * the request creator immediately submitted the request without | |
921 | * adding any commands to it then there might not actually be | |
922 | * sufficient room for the submission commands. | |
923 | */ | |
924 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
925 | ||
926 | return intel_logical_ring_begin(request, 0); | |
927 | } | |
928 | ||
73e4d07f OM |
929 | /** |
930 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
931 | * @dev: DRM device. | |
932 | * @file: DRM file. | |
933 | * @ring: Engine Command Streamer to submit to. | |
934 | * @ctx: Context to employ for this submission. | |
935 | * @args: execbuffer call arguments. | |
936 | * @vmas: list of vmas. | |
937 | * @batch_obj: the batchbuffer to submit. | |
938 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 939 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
940 | * |
941 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
942 | * away the submission details of the execbuffer ioctl call. | |
943 | * | |
944 | * Return: non-zero if the submission fails. | |
945 | */ | |
5f19e2bf | 946 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 947 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 948 | struct list_head *vmas) |
454afebd | 949 | { |
5f19e2bf | 950 | struct drm_device *dev = params->dev; |
4a570db5 | 951 | struct intel_engine_cs *engine = params->engine; |
ba8b7ccb | 952 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 953 | struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf; |
5f19e2bf | 954 | u64 exec_start; |
ba8b7ccb OM |
955 | int instp_mode; |
956 | u32 instp_mask; | |
957 | int ret; | |
958 | ||
959 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
960 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
961 | switch (instp_mode) { | |
962 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
963 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
964 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
4a570db5 | 965 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
ba8b7ccb OM |
966 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
967 | return -EINVAL; | |
968 | } | |
969 | ||
970 | if (instp_mode != dev_priv->relative_constants_mode) { | |
971 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
972 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
973 | return -EINVAL; | |
974 | } | |
975 | ||
976 | /* The HW changed the meaning on this bit on gen6 */ | |
977 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
978 | } | |
979 | break; | |
980 | default: | |
981 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
982 | return -EINVAL; | |
983 | } | |
984 | ||
ba8b7ccb OM |
985 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
986 | DRM_DEBUG("sol reset is gen7 only\n"); | |
987 | return -EINVAL; | |
988 | } | |
989 | ||
535fbe82 | 990 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
991 | if (ret) |
992 | return ret; | |
993 | ||
4a570db5 | 994 | if (engine == &dev_priv->engine[RCS] && |
ba8b7ccb | 995 | instp_mode != dev_priv->relative_constants_mode) { |
4d616a29 | 996 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
997 | if (ret) |
998 | return ret; | |
999 | ||
1000 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1001 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1002 | intel_logical_ring_emit_reg(ringbuf, INSTPM); |
ba8b7ccb OM |
1003 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
1004 | intel_logical_ring_advance(ringbuf); | |
1005 | ||
1006 | dev_priv->relative_constants_mode = instp_mode; | |
1007 | } | |
1008 | ||
5f19e2bf JH |
1009 | exec_start = params->batch_obj_vm_offset + |
1010 | args->batch_start_offset; | |
1011 | ||
e2f80391 | 1012 | ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
1013 | if (ret) |
1014 | return ret; | |
1015 | ||
95c24161 | 1016 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 1017 | |
8a8edb59 | 1018 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1019 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 1020 | |
454afebd OM |
1021 | return 0; |
1022 | } | |
1023 | ||
0bc40be8 | 1024 | void intel_execlists_retire_requests(struct intel_engine_cs *engine) |
c86ee3a9 | 1025 | { |
6d3d8274 | 1026 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
1027 | struct list_head retired_list; |
1028 | ||
0bc40be8 TU |
1029 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
1030 | if (list_empty(&engine->execlist_retired_req_list)) | |
c86ee3a9 TD |
1031 | return; |
1032 | ||
1033 | INIT_LIST_HEAD(&retired_list); | |
27af5eea | 1034 | spin_lock_bh(&engine->execlist_lock); |
0bc40be8 | 1035 | list_replace_init(&engine->execlist_retired_req_list, &retired_list); |
27af5eea | 1036 | spin_unlock_bh(&engine->execlist_lock); |
c86ee3a9 TD |
1037 | |
1038 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
af3302b9 DV |
1039 | struct intel_context *ctx = req->ctx; |
1040 | struct drm_i915_gem_object *ctx_obj = | |
0bc40be8 | 1041 | ctx->engine[engine->id].state; |
af3302b9 | 1042 | |
ed54c1a1 | 1043 | if (ctx_obj && (ctx != req->i915->kernel_context)) |
0bc40be8 | 1044 | intel_lr_context_unpin(ctx, engine); |
e5292823 | 1045 | |
c86ee3a9 | 1046 | list_del(&req->execlist_link); |
f8210795 | 1047 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
1048 | } |
1049 | } | |
1050 | ||
0bc40be8 | 1051 | void intel_logical_ring_stop(struct intel_engine_cs *engine) |
454afebd | 1052 | { |
0bc40be8 | 1053 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
9832b9da OM |
1054 | int ret; |
1055 | ||
117897f4 | 1056 | if (!intel_engine_initialized(engine)) |
9832b9da OM |
1057 | return; |
1058 | ||
666796da | 1059 | ret = intel_engine_idle(engine); |
0bc40be8 | 1060 | if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error)) |
9832b9da | 1061 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 1062 | engine->name, ret); |
9832b9da OM |
1063 | |
1064 | /* TODO: Is this correct with Execlists enabled? */ | |
0bc40be8 TU |
1065 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
1066 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
1067 | DRM_ERROR("%s :timed out trying to stop ring\n", engine->name); | |
9832b9da OM |
1068 | return; |
1069 | } | |
0bc40be8 | 1070 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
454afebd OM |
1071 | } |
1072 | ||
4866d729 | 1073 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 1074 | { |
4a570db5 | 1075 | struct intel_engine_cs *engine = req->engine; |
48e29f55 OM |
1076 | int ret; |
1077 | ||
e2f80391 | 1078 | if (!engine->gpu_caches_dirty) |
48e29f55 OM |
1079 | return 0; |
1080 | ||
e2f80391 | 1081 | ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1082 | if (ret) |
1083 | return ret; | |
1084 | ||
e2f80391 | 1085 | engine->gpu_caches_dirty = false; |
48e29f55 OM |
1086 | return 0; |
1087 | } | |
1088 | ||
e5292823 | 1089 | static int intel_lr_context_do_pin(struct intel_context *ctx, |
0bc40be8 | 1090 | struct intel_engine_cs *engine) |
dcb4c12a | 1091 | { |
0bc40be8 | 1092 | struct drm_device *dev = engine->dev; |
e84fe803 | 1093 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 TU |
1094 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
1095 | struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; | |
82352e90 | 1096 | struct page *lrc_state_page; |
77b04a04 | 1097 | uint32_t *lrc_reg_state; |
ca82580c | 1098 | int ret; |
dcb4c12a | 1099 | |
0bc40be8 | 1100 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
ca82580c | 1101 | |
e84fe803 NH |
1102 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
1103 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
1104 | if (ret) | |
1105 | return ret; | |
7ba717cf | 1106 | |
82352e90 TU |
1107 | lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
1108 | if (WARN_ON(!lrc_state_page)) { | |
1109 | ret = -ENODEV; | |
1110 | goto unpin_ctx_obj; | |
1111 | } | |
1112 | ||
0bc40be8 | 1113 | ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf); |
e84fe803 NH |
1114 | if (ret) |
1115 | goto unpin_ctx_obj; | |
d1675198 | 1116 | |
0bc40be8 TU |
1117 | ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj); |
1118 | intel_lr_context_descriptor_update(ctx, engine); | |
77b04a04 TU |
1119 | lrc_reg_state = kmap(lrc_state_page); |
1120 | lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start; | |
0bc40be8 | 1121 | ctx->engine[engine->id].lrc_reg_state = lrc_reg_state; |
e84fe803 | 1122 | ctx_obj->dirty = true; |
e93c28f3 | 1123 | |
e84fe803 NH |
1124 | /* Invalidate GuC TLB. */ |
1125 | if (i915.enable_guc_submission) | |
1126 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a | 1127 | |
7ba717cf TD |
1128 | return ret; |
1129 | ||
1130 | unpin_ctx_obj: | |
1131 | i915_gem_object_ggtt_unpin(ctx_obj); | |
e84fe803 NH |
1132 | |
1133 | return ret; | |
1134 | } | |
1135 | ||
e5292823 TU |
1136 | static int intel_lr_context_pin(struct intel_context *ctx, |
1137 | struct intel_engine_cs *engine) | |
e84fe803 NH |
1138 | { |
1139 | int ret = 0; | |
e84fe803 | 1140 | |
e5292823 TU |
1141 | if (ctx->engine[engine->id].pin_count++ == 0) { |
1142 | ret = intel_lr_context_do_pin(ctx, engine); | |
e84fe803 NH |
1143 | if (ret) |
1144 | goto reset_pin_count; | |
321fe304 TU |
1145 | |
1146 | i915_gem_context_reference(ctx); | |
e84fe803 NH |
1147 | } |
1148 | return ret; | |
1149 | ||
a7cbedec | 1150 | reset_pin_count: |
e5292823 | 1151 | ctx->engine[engine->id].pin_count = 0; |
dcb4c12a OM |
1152 | return ret; |
1153 | } | |
1154 | ||
e5292823 TU |
1155 | void intel_lr_context_unpin(struct intel_context *ctx, |
1156 | struct intel_engine_cs *engine) | |
dcb4c12a | 1157 | { |
e5292823 | 1158 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
af3302b9 | 1159 | |
f4e2dece | 1160 | WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex)); |
e5292823 TU |
1161 | if (--ctx->engine[engine->id].pin_count == 0) { |
1162 | kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state)); | |
1163 | intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf); | |
82352e90 | 1164 | i915_gem_object_ggtt_unpin(ctx_obj); |
e5292823 TU |
1165 | ctx->engine[engine->id].lrc_vma = NULL; |
1166 | ctx->engine[engine->id].lrc_desc = 0; | |
1167 | ctx->engine[engine->id].lrc_reg_state = NULL; | |
321fe304 TU |
1168 | |
1169 | i915_gem_context_unreference(ctx); | |
dcb4c12a OM |
1170 | } |
1171 | } | |
1172 | ||
e2be4faf | 1173 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1174 | { |
1175 | int ret, i; | |
4a570db5 | 1176 | struct intel_engine_cs *engine = req->engine; |
e2be4faf | 1177 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
e2f80391 | 1178 | struct drm_device *dev = engine->dev; |
771b9a53 MT |
1179 | struct drm_i915_private *dev_priv = dev->dev_private; |
1180 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1181 | ||
cd7feaaa | 1182 | if (w->count == 0) |
771b9a53 MT |
1183 | return 0; |
1184 | ||
e2f80391 | 1185 | engine->gpu_caches_dirty = true; |
4866d729 | 1186 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1187 | if (ret) |
1188 | return ret; | |
1189 | ||
4d616a29 | 1190 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1191 | if (ret) |
1192 | return ret; | |
1193 | ||
1194 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1195 | for (i = 0; i < w->count; i++) { | |
f92a9162 | 1196 | intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr); |
771b9a53 MT |
1197 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
1198 | } | |
1199 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1200 | ||
1201 | intel_logical_ring_advance(ringbuf); | |
1202 | ||
e2f80391 | 1203 | engine->gpu_caches_dirty = true; |
4866d729 | 1204 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
83b8a982 | 1211 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1212 | do { \ |
83b8a982 AS |
1213 | int __index = (index)++; \ |
1214 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1215 | return -ENOSPC; \ |
1216 | } \ | |
83b8a982 | 1217 | batch[__index] = (cmd); \ |
17ee950d AS |
1218 | } while (0) |
1219 | ||
8f40db77 | 1220 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 1221 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
1222 | |
1223 | /* | |
1224 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1225 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1226 | * but there is a slight complication as this is applied in WA batch where the | |
1227 | * values are only initialized once so we cannot take register value at the | |
1228 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1229 | * constant value with bit21 set and then we restore it back with the saved value. | |
1230 | * To simplify the WA, a constant value is formed by using the default value | |
1231 | * of this register. This shouldn't be a problem because we are only modifying | |
1232 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1233 | * use additional instructions that read the actual value of the register | |
1234 | * at that time and set our bit of interest but it makes the WA complicated. | |
1235 | * | |
1236 | * This WA is also required for Gen9 so extracting as a function avoids | |
1237 | * code duplication. | |
1238 | */ | |
0bc40be8 | 1239 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
9e000847 AS |
1240 | uint32_t *const batch, |
1241 | uint32_t index) | |
1242 | { | |
1243 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1244 | ||
a4106a78 AS |
1245 | /* |
1246 | * WaDisableLSQCROPERFforOCL:skl | |
1247 | * This WA is implemented in skl_init_clock_gating() but since | |
1248 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1249 | * set this bit here to retain the WA during flush. | |
1250 | */ | |
0bc40be8 | 1251 | if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0)) |
a4106a78 AS |
1252 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
1253 | ||
f1afe24f | 1254 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 1255 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1256 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1257 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 AS |
1258 | wa_ctx_emit(batch, index, 0); |
1259 | ||
1260 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 1261 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
1262 | wa_ctx_emit(batch, index, l3sqc4_flush); |
1263 | ||
1264 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1265 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1266 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1267 | wa_ctx_emit(batch, index, 0); | |
1268 | wa_ctx_emit(batch, index, 0); | |
1269 | wa_ctx_emit(batch, index, 0); | |
1270 | wa_ctx_emit(batch, index, 0); | |
1271 | ||
f1afe24f | 1272 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 1273 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1274 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1275 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 | 1276 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
1277 | |
1278 | return index; | |
1279 | } | |
1280 | ||
17ee950d AS |
1281 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1282 | uint32_t offset, | |
1283 | uint32_t start_alignment) | |
1284 | { | |
1285 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1286 | } | |
1287 | ||
1288 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1289 | uint32_t offset, | |
1290 | uint32_t size_alignment) | |
1291 | { | |
1292 | wa_ctx->size = offset - wa_ctx->offset; | |
1293 | ||
1294 | WARN(wa_ctx->size % size_alignment, | |
1295 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1296 | wa_ctx->size, size_alignment); | |
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | /** | |
1301 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1302 | * | |
1303 | * @ring: only applicable for RCS | |
1304 | * @wa_ctx: structure representing wa_ctx | |
1305 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1306 | * with the offset value received as input. | |
1307 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1308 | * @batch: page in which WA are loaded | |
1309 | * @offset: This field specifies the start of the batch, it should be | |
1310 | * cache-aligned otherwise it is adjusted accordingly. | |
1311 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1312 | * initialized at the beginning and shared across all contexts but this field | |
1313 | * helps us to have multiple batches at different offsets and select them based | |
1314 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1315 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1316 | * | |
1317 | * The number of WA applied are not known at the beginning; we use this field | |
1318 | * to return the no of DWORDS written. | |
4d78c8dc | 1319 | * |
17ee950d AS |
1320 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1321 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1322 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1323 | * makes a complete batch buffer. | |
1324 | * | |
1325 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1326 | */ | |
1327 | ||
0bc40be8 | 1328 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1329 | struct i915_wa_ctx_bb *wa_ctx, |
1330 | uint32_t *const batch, | |
1331 | uint32_t *offset) | |
1332 | { | |
0160f055 | 1333 | uint32_t scratch_addr; |
17ee950d AS |
1334 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1335 | ||
7ad00d1a | 1336 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1337 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1338 | |
c82435bb | 1339 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
0bc40be8 TU |
1340 | if (IS_BROADWELL(engine->dev)) { |
1341 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); | |
604ef734 AH |
1342 | if (rc < 0) |
1343 | return rc; | |
1344 | index = rc; | |
c82435bb AS |
1345 | } |
1346 | ||
0160f055 AS |
1347 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1348 | /* Actual scratch location is at 128 bytes offset */ | |
0bc40be8 | 1349 | scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; |
0160f055 | 1350 | |
83b8a982 AS |
1351 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1352 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1353 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1354 | PIPE_CONTROL_CS_STALL | | |
1355 | PIPE_CONTROL_QW_WRITE)); | |
1356 | wa_ctx_emit(batch, index, scratch_addr); | |
1357 | wa_ctx_emit(batch, index, 0); | |
1358 | wa_ctx_emit(batch, index, 0); | |
1359 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1360 | |
17ee950d AS |
1361 | /* Pad to end of cacheline */ |
1362 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1363 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1364 | |
1365 | /* | |
1366 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1367 | * execution depends on the length specified in terms of cache lines | |
1368 | * in the register CTX_RCS_INDIRECT_CTX | |
1369 | */ | |
1370 | ||
1371 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1372 | } | |
1373 | ||
1374 | /** | |
1375 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1376 | * | |
1377 | * @ring: only applicable for RCS | |
1378 | * @wa_ctx: structure representing wa_ctx | |
1379 | * offset: specifies start of the batch, should be cache-aligned. | |
1380 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1381 | * @batch: page in which WA are loaded |
17ee950d AS |
1382 | * @offset: This field specifies the start of this batch. |
1383 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1384 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1385 | * | |
1386 | * The number of DWORDS written are returned using this field. | |
1387 | * | |
1388 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1389 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1390 | */ | |
0bc40be8 | 1391 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1392 | struct i915_wa_ctx_bb *wa_ctx, |
1393 | uint32_t *const batch, | |
1394 | uint32_t *offset) | |
1395 | { | |
1396 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1397 | ||
7ad00d1a | 1398 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1399 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1400 | |
83b8a982 | 1401 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1402 | |
1403 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1404 | } | |
1405 | ||
0bc40be8 | 1406 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1407 | struct i915_wa_ctx_bb *wa_ctx, |
1408 | uint32_t *const batch, | |
1409 | uint32_t *offset) | |
1410 | { | |
a4106a78 | 1411 | int ret; |
0bc40be8 | 1412 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1413 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1414 | ||
0907c8f7 | 1415 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1416 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1417 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 | 1418 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1419 | |
a4106a78 | 1420 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1421 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1422 | if (ret < 0) |
1423 | return ret; | |
1424 | index = ret; | |
1425 | ||
0504cffc AS |
1426 | /* Pad to end of cacheline */ |
1427 | while (index % CACHELINE_DWORDS) | |
1428 | wa_ctx_emit(batch, index, MI_NOOP); | |
1429 | ||
1430 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1431 | } | |
1432 | ||
0bc40be8 | 1433 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1434 | struct i915_wa_ctx_bb *wa_ctx, |
1435 | uint32_t *const batch, | |
1436 | uint32_t *offset) | |
1437 | { | |
0bc40be8 | 1438 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1439 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1440 | ||
9b01435d | 1441 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
e87a005d | 1442 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
cbdc12a9 | 1443 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9b01435d | 1444 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1445 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1446 | wa_ctx_emit(batch, index, |
1447 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1448 | wa_ctx_emit(batch, index, MI_NOOP); | |
1449 | } | |
1450 | ||
0907c8f7 | 1451 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1452 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1453 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 AS |
1454 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1455 | ||
0504cffc AS |
1456 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1457 | ||
1458 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1459 | } | |
1460 | ||
0bc40be8 | 1461 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d AS |
1462 | { |
1463 | int ret; | |
1464 | ||
0bc40be8 TU |
1465 | engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev, |
1466 | PAGE_ALIGN(size)); | |
1467 | if (!engine->wa_ctx.obj) { | |
17ee950d AS |
1468 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
1469 | return -ENOMEM; | |
1470 | } | |
1471 | ||
0bc40be8 | 1472 | ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0); |
17ee950d AS |
1473 | if (ret) { |
1474 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1475 | ret); | |
0bc40be8 | 1476 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
17ee950d AS |
1477 | return ret; |
1478 | } | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
0bc40be8 | 1483 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1484 | { |
0bc40be8 TU |
1485 | if (engine->wa_ctx.obj) { |
1486 | i915_gem_object_ggtt_unpin(engine->wa_ctx.obj); | |
1487 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); | |
1488 | engine->wa_ctx.obj = NULL; | |
17ee950d AS |
1489 | } |
1490 | } | |
1491 | ||
0bc40be8 | 1492 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d AS |
1493 | { |
1494 | int ret; | |
1495 | uint32_t *batch; | |
1496 | uint32_t offset; | |
1497 | struct page *page; | |
0bc40be8 | 1498 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d | 1499 | |
0bc40be8 | 1500 | WARN_ON(engine->id != RCS); |
17ee950d | 1501 | |
5e60d790 | 1502 | /* update this when WA for higher Gen are added */ |
0bc40be8 | 1503 | if (INTEL_INFO(engine->dev)->gen > 9) { |
0504cffc | 1504 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
0bc40be8 | 1505 | INTEL_INFO(engine->dev)->gen); |
5e60d790 | 1506 | return 0; |
0504cffc | 1507 | } |
5e60d790 | 1508 | |
c4db7599 | 1509 | /* some WA perform writes to scratch page, ensure it is valid */ |
0bc40be8 TU |
1510 | if (engine->scratch.obj == NULL) { |
1511 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); | |
c4db7599 AS |
1512 | return -EINVAL; |
1513 | } | |
1514 | ||
0bc40be8 | 1515 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1516 | if (ret) { |
1517 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1518 | return ret; | |
1519 | } | |
1520 | ||
033908ae | 1521 | page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0); |
17ee950d AS |
1522 | batch = kmap_atomic(page); |
1523 | offset = 0; | |
1524 | ||
0bc40be8 TU |
1525 | if (INTEL_INFO(engine->dev)->gen == 8) { |
1526 | ret = gen8_init_indirectctx_bb(engine, | |
17ee950d AS |
1527 | &wa_ctx->indirect_ctx, |
1528 | batch, | |
1529 | &offset); | |
1530 | if (ret) | |
1531 | goto out; | |
1532 | ||
0bc40be8 | 1533 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1534 | &wa_ctx->per_ctx, |
1535 | batch, | |
1536 | &offset); | |
1537 | if (ret) | |
1538 | goto out; | |
0bc40be8 TU |
1539 | } else if (INTEL_INFO(engine->dev)->gen == 9) { |
1540 | ret = gen9_init_indirectctx_bb(engine, | |
0504cffc AS |
1541 | &wa_ctx->indirect_ctx, |
1542 | batch, | |
1543 | &offset); | |
1544 | if (ret) | |
1545 | goto out; | |
1546 | ||
0bc40be8 | 1547 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1548 | &wa_ctx->per_ctx, |
1549 | batch, | |
1550 | &offset); | |
1551 | if (ret) | |
1552 | goto out; | |
17ee950d AS |
1553 | } |
1554 | ||
1555 | out: | |
1556 | kunmap_atomic(batch); | |
1557 | if (ret) | |
0bc40be8 | 1558 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1559 | |
1560 | return ret; | |
1561 | } | |
1562 | ||
0bc40be8 | 1563 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1564 | { |
0bc40be8 | 1565 | struct drm_device *dev = engine->dev; |
9b1136d5 | 1566 | struct drm_i915_private *dev_priv = dev->dev_private; |
c6a2ac71 | 1567 | unsigned int next_context_status_buffer_hw; |
9b1136d5 | 1568 | |
0bc40be8 TU |
1569 | lrc_setup_hardware_status_page(engine, |
1570 | dev_priv->kernel_context->engine[engine->id].state); | |
e84fe803 | 1571 | |
0bc40be8 TU |
1572 | I915_WRITE_IMR(engine, |
1573 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1574 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
73d477f6 | 1575 | |
0bc40be8 | 1576 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1577 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1578 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
0bc40be8 | 1579 | POSTING_READ(RING_MODE_GEN7(engine)); |
dfc53c5e MT |
1580 | |
1581 | /* | |
1582 | * Instead of resetting the Context Status Buffer (CSB) read pointer to | |
1583 | * zero, we need to read the write pointer from hardware and use its | |
1584 | * value because "this register is power context save restored". | |
1585 | * Effectively, these states have been observed: | |
1586 | * | |
1587 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | | |
1588 | * BDW | CSB regs not reset | CSB regs reset | | |
1589 | * CHT | CSB regs not reset | CSB regs not reset | | |
5590a5f0 BW |
1590 | * SKL | ? | ? | |
1591 | * BXT | ? | ? | | |
dfc53c5e | 1592 | */ |
5590a5f0 | 1593 | next_context_status_buffer_hw = |
0bc40be8 | 1594 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
dfc53c5e MT |
1595 | |
1596 | /* | |
1597 | * When the CSB registers are reset (also after power-up / gpu reset), | |
1598 | * CSB write pointer is set to all 1's, which is not valid, use '5' in | |
1599 | * this special case, so the first element read is CSB[0]. | |
1600 | */ | |
1601 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) | |
1602 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); | |
1603 | ||
0bc40be8 TU |
1604 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
1605 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); | |
9b1136d5 | 1606 | |
fc0768ce | 1607 | intel_engine_init_hangcheck(engine); |
9b1136d5 OM |
1608 | |
1609 | return 0; | |
1610 | } | |
1611 | ||
0bc40be8 | 1612 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1613 | { |
0bc40be8 | 1614 | struct drm_device *dev = engine->dev; |
9b1136d5 OM |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; |
1616 | int ret; | |
1617 | ||
0bc40be8 | 1618 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1619 | if (ret) |
1620 | return ret; | |
1621 | ||
1622 | /* We need to disable the AsyncFlip performance optimisations in order | |
1623 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1624 | * programmed to '1' on all products. | |
1625 | * | |
1626 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1627 | */ | |
1628 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1629 | ||
9b1136d5 OM |
1630 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1631 | ||
0bc40be8 | 1632 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1633 | } |
1634 | ||
0bc40be8 | 1635 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1636 | { |
1637 | int ret; | |
1638 | ||
0bc40be8 | 1639 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1640 | if (ret) |
1641 | return ret; | |
1642 | ||
0bc40be8 | 1643 | return init_workarounds_ring(engine); |
82ef822e DL |
1644 | } |
1645 | ||
7a01a0a2 MT |
1646 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1647 | { | |
1648 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1649 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1650 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
1651 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1652 | int i, ret; | |
1653 | ||
1654 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1655 | if (ret) | |
1656 | return ret; | |
1657 | ||
1658 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1659 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1660 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1661 | ||
e2f80391 TU |
1662 | intel_logical_ring_emit_reg(ringbuf, |
1663 | GEN8_RING_PDP_UDW(engine, i)); | |
7a01a0a2 | 1664 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
e2f80391 TU |
1665 | intel_logical_ring_emit_reg(ringbuf, |
1666 | GEN8_RING_PDP_LDW(engine, i)); | |
7a01a0a2 MT |
1667 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
1668 | } | |
1669 | ||
1670 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1671 | intel_logical_ring_advance(ringbuf); | |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
be795fc1 | 1676 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1677 | u64 offset, unsigned dispatch_flags) |
15648585 | 1678 | { |
be795fc1 | 1679 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1680 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1681 | int ret; |
1682 | ||
7a01a0a2 MT |
1683 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1684 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1685 | * but we can't. Force Restore would be a second option, but | |
1686 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1687 | * not idle). PML4 is allocated during ppgtt init so this is |
1688 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1689 | if (req->ctx->ppgtt && |
666796da | 1690 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 ZL |
1691 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
1692 | !intel_vgpu_active(req->i915->dev)) { | |
2dba3239 MT |
1693 | ret = intel_logical_ring_emit_pdps(req); |
1694 | if (ret) | |
1695 | return ret; | |
1696 | } | |
7a01a0a2 | 1697 | |
666796da | 1698 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1699 | } |
1700 | ||
4d616a29 | 1701 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1702 | if (ret) |
1703 | return ret; | |
1704 | ||
1705 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1706 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1707 | (ppgtt<<8) | | |
1708 | (dispatch_flags & I915_DISPATCH_RS ? | |
1709 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1710 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1711 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1712 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1713 | intel_logical_ring_advance(ringbuf); | |
1714 | ||
1715 | return 0; | |
1716 | } | |
1717 | ||
0bc40be8 | 1718 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine) |
73d477f6 | 1719 | { |
0bc40be8 | 1720 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1721 | struct drm_i915_private *dev_priv = dev->dev_private; |
1722 | unsigned long flags; | |
1723 | ||
7cd512f1 | 1724 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1725 | return false; |
1726 | ||
1727 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1728 | if (engine->irq_refcount++ == 0) { |
1729 | I915_WRITE_IMR(engine, | |
1730 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1731 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1732 | } |
1733 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1734 | ||
1735 | return true; | |
1736 | } | |
1737 | ||
0bc40be8 | 1738 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine) |
73d477f6 | 1739 | { |
0bc40be8 | 1740 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1741 | struct drm_i915_private *dev_priv = dev->dev_private; |
1742 | unsigned long flags; | |
1743 | ||
1744 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1745 | if (--engine->irq_refcount == 0) { |
1746 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
1747 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1748 | } |
1749 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1750 | } | |
1751 | ||
7deb4d39 | 1752 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1753 | u32 invalidate_domains, |
1754 | u32 unused) | |
1755 | { | |
7deb4d39 | 1756 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1757 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1758 | struct drm_device *dev = engine->dev; |
4712274c OM |
1759 | struct drm_i915_private *dev_priv = dev->dev_private; |
1760 | uint32_t cmd; | |
1761 | int ret; | |
1762 | ||
4d616a29 | 1763 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1764 | if (ret) |
1765 | return ret; | |
1766 | ||
1767 | cmd = MI_FLUSH_DW + 1; | |
1768 | ||
f0a1fb10 CW |
1769 | /* We always require a command barrier so that subsequent |
1770 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1771 | * wrt the contents of the write cache being flushed to memory | |
1772 | * (and thus being coherent from the CPU). | |
1773 | */ | |
1774 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1775 | ||
1776 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1777 | cmd |= MI_INVALIDATE_TLB; | |
4a570db5 | 1778 | if (engine == &dev_priv->engine[VCS]) |
f0a1fb10 | 1779 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1780 | } |
1781 | ||
1782 | intel_logical_ring_emit(ringbuf, cmd); | |
1783 | intel_logical_ring_emit(ringbuf, | |
1784 | I915_GEM_HWS_SCRATCH_ADDR | | |
1785 | MI_FLUSH_DW_USE_GTT); | |
1786 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1787 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1788 | intel_logical_ring_advance(ringbuf); | |
1789 | ||
1790 | return 0; | |
1791 | } | |
1792 | ||
7deb4d39 | 1793 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1794 | u32 invalidate_domains, |
1795 | u32 flush_domains) | |
1796 | { | |
7deb4d39 | 1797 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1798 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1799 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
1a5a9ce7 | 1800 | bool vf_flush_wa = false; |
4712274c OM |
1801 | u32 flags = 0; |
1802 | int ret; | |
1803 | ||
1804 | flags |= PIPE_CONTROL_CS_STALL; | |
1805 | ||
1806 | if (flush_domains) { | |
1807 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1808 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1809 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1810 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1811 | } |
1812 | ||
1813 | if (invalidate_domains) { | |
1814 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1815 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1816 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1817 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1818 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1819 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1820 | flags |= PIPE_CONTROL_QW_WRITE; | |
1821 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1822 | |
1a5a9ce7 BW |
1823 | /* |
1824 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1825 | * pipe control. | |
1826 | */ | |
e2f80391 | 1827 | if (IS_GEN9(engine->dev)) |
1a5a9ce7 BW |
1828 | vf_flush_wa = true; |
1829 | } | |
9647ff36 | 1830 | |
4d616a29 | 1831 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1832 | if (ret) |
1833 | return ret; | |
1834 | ||
9647ff36 ID |
1835 | if (vf_flush_wa) { |
1836 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1837 | intel_logical_ring_emit(ringbuf, 0); | |
1838 | intel_logical_ring_emit(ringbuf, 0); | |
1839 | intel_logical_ring_emit(ringbuf, 0); | |
1840 | intel_logical_ring_emit(ringbuf, 0); | |
1841 | intel_logical_ring_emit(ringbuf, 0); | |
1842 | } | |
1843 | ||
4712274c OM |
1844 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1845 | intel_logical_ring_emit(ringbuf, flags); | |
1846 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1847 | intel_logical_ring_emit(ringbuf, 0); | |
1848 | intel_logical_ring_emit(ringbuf, 0); | |
1849 | intel_logical_ring_emit(ringbuf, 0); | |
1850 | intel_logical_ring_advance(ringbuf); | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
c04e0f3b | 1855 | static u32 gen8_get_seqno(struct intel_engine_cs *engine) |
e94e37ad | 1856 | { |
0bc40be8 | 1857 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
e94e37ad OM |
1858 | } |
1859 | ||
0bc40be8 | 1860 | static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
e94e37ad | 1861 | { |
0bc40be8 | 1862 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
e94e37ad OM |
1863 | } |
1864 | ||
c04e0f3b | 1865 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1866 | { |
319404df ID |
1867 | /* |
1868 | * On BXT A steppings there is a HW coherency issue whereby the | |
1869 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1870 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1871 | * clflushing the corresponding cacheline whenever the caller wants | |
1872 | * the coherency to be guaranteed. Note that this cacheline is known | |
1873 | * to be clean at this point, since we only write it in | |
1874 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1875 | * this clflush in practice becomes an invalidate operation. | |
1876 | */ | |
c04e0f3b | 1877 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1878 | } |
1879 | ||
0bc40be8 | 1880 | static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
319404df | 1881 | { |
0bc40be8 | 1882 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
319404df ID |
1883 | |
1884 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ | |
0bc40be8 | 1885 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1886 | } |
1887 | ||
7c17d377 CW |
1888 | /* |
1889 | * Reserve space for 2 NOOPs at the end of each request to be | |
1890 | * used as a workaround for not being allowed to do lite | |
1891 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1892 | */ | |
1893 | #define WA_TAIL_DWORDS 2 | |
1894 | ||
1895 | static inline u32 hws_seqno_address(struct intel_engine_cs *engine) | |
1896 | { | |
1897 | return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; | |
1898 | } | |
1899 | ||
c4e76638 | 1900 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1901 | { |
c4e76638 | 1902 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1903 | int ret; |
1904 | ||
7c17d377 | 1905 | ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1906 | if (ret) |
1907 | return ret; | |
1908 | ||
7c17d377 CW |
1909 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1910 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1911 | |
4da46e1e | 1912 | intel_logical_ring_emit(ringbuf, |
7c17d377 CW |
1913 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1914 | intel_logical_ring_emit(ringbuf, | |
4a570db5 | 1915 | hws_seqno_address(request->engine) | |
7c17d377 | 1916 | MI_FLUSH_DW_USE_GTT); |
4da46e1e | 1917 | intel_logical_ring_emit(ringbuf, 0); |
c4e76638 | 1918 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1919 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1920 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
7c17d377 CW |
1921 | return intel_logical_ring_advance_and_submit(request); |
1922 | } | |
4da46e1e | 1923 | |
7c17d377 CW |
1924 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1925 | { | |
1926 | struct intel_ringbuffer *ringbuf = request->ringbuf; | |
1927 | int ret; | |
53292cdb | 1928 | |
7c17d377 CW |
1929 | ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); |
1930 | if (ret) | |
1931 | return ret; | |
1932 | ||
1933 | /* w/a for post sync ops following a GPGPU operation we | |
1934 | * need a prior CS_STALL, which is emitted by the flush | |
1935 | * following the batch. | |
1936 | */ | |
1937 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5)); | |
1938 | intel_logical_ring_emit(ringbuf, | |
1939 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1940 | PIPE_CONTROL_CS_STALL | | |
1941 | PIPE_CONTROL_QW_WRITE)); | |
4a570db5 | 1942 | intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine)); |
7c17d377 CW |
1943 | intel_logical_ring_emit(ringbuf, 0); |
1944 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); | |
1945 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
1946 | return intel_logical_ring_advance_and_submit(request); | |
4da46e1e OM |
1947 | } |
1948 | ||
be01363f | 1949 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1950 | { |
cef437ad | 1951 | struct render_state so; |
cef437ad DL |
1952 | int ret; |
1953 | ||
4a570db5 | 1954 | ret = i915_gem_render_state_prepare(req->engine, &so); |
cef437ad DL |
1955 | if (ret) |
1956 | return ret; | |
1957 | ||
1958 | if (so.rodata == NULL) | |
1959 | return 0; | |
1960 | ||
4a570db5 | 1961 | ret = req->engine->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1962 | I915_DISPATCH_SECURE); |
cef437ad DL |
1963 | if (ret) |
1964 | goto out; | |
1965 | ||
4a570db5 | 1966 | ret = req->engine->emit_bb_start(req, |
84e81020 AS |
1967 | (so.ggtt_offset + so.aux_batch_offset), |
1968 | I915_DISPATCH_SECURE); | |
1969 | if (ret) | |
1970 | goto out; | |
1971 | ||
b2af0376 | 1972 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1973 | |
cef437ad DL |
1974 | out: |
1975 | i915_gem_render_state_fini(&so); | |
1976 | return ret; | |
1977 | } | |
1978 | ||
8753181e | 1979 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1980 | { |
1981 | int ret; | |
1982 | ||
e2be4faf | 1983 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1984 | if (ret) |
1985 | return ret; | |
1986 | ||
3bbaba0c PA |
1987 | ret = intel_rcs_context_init_mocs(req); |
1988 | /* | |
1989 | * Failing to program the MOCS is non-fatal.The system will not | |
1990 | * run at peak performance. So generate an error and carry on. | |
1991 | */ | |
1992 | if (ret) | |
1993 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1994 | ||
be01363f | 1995 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1996 | } |
1997 | ||
73e4d07f OM |
1998 | /** |
1999 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
2000 | * | |
2001 | * @ring: Engine Command Streamer. | |
2002 | * | |
2003 | */ | |
0bc40be8 | 2004 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 2005 | { |
6402c330 | 2006 | struct drm_i915_private *dev_priv; |
9832b9da | 2007 | |
117897f4 | 2008 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
2009 | return; |
2010 | ||
27af5eea TU |
2011 | /* |
2012 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
2013 | * so this is just for documentation. | |
2014 | */ | |
2015 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
2016 | tasklet_kill(&engine->irq_tasklet); | |
2017 | ||
0bc40be8 | 2018 | dev_priv = engine->dev->dev_private; |
6402c330 | 2019 | |
0bc40be8 TU |
2020 | if (engine->buffer) { |
2021 | intel_logical_ring_stop(engine); | |
2022 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
b0366a54 | 2023 | } |
48d82387 | 2024 | |
0bc40be8 TU |
2025 | if (engine->cleanup) |
2026 | engine->cleanup(engine); | |
48d82387 | 2027 | |
0bc40be8 TU |
2028 | i915_cmd_parser_fini_ring(engine); |
2029 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
48d82387 | 2030 | |
0bc40be8 TU |
2031 | if (engine->status_page.obj) { |
2032 | kunmap(sg_page(engine->status_page.obj->pages->sgl)); | |
2033 | engine->status_page.obj = NULL; | |
48d82387 | 2034 | } |
17ee950d | 2035 | |
0bc40be8 TU |
2036 | engine->idle_lite_restore_wa = 0; |
2037 | engine->disable_lite_restore_wa = false; | |
2038 | engine->ctx_desc_template = 0; | |
ca82580c | 2039 | |
0bc40be8 TU |
2040 | lrc_destroy_wa_ctx_obj(engine); |
2041 | engine->dev = NULL; | |
454afebd OM |
2042 | } |
2043 | ||
c9cacf93 TU |
2044 | static void |
2045 | logical_ring_default_vfuncs(struct drm_device *dev, | |
0bc40be8 | 2046 | struct intel_engine_cs *engine) |
c9cacf93 TU |
2047 | { |
2048 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 TU |
2049 | engine->init_hw = gen8_init_common_ring; |
2050 | engine->emit_request = gen8_emit_request; | |
2051 | engine->emit_flush = gen8_emit_flush; | |
2052 | engine->irq_get = gen8_logical_ring_get_irq; | |
2053 | engine->irq_put = gen8_logical_ring_put_irq; | |
2054 | engine->emit_bb_start = gen8_emit_bb_start; | |
c04e0f3b CW |
2055 | engine->get_seqno = gen8_get_seqno; |
2056 | engine->set_seqno = gen8_set_seqno; | |
c9cacf93 | 2057 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
c04e0f3b | 2058 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
0bc40be8 | 2059 | engine->set_seqno = bxt_a_set_seqno; |
c9cacf93 TU |
2060 | } |
2061 | } | |
2062 | ||
d9f3af96 | 2063 | static inline void |
0bc40be8 | 2064 | logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) |
d9f3af96 | 2065 | { |
0bc40be8 TU |
2066 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
2067 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
2068 | } |
2069 | ||
c9cacf93 | 2070 | static int |
0bc40be8 | 2071 | logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) |
454afebd | 2072 | { |
ed54c1a1 | 2073 | struct intel_context *dctx = to_i915(dev)->kernel_context; |
48d82387 | 2074 | int ret; |
48d82387 OM |
2075 | |
2076 | /* Intentionally left blank. */ | |
0bc40be8 | 2077 | engine->buffer = NULL; |
48d82387 | 2078 | |
0bc40be8 TU |
2079 | engine->dev = dev; |
2080 | INIT_LIST_HEAD(&engine->active_list); | |
2081 | INIT_LIST_HEAD(&engine->request_list); | |
2082 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2083 | init_waitqueue_head(&engine->irq_queue); | |
48d82387 | 2084 | |
0bc40be8 TU |
2085 | INIT_LIST_HEAD(&engine->buffers); |
2086 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2087 | INIT_LIST_HEAD(&engine->execlist_retired_req_list); | |
2088 | spin_lock_init(&engine->execlist_lock); | |
acdd884a | 2089 | |
27af5eea TU |
2090 | tasklet_init(&engine->irq_tasklet, |
2091 | intel_lrc_irq_handler, (unsigned long)engine); | |
2092 | ||
0bc40be8 | 2093 | logical_ring_init_platform_invariants(engine); |
ca82580c | 2094 | |
0bc40be8 | 2095 | ret = i915_cmd_parser_init_ring(engine); |
48d82387 | 2096 | if (ret) |
b0366a54 | 2097 | goto error; |
48d82387 | 2098 | |
0bc40be8 | 2099 | ret = intel_lr_context_deferred_alloc(dctx, engine); |
e84fe803 | 2100 | if (ret) |
b0366a54 | 2101 | goto error; |
e84fe803 NH |
2102 | |
2103 | /* As this is the default context, always pin it */ | |
0bc40be8 | 2104 | ret = intel_lr_context_do_pin(dctx, engine); |
e84fe803 NH |
2105 | if (ret) { |
2106 | DRM_ERROR( | |
2107 | "Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2108 | engine->name, ret); |
b0366a54 | 2109 | goto error; |
e84fe803 | 2110 | } |
564ddb2f | 2111 | |
b0366a54 DG |
2112 | return 0; |
2113 | ||
2114 | error: | |
0bc40be8 | 2115 | intel_logical_ring_cleanup(engine); |
564ddb2f | 2116 | return ret; |
454afebd OM |
2117 | } |
2118 | ||
2119 | static int logical_render_ring_init(struct drm_device *dev) | |
2120 | { | |
2121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2122 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
99be1dfe | 2123 | int ret; |
454afebd | 2124 | |
e2f80391 TU |
2125 | engine->name = "render ring"; |
2126 | engine->id = RCS; | |
2127 | engine->exec_id = I915_EXEC_RENDER; | |
2128 | engine->guc_id = GUC_RENDER_ENGINE; | |
2129 | engine->mmio_base = RENDER_RING_BASE; | |
d9f3af96 | 2130 | |
e2f80391 | 2131 | logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT); |
73d477f6 | 2132 | if (HAS_L3_DPF(dev)) |
e2f80391 | 2133 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
454afebd | 2134 | |
e2f80391 | 2135 | logical_ring_default_vfuncs(dev, engine); |
c9cacf93 TU |
2136 | |
2137 | /* Override some for render ring. */ | |
82ef822e | 2138 | if (INTEL_INFO(dev)->gen >= 9) |
e2f80391 | 2139 | engine->init_hw = gen9_init_render_ring; |
82ef822e | 2140 | else |
e2f80391 TU |
2141 | engine->init_hw = gen8_init_render_ring; |
2142 | engine->init_context = gen8_init_rcs_context; | |
2143 | engine->cleanup = intel_fini_pipe_control; | |
2144 | engine->emit_flush = gen8_emit_flush_render; | |
2145 | engine->emit_request = gen8_emit_request_render; | |
9b1136d5 | 2146 | |
e2f80391 | 2147 | engine->dev = dev; |
c4db7599 | 2148 | |
e2f80391 | 2149 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2150 | if (ret) |
2151 | return ret; | |
2152 | ||
e2f80391 | 2153 | ret = intel_init_workaround_bb(engine); |
17ee950d AS |
2154 | if (ret) { |
2155 | /* | |
2156 | * We continue even if we fail to initialize WA batch | |
2157 | * because we only expect rare glitches but nothing | |
2158 | * critical to prevent us from using GPU | |
2159 | */ | |
2160 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2161 | ret); | |
2162 | } | |
2163 | ||
e2f80391 | 2164 | ret = logical_ring_init(dev, engine); |
c4db7599 | 2165 | if (ret) { |
e2f80391 | 2166 | lrc_destroy_wa_ctx_obj(engine); |
c4db7599 | 2167 | } |
17ee950d AS |
2168 | |
2169 | return ret; | |
454afebd OM |
2170 | } |
2171 | ||
2172 | static int logical_bsd_ring_init(struct drm_device *dev) | |
2173 | { | |
2174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2175 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
454afebd | 2176 | |
e2f80391 TU |
2177 | engine->name = "bsd ring"; |
2178 | engine->id = VCS; | |
2179 | engine->exec_id = I915_EXEC_BSD; | |
2180 | engine->guc_id = GUC_VIDEO_ENGINE; | |
2181 | engine->mmio_base = GEN6_BSD_RING_BASE; | |
454afebd | 2182 | |
e2f80391 TU |
2183 | logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT); |
2184 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2185 | |
e2f80391 | 2186 | return logical_ring_init(dev, engine); |
454afebd OM |
2187 | } |
2188 | ||
2189 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
2190 | { | |
2191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2192 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
454afebd | 2193 | |
e2f80391 TU |
2194 | engine->name = "bsd2 ring"; |
2195 | engine->id = VCS2; | |
2196 | engine->exec_id = I915_EXEC_BSD; | |
2197 | engine->guc_id = GUC_VIDEO_ENGINE2; | |
2198 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
454afebd | 2199 | |
e2f80391 TU |
2200 | logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT); |
2201 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2202 | |
e2f80391 | 2203 | return logical_ring_init(dev, engine); |
454afebd OM |
2204 | } |
2205 | ||
2206 | static int logical_blt_ring_init(struct drm_device *dev) | |
2207 | { | |
2208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2209 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
454afebd | 2210 | |
e2f80391 TU |
2211 | engine->name = "blitter ring"; |
2212 | engine->id = BCS; | |
2213 | engine->exec_id = I915_EXEC_BLT; | |
2214 | engine->guc_id = GUC_BLITTER_ENGINE; | |
2215 | engine->mmio_base = BLT_RING_BASE; | |
454afebd | 2216 | |
e2f80391 TU |
2217 | logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT); |
2218 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2219 | |
e2f80391 | 2220 | return logical_ring_init(dev, engine); |
454afebd OM |
2221 | } |
2222 | ||
2223 | static int logical_vebox_ring_init(struct drm_device *dev) | |
2224 | { | |
2225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2226 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
454afebd | 2227 | |
e2f80391 TU |
2228 | engine->name = "video enhancement ring"; |
2229 | engine->id = VECS; | |
2230 | engine->exec_id = I915_EXEC_VEBOX; | |
2231 | engine->guc_id = GUC_VIDEOENHANCE_ENGINE; | |
2232 | engine->mmio_base = VEBOX_RING_BASE; | |
454afebd | 2233 | |
e2f80391 TU |
2234 | logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT); |
2235 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2236 | |
e2f80391 | 2237 | return logical_ring_init(dev, engine); |
454afebd OM |
2238 | } |
2239 | ||
73e4d07f OM |
2240 | /** |
2241 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2242 | * @dev: DRM device. | |
2243 | * | |
2244 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
117897f4 | 2245 | * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for |
73e4d07f OM |
2246 | * those engines that are present in the hardware. |
2247 | * | |
2248 | * Return: non-zero if the initialization failed. | |
2249 | */ | |
454afebd OM |
2250 | int intel_logical_rings_init(struct drm_device *dev) |
2251 | { | |
2252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2253 | int ret; | |
2254 | ||
2255 | ret = logical_render_ring_init(dev); | |
2256 | if (ret) | |
2257 | return ret; | |
2258 | ||
2259 | if (HAS_BSD(dev)) { | |
2260 | ret = logical_bsd_ring_init(dev); | |
2261 | if (ret) | |
2262 | goto cleanup_render_ring; | |
2263 | } | |
2264 | ||
2265 | if (HAS_BLT(dev)) { | |
2266 | ret = logical_blt_ring_init(dev); | |
2267 | if (ret) | |
2268 | goto cleanup_bsd_ring; | |
2269 | } | |
2270 | ||
2271 | if (HAS_VEBOX(dev)) { | |
2272 | ret = logical_vebox_ring_init(dev); | |
2273 | if (ret) | |
2274 | goto cleanup_blt_ring; | |
2275 | } | |
2276 | ||
2277 | if (HAS_BSD2(dev)) { | |
2278 | ret = logical_bsd2_ring_init(dev); | |
2279 | if (ret) | |
2280 | goto cleanup_vebox_ring; | |
2281 | } | |
2282 | ||
454afebd OM |
2283 | return 0; |
2284 | ||
454afebd | 2285 | cleanup_vebox_ring: |
4a570db5 | 2286 | intel_logical_ring_cleanup(&dev_priv->engine[VECS]); |
454afebd | 2287 | cleanup_blt_ring: |
4a570db5 | 2288 | intel_logical_ring_cleanup(&dev_priv->engine[BCS]); |
454afebd | 2289 | cleanup_bsd_ring: |
4a570db5 | 2290 | intel_logical_ring_cleanup(&dev_priv->engine[VCS]); |
454afebd | 2291 | cleanup_render_ring: |
4a570db5 | 2292 | intel_logical_ring_cleanup(&dev_priv->engine[RCS]); |
454afebd OM |
2293 | |
2294 | return ret; | |
2295 | } | |
2296 | ||
0cea6502 JM |
2297 | static u32 |
2298 | make_rpcs(struct drm_device *dev) | |
2299 | { | |
2300 | u32 rpcs = 0; | |
2301 | ||
2302 | /* | |
2303 | * No explicit RPCS request is needed to ensure full | |
2304 | * slice/subslice/EU enablement prior to Gen9. | |
2305 | */ | |
2306 | if (INTEL_INFO(dev)->gen < 9) | |
2307 | return 0; | |
2308 | ||
2309 | /* | |
2310 | * Starting in Gen9, render power gating can leave | |
2311 | * slice/subslice/EU in a partially enabled state. We | |
2312 | * must make an explicit request through RPCS for full | |
2313 | * enablement. | |
2314 | */ | |
2315 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2316 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2317 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2318 | GEN8_RPCS_S_CNT_SHIFT; | |
2319 | rpcs |= GEN8_RPCS_ENABLE; | |
2320 | } | |
2321 | ||
2322 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2323 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2324 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2325 | GEN8_RPCS_SS_CNT_SHIFT; | |
2326 | rpcs |= GEN8_RPCS_ENABLE; | |
2327 | } | |
2328 | ||
2329 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2330 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2331 | GEN8_RPCS_EU_MIN_SHIFT; | |
2332 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2333 | GEN8_RPCS_EU_MAX_SHIFT; | |
2334 | rpcs |= GEN8_RPCS_ENABLE; | |
2335 | } | |
2336 | ||
2337 | return rpcs; | |
2338 | } | |
2339 | ||
0bc40be8 | 2340 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2341 | { |
2342 | u32 indirect_ctx_offset; | |
2343 | ||
0bc40be8 | 2344 | switch (INTEL_INFO(engine->dev)->gen) { |
71562919 | 2345 | default: |
0bc40be8 | 2346 | MISSING_CASE(INTEL_INFO(engine->dev)->gen); |
71562919 MT |
2347 | /* fall through */ |
2348 | case 9: | |
2349 | indirect_ctx_offset = | |
2350 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2351 | break; | |
2352 | case 8: | |
2353 | indirect_ctx_offset = | |
2354 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2355 | break; | |
2356 | } | |
2357 | ||
2358 | return indirect_ctx_offset; | |
2359 | } | |
2360 | ||
8670d6f9 OM |
2361 | static int |
2362 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
0bc40be8 TU |
2363 | struct intel_engine_cs *engine, |
2364 | struct intel_ringbuffer *ringbuf) | |
8670d6f9 | 2365 | { |
0bc40be8 | 2366 | struct drm_device *dev = engine->dev; |
2d965536 | 2367 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae6c4806 | 2368 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2369 | struct page *page; |
2370 | uint32_t *reg_state; | |
2371 | int ret; | |
2372 | ||
2d965536 TD |
2373 | if (!ppgtt) |
2374 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2375 | ||
8670d6f9 OM |
2376 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2377 | if (ret) { | |
2378 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2379 | return ret; | |
2380 | } | |
2381 | ||
2382 | ret = i915_gem_object_get_pages(ctx_obj); | |
2383 | if (ret) { | |
2384 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2385 | return ret; | |
2386 | } | |
2387 | ||
2388 | i915_gem_object_pin_pages(ctx_obj); | |
2389 | ||
2390 | /* The second page of the context object contains some fields which must | |
2391 | * be set up prior to the first execution. */ | |
033908ae | 2392 | page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
8670d6f9 OM |
2393 | reg_state = kmap_atomic(page); |
2394 | ||
2395 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2396 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2397 | * only for the first context restore: on a subsequent save, the GPU will | |
2398 | * recreate this batchbuffer with new values (including all the missing | |
2399 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 2400 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
2401 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
2402 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
2403 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
2404 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
2405 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
99cf8ea1 MT |
2406 | (HAS_RESOURCE_STREAMER(dev) ? |
2407 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
0bc40be8 TU |
2408 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
2409 | 0); | |
2410 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
2411 | 0); | |
7ba717cf TD |
2412 | /* Ring buffer start address is not known until the buffer is pinned. |
2413 | * It is written to the context image in execlists_update_context() | |
2414 | */ | |
0bc40be8 TU |
2415 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
2416 | RING_START(engine->mmio_base), 0); | |
2417 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2418 | RING_CTL(engine->mmio_base), | |
0d925ea0 | 2419 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
2420 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2421 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2422 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2423 | RING_BBADDR(engine->mmio_base), 0); | |
2424 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2425 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2426 | RING_BB_PPGTT); |
0bc40be8 TU |
2427 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2428 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2429 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2430 | RING_SBBADDR(engine->mmio_base), 0); | |
2431 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2432 | RING_SBBSTATE(engine->mmio_base), 0); | |
2433 | if (engine->id == RCS) { | |
2434 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2435 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2436 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2437 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2438 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2439 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
2440 | if (engine->wa_ctx.obj) { | |
2441 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; | |
17ee950d AS |
2442 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
2443 | ||
2444 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2445 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2446 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2447 | ||
2448 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2449 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2450 | |
2451 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2452 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2453 | 0x01; | |
2454 | } | |
8670d6f9 | 2455 | } |
0d925ea0 | 2456 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2457 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2458 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2459 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2460 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2461 | 0); | |
2462 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2463 | 0); | |
2464 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2465 | 0); | |
2466 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2467 | 0); | |
2468 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2469 | 0); | |
2470 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2471 | 0); | |
2472 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2473 | 0); | |
2474 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2475 | 0); | |
d7b2633d | 2476 | |
2dba3239 MT |
2477 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2478 | /* 64b PPGTT (48bit canonical) | |
2479 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2480 | * other PDP Descriptors are ignored. | |
2481 | */ | |
2482 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2483 | } else { | |
2484 | /* 32b PPGTT | |
2485 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2486 | * With dynamic page allocation, PDPs may not be allocated at | |
2487 | * this point. Point the unallocated PDPs to the scratch page | |
2488 | */ | |
c6a2ac71 | 2489 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2490 | } |
2491 | ||
0bc40be8 | 2492 | if (engine->id == RCS) { |
8670d6f9 | 2493 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 VS |
2494 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
2495 | make_rpcs(dev)); | |
8670d6f9 OM |
2496 | } |
2497 | ||
2498 | kunmap_atomic(reg_state); | |
8670d6f9 OM |
2499 | i915_gem_object_unpin_pages(ctx_obj); |
2500 | ||
2501 | return 0; | |
2502 | } | |
2503 | ||
73e4d07f OM |
2504 | /** |
2505 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2506 | * @ctx: the LR context to free. | |
2507 | * | |
2508 | * The real context freeing is done in i915_gem_context_free: this only | |
2509 | * takes care of the bits that are LRC related: the per-engine backing | |
2510 | * objects and the logical ringbuffer. | |
2511 | */ | |
ede7d42b OM |
2512 | void intel_lr_context_free(struct intel_context *ctx) |
2513 | { | |
8c857917 OM |
2514 | int i; |
2515 | ||
666796da | 2516 | for (i = I915_NUM_ENGINES; --i >= 0; ) { |
e28e404c | 2517 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
8c857917 | 2518 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
84c2377f | 2519 | |
e28e404c DG |
2520 | if (!ctx_obj) |
2521 | continue; | |
dcb4c12a | 2522 | |
e28e404c DG |
2523 | if (ctx == ctx->i915->kernel_context) { |
2524 | intel_unpin_ringbuffer_obj(ringbuf); | |
2525 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8c857917 | 2526 | } |
e28e404c DG |
2527 | |
2528 | WARN_ON(ctx->engine[i].pin_count); | |
2529 | intel_ringbuffer_free(ringbuf); | |
2530 | drm_gem_object_unreference(&ctx_obj->base); | |
8c857917 OM |
2531 | } |
2532 | } | |
2533 | ||
c5d46ee2 DG |
2534 | /** |
2535 | * intel_lr_context_size() - return the size of the context for an engine | |
2536 | * @ring: which engine to find the context size for | |
2537 | * | |
2538 | * Each engine may require a different amount of space for a context image, | |
2539 | * so when allocating (or copying) an image, this function can be used to | |
2540 | * find the right size for the specific engine. | |
2541 | * | |
2542 | * Return: size (in bytes) of an engine-specific context image | |
2543 | * | |
2544 | * Note: this size includes the HWSP, which is part of the context image | |
2545 | * in LRC mode, but does not include the "shared data page" used with | |
2546 | * GuC submission. The caller should account for this if using the GuC. | |
2547 | */ | |
0bc40be8 | 2548 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2549 | { |
2550 | int ret = 0; | |
2551 | ||
0bc40be8 | 2552 | WARN_ON(INTEL_INFO(engine->dev)->gen < 8); |
8c857917 | 2553 | |
0bc40be8 | 2554 | switch (engine->id) { |
8c857917 | 2555 | case RCS: |
0bc40be8 | 2556 | if (INTEL_INFO(engine->dev)->gen >= 9) |
468c6816 MN |
2557 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2558 | else | |
2559 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2560 | break; |
2561 | case VCS: | |
2562 | case BCS: | |
2563 | case VECS: | |
2564 | case VCS2: | |
2565 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2566 | break; | |
2567 | } | |
2568 | ||
2569 | return ret; | |
ede7d42b OM |
2570 | } |
2571 | ||
0bc40be8 TU |
2572 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, |
2573 | struct drm_i915_gem_object *default_ctx_obj) | |
1df06b75 | 2574 | { |
0bc40be8 | 2575 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
d1675198 | 2576 | struct page *page; |
1df06b75 | 2577 | |
d1675198 | 2578 | /* The HWSP is part of the default context object in LRC mode. */ |
0bc40be8 | 2579 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) |
d1675198 AD |
2580 | + LRC_PPHWSP_PN * PAGE_SIZE; |
2581 | page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); | |
0bc40be8 TU |
2582 | engine->status_page.page_addr = kmap(page); |
2583 | engine->status_page.obj = default_ctx_obj; | |
1df06b75 | 2584 | |
0bc40be8 TU |
2585 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
2586 | (u32)engine->status_page.gfx_addr); | |
2587 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
1df06b75 TD |
2588 | } |
2589 | ||
73e4d07f | 2590 | /** |
e84fe803 | 2591 | * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
73e4d07f OM |
2592 | * @ctx: LR context to create. |
2593 | * @ring: engine to be used with the context. | |
2594 | * | |
2595 | * This function can be called more than once, with different engines, if we plan | |
2596 | * to use the context with them. The context backing objects and the ringbuffers | |
2597 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2598 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2599 | * a given ring with the context. | |
2600 | * | |
32197aab | 2601 | * Return: non-zero on error. |
73e4d07f | 2602 | */ |
e84fe803 NH |
2603 | |
2604 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, | |
0bc40be8 | 2605 | struct intel_engine_cs *engine) |
ede7d42b | 2606 | { |
0bc40be8 | 2607 | struct drm_device *dev = engine->dev; |
8c857917 OM |
2608 | struct drm_i915_gem_object *ctx_obj; |
2609 | uint32_t context_size; | |
84c2377f | 2610 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2611 | int ret; |
2612 | ||
ede7d42b | 2613 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
0bc40be8 | 2614 | WARN_ON(ctx->engine[engine->id].state); |
ede7d42b | 2615 | |
0bc40be8 | 2616 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2617 | |
d1675198 AD |
2618 | /* One extra page as the sharing data between driver and GuC */ |
2619 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2620 | ||
149c86e7 | 2621 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2622 | if (!ctx_obj) { |
2623 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2624 | return -ENOMEM; | |
8c857917 OM |
2625 | } |
2626 | ||
0bc40be8 | 2627 | ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE); |
01101fa7 CW |
2628 | if (IS_ERR(ringbuf)) { |
2629 | ret = PTR_ERR(ringbuf); | |
e84fe803 | 2630 | goto error_deref_obj; |
8670d6f9 OM |
2631 | } |
2632 | ||
0bc40be8 | 2633 | ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf); |
8670d6f9 OM |
2634 | if (ret) { |
2635 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
e84fe803 | 2636 | goto error_ringbuf; |
84c2377f OM |
2637 | } |
2638 | ||
0bc40be8 TU |
2639 | ctx->engine[engine->id].ringbuf = ringbuf; |
2640 | ctx->engine[engine->id].state = ctx_obj; | |
ede7d42b | 2641 | |
0bc40be8 | 2642 | if (ctx != ctx->i915->kernel_context && engine->init_context) { |
e84fe803 | 2643 | struct drm_i915_gem_request *req; |
76c39168 | 2644 | |
0bc40be8 | 2645 | req = i915_gem_request_alloc(engine, ctx); |
26827088 DG |
2646 | if (IS_ERR(req)) { |
2647 | ret = PTR_ERR(req); | |
2648 | DRM_ERROR("ring create req: %d\n", ret); | |
e84fe803 | 2649 | goto error_ringbuf; |
771b9a53 MT |
2650 | } |
2651 | ||
0bc40be8 | 2652 | ret = engine->init_context(req); |
e84fe803 NH |
2653 | if (ret) { |
2654 | DRM_ERROR("ring init context: %d\n", | |
2655 | ret); | |
2656 | i915_gem_request_cancel(req); | |
2657 | goto error_ringbuf; | |
2658 | } | |
2659 | i915_add_request_no_flush(req); | |
564ddb2f | 2660 | } |
ede7d42b | 2661 | return 0; |
8670d6f9 | 2662 | |
01101fa7 CW |
2663 | error_ringbuf: |
2664 | intel_ringbuffer_free(ringbuf); | |
e84fe803 | 2665 | error_deref_obj: |
8670d6f9 | 2666 | drm_gem_object_unreference(&ctx_obj->base); |
0bc40be8 TU |
2667 | ctx->engine[engine->id].ringbuf = NULL; |
2668 | ctx->engine[engine->id].state = NULL; | |
8670d6f9 | 2669 | return ret; |
ede7d42b | 2670 | } |
3e5b6f05 TD |
2671 | |
2672 | void intel_lr_context_reset(struct drm_device *dev, | |
2673 | struct intel_context *ctx) | |
2674 | { | |
2675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2676 | struct intel_engine_cs *engine; |
3e5b6f05 | 2677 | |
b4ac5afc | 2678 | for_each_engine(engine, dev_priv) { |
3e5b6f05 | 2679 | struct drm_i915_gem_object *ctx_obj = |
e2f80391 | 2680 | ctx->engine[engine->id].state; |
3e5b6f05 | 2681 | struct intel_ringbuffer *ringbuf = |
e2f80391 | 2682 | ctx->engine[engine->id].ringbuf; |
3e5b6f05 TD |
2683 | uint32_t *reg_state; |
2684 | struct page *page; | |
2685 | ||
2686 | if (!ctx_obj) | |
2687 | continue; | |
2688 | ||
2689 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2690 | WARN(1, "Failed get_pages for context obj\n"); | |
2691 | continue; | |
2692 | } | |
033908ae | 2693 | page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
3e5b6f05 TD |
2694 | reg_state = kmap_atomic(page); |
2695 | ||
2696 | reg_state[CTX_RING_HEAD+1] = 0; | |
2697 | reg_state[CTX_RING_TAIL+1] = 0; | |
2698 | ||
2699 | kunmap_atomic(reg_state); | |
2700 | ||
2701 | ringbuf->head = 0; | |
2702 | ringbuf->tail = 0; | |
2703 | } | |
2704 | } |