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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
3bbaba0c | 138 | #include "intel_mocs.h" |
127f1003 | 139 | |
468c6816 | 140 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
141 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
142 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
143 | ||
e981e7b1 TD |
144 | #define RING_EXECLIST_QFULL (1 << 0x2) |
145 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
146 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
147 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
148 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
149 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
150 | ||
151 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
152 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
153 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
154 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
155 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
156 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
157 | |
158 | #define CTX_LRI_HEADER_0 0x01 | |
159 | #define CTX_CONTEXT_CONTROL 0x02 | |
160 | #define CTX_RING_HEAD 0x04 | |
161 | #define CTX_RING_TAIL 0x06 | |
162 | #define CTX_RING_BUFFER_START 0x08 | |
163 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
164 | #define CTX_BB_HEAD_U 0x0c | |
165 | #define CTX_BB_HEAD_L 0x0e | |
166 | #define CTX_BB_STATE 0x10 | |
167 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
168 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
169 | #define CTX_SECOND_BB_STATE 0x16 | |
170 | #define CTX_BB_PER_CTX_PTR 0x18 | |
171 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
172 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
173 | #define CTX_LRI_HEADER_1 0x21 | |
174 | #define CTX_CTX_TIMESTAMP 0x22 | |
175 | #define CTX_PDP3_UDW 0x24 | |
176 | #define CTX_PDP3_LDW 0x26 | |
177 | #define CTX_PDP2_UDW 0x28 | |
178 | #define CTX_PDP2_LDW 0x2a | |
179 | #define CTX_PDP1_UDW 0x2c | |
180 | #define CTX_PDP1_LDW 0x2e | |
181 | #define CTX_PDP0_UDW 0x30 | |
182 | #define CTX_PDP0_LDW 0x32 | |
183 | #define CTX_LRI_HEADER_2 0x41 | |
184 | #define CTX_R_PWR_CLK_STATE 0x42 | |
185 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
186 | ||
84b790f8 BW |
187 | #define GEN8_CTX_VALID (1<<0) |
188 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
189 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
190 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
191 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
192 | |
193 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d852c7bf | 194 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
195 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
196 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
197 | } | |
198 | ||
2dba3239 MT |
199 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \ |
200 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ | |
201 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
202 | } | |
203 | ||
84b790f8 BW |
204 | enum { |
205 | ADVANCED_CONTEXT = 0, | |
2dba3239 | 206 | LEGACY_32B_CONTEXT, |
84b790f8 BW |
207 | ADVANCED_AD_CONTEXT, |
208 | LEGACY_64B_CONTEXT | |
209 | }; | |
2dba3239 MT |
210 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
211 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ | |
212 | LEGACY_64B_CONTEXT :\ | |
213 | LEGACY_32B_CONTEXT) | |
84b790f8 BW |
214 | enum { |
215 | FAULT_AND_HANG = 0, | |
216 | FAULT_AND_HALT, /* Debug only */ | |
217 | FAULT_AND_STREAM, | |
218 | FAULT_AND_CONTINUE /* Unsupported */ | |
219 | }; | |
220 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 221 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 222 | |
8ba319da | 223 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq); |
7ba717cf | 224 | |
73e4d07f OM |
225 | /** |
226 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
227 | * @dev: DRM device. | |
228 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
229 | * | |
230 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 231 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
232 | * |
233 | * Return: 1 if Execlists is supported and has to be enabled. | |
234 | */ | |
127f1003 OM |
235 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
236 | { | |
bd84b1e9 DV |
237 | WARN_ON(i915.enable_ppgtt == -1); |
238 | ||
a0bd6c31 ZL |
239 | /* On platforms with execlist available, vGPU will only |
240 | * support execlist mode, no ring buffer mode. | |
241 | */ | |
242 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) | |
243 | return 1; | |
244 | ||
70ee45e1 DL |
245 | if (INTEL_INFO(dev)->gen >= 9) |
246 | return 1; | |
247 | ||
127f1003 OM |
248 | if (enable_execlists == 0) |
249 | return 0; | |
250 | ||
14bf993e OM |
251 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
252 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
253 | return 1; |
254 | ||
255 | return 0; | |
256 | } | |
ede7d42b | 257 | |
73e4d07f OM |
258 | /** |
259 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
260 | * @ctx_obj: Logical Ring Context backing object. | |
261 | * | |
262 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
263 | * here: the old context ID we pass to userspace as a handler so that | |
264 | * they can refer to a context, and the new context ID we pass to the | |
265 | * ELSP so that the GPU can inform us of the context status via | |
266 | * interrupts. | |
267 | * | |
268 | * Return: 20-bits globally unique context ID. | |
269 | */ | |
84b790f8 BW |
270 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
271 | { | |
d1675198 AD |
272 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
273 | LRC_PPHWSP_PN * PAGE_SIZE; | |
84b790f8 BW |
274 | |
275 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
276 | * are globally unique */ | |
277 | return lrca >> 12; | |
278 | } | |
279 | ||
5af05fef MT |
280 | static bool disable_lite_restore_wa(struct intel_engine_cs *ring) |
281 | { | |
282 | struct drm_device *dev = ring->dev; | |
283 | ||
284 | return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || | |
285 | (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) && | |
286 | (ring->id == VCS || ring->id == VCS2); | |
287 | } | |
288 | ||
919f1f55 DG |
289 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
290 | struct intel_engine_cs *ring) | |
84b790f8 | 291 | { |
919f1f55 | 292 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
84b790f8 | 293 | uint64_t desc; |
d1675198 AD |
294 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
295 | LRC_PPHWSP_PN * PAGE_SIZE; | |
acdd884a MT |
296 | |
297 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
298 | |
299 | desc = GEN8_CTX_VALID; | |
2dba3239 | 300 | desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT; |
51847fb9 AS |
301 | if (IS_GEN8(ctx_obj->base.dev)) |
302 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
303 | desc |= GEN8_CTX_PRIVILEGE; |
304 | desc |= lrca; | |
305 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
306 | ||
307 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
308 | * signalling between Command Streamers */ | |
309 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
310 | ||
203a571b | 311 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
ec72d588 | 312 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ |
5af05fef | 313 | if (disable_lite_restore_wa(ring)) |
203a571b NH |
314 | desc |= GEN8_CTX_FORCE_RESTORE; |
315 | ||
84b790f8 BW |
316 | return desc; |
317 | } | |
318 | ||
cc3c4253 MK |
319 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
320 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 321 | { |
cc3c4253 MK |
322 | |
323 | struct intel_engine_cs *ring = rq0->ring; | |
6e7cc470 TU |
324 | struct drm_device *dev = ring->dev; |
325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1cff8cc3 | 326 | uint64_t desc[2]; |
84b790f8 | 327 | |
1cff8cc3 | 328 | if (rq1) { |
919f1f55 | 329 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring); |
1cff8cc3 MK |
330 | rq1->elsp_submitted++; |
331 | } else { | |
332 | desc[1] = 0; | |
333 | } | |
84b790f8 | 334 | |
919f1f55 | 335 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring); |
1cff8cc3 | 336 | rq0->elsp_submitted++; |
84b790f8 | 337 | |
1cff8cc3 | 338 | /* You must always write both descriptors in the order below. */ |
a6111f7b CW |
339 | spin_lock(&dev_priv->uncore.lock); |
340 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
1cff8cc3 MK |
341 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1])); |
342 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1])); | |
6daccb0b | 343 | |
1cff8cc3 | 344 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0])); |
84b790f8 | 345 | /* The context is automatically loaded after the following */ |
1cff8cc3 | 346 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0])); |
84b790f8 | 347 | |
1cff8cc3 | 348 | /* ELSP is a wo register, use another nearby reg for posting */ |
a6111f7b CW |
349 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
350 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
351 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
352 | } |
353 | ||
05d9824b | 354 | static int execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 355 | { |
05d9824b MK |
356 | struct intel_engine_cs *ring = rq->ring; |
357 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; | |
358 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
359 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; | |
ae1250b9 OM |
360 | struct page *page; |
361 | uint32_t *reg_state; | |
362 | ||
05d9824b MK |
363 | BUG_ON(!ctx_obj); |
364 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); | |
365 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); | |
366 | ||
d1675198 | 367 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
ae1250b9 OM |
368 | reg_state = kmap_atomic(page); |
369 | ||
05d9824b MK |
370 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
371 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); | |
ae1250b9 | 372 | |
2dba3239 MT |
373 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
374 | /* True 32b PPGTT with dynamic page allocation: update PDP | |
375 | * registers and point the unallocated PDPs to scratch page. | |
376 | * PML4 is allocated during ppgtt init, so this is not needed | |
377 | * in 48-bit mode. | |
378 | */ | |
d7b2633d MT |
379 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); |
380 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
381 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
382 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
383 | } | |
384 | ||
ae1250b9 OM |
385 | kunmap_atomic(reg_state); |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
d8cb8875 MK |
390 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
391 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 392 | { |
05d9824b | 393 | execlists_update_context(rq0); |
d8cb8875 | 394 | |
cc3c4253 | 395 | if (rq1) |
05d9824b | 396 | execlists_update_context(rq1); |
84b790f8 | 397 | |
cc3c4253 | 398 | execlists_elsp_write(rq0, rq1); |
84b790f8 BW |
399 | } |
400 | ||
acdd884a MT |
401 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
402 | { | |
6d3d8274 NH |
403 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
404 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
405 | |
406 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 407 | |
779949f4 PA |
408 | /* |
409 | * If irqs are not active generate a warning as batches that finish | |
410 | * without the irqs may get lost and a GPU Hang may occur. | |
411 | */ | |
412 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
413 | ||
acdd884a MT |
414 | if (list_empty(&ring->execlist_queue)) |
415 | return; | |
416 | ||
417 | /* Try to read in pairs */ | |
418 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
419 | execlist_link) { | |
420 | if (!req0) { | |
421 | req0 = cursor; | |
6d3d8274 | 422 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
423 | /* Same ctx: ignore first request, as second request |
424 | * will update tail past first request's workload */ | |
e1fee72c | 425 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 426 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
427 | list_add_tail(&req0->execlist_link, |
428 | &ring->execlist_retired_req_list); | |
acdd884a MT |
429 | req0 = cursor; |
430 | } else { | |
431 | req1 = cursor; | |
432 | break; | |
433 | } | |
434 | } | |
435 | ||
53292cdb MT |
436 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
437 | /* | |
438 | * WaIdleLiteRestore: make sure we never cause a lite | |
439 | * restore with HEAD==TAIL | |
440 | */ | |
d63f820f | 441 | if (req0->elsp_submitted) { |
53292cdb MT |
442 | /* |
443 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
444 | * as we resubmit the request. See gen8_emit_request() | |
445 | * for where we prepare the padding after the end of the | |
446 | * request. | |
447 | */ | |
448 | struct intel_ringbuffer *ringbuf; | |
449 | ||
450 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
451 | req0->tail += 8; | |
452 | req0->tail &= ringbuf->size - 1; | |
453 | } | |
454 | } | |
455 | ||
e1fee72c OM |
456 | WARN_ON(req1 && req1->elsp_submitted); |
457 | ||
d8cb8875 | 458 | execlists_submit_requests(req0, req1); |
acdd884a MT |
459 | } |
460 | ||
e981e7b1 TD |
461 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
462 | u32 request_id) | |
463 | { | |
6d3d8274 | 464 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
465 | |
466 | assert_spin_locked(&ring->execlist_lock); | |
467 | ||
468 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 469 | struct drm_i915_gem_request, |
e981e7b1 TD |
470 | execlist_link); |
471 | ||
472 | if (head_req != NULL) { | |
473 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 474 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 475 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
476 | WARN(head_req->elsp_submitted == 0, |
477 | "Never submitted head request\n"); | |
478 | ||
479 | if (--head_req->elsp_submitted <= 0) { | |
480 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
481 | list_add_tail(&head_req->execlist_link, |
482 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
483 | return true; |
484 | } | |
e981e7b1 TD |
485 | } |
486 | } | |
487 | ||
488 | return false; | |
489 | } | |
490 | ||
73e4d07f | 491 | /** |
3f7531c3 | 492 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
493 | * @ring: Engine Command Streamer to handle. |
494 | * | |
495 | * Check the unread Context Status Buffers and manage the submission of new | |
496 | * contexts to the ELSP accordingly. | |
497 | */ | |
3f7531c3 | 498 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
499 | { |
500 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
501 | u32 status_pointer; | |
502 | u8 read_pointer; | |
503 | u8 write_pointer; | |
5af05fef | 504 | u32 status = 0; |
e981e7b1 TD |
505 | u32 status_id; |
506 | u32 submit_contexts = 0; | |
507 | ||
508 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
509 | ||
510 | read_pointer = ring->next_context_status_buffer; | |
511 | write_pointer = status_pointer & 0x07; | |
512 | if (read_pointer > write_pointer) | |
513 | write_pointer += 6; | |
514 | ||
515 | spin_lock(&ring->execlist_lock); | |
516 | ||
517 | while (read_pointer < write_pointer) { | |
518 | read_pointer++; | |
519 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
520 | (read_pointer % 6) * 8); | |
521 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
522 | (read_pointer % 6) * 8 + 4); | |
523 | ||
031a8936 MK |
524 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) |
525 | continue; | |
526 | ||
e1fee72c OM |
527 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
528 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
529 | if (execlists_check_remove_request(ring, status_id)) | |
530 | WARN(1, "Lite Restored request removed from queue\n"); | |
531 | } else | |
532 | WARN(1, "Preemption without Lite Restore\n"); | |
533 | } | |
534 | ||
535 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
536 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
537 | if (execlists_check_remove_request(ring, status_id)) |
538 | submit_contexts++; | |
539 | } | |
540 | } | |
541 | ||
5af05fef MT |
542 | if (disable_lite_restore_wa(ring)) { |
543 | /* Prevent a ctx to preempt itself */ | |
544 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) && | |
545 | (submit_contexts != 0)) | |
546 | execlists_context_unqueue(ring); | |
547 | } else if (submit_contexts != 0) { | |
e981e7b1 | 548 | execlists_context_unqueue(ring); |
5af05fef | 549 | } |
e981e7b1 TD |
550 | |
551 | spin_unlock(&ring->execlist_lock); | |
552 | ||
553 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
554 | ring->next_context_status_buffer = write_pointer % 6; | |
555 | ||
556 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
cc53699b | 557 | _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); |
e981e7b1 TD |
558 | } |
559 | ||
ae70797d | 560 | static int execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 561 | { |
ae70797d | 562 | struct intel_engine_cs *ring = request->ring; |
6d3d8274 | 563 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 564 | int num_elements = 0; |
acdd884a | 565 | |
ae70797d | 566 | if (request->ctx != ring->default_context) |
8ba319da | 567 | intel_lr_context_pin(request); |
9bb1af44 JH |
568 | |
569 | i915_gem_request_reference(request); | |
570 | ||
b5eba372 | 571 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 572 | |
f1ad5a1f OM |
573 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
574 | if (++num_elements > 2) | |
575 | break; | |
576 | ||
577 | if (num_elements > 2) { | |
6d3d8274 | 578 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
579 | |
580 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 581 | struct drm_i915_gem_request, |
f1ad5a1f OM |
582 | execlist_link); |
583 | ||
ae70797d | 584 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 585 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 586 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 587 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
588 | list_add_tail(&tail_req->execlist_link, |
589 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
590 | } |
591 | } | |
592 | ||
6d3d8274 | 593 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 594 | if (num_elements == 0) |
acdd884a MT |
595 | execlists_context_unqueue(ring); |
596 | ||
b5eba372 | 597 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
2f20055d | 602 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 603 | { |
2f20055d | 604 | struct intel_engine_cs *ring = req->ring; |
ba8b7ccb OM |
605 | uint32_t flush_domains; |
606 | int ret; | |
607 | ||
608 | flush_domains = 0; | |
609 | if (ring->gpu_caches_dirty) | |
610 | flush_domains = I915_GEM_GPU_DOMAINS; | |
611 | ||
7deb4d39 | 612 | ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
613 | if (ret) |
614 | return ret; | |
615 | ||
616 | ring->gpu_caches_dirty = false; | |
617 | return 0; | |
618 | } | |
619 | ||
535fbe82 | 620 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
621 | struct list_head *vmas) |
622 | { | |
535fbe82 | 623 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
ba8b7ccb OM |
624 | struct i915_vma *vma; |
625 | uint32_t flush_domains = 0; | |
626 | bool flush_chipset = false; | |
627 | int ret; | |
628 | ||
629 | list_for_each_entry(vma, vmas, exec_list) { | |
630 | struct drm_i915_gem_object *obj = vma->obj; | |
631 | ||
03ade511 | 632 | if (obj->active & other_rings) { |
91af127f | 633 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
634 | if (ret) |
635 | return ret; | |
636 | } | |
ba8b7ccb OM |
637 | |
638 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
639 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
640 | ||
641 | flush_domains |= obj->base.write_domain; | |
642 | } | |
643 | ||
644 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
645 | wmb(); | |
646 | ||
647 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
648 | * any residual writes from the previous batch. | |
649 | */ | |
2f20055d | 650 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
651 | } |
652 | ||
40e895ce | 653 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 654 | { |
bc0dce3f JH |
655 | int ret; |
656 | ||
f3cc01f0 MK |
657 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
658 | ||
40e895ce | 659 | if (request->ctx != request->ring->default_context) { |
8ba319da | 660 | ret = intel_lr_context_pin(request); |
6689cb2b | 661 | if (ret) |
bc0dce3f | 662 | return ret; |
bc0dce3f JH |
663 | } |
664 | ||
bc0dce3f JH |
665 | return 0; |
666 | } | |
667 | ||
ae70797d | 668 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 669 | int bytes) |
bc0dce3f | 670 | { |
ae70797d JH |
671 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
672 | struct intel_engine_cs *ring = req->ring; | |
673 | struct drm_i915_gem_request *target; | |
b4716185 CW |
674 | unsigned space; |
675 | int ret; | |
bc0dce3f JH |
676 | |
677 | if (intel_ring_space(ringbuf) >= bytes) | |
678 | return 0; | |
679 | ||
79bbcc29 JH |
680 | /* The whole point of reserving space is to not wait! */ |
681 | WARN_ON(ringbuf->reserved_in_use); | |
682 | ||
ae70797d | 683 | list_for_each_entry(target, &ring->request_list, list) { |
bc0dce3f JH |
684 | /* |
685 | * The request queue is per-engine, so can contain requests | |
686 | * from multiple ringbuffers. Here, we must ignore any that | |
687 | * aren't from the ringbuffer we're considering. | |
688 | */ | |
ae70797d | 689 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
690 | continue; |
691 | ||
692 | /* Would completion of this request free enough space? */ | |
ae70797d | 693 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
694 | ringbuf->size); |
695 | if (space >= bytes) | |
bc0dce3f | 696 | break; |
bc0dce3f JH |
697 | } |
698 | ||
ae70797d | 699 | if (WARN_ON(&target->list == &ring->request_list)) |
bc0dce3f JH |
700 | return -ENOSPC; |
701 | ||
ae70797d | 702 | ret = i915_wait_request(target); |
bc0dce3f JH |
703 | if (ret) |
704 | return ret; | |
705 | ||
b4716185 CW |
706 | ringbuf->space = space; |
707 | return 0; | |
bc0dce3f JH |
708 | } |
709 | ||
710 | /* | |
711 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 712 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
713 | * |
714 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
715 | * really happens during submission is that the context and current tail will be placed | |
716 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
717 | * point, the tail *inside* the context is updated and the ELSP written to. | |
718 | */ | |
719 | static void | |
ae70797d | 720 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 721 | { |
ae70797d | 722 | struct intel_engine_cs *ring = request->ring; |
d1675198 | 723 | struct drm_i915_private *dev_priv = request->i915; |
bc0dce3f | 724 | |
ae70797d | 725 | intel_logical_ring_advance(request->ringbuf); |
bc0dce3f | 726 | |
d1675198 AD |
727 | request->tail = request->ringbuf->tail; |
728 | ||
bc0dce3f JH |
729 | if (intel_ring_stopped(ring)) |
730 | return; | |
731 | ||
d1675198 AD |
732 | if (dev_priv->guc.execbuf_client) |
733 | i915_guc_submit(dev_priv->guc.execbuf_client, request); | |
734 | else | |
735 | execlists_context_queue(request); | |
bc0dce3f JH |
736 | } |
737 | ||
79bbcc29 | 738 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
739 | { |
740 | uint32_t __iomem *virt; | |
741 | int rem = ringbuf->size - ringbuf->tail; | |
742 | ||
bc0dce3f JH |
743 | virt = ringbuf->virtual_start + ringbuf->tail; |
744 | rem /= 4; | |
745 | while (rem--) | |
746 | iowrite32(MI_NOOP, virt++); | |
747 | ||
748 | ringbuf->tail = 0; | |
749 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
750 | } |
751 | ||
ae70797d | 752 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 753 | { |
ae70797d | 754 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
755 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
756 | int remain_actual = ringbuf->size - ringbuf->tail; | |
757 | int ret, total_bytes, wait_bytes = 0; | |
758 | bool need_wrap = false; | |
29b1b415 | 759 | |
79bbcc29 JH |
760 | if (ringbuf->reserved_in_use) |
761 | total_bytes = bytes; | |
762 | else | |
763 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 764 | |
79bbcc29 JH |
765 | if (unlikely(bytes > remain_usable)) { |
766 | /* | |
767 | * Not enough space for the basic request. So need to flush | |
768 | * out the remainder and then wait for base + reserved. | |
769 | */ | |
770 | wait_bytes = remain_actual + total_bytes; | |
771 | need_wrap = true; | |
772 | } else { | |
773 | if (unlikely(total_bytes > remain_usable)) { | |
774 | /* | |
775 | * The base request will fit but the reserved space | |
776 | * falls off the end. So only need to to wait for the | |
777 | * reserved size after flushing out the remainder. | |
778 | */ | |
779 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
780 | need_wrap = true; | |
781 | } else if (total_bytes > ringbuf->space) { | |
782 | /* No wrapping required, just waiting. */ | |
783 | wait_bytes = total_bytes; | |
29b1b415 | 784 | } |
bc0dce3f JH |
785 | } |
786 | ||
79bbcc29 JH |
787 | if (wait_bytes) { |
788 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
789 | if (unlikely(ret)) |
790 | return ret; | |
79bbcc29 JH |
791 | |
792 | if (need_wrap) | |
793 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
794 | } |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | /** | |
800 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
801 | * | |
4d616a29 | 802 | * @request: The request to start some new work for |
4d78c8dc | 803 | * @ctx: Logical ring context whose ringbuffer is being prepared. |
bc0dce3f JH |
804 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
805 | * | |
806 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
807 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
808 | * and also preallocates a request (every workload submission is still mediated through | |
809 | * requests, same as it did with legacy ringbuffer submission). | |
810 | * | |
811 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
812 | */ | |
3bbaba0c | 813 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
bc0dce3f | 814 | { |
4d616a29 | 815 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
816 | int ret; |
817 | ||
4d616a29 JH |
818 | WARN_ON(req == NULL); |
819 | dev_priv = req->ring->dev->dev_private; | |
820 | ||
bc0dce3f JH |
821 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
822 | dev_priv->mm.interruptible); | |
823 | if (ret) | |
824 | return ret; | |
825 | ||
ae70797d | 826 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
827 | if (ret) |
828 | return ret; | |
829 | ||
4d616a29 | 830 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
831 | return 0; |
832 | } | |
833 | ||
ccd98fe4 JH |
834 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
835 | { | |
836 | /* | |
837 | * The first call merely notes the reserve request and is common for | |
838 | * all back ends. The subsequent localised _begin() call actually | |
839 | * ensures that the reservation is available. Without the begin, if | |
840 | * the request creator immediately submitted the request without | |
841 | * adding any commands to it then there might not actually be | |
842 | * sufficient room for the submission commands. | |
843 | */ | |
844 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
845 | ||
846 | return intel_logical_ring_begin(request, 0); | |
847 | } | |
848 | ||
73e4d07f OM |
849 | /** |
850 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
851 | * @dev: DRM device. | |
852 | * @file: DRM file. | |
853 | * @ring: Engine Command Streamer to submit to. | |
854 | * @ctx: Context to employ for this submission. | |
855 | * @args: execbuffer call arguments. | |
856 | * @vmas: list of vmas. | |
857 | * @batch_obj: the batchbuffer to submit. | |
858 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 859 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
860 | * |
861 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
862 | * away the submission details of the execbuffer ioctl call. | |
863 | * | |
864 | * Return: non-zero if the submission fails. | |
865 | */ | |
5f19e2bf | 866 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 867 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 868 | struct list_head *vmas) |
454afebd | 869 | { |
5f19e2bf JH |
870 | struct drm_device *dev = params->dev; |
871 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 872 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
873 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
874 | u64 exec_start; | |
ba8b7ccb OM |
875 | int instp_mode; |
876 | u32 instp_mask; | |
877 | int ret; | |
878 | ||
879 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
880 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
881 | switch (instp_mode) { | |
882 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
883 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
884 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
885 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
886 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
887 | return -EINVAL; | |
888 | } | |
889 | ||
890 | if (instp_mode != dev_priv->relative_constants_mode) { | |
891 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
892 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
893 | return -EINVAL; | |
894 | } | |
895 | ||
896 | /* The HW changed the meaning on this bit on gen6 */ | |
897 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
898 | } | |
899 | break; | |
900 | default: | |
901 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
902 | return -EINVAL; | |
903 | } | |
904 | ||
905 | if (args->num_cliprects != 0) { | |
906 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
907 | return -EINVAL; | |
908 | } else { | |
909 | if (args->DR4 == 0xffffffff) { | |
910 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
911 | args->DR4 = 0; | |
912 | } | |
913 | ||
914 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
915 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
916 | return -EINVAL; | |
917 | } | |
918 | } | |
919 | ||
920 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
921 | DRM_DEBUG("sol reset is gen7 only\n"); | |
922 | return -EINVAL; | |
923 | } | |
924 | ||
535fbe82 | 925 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
926 | if (ret) |
927 | return ret; | |
928 | ||
929 | if (ring == &dev_priv->ring[RCS] && | |
930 | instp_mode != dev_priv->relative_constants_mode) { | |
4d616a29 | 931 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
932 | if (ret) |
933 | return ret; | |
934 | ||
935 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
936 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
937 | intel_logical_ring_emit(ringbuf, INSTPM); | |
938 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
939 | intel_logical_ring_advance(ringbuf); | |
940 | ||
941 | dev_priv->relative_constants_mode = instp_mode; | |
942 | } | |
943 | ||
5f19e2bf JH |
944 | exec_start = params->batch_obj_vm_offset + |
945 | args->batch_start_offset; | |
946 | ||
be795fc1 | 947 | ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
948 | if (ret) |
949 | return ret; | |
950 | ||
95c24161 | 951 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 952 | |
8a8edb59 | 953 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 954 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 955 | |
454afebd OM |
956 | return 0; |
957 | } | |
958 | ||
c86ee3a9 TD |
959 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
960 | { | |
6d3d8274 | 961 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
962 | struct list_head retired_list; |
963 | ||
964 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
965 | if (list_empty(&ring->execlist_retired_req_list)) | |
966 | return; | |
967 | ||
968 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 969 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 970 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 971 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
972 | |
973 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 974 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
975 | struct drm_i915_gem_object *ctx_obj = |
976 | ctx->engine[ring->id].state; | |
977 | ||
978 | if (ctx_obj && (ctx != ring->default_context)) | |
8ba319da | 979 | intel_lr_context_unpin(req); |
c86ee3a9 | 980 | list_del(&req->execlist_link); |
f8210795 | 981 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
982 | } |
983 | } | |
984 | ||
454afebd OM |
985 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
986 | { | |
9832b9da OM |
987 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
988 | int ret; | |
989 | ||
990 | if (!intel_ring_initialized(ring)) | |
991 | return; | |
992 | ||
993 | ret = intel_ring_idle(ring); | |
994 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
995 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
996 | ring->name, ret); | |
997 | ||
998 | /* TODO: Is this correct with Execlists enabled? */ | |
999 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
1000 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
1001 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
1002 | return; | |
1003 | } | |
1004 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
1005 | } |
1006 | ||
4866d729 | 1007 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 1008 | { |
4866d729 | 1009 | struct intel_engine_cs *ring = req->ring; |
48e29f55 OM |
1010 | int ret; |
1011 | ||
1012 | if (!ring->gpu_caches_dirty) | |
1013 | return 0; | |
1014 | ||
7deb4d39 | 1015 | ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1016 | if (ret) |
1017 | return ret; | |
1018 | ||
1019 | ring->gpu_caches_dirty = false; | |
1020 | return 0; | |
1021 | } | |
1022 | ||
8ba319da | 1023 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq) |
dcb4c12a | 1024 | { |
d1675198 | 1025 | struct drm_i915_private *dev_priv = rq->i915; |
8ba319da MK |
1026 | struct intel_engine_cs *ring = rq->ring; |
1027 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
1028 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
dcb4c12a OM |
1029 | int ret = 0; |
1030 | ||
1031 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
8ba319da | 1032 | if (rq->ctx->engine[ring->id].pin_count++ == 0) { |
d1675198 AD |
1033 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
1034 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
dcb4c12a | 1035 | if (ret) |
a7cbedec | 1036 | goto reset_pin_count; |
7ba717cf TD |
1037 | |
1038 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); | |
1039 | if (ret) | |
1040 | goto unpin_ctx_obj; | |
d1675198 | 1041 | |
903ecd0b | 1042 | ctx_obj->dirty = true; |
e93c28f3 | 1043 | |
d1675198 AD |
1044 | /* Invalidate GuC TLB. */ |
1045 | if (i915.enable_guc_submission) | |
1046 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a OM |
1047 | } |
1048 | ||
7ba717cf TD |
1049 | return ret; |
1050 | ||
1051 | unpin_ctx_obj: | |
1052 | i915_gem_object_ggtt_unpin(ctx_obj); | |
a7cbedec | 1053 | reset_pin_count: |
8ba319da | 1054 | rq->ctx->engine[ring->id].pin_count = 0; |
7ba717cf | 1055 | |
dcb4c12a OM |
1056 | return ret; |
1057 | } | |
1058 | ||
8ba319da | 1059 | void intel_lr_context_unpin(struct drm_i915_gem_request *rq) |
dcb4c12a | 1060 | { |
8ba319da MK |
1061 | struct intel_engine_cs *ring = rq->ring; |
1062 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
1063 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
dcb4c12a OM |
1064 | |
1065 | if (ctx_obj) { | |
1066 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
8ba319da | 1067 | if (--rq->ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1068 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1069 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1070 | } |
dcb4c12a OM |
1071 | } |
1072 | } | |
1073 | ||
e2be4faf | 1074 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1075 | { |
1076 | int ret, i; | |
e2be4faf JH |
1077 | struct intel_engine_cs *ring = req->ring; |
1078 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
771b9a53 MT |
1079 | struct drm_device *dev = ring->dev; |
1080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1081 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1082 | ||
e6c1abb7 | 1083 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1084 | return 0; |
1085 | ||
1086 | ring->gpu_caches_dirty = true; | |
4866d729 | 1087 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1088 | if (ret) |
1089 | return ret; | |
1090 | ||
4d616a29 | 1091 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1092 | if (ret) |
1093 | return ret; | |
1094 | ||
1095 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1096 | for (i = 0; i < w->count; i++) { | |
1097 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1098 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1099 | } | |
1100 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1101 | ||
1102 | intel_logical_ring_advance(ringbuf); | |
1103 | ||
1104 | ring->gpu_caches_dirty = true; | |
4866d729 | 1105 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1106 | if (ret) |
1107 | return ret; | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
83b8a982 | 1112 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1113 | do { \ |
83b8a982 AS |
1114 | int __index = (index)++; \ |
1115 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1116 | return -ENOSPC; \ |
1117 | } \ | |
83b8a982 | 1118 | batch[__index] = (cmd); \ |
17ee950d AS |
1119 | } while (0) |
1120 | ||
9e000847 AS |
1121 | |
1122 | /* | |
1123 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1124 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1125 | * but there is a slight complication as this is applied in WA batch where the | |
1126 | * values are only initialized once so we cannot take register value at the | |
1127 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1128 | * constant value with bit21 set and then we restore it back with the saved value. | |
1129 | * To simplify the WA, a constant value is formed by using the default value | |
1130 | * of this register. This shouldn't be a problem because we are only modifying | |
1131 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1132 | * use additional instructions that read the actual value of the register | |
1133 | * at that time and set our bit of interest but it makes the WA complicated. | |
1134 | * | |
1135 | * This WA is also required for Gen9 so extracting as a function avoids | |
1136 | * code duplication. | |
1137 | */ | |
1138 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, | |
1139 | uint32_t *const batch, | |
1140 | uint32_t index) | |
1141 | { | |
1142 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1143 | ||
a4106a78 AS |
1144 | /* |
1145 | * WaDisableLSQCROPERFforOCL:skl | |
1146 | * This WA is implemented in skl_init_clock_gating() but since | |
1147 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1148 | * set this bit here to retain the WA during flush. | |
1149 | */ | |
1150 | if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) | |
1151 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; | |
1152 | ||
f1afe24f | 1153 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 AS |
1154 | MI_SRM_LRM_GLOBAL_GTT)); |
1155 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1156 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1157 | wa_ctx_emit(batch, index, 0); | |
1158 | ||
1159 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1160 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1161 | wa_ctx_emit(batch, index, l3sqc4_flush); | |
1162 | ||
1163 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1164 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1165 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1166 | wa_ctx_emit(batch, index, 0); | |
1167 | wa_ctx_emit(batch, index, 0); | |
1168 | wa_ctx_emit(batch, index, 0); | |
1169 | wa_ctx_emit(batch, index, 0); | |
1170 | ||
f1afe24f | 1171 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 AS |
1172 | MI_SRM_LRM_GLOBAL_GTT)); |
1173 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1174 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1175 | wa_ctx_emit(batch, index, 0); | |
9e000847 AS |
1176 | |
1177 | return index; | |
1178 | } | |
1179 | ||
17ee950d AS |
1180 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1181 | uint32_t offset, | |
1182 | uint32_t start_alignment) | |
1183 | { | |
1184 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1185 | } | |
1186 | ||
1187 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1188 | uint32_t offset, | |
1189 | uint32_t size_alignment) | |
1190 | { | |
1191 | wa_ctx->size = offset - wa_ctx->offset; | |
1192 | ||
1193 | WARN(wa_ctx->size % size_alignment, | |
1194 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1195 | wa_ctx->size, size_alignment); | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1201 | * | |
1202 | * @ring: only applicable for RCS | |
1203 | * @wa_ctx: structure representing wa_ctx | |
1204 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1205 | * with the offset value received as input. | |
1206 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1207 | * @batch: page in which WA are loaded | |
1208 | * @offset: This field specifies the start of the batch, it should be | |
1209 | * cache-aligned otherwise it is adjusted accordingly. | |
1210 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1211 | * initialized at the beginning and shared across all contexts but this field | |
1212 | * helps us to have multiple batches at different offsets and select them based | |
1213 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1214 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1215 | * | |
1216 | * The number of WA applied are not known at the beginning; we use this field | |
1217 | * to return the no of DWORDS written. | |
4d78c8dc | 1218 | * |
17ee950d AS |
1219 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1220 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1221 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1222 | * makes a complete batch buffer. | |
1223 | * | |
1224 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1225 | */ | |
1226 | ||
1227 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1228 | struct i915_wa_ctx_bb *wa_ctx, | |
1229 | uint32_t *const batch, | |
1230 | uint32_t *offset) | |
1231 | { | |
0160f055 | 1232 | uint32_t scratch_addr; |
17ee950d AS |
1233 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1234 | ||
7ad00d1a | 1235 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1236 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1237 | |
c82435bb AS |
1238 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1239 | if (IS_BROADWELL(ring->dev)) { | |
9e000847 AS |
1240 | index = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
1241 | if (index < 0) | |
1242 | return index; | |
c82435bb AS |
1243 | } |
1244 | ||
0160f055 AS |
1245 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1246 | /* Actual scratch location is at 128 bytes offset */ | |
1247 | scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; | |
1248 | ||
83b8a982 AS |
1249 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1250 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1251 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1252 | PIPE_CONTROL_CS_STALL | | |
1253 | PIPE_CONTROL_QW_WRITE)); | |
1254 | wa_ctx_emit(batch, index, scratch_addr); | |
1255 | wa_ctx_emit(batch, index, 0); | |
1256 | wa_ctx_emit(batch, index, 0); | |
1257 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1258 | |
17ee950d AS |
1259 | /* Pad to end of cacheline */ |
1260 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1261 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1262 | |
1263 | /* | |
1264 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1265 | * execution depends on the length specified in terms of cache lines | |
1266 | * in the register CTX_RCS_INDIRECT_CTX | |
1267 | */ | |
1268 | ||
1269 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1274 | * | |
1275 | * @ring: only applicable for RCS | |
1276 | * @wa_ctx: structure representing wa_ctx | |
1277 | * offset: specifies start of the batch, should be cache-aligned. | |
1278 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1279 | * @batch: page in which WA are loaded |
17ee950d AS |
1280 | * @offset: This field specifies the start of this batch. |
1281 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1282 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1283 | * | |
1284 | * The number of DWORDS written are returned using this field. | |
1285 | * | |
1286 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1287 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1288 | */ | |
1289 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1290 | struct i915_wa_ctx_bb *wa_ctx, | |
1291 | uint32_t *const batch, | |
1292 | uint32_t *offset) | |
1293 | { | |
1294 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1295 | ||
7ad00d1a | 1296 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1297 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1298 | |
83b8a982 | 1299 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1300 | |
1301 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1302 | } | |
1303 | ||
0504cffc AS |
1304 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, |
1305 | struct i915_wa_ctx_bb *wa_ctx, | |
1306 | uint32_t *const batch, | |
1307 | uint32_t *offset) | |
1308 | { | |
a4106a78 | 1309 | int ret; |
0907c8f7 | 1310 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1311 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1312 | ||
0907c8f7 AS |
1313 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1314 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1315 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1316 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
0504cffc | 1317 | |
a4106a78 AS |
1318 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
1319 | ret = gen8_emit_flush_coherentl3_wa(ring, batch, index); | |
1320 | if (ret < 0) | |
1321 | return ret; | |
1322 | index = ret; | |
1323 | ||
0504cffc AS |
1324 | /* Pad to end of cacheline */ |
1325 | while (index % CACHELINE_DWORDS) | |
1326 | wa_ctx_emit(batch, index, MI_NOOP); | |
1327 | ||
1328 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1329 | } | |
1330 | ||
1331 | static int gen9_init_perctx_bb(struct intel_engine_cs *ring, | |
1332 | struct i915_wa_ctx_bb *wa_ctx, | |
1333 | uint32_t *const batch, | |
1334 | uint32_t *offset) | |
1335 | { | |
0907c8f7 | 1336 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1337 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1338 | ||
9b01435d AS |
1339 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
1340 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || | |
1341 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { | |
1342 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1343 | wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); | |
1344 | wa_ctx_emit(batch, index, | |
1345 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1346 | wa_ctx_emit(batch, index, MI_NOOP); | |
1347 | } | |
1348 | ||
0907c8f7 AS |
1349 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1350 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1351 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1352 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1353 | ||
0504cffc AS |
1354 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1355 | ||
1356 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1357 | } | |
1358 | ||
17ee950d AS |
1359 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) |
1360 | { | |
1361 | int ret; | |
1362 | ||
1363 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1364 | if (!ring->wa_ctx.obj) { | |
1365 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1366 | return -ENOMEM; | |
1367 | } | |
1368 | ||
1369 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1370 | if (ret) { | |
1371 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1372 | ret); | |
1373 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1374 | return ret; | |
1375 | } | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1381 | { | |
1382 | if (ring->wa_ctx.obj) { | |
1383 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1384 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1385 | ring->wa_ctx.obj = NULL; | |
1386 | } | |
1387 | } | |
1388 | ||
1389 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1390 | { | |
1391 | int ret; | |
1392 | uint32_t *batch; | |
1393 | uint32_t offset; | |
1394 | struct page *page; | |
1395 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1396 | ||
1397 | WARN_ON(ring->id != RCS); | |
1398 | ||
5e60d790 | 1399 | /* update this when WA for higher Gen are added */ |
0504cffc AS |
1400 | if (INTEL_INFO(ring->dev)->gen > 9) { |
1401 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", | |
1402 | INTEL_INFO(ring->dev)->gen); | |
5e60d790 | 1403 | return 0; |
0504cffc | 1404 | } |
5e60d790 | 1405 | |
c4db7599 AS |
1406 | /* some WA perform writes to scratch page, ensure it is valid */ |
1407 | if (ring->scratch.obj == NULL) { | |
1408 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
17ee950d AS |
1412 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1413 | if (ret) { | |
1414 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1415 | return ret; | |
1416 | } | |
1417 | ||
1418 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1419 | batch = kmap_atomic(page); | |
1420 | offset = 0; | |
1421 | ||
1422 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1423 | ret = gen8_init_indirectctx_bb(ring, | |
1424 | &wa_ctx->indirect_ctx, | |
1425 | batch, | |
1426 | &offset); | |
1427 | if (ret) | |
1428 | goto out; | |
1429 | ||
1430 | ret = gen8_init_perctx_bb(ring, | |
1431 | &wa_ctx->per_ctx, | |
1432 | batch, | |
1433 | &offset); | |
1434 | if (ret) | |
1435 | goto out; | |
0504cffc AS |
1436 | } else if (INTEL_INFO(ring->dev)->gen == 9) { |
1437 | ret = gen9_init_indirectctx_bb(ring, | |
1438 | &wa_ctx->indirect_ctx, | |
1439 | batch, | |
1440 | &offset); | |
1441 | if (ret) | |
1442 | goto out; | |
1443 | ||
1444 | ret = gen9_init_perctx_bb(ring, | |
1445 | &wa_ctx->per_ctx, | |
1446 | batch, | |
1447 | &offset); | |
1448 | if (ret) | |
1449 | goto out; | |
17ee950d AS |
1450 | } |
1451 | ||
1452 | out: | |
1453 | kunmap_atomic(batch); | |
1454 | if (ret) | |
1455 | lrc_destroy_wa_ctx_obj(ring); | |
1456 | ||
1457 | return ret; | |
1458 | } | |
1459 | ||
9b1136d5 OM |
1460 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1461 | { | |
1462 | struct drm_device *dev = ring->dev; | |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1464 | ||
73d477f6 OM |
1465 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1466 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1467 | ||
2e5356da AS |
1468 | if (ring->status_page.obj) { |
1469 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
1470 | (u32)ring->status_page.gfx_addr); | |
1471 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1472 | } | |
1473 | ||
9b1136d5 OM |
1474 | I915_WRITE(RING_MODE_GEN7(ring), |
1475 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1476 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1477 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1478 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1479 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1480 | ||
1481 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1482 | ||
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1487 | { | |
1488 | struct drm_device *dev = ring->dev; | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | int ret; | |
1491 | ||
1492 | ret = gen8_init_common_ring(ring); | |
1493 | if (ret) | |
1494 | return ret; | |
1495 | ||
1496 | /* We need to disable the AsyncFlip performance optimisations in order | |
1497 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1498 | * programmed to '1' on all products. | |
1499 | * | |
1500 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1501 | */ | |
1502 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1503 | ||
9b1136d5 OM |
1504 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1505 | ||
771b9a53 | 1506 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1507 | } |
1508 | ||
82ef822e DL |
1509 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1510 | { | |
1511 | int ret; | |
1512 | ||
1513 | ret = gen8_init_common_ring(ring); | |
1514 | if (ret) | |
1515 | return ret; | |
1516 | ||
1517 | return init_workarounds_ring(ring); | |
1518 | } | |
1519 | ||
7a01a0a2 MT |
1520 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1521 | { | |
1522 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
1523 | struct intel_engine_cs *ring = req->ring; | |
1524 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
1525 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1526 | int i, ret; | |
1527 | ||
1528 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1529 | if (ret) | |
1530 | return ret; | |
1531 | ||
1532 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1533 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1534 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1535 | ||
1536 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); | |
1537 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); | |
1538 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); | |
1539 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); | |
1540 | } | |
1541 | ||
1542 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1543 | intel_logical_ring_advance(ringbuf); | |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
be795fc1 | 1548 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1549 | u64 offset, unsigned dispatch_flags) |
15648585 | 1550 | { |
be795fc1 | 1551 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1552 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1553 | int ret; |
1554 | ||
7a01a0a2 MT |
1555 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1556 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1557 | * but we can't. Force Restore would be a second option, but | |
1558 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1559 | * not idle). PML4 is allocated during ppgtt init so this is |
1560 | * not needed in 48-bit.*/ | |
7a01a0a2 MT |
1561 | if (req->ctx->ppgtt && |
1562 | (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { | |
331f38e7 ZL |
1563 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
1564 | !intel_vgpu_active(req->i915->dev)) { | |
2dba3239 MT |
1565 | ret = intel_logical_ring_emit_pdps(req); |
1566 | if (ret) | |
1567 | return ret; | |
1568 | } | |
7a01a0a2 MT |
1569 | |
1570 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); | |
1571 | } | |
1572 | ||
4d616a29 | 1573 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1574 | if (ret) |
1575 | return ret; | |
1576 | ||
1577 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1578 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1579 | (ppgtt<<8) | | |
1580 | (dispatch_flags & I915_DISPATCH_RS ? | |
1581 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1582 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1583 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1584 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1585 | intel_logical_ring_advance(ringbuf); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | ||
73d477f6 OM |
1590 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1591 | { | |
1592 | struct drm_device *dev = ring->dev; | |
1593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1594 | unsigned long flags; | |
1595 | ||
7cd512f1 | 1596 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1597 | return false; |
1598 | ||
1599 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1600 | if (ring->irq_refcount++ == 0) { | |
1601 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1602 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1603 | } | |
1604 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1605 | ||
1606 | return true; | |
1607 | } | |
1608 | ||
1609 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1610 | { | |
1611 | struct drm_device *dev = ring->dev; | |
1612 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1613 | unsigned long flags; | |
1614 | ||
1615 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1616 | if (--ring->irq_refcount == 0) { | |
1617 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1618 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1619 | } | |
1620 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1621 | } | |
1622 | ||
7deb4d39 | 1623 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1624 | u32 invalidate_domains, |
1625 | u32 unused) | |
1626 | { | |
7deb4d39 | 1627 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1628 | struct intel_engine_cs *ring = ringbuf->ring; |
1629 | struct drm_device *dev = ring->dev; | |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | uint32_t cmd; | |
1632 | int ret; | |
1633 | ||
4d616a29 | 1634 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1635 | if (ret) |
1636 | return ret; | |
1637 | ||
1638 | cmd = MI_FLUSH_DW + 1; | |
1639 | ||
f0a1fb10 CW |
1640 | /* We always require a command barrier so that subsequent |
1641 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1642 | * wrt the contents of the write cache being flushed to memory | |
1643 | * (and thus being coherent from the CPU). | |
1644 | */ | |
1645 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1646 | ||
1647 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1648 | cmd |= MI_INVALIDATE_TLB; | |
1649 | if (ring == &dev_priv->ring[VCS]) | |
1650 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1651 | } |
1652 | ||
1653 | intel_logical_ring_emit(ringbuf, cmd); | |
1654 | intel_logical_ring_emit(ringbuf, | |
1655 | I915_GEM_HWS_SCRATCH_ADDR | | |
1656 | MI_FLUSH_DW_USE_GTT); | |
1657 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1658 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1659 | intel_logical_ring_advance(ringbuf); | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
7deb4d39 | 1664 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1665 | u32 invalidate_domains, |
1666 | u32 flush_domains) | |
1667 | { | |
7deb4d39 | 1668 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1669 | struct intel_engine_cs *ring = ringbuf->ring; |
1670 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1671 | bool vf_flush_wa; |
4712274c OM |
1672 | u32 flags = 0; |
1673 | int ret; | |
1674 | ||
1675 | flags |= PIPE_CONTROL_CS_STALL; | |
1676 | ||
1677 | if (flush_domains) { | |
1678 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1679 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1680 | } | |
1681 | ||
1682 | if (invalidate_domains) { | |
1683 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1684 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1685 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1686 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1687 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1688 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1689 | flags |= PIPE_CONTROL_QW_WRITE; | |
1690 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1691 | } | |
1692 | ||
9647ff36 ID |
1693 | /* |
1694 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1695 | * control. | |
1696 | */ | |
1697 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1698 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1699 | ||
4d616a29 | 1700 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1701 | if (ret) |
1702 | return ret; | |
1703 | ||
9647ff36 ID |
1704 | if (vf_flush_wa) { |
1705 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1706 | intel_logical_ring_emit(ringbuf, 0); | |
1707 | intel_logical_ring_emit(ringbuf, 0); | |
1708 | intel_logical_ring_emit(ringbuf, 0); | |
1709 | intel_logical_ring_emit(ringbuf, 0); | |
1710 | intel_logical_ring_emit(ringbuf, 0); | |
1711 | } | |
1712 | ||
4712274c OM |
1713 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1714 | intel_logical_ring_emit(ringbuf, flags); | |
1715 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1716 | intel_logical_ring_emit(ringbuf, 0); | |
1717 | intel_logical_ring_emit(ringbuf, 0); | |
1718 | intel_logical_ring_emit(ringbuf, 0); | |
1719 | intel_logical_ring_advance(ringbuf); | |
1720 | ||
1721 | return 0; | |
1722 | } | |
1723 | ||
e94e37ad OM |
1724 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1725 | { | |
1726 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1727 | } | |
1728 | ||
1729 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1730 | { | |
1731 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1732 | } | |
1733 | ||
319404df ID |
1734 | static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1735 | { | |
1736 | ||
1737 | /* | |
1738 | * On BXT A steppings there is a HW coherency issue whereby the | |
1739 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1740 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1741 | * clflushing the corresponding cacheline whenever the caller wants | |
1742 | * the coherency to be guaranteed. Note that this cacheline is known | |
1743 | * to be clean at this point, since we only write it in | |
1744 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1745 | * this clflush in practice becomes an invalidate operation. | |
1746 | */ | |
1747 | ||
1748 | if (!lazy_coherency) | |
1749 | intel_flush_status_page(ring, I915_GEM_HWS_INDEX); | |
1750 | ||
1751 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1752 | } | |
1753 | ||
1754 | static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1755 | { | |
1756 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1757 | ||
1758 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ | |
1759 | intel_flush_status_page(ring, I915_GEM_HWS_INDEX); | |
1760 | } | |
1761 | ||
c4e76638 | 1762 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1763 | { |
c4e76638 | 1764 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1765 | struct intel_engine_cs *ring = ringbuf->ring; |
1766 | u32 cmd; | |
1767 | int ret; | |
1768 | ||
53292cdb MT |
1769 | /* |
1770 | * Reserve space for 2 NOOPs at the end of each request to be | |
1771 | * used as a workaround for not being allowed to do lite | |
1772 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1773 | */ | |
4d616a29 | 1774 | ret = intel_logical_ring_begin(request, 8); |
4da46e1e OM |
1775 | if (ret) |
1776 | return ret; | |
1777 | ||
8edfbb8b | 1778 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1779 | cmd |= MI_GLOBAL_GTT; |
1780 | ||
1781 | intel_logical_ring_emit(ringbuf, cmd); | |
1782 | intel_logical_ring_emit(ringbuf, | |
1783 | (ring->status_page.gfx_addr + | |
1784 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1785 | intel_logical_ring_emit(ringbuf, 0); | |
c4e76638 | 1786 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1787 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1788 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
ae70797d | 1789 | intel_logical_ring_advance_and_submit(request); |
4da46e1e | 1790 | |
53292cdb MT |
1791 | /* |
1792 | * Here we add two extra NOOPs as padding to avoid | |
1793 | * lite restore of a context with HEAD==TAIL. | |
1794 | */ | |
1795 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1796 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1797 | intel_logical_ring_advance(ringbuf); | |
1798 | ||
4da46e1e OM |
1799 | return 0; |
1800 | } | |
1801 | ||
be01363f | 1802 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1803 | { |
cef437ad | 1804 | struct render_state so; |
cef437ad DL |
1805 | int ret; |
1806 | ||
be01363f | 1807 | ret = i915_gem_render_state_prepare(req->ring, &so); |
cef437ad DL |
1808 | if (ret) |
1809 | return ret; | |
1810 | ||
1811 | if (so.rodata == NULL) | |
1812 | return 0; | |
1813 | ||
be795fc1 | 1814 | ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1815 | I915_DISPATCH_SECURE); |
cef437ad DL |
1816 | if (ret) |
1817 | goto out; | |
1818 | ||
84e81020 AS |
1819 | ret = req->ring->emit_bb_start(req, |
1820 | (so.ggtt_offset + so.aux_batch_offset), | |
1821 | I915_DISPATCH_SECURE); | |
1822 | if (ret) | |
1823 | goto out; | |
1824 | ||
b2af0376 | 1825 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1826 | |
cef437ad DL |
1827 | out: |
1828 | i915_gem_render_state_fini(&so); | |
1829 | return ret; | |
1830 | } | |
1831 | ||
8753181e | 1832 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1833 | { |
1834 | int ret; | |
1835 | ||
e2be4faf | 1836 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1837 | if (ret) |
1838 | return ret; | |
1839 | ||
3bbaba0c PA |
1840 | ret = intel_rcs_context_init_mocs(req); |
1841 | /* | |
1842 | * Failing to program the MOCS is non-fatal.The system will not | |
1843 | * run at peak performance. So generate an error and carry on. | |
1844 | */ | |
1845 | if (ret) | |
1846 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1847 | ||
be01363f | 1848 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1849 | } |
1850 | ||
73e4d07f OM |
1851 | /** |
1852 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1853 | * | |
1854 | * @ring: Engine Command Streamer. | |
1855 | * | |
1856 | */ | |
454afebd OM |
1857 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1858 | { | |
6402c330 | 1859 | struct drm_i915_private *dev_priv; |
9832b9da | 1860 | |
48d82387 OM |
1861 | if (!intel_ring_initialized(ring)) |
1862 | return; | |
1863 | ||
6402c330 JH |
1864 | dev_priv = ring->dev->dev_private; |
1865 | ||
9832b9da OM |
1866 | intel_logical_ring_stop(ring); |
1867 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1868 | |
1869 | if (ring->cleanup) | |
1870 | ring->cleanup(ring); | |
1871 | ||
1872 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1873 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1874 | |
1875 | if (ring->status_page.obj) { | |
1876 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1877 | ring->status_page.obj = NULL; | |
1878 | } | |
17ee950d AS |
1879 | |
1880 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1881 | } |
1882 | ||
1883 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1884 | { | |
48d82387 | 1885 | int ret; |
48d82387 OM |
1886 | |
1887 | /* Intentionally left blank. */ | |
1888 | ring->buffer = NULL; | |
1889 | ||
1890 | ring->dev = dev; | |
1891 | INIT_LIST_HEAD(&ring->active_list); | |
1892 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1893 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1894 | init_waitqueue_head(&ring->irq_queue); |
1895 | ||
acdd884a | 1896 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1897 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1898 | spin_lock_init(&ring->execlist_lock); |
1899 | ||
48d82387 OM |
1900 | ret = i915_cmd_parser_init_ring(ring); |
1901 | if (ret) | |
1902 | return ret; | |
1903 | ||
564ddb2f OM |
1904 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1905 | ||
1906 | return ret; | |
454afebd OM |
1907 | } |
1908 | ||
1909 | static int logical_render_ring_init(struct drm_device *dev) | |
1910 | { | |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1912 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1913 | int ret; |
454afebd OM |
1914 | |
1915 | ring->name = "render ring"; | |
1916 | ring->id = RCS; | |
1917 | ring->mmio_base = RENDER_RING_BASE; | |
1918 | ring->irq_enable_mask = | |
1919 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1920 | ring->irq_keep_mask = |
1921 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1922 | if (HAS_L3_DPF(dev)) | |
1923 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1924 | |
82ef822e DL |
1925 | if (INTEL_INFO(dev)->gen >= 9) |
1926 | ring->init_hw = gen9_init_render_ring; | |
1927 | else | |
1928 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1929 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1930 | ring->cleanup = intel_fini_pipe_control; |
319404df ID |
1931 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
1932 | ring->get_seqno = bxt_a_get_seqno; | |
1933 | ring->set_seqno = bxt_a_set_seqno; | |
1934 | } else { | |
1935 | ring->get_seqno = gen8_get_seqno; | |
1936 | ring->set_seqno = gen8_set_seqno; | |
1937 | } | |
4da46e1e | 1938 | ring->emit_request = gen8_emit_request; |
4712274c | 1939 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1940 | ring->irq_get = gen8_logical_ring_get_irq; |
1941 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1942 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1943 | |
99be1dfe | 1944 | ring->dev = dev; |
c4db7599 AS |
1945 | |
1946 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1947 | if (ret) |
1948 | return ret; | |
1949 | ||
17ee950d AS |
1950 | ret = intel_init_workaround_bb(ring); |
1951 | if (ret) { | |
1952 | /* | |
1953 | * We continue even if we fail to initialize WA batch | |
1954 | * because we only expect rare glitches but nothing | |
1955 | * critical to prevent us from using GPU | |
1956 | */ | |
1957 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1958 | ret); | |
1959 | } | |
1960 | ||
c4db7599 AS |
1961 | ret = logical_ring_init(dev, ring); |
1962 | if (ret) { | |
17ee950d | 1963 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1964 | } |
17ee950d AS |
1965 | |
1966 | return ret; | |
454afebd OM |
1967 | } |
1968 | ||
1969 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1970 | { | |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1972 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1973 | ||
1974 | ring->name = "bsd ring"; | |
1975 | ring->id = VCS; | |
1976 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1977 | ring->irq_enable_mask = | |
1978 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1979 | ring->irq_keep_mask = |
1980 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1981 | |
ecfe00d8 | 1982 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
1983 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
1984 | ring->get_seqno = bxt_a_get_seqno; | |
1985 | ring->set_seqno = bxt_a_set_seqno; | |
1986 | } else { | |
1987 | ring->get_seqno = gen8_get_seqno; | |
1988 | ring->set_seqno = gen8_set_seqno; | |
1989 | } | |
4da46e1e | 1990 | ring->emit_request = gen8_emit_request; |
4712274c | 1991 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1992 | ring->irq_get = gen8_logical_ring_get_irq; |
1993 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1994 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1995 | |
454afebd OM |
1996 | return logical_ring_init(dev, ring); |
1997 | } | |
1998 | ||
1999 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
2000 | { | |
2001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2002 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
2003 | ||
2004 | ring->name = "bds2 ring"; | |
2005 | ring->id = VCS2; | |
2006 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2007 | ring->irq_enable_mask = | |
2008 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
2009 | ring->irq_keep_mask = |
2010 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 2011 | |
ecfe00d8 | 2012 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
2013 | ring->get_seqno = gen8_get_seqno; |
2014 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 2015 | ring->emit_request = gen8_emit_request; |
4712274c | 2016 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2017 | ring->irq_get = gen8_logical_ring_get_irq; |
2018 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2019 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2020 | |
454afebd OM |
2021 | return logical_ring_init(dev, ring); |
2022 | } | |
2023 | ||
2024 | static int logical_blt_ring_init(struct drm_device *dev) | |
2025 | { | |
2026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2027 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
2028 | ||
2029 | ring->name = "blitter ring"; | |
2030 | ring->id = BCS; | |
2031 | ring->mmio_base = BLT_RING_BASE; | |
2032 | ring->irq_enable_mask = | |
2033 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
2034 | ring->irq_keep_mask = |
2035 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 2036 | |
ecfe00d8 | 2037 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
2038 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
2039 | ring->get_seqno = bxt_a_get_seqno; | |
2040 | ring->set_seqno = bxt_a_set_seqno; | |
2041 | } else { | |
2042 | ring->get_seqno = gen8_get_seqno; | |
2043 | ring->set_seqno = gen8_set_seqno; | |
2044 | } | |
4da46e1e | 2045 | ring->emit_request = gen8_emit_request; |
4712274c | 2046 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2047 | ring->irq_get = gen8_logical_ring_get_irq; |
2048 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2049 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2050 | |
454afebd OM |
2051 | return logical_ring_init(dev, ring); |
2052 | } | |
2053 | ||
2054 | static int logical_vebox_ring_init(struct drm_device *dev) | |
2055 | { | |
2056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2057 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
2058 | ||
2059 | ring->name = "video enhancement ring"; | |
2060 | ring->id = VECS; | |
2061 | ring->mmio_base = VEBOX_RING_BASE; | |
2062 | ring->irq_enable_mask = | |
2063 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
2064 | ring->irq_keep_mask = |
2065 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 2066 | |
ecfe00d8 | 2067 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
2068 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
2069 | ring->get_seqno = bxt_a_get_seqno; | |
2070 | ring->set_seqno = bxt_a_set_seqno; | |
2071 | } else { | |
2072 | ring->get_seqno = gen8_get_seqno; | |
2073 | ring->set_seqno = gen8_set_seqno; | |
2074 | } | |
4da46e1e | 2075 | ring->emit_request = gen8_emit_request; |
4712274c | 2076 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2077 | ring->irq_get = gen8_logical_ring_get_irq; |
2078 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2079 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2080 | |
454afebd OM |
2081 | return logical_ring_init(dev, ring); |
2082 | } | |
2083 | ||
73e4d07f OM |
2084 | /** |
2085 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2086 | * @dev: DRM device. | |
2087 | * | |
2088 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
2089 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
2090 | * those engines that are present in the hardware. | |
2091 | * | |
2092 | * Return: non-zero if the initialization failed. | |
2093 | */ | |
454afebd OM |
2094 | int intel_logical_rings_init(struct drm_device *dev) |
2095 | { | |
2096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2097 | int ret; | |
2098 | ||
2099 | ret = logical_render_ring_init(dev); | |
2100 | if (ret) | |
2101 | return ret; | |
2102 | ||
2103 | if (HAS_BSD(dev)) { | |
2104 | ret = logical_bsd_ring_init(dev); | |
2105 | if (ret) | |
2106 | goto cleanup_render_ring; | |
2107 | } | |
2108 | ||
2109 | if (HAS_BLT(dev)) { | |
2110 | ret = logical_blt_ring_init(dev); | |
2111 | if (ret) | |
2112 | goto cleanup_bsd_ring; | |
2113 | } | |
2114 | ||
2115 | if (HAS_VEBOX(dev)) { | |
2116 | ret = logical_vebox_ring_init(dev); | |
2117 | if (ret) | |
2118 | goto cleanup_blt_ring; | |
2119 | } | |
2120 | ||
2121 | if (HAS_BSD2(dev)) { | |
2122 | ret = logical_bsd2_ring_init(dev); | |
2123 | if (ret) | |
2124 | goto cleanup_vebox_ring; | |
2125 | } | |
2126 | ||
2127 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
2128 | if (ret) | |
2129 | goto cleanup_bsd2_ring; | |
2130 | ||
2131 | return 0; | |
2132 | ||
2133 | cleanup_bsd2_ring: | |
2134 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
2135 | cleanup_vebox_ring: | |
2136 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
2137 | cleanup_blt_ring: | |
2138 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
2139 | cleanup_bsd_ring: | |
2140 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
2141 | cleanup_render_ring: | |
2142 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
2143 | ||
2144 | return ret; | |
2145 | } | |
2146 | ||
0cea6502 JM |
2147 | static u32 |
2148 | make_rpcs(struct drm_device *dev) | |
2149 | { | |
2150 | u32 rpcs = 0; | |
2151 | ||
2152 | /* | |
2153 | * No explicit RPCS request is needed to ensure full | |
2154 | * slice/subslice/EU enablement prior to Gen9. | |
2155 | */ | |
2156 | if (INTEL_INFO(dev)->gen < 9) | |
2157 | return 0; | |
2158 | ||
2159 | /* | |
2160 | * Starting in Gen9, render power gating can leave | |
2161 | * slice/subslice/EU in a partially enabled state. We | |
2162 | * must make an explicit request through RPCS for full | |
2163 | * enablement. | |
2164 | */ | |
2165 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2166 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2167 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2168 | GEN8_RPCS_S_CNT_SHIFT; | |
2169 | rpcs |= GEN8_RPCS_ENABLE; | |
2170 | } | |
2171 | ||
2172 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2173 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2174 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2175 | GEN8_RPCS_SS_CNT_SHIFT; | |
2176 | rpcs |= GEN8_RPCS_ENABLE; | |
2177 | } | |
2178 | ||
2179 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2180 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2181 | GEN8_RPCS_EU_MIN_SHIFT; | |
2182 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2183 | GEN8_RPCS_EU_MAX_SHIFT; | |
2184 | rpcs |= GEN8_RPCS_ENABLE; | |
2185 | } | |
2186 | ||
2187 | return rpcs; | |
2188 | } | |
2189 | ||
8670d6f9 OM |
2190 | static int |
2191 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
2192 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
2193 | { | |
2d965536 TD |
2194 | struct drm_device *dev = ring->dev; |
2195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 2196 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2197 | struct page *page; |
2198 | uint32_t *reg_state; | |
2199 | int ret; | |
2200 | ||
2d965536 TD |
2201 | if (!ppgtt) |
2202 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2203 | ||
8670d6f9 OM |
2204 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2205 | if (ret) { | |
2206 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2207 | return ret; | |
2208 | } | |
2209 | ||
2210 | ret = i915_gem_object_get_pages(ctx_obj); | |
2211 | if (ret) { | |
2212 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2213 | return ret; | |
2214 | } | |
2215 | ||
2216 | i915_gem_object_pin_pages(ctx_obj); | |
2217 | ||
2218 | /* The second page of the context object contains some fields which must | |
2219 | * be set up prior to the first execution. */ | |
d1675198 | 2220 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
8670d6f9 OM |
2221 | reg_state = kmap_atomic(page); |
2222 | ||
2223 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2224 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2225 | * only for the first context restore: on a subsequent save, the GPU will | |
2226 | * recreate this batchbuffer with new values (including all the missing | |
2227 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
2228 | if (ring->id == RCS) | |
2229 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
2230 | else | |
2231 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
2232 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
2233 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
2234 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 | 2235 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
6922528a AJ |
2236 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
2237 | CTX_CTRL_RS_CTX_ENABLE); | |
8670d6f9 OM |
2238 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
2239 | reg_state[CTX_RING_HEAD+1] = 0; | |
2240 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
2241 | reg_state[CTX_RING_TAIL+1] = 0; | |
2242 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
2243 | /* Ring buffer start address is not known until the buffer is pinned. |
2244 | * It is written to the context image in execlists_update_context() | |
2245 | */ | |
8670d6f9 OM |
2246 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
2247 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
2248 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
2249 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
2250 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
2251 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
2252 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
2253 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
2254 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
2255 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
2256 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
2257 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
2258 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
2259 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
2260 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
2261 | if (ring->id == RCS) { | |
8670d6f9 OM |
2262 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
2263 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
2264 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
2265 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
2266 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
2267 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
2268 | if (ring->wa_ctx.obj) { |
2269 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2270 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2271 | ||
2272 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2273 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2274 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2275 | ||
2276 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2277 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2278 | ||
2279 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2280 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2281 | 0x01; | |
2282 | } | |
8670d6f9 OM |
2283 | } |
2284 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2285 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2286 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2287 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2288 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2289 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2290 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2291 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2292 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2293 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2294 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2295 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d | 2296 | |
2dba3239 MT |
2297 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2298 | /* 64b PPGTT (48bit canonical) | |
2299 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2300 | * other PDP Descriptors are ignored. | |
2301 | */ | |
2302 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2303 | } else { | |
2304 | /* 32b PPGTT | |
2305 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2306 | * With dynamic page allocation, PDPs may not be allocated at | |
2307 | * this point. Point the unallocated PDPs to the scratch page | |
2308 | */ | |
2309 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2310 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2311 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2312 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
2313 | } | |
2314 | ||
8670d6f9 OM |
2315 | if (ring->id == RCS) { |
2316 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2317 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2318 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2319 | } |
2320 | ||
2321 | kunmap_atomic(reg_state); | |
2322 | ||
2323 | ctx_obj->dirty = 1; | |
2324 | set_page_dirty(page); | |
2325 | i915_gem_object_unpin_pages(ctx_obj); | |
2326 | ||
2327 | return 0; | |
2328 | } | |
2329 | ||
73e4d07f OM |
2330 | /** |
2331 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2332 | * @ctx: the LR context to free. | |
2333 | * | |
2334 | * The real context freeing is done in i915_gem_context_free: this only | |
2335 | * takes care of the bits that are LRC related: the per-engine backing | |
2336 | * objects and the logical ringbuffer. | |
2337 | */ | |
ede7d42b OM |
2338 | void intel_lr_context_free(struct intel_context *ctx) |
2339 | { | |
8c857917 OM |
2340 | int i; |
2341 | ||
2342 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2343 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2344 | |
8c857917 | 2345 | if (ctx_obj) { |
dcb4c12a OM |
2346 | struct intel_ringbuffer *ringbuf = |
2347 | ctx->engine[i].ringbuf; | |
2348 | struct intel_engine_cs *ring = ringbuf->ring; | |
2349 | ||
7ba717cf TD |
2350 | if (ctx == ring->default_context) { |
2351 | intel_unpin_ringbuffer_obj(ringbuf); | |
2352 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2353 | } | |
a7cbedec | 2354 | WARN_ON(ctx->engine[ring->id].pin_count); |
01101fa7 | 2355 | intel_ringbuffer_free(ringbuf); |
8c857917 OM |
2356 | drm_gem_object_unreference(&ctx_obj->base); |
2357 | } | |
2358 | } | |
2359 | } | |
2360 | ||
2361 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2362 | { | |
2363 | int ret = 0; | |
2364 | ||
468c6816 | 2365 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2366 | |
2367 | switch (ring->id) { | |
2368 | case RCS: | |
468c6816 MN |
2369 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2370 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2371 | else | |
2372 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2373 | break; |
2374 | case VCS: | |
2375 | case BCS: | |
2376 | case VECS: | |
2377 | case VCS2: | |
2378 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2379 | break; | |
2380 | } | |
2381 | ||
2382 | return ret; | |
ede7d42b OM |
2383 | } |
2384 | ||
70b0ea86 | 2385 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2386 | struct drm_i915_gem_object *default_ctx_obj) |
2387 | { | |
2388 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
d1675198 | 2389 | struct page *page; |
1df06b75 | 2390 | |
d1675198 AD |
2391 | /* The HWSP is part of the default context object in LRC mode. */ |
2392 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) | |
2393 | + LRC_PPHWSP_PN * PAGE_SIZE; | |
2394 | page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); | |
2395 | ring->status_page.page_addr = kmap(page); | |
1df06b75 TD |
2396 | ring->status_page.obj = default_ctx_obj; |
2397 | ||
2398 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2399 | (u32)ring->status_page.gfx_addr); | |
2400 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2401 | } |
2402 | ||
73e4d07f OM |
2403 | /** |
2404 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
2405 | * @ctx: LR context to create. | |
2406 | * @ring: engine to be used with the context. | |
2407 | * | |
2408 | * This function can be called more than once, with different engines, if we plan | |
2409 | * to use the context with them. The context backing objects and the ringbuffers | |
2410 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2411 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2412 | * a given ring with the context. | |
2413 | * | |
32197aab | 2414 | * Return: non-zero on error. |
73e4d07f | 2415 | */ |
ede7d42b OM |
2416 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
2417 | struct intel_engine_cs *ring) | |
2418 | { | |
dcb4c12a | 2419 | const bool is_global_default_ctx = (ctx == ring->default_context); |
8c857917 | 2420 | struct drm_device *dev = ring->dev; |
d1675198 | 2421 | struct drm_i915_private *dev_priv = dev->dev_private; |
8c857917 OM |
2422 | struct drm_i915_gem_object *ctx_obj; |
2423 | uint32_t context_size; | |
84c2377f | 2424 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2425 | int ret; |
2426 | ||
ede7d42b | 2427 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2428 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2429 | |
8c857917 OM |
2430 | context_size = round_up(get_lr_context_size(ring), 4096); |
2431 | ||
d1675198 AD |
2432 | /* One extra page as the sharing data between driver and GuC */ |
2433 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2434 | ||
149c86e7 | 2435 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2436 | if (!ctx_obj) { |
2437 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2438 | return -ENOMEM; | |
8c857917 OM |
2439 | } |
2440 | ||
dcb4c12a | 2441 | if (is_global_default_ctx) { |
d1675198 AD |
2442 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
2443 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
dcb4c12a OM |
2444 | if (ret) { |
2445 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", | |
2446 | ret); | |
2447 | drm_gem_object_unreference(&ctx_obj->base); | |
2448 | return ret; | |
2449 | } | |
d1675198 AD |
2450 | |
2451 | /* Invalidate GuC TLB. */ | |
2452 | if (i915.enable_guc_submission) | |
2453 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
8c857917 OM |
2454 | } |
2455 | ||
01101fa7 CW |
2456 | ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE); |
2457 | if (IS_ERR(ringbuf)) { | |
2458 | ret = PTR_ERR(ringbuf); | |
7ba717cf | 2459 | goto error_unpin_ctx; |
84c2377f OM |
2460 | } |
2461 | ||
01101fa7 CW |
2462 | if (is_global_default_ctx) { |
2463 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
7ba717cf | 2464 | if (ret) { |
01101fa7 CW |
2465 | DRM_ERROR( |
2466 | "Failed to pin and map ringbuffer %s: %d\n", | |
2467 | ring->name, ret); | |
2468 | goto error_ringbuf; | |
7ba717cf | 2469 | } |
8670d6f9 OM |
2470 | } |
2471 | ||
2472 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2473 | if (ret) { | |
2474 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
8670d6f9 | 2475 | goto error; |
84c2377f OM |
2476 | } |
2477 | ||
2478 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2479 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2480 | |
70b0ea86 DV |
2481 | if (ctx == ring->default_context) |
2482 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
e7778be1 | 2483 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
771b9a53 | 2484 | if (ring->init_context) { |
76c39168 JH |
2485 | struct drm_i915_gem_request *req; |
2486 | ||
2487 | ret = i915_gem_request_alloc(ring, ctx, &req); | |
2488 | if (ret) | |
2489 | return ret; | |
2490 | ||
8753181e | 2491 | ret = ring->init_context(req); |
e7778be1 | 2492 | if (ret) { |
771b9a53 | 2493 | DRM_ERROR("ring init context: %d\n", ret); |
76c39168 | 2494 | i915_gem_request_cancel(req); |
e7778be1 TD |
2495 | ctx->engine[ring->id].ringbuf = NULL; |
2496 | ctx->engine[ring->id].state = NULL; | |
2497 | goto error; | |
2498 | } | |
76c39168 | 2499 | |
75289874 | 2500 | i915_add_request_no_flush(req); |
771b9a53 MT |
2501 | } |
2502 | ||
564ddb2f OM |
2503 | ctx->rcs_initialized = true; |
2504 | } | |
2505 | ||
ede7d42b | 2506 | return 0; |
8670d6f9 OM |
2507 | |
2508 | error: | |
7ba717cf TD |
2509 | if (is_global_default_ctx) |
2510 | intel_unpin_ringbuffer_obj(ringbuf); | |
01101fa7 CW |
2511 | error_ringbuf: |
2512 | intel_ringbuffer_free(ringbuf); | |
7ba717cf | 2513 | error_unpin_ctx: |
dcb4c12a OM |
2514 | if (is_global_default_ctx) |
2515 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8670d6f9 OM |
2516 | drm_gem_object_unreference(&ctx_obj->base); |
2517 | return ret; | |
ede7d42b | 2518 | } |
3e5b6f05 TD |
2519 | |
2520 | void intel_lr_context_reset(struct drm_device *dev, | |
2521 | struct intel_context *ctx) | |
2522 | { | |
2523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2524 | struct intel_engine_cs *ring; | |
2525 | int i; | |
2526 | ||
2527 | for_each_ring(ring, dev_priv, i) { | |
2528 | struct drm_i915_gem_object *ctx_obj = | |
2529 | ctx->engine[ring->id].state; | |
2530 | struct intel_ringbuffer *ringbuf = | |
2531 | ctx->engine[ring->id].ringbuf; | |
2532 | uint32_t *reg_state; | |
2533 | struct page *page; | |
2534 | ||
2535 | if (!ctx_obj) | |
2536 | continue; | |
2537 | ||
2538 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2539 | WARN(1, "Failed get_pages for context obj\n"); | |
2540 | continue; | |
2541 | } | |
d1675198 | 2542 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
3e5b6f05 TD |
2543 | reg_state = kmap_atomic(page); |
2544 | ||
2545 | reg_state[CTX_RING_HEAD+1] = 0; | |
2546 | reg_state[CTX_RING_TAIL+1] = 0; | |
2547 | ||
2548 | kunmap_atomic(reg_state); | |
2549 | ||
2550 | ringbuf->head = 0; | |
2551 | ringbuf->tail = 0; | |
2552 | } | |
2553 | } |