[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lrc.c

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

/*
 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
 */

#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"

#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

#define GEN8_LR_CONTEXT_ALIGN 4096

int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
{
	WARN_ON(i915.enable_ppgtt == -1);

	if (enable_execlists == 0)
		return 0;

	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev))
		return 1;

	return 0;
}

void intel_lr_context_free(struct intel_context *ctx)
{
	int i;

	for (i = 0; i < I915_NUM_RINGS; i++) {
		struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
		if (ctx_obj) {
			i915_gem_object_ggtt_unpin(ctx_obj);
			drm_gem_object_unreference(&ctx_obj->base);
		}
	}
}

static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
{
	int ret = 0;

	WARN_ON(INTEL_INFO(ring->dev)->gen != 8);

	switch (ring->id) {
	case RCS:
		ret = GEN8_LR_CONTEXT_RENDER_SIZE;
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
}

int intel_lr_context_deferred_create(struct intel_context *ctx,
				     struct intel_engine_cs *ring)
{
	struct drm_device *dev = ring->dev;
	struct drm_i915_gem_object *ctx_obj;
	uint32_t context_size;
	int ret;

	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);

	context_size = round_up(get_lr_context_size(ring), 4096);

	ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
	if (IS_ERR(ctx_obj)) {
		ret = PTR_ERR(ctx_obj);
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
		return ret;
	}

	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
	if (ret) {
		DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
		drm_gem_object_unreference(&ctx_obj->base);
		return ret;
	}

	ctx->engine[ring->id].state = ctx_obj;

	return 0;
}
Commit	Line	Data
b20385f1 OM	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Ben Widawsky <ben@bwidawsk.net>
	25	* Michel Thierry <michel.thierry@intel.com>
	26	* Thomas Daniel <thomas.daniel@intel.com>
	27	* Oscar Mateo <oscar.mateo@intel.com>
	28	*
	29	*/
	30
	31	/*
	32	* GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
	33	* These expanded contexts enable a number of new abilities, especially
	34	* "Execlists" (also implemented in this file).
	35	*
	36	* Execlists are the new method by which, on gen8+ hardware, workloads are
	37	* submitted for execution (as opposed to the legacy, ringbuffer-based, method).
	38	*/
	39
	40	#include <drm/drmP.h>
	41	#include <drm/i915_drm.h>
	42	#include "i915_drv.h"
127f1003	43
8c857917 OM	44	#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
	45	#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
	46
	47	#define GEN8_LR_CONTEXT_ALIGN 4096
	48
127f1003 OM	49	int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
127f1003 OM	50	{
bd84b1e9 DV	51	WARN_ON(i915.enable_ppgtt == -1);
bd84b1e9 DV	52
127f1003 OM	53	if (enable_execlists == 0)
	54	return 0;
	55
	56	if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev))
	57	return 1;
	58
	59	return 0;
	60	}
ede7d42b OM	61
	62	void intel_lr_context_free(struct intel_context *ctx)
	63	{
8c857917 OM	64	int i;
	65
	66	for (i = 0; i < I915_NUM_RINGS; i++) {
	67	struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
	68	if (ctx_obj) {
	69	i915_gem_object_ggtt_unpin(ctx_obj);
	70	drm_gem_object_unreference(&ctx_obj->base);
	71	}
	72	}
	73	}
	74
	75	static uint32_t get_lr_context_size(struct intel_engine_cs *ring)
	76	{
	77	int ret = 0;
	78
	79	WARN_ON(INTEL_INFO(ring->dev)->gen != 8);
	80
	81	switch (ring->id) {
	82	case RCS:
	83	ret = GEN8_LR_CONTEXT_RENDER_SIZE;
	84	break;
	85	case VCS:
	86	case BCS:
	87	case VECS:
	88	case VCS2:
	89	ret = GEN8_LR_CONTEXT_OTHER_SIZE;
	90	break;
	91	}
	92
	93	return ret;
ede7d42b OM	94	}
	95
	96	int intel_lr_context_deferred_create(struct intel_context *ctx,
	97	struct intel_engine_cs *ring)
	98	{
8c857917 OM	99	struct drm_device *dev = ring->dev;
	100	struct drm_i915_gem_object *ctx_obj;
	101	uint32_t context_size;
	102	int ret;
	103
ede7d42b OM	104	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
ede7d42b OM	105
8c857917 OM	106	context_size = round_up(get_lr_context_size(ring), 4096);
	107
	108	ctx_obj = i915_gem_alloc_context_obj(dev, context_size);
	109	if (IS_ERR(ctx_obj)) {
	110	ret = PTR_ERR(ctx_obj);
	111	DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret);
	112	return ret;
	113	}
	114
	115	ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0);
	116	if (ret) {
	117	DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret);
	118	drm_gem_object_unreference(&ctx_obj->base);
	119	return ret;
	120	}
	121
	122	ctx->engine[ring->id].state = ctx_obj;
ede7d42b OM	123
	124	return 0;
	125	}