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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
127f1003 | 138 | |
468c6816 | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
142 | ||
e981e7b1 TD |
143 | #define RING_EXECLIST_QFULL (1 << 0x2) |
144 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
145 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
146 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
147 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
148 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
149 | ||
150 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
151 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
152 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
153 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
154 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
155 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
156 | |
157 | #define CTX_LRI_HEADER_0 0x01 | |
158 | #define CTX_CONTEXT_CONTROL 0x02 | |
159 | #define CTX_RING_HEAD 0x04 | |
160 | #define CTX_RING_TAIL 0x06 | |
161 | #define CTX_RING_BUFFER_START 0x08 | |
162 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
163 | #define CTX_BB_HEAD_U 0x0c | |
164 | #define CTX_BB_HEAD_L 0x0e | |
165 | #define CTX_BB_STATE 0x10 | |
166 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
167 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
168 | #define CTX_SECOND_BB_STATE 0x16 | |
169 | #define CTX_BB_PER_CTX_PTR 0x18 | |
170 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
171 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
172 | #define CTX_LRI_HEADER_1 0x21 | |
173 | #define CTX_CTX_TIMESTAMP 0x22 | |
174 | #define CTX_PDP3_UDW 0x24 | |
175 | #define CTX_PDP3_LDW 0x26 | |
176 | #define CTX_PDP2_UDW 0x28 | |
177 | #define CTX_PDP2_LDW 0x2a | |
178 | #define CTX_PDP1_UDW 0x2c | |
179 | #define CTX_PDP1_LDW 0x2e | |
180 | #define CTX_PDP0_UDW 0x30 | |
181 | #define CTX_PDP0_LDW 0x32 | |
182 | #define CTX_LRI_HEADER_2 0x41 | |
183 | #define CTX_R_PWR_CLK_STATE 0x42 | |
184 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
185 | ||
84b790f8 BW |
186 | #define GEN8_CTX_VALID (1<<0) |
187 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
188 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
189 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
190 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
191 | |
192 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d7b2633d | 193 | const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \ |
e5815a2e MT |
194 | ppgtt->pdp.page_directory[n]->daddr : \ |
195 | ppgtt->scratch_pd->daddr; \ | |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ | |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
198 | } | |
199 | ||
84b790f8 BW |
200 | enum { |
201 | ADVANCED_CONTEXT = 0, | |
202 | LEGACY_CONTEXT, | |
203 | ADVANCED_AD_CONTEXT, | |
204 | LEGACY_64B_CONTEXT | |
205 | }; | |
206 | #define GEN8_CTX_MODE_SHIFT 3 | |
207 | enum { | |
208 | FAULT_AND_HANG = 0, | |
209 | FAULT_AND_HALT, /* Debug only */ | |
210 | FAULT_AND_STREAM, | |
211 | FAULT_AND_CONTINUE /* Unsupported */ | |
212 | }; | |
213 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 214 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 215 | |
7ba717cf TD |
216 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
217 | struct intel_context *ctx); | |
218 | ||
73e4d07f OM |
219 | /** |
220 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
221 | * @dev: DRM device. | |
222 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
223 | * | |
224 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 225 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
226 | * |
227 | * Return: 1 if Execlists is supported and has to be enabled. | |
228 | */ | |
127f1003 OM |
229 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
230 | { | |
bd84b1e9 DV |
231 | WARN_ON(i915.enable_ppgtt == -1); |
232 | ||
70ee45e1 DL |
233 | if (INTEL_INFO(dev)->gen >= 9) |
234 | return 1; | |
235 | ||
127f1003 OM |
236 | if (enable_execlists == 0) |
237 | return 0; | |
238 | ||
14bf993e OM |
239 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
240 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
241 | return 1; |
242 | ||
243 | return 0; | |
244 | } | |
ede7d42b | 245 | |
73e4d07f OM |
246 | /** |
247 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
248 | * @ctx_obj: Logical Ring Context backing object. | |
249 | * | |
250 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
251 | * here: the old context ID we pass to userspace as a handler so that | |
252 | * they can refer to a context, and the new context ID we pass to the | |
253 | * ELSP so that the GPU can inform us of the context status via | |
254 | * interrupts. | |
255 | * | |
256 | * Return: 20-bits globally unique context ID. | |
257 | */ | |
84b790f8 BW |
258 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
259 | { | |
260 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
261 | ||
262 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
263 | * are globally unique */ | |
264 | return lrca >> 12; | |
265 | } | |
266 | ||
203a571b NH |
267 | static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, |
268 | struct drm_i915_gem_object *ctx_obj) | |
84b790f8 | 269 | { |
203a571b | 270 | struct drm_device *dev = ring->dev; |
84b790f8 BW |
271 | uint64_t desc; |
272 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
273 | |
274 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
275 | |
276 | desc = GEN8_CTX_VALID; | |
277 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
51847fb9 AS |
278 | if (IS_GEN8(ctx_obj->base.dev)) |
279 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
280 | desc |= GEN8_CTX_PRIVILEGE; |
281 | desc |= lrca; | |
282 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
283 | ||
284 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
285 | * signalling between Command Streamers */ | |
286 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
287 | ||
203a571b NH |
288 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
289 | if (IS_GEN9(dev) && | |
290 | INTEL_REVID(dev) <= SKL_REVID_B0 && | |
291 | (ring->id == BCS || ring->id == VCS || | |
292 | ring->id == VECS || ring->id == VCS2)) | |
293 | desc |= GEN8_CTX_FORCE_RESTORE; | |
294 | ||
84b790f8 BW |
295 | return desc; |
296 | } | |
297 | ||
298 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
299 | struct drm_i915_gem_object *ctx_obj0, | |
300 | struct drm_i915_gem_object *ctx_obj1) | |
301 | { | |
6e7cc470 TU |
302 | struct drm_device *dev = ring->dev; |
303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84b790f8 BW |
304 | uint64_t temp = 0; |
305 | uint32_t desc[4]; | |
306 | ||
307 | /* XXX: You must always write both descriptors in the order below. */ | |
308 | if (ctx_obj1) | |
203a571b | 309 | temp = execlists_ctx_descriptor(ring, ctx_obj1); |
84b790f8 BW |
310 | else |
311 | temp = 0; | |
312 | desc[1] = (u32)(temp >> 32); | |
313 | desc[0] = (u32)temp; | |
314 | ||
203a571b | 315 | temp = execlists_ctx_descriptor(ring, ctx_obj0); |
84b790f8 BW |
316 | desc[3] = (u32)(temp >> 32); |
317 | desc[2] = (u32)temp; | |
318 | ||
a6111f7b CW |
319 | spin_lock(&dev_priv->uncore.lock); |
320 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
321 | I915_WRITE_FW(RING_ELSP(ring), desc[1]); | |
322 | I915_WRITE_FW(RING_ELSP(ring), desc[0]); | |
323 | I915_WRITE_FW(RING_ELSP(ring), desc[3]); | |
6daccb0b | 324 | |
84b790f8 | 325 | /* The context is automatically loaded after the following */ |
a6111f7b | 326 | I915_WRITE_FW(RING_ELSP(ring), desc[2]); |
84b790f8 BW |
327 | |
328 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
a6111f7b CW |
329 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
330 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
331 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
332 | } |
333 | ||
7ba717cf TD |
334 | static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, |
335 | struct drm_i915_gem_object *ring_obj, | |
d7b2633d | 336 | struct i915_hw_ppgtt *ppgtt, |
7ba717cf | 337 | u32 tail) |
ae1250b9 OM |
338 | { |
339 | struct page *page; | |
340 | uint32_t *reg_state; | |
341 | ||
342 | page = i915_gem_object_get_page(ctx_obj, 1); | |
343 | reg_state = kmap_atomic(page); | |
344 | ||
345 | reg_state[CTX_RING_TAIL+1] = tail; | |
7ba717cf | 346 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); |
ae1250b9 | 347 | |
d7b2633d MT |
348 | /* True PPGTT with dynamic page allocation: update PDP registers and |
349 | * point the unallocated PDPs to the scratch page | |
350 | */ | |
351 | if (ppgtt) { | |
352 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
353 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
354 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
355 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
356 | } | |
357 | ||
ae1250b9 OM |
358 | kunmap_atomic(reg_state); |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
cd0707cb DG |
363 | static void execlists_submit_contexts(struct intel_engine_cs *ring, |
364 | struct intel_context *to0, u32 tail0, | |
365 | struct intel_context *to1, u32 tail1) | |
84b790f8 | 366 | { |
7ba717cf TD |
367 | struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; |
368 | struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; | |
84b790f8 | 369 | struct drm_i915_gem_object *ctx_obj1 = NULL; |
7ba717cf | 370 | struct intel_ringbuffer *ringbuf1 = NULL; |
84b790f8 | 371 | |
84b790f8 | 372 | BUG_ON(!ctx_obj0); |
acdd884a | 373 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); |
7ba717cf | 374 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); |
84b790f8 | 375 | |
d7b2633d | 376 | execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0); |
ae1250b9 | 377 | |
84b790f8 | 378 | if (to1) { |
7ba717cf | 379 | ringbuf1 = to1->engine[ring->id].ringbuf; |
84b790f8 BW |
380 | ctx_obj1 = to1->engine[ring->id].state; |
381 | BUG_ON(!ctx_obj1); | |
acdd884a | 382 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); |
7ba717cf | 383 | WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); |
ae1250b9 | 384 | |
d7b2633d | 385 | execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1); |
84b790f8 BW |
386 | } |
387 | ||
388 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
84b790f8 BW |
389 | } |
390 | ||
acdd884a MT |
391 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
392 | { | |
6d3d8274 NH |
393 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
394 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
395 | |
396 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 397 | |
779949f4 PA |
398 | /* |
399 | * If irqs are not active generate a warning as batches that finish | |
400 | * without the irqs may get lost and a GPU Hang may occur. | |
401 | */ | |
402 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
403 | ||
acdd884a MT |
404 | if (list_empty(&ring->execlist_queue)) |
405 | return; | |
406 | ||
407 | /* Try to read in pairs */ | |
408 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
409 | execlist_link) { | |
410 | if (!req0) { | |
411 | req0 = cursor; | |
6d3d8274 | 412 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
413 | /* Same ctx: ignore first request, as second request |
414 | * will update tail past first request's workload */ | |
e1fee72c | 415 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 416 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
417 | list_add_tail(&req0->execlist_link, |
418 | &ring->execlist_retired_req_list); | |
acdd884a MT |
419 | req0 = cursor; |
420 | } else { | |
421 | req1 = cursor; | |
422 | break; | |
423 | } | |
424 | } | |
425 | ||
53292cdb MT |
426 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
427 | /* | |
428 | * WaIdleLiteRestore: make sure we never cause a lite | |
429 | * restore with HEAD==TAIL | |
430 | */ | |
d63f820f | 431 | if (req0->elsp_submitted) { |
53292cdb MT |
432 | /* |
433 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
434 | * as we resubmit the request. See gen8_emit_request() | |
435 | * for where we prepare the padding after the end of the | |
436 | * request. | |
437 | */ | |
438 | struct intel_ringbuffer *ringbuf; | |
439 | ||
440 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
441 | req0->tail += 8; | |
442 | req0->tail &= ringbuf->size - 1; | |
443 | } | |
444 | } | |
445 | ||
e1fee72c OM |
446 | WARN_ON(req1 && req1->elsp_submitted); |
447 | ||
6d3d8274 NH |
448 | execlists_submit_contexts(ring, req0->ctx, req0->tail, |
449 | req1 ? req1->ctx : NULL, | |
450 | req1 ? req1->tail : 0); | |
e1fee72c OM |
451 | |
452 | req0->elsp_submitted++; | |
453 | if (req1) | |
454 | req1->elsp_submitted++; | |
acdd884a MT |
455 | } |
456 | ||
e981e7b1 TD |
457 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
458 | u32 request_id) | |
459 | { | |
6d3d8274 | 460 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
461 | |
462 | assert_spin_locked(&ring->execlist_lock); | |
463 | ||
464 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 465 | struct drm_i915_gem_request, |
e981e7b1 TD |
466 | execlist_link); |
467 | ||
468 | if (head_req != NULL) { | |
469 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 470 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 471 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
472 | WARN(head_req->elsp_submitted == 0, |
473 | "Never submitted head request\n"); | |
474 | ||
475 | if (--head_req->elsp_submitted <= 0) { | |
476 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
477 | list_add_tail(&head_req->execlist_link, |
478 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
479 | return true; |
480 | } | |
e981e7b1 TD |
481 | } |
482 | } | |
483 | ||
484 | return false; | |
485 | } | |
486 | ||
73e4d07f | 487 | /** |
3f7531c3 | 488 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
489 | * @ring: Engine Command Streamer to handle. |
490 | * | |
491 | * Check the unread Context Status Buffers and manage the submission of new | |
492 | * contexts to the ELSP accordingly. | |
493 | */ | |
3f7531c3 | 494 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
495 | { |
496 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
497 | u32 status_pointer; | |
498 | u8 read_pointer; | |
499 | u8 write_pointer; | |
500 | u32 status; | |
501 | u32 status_id; | |
502 | u32 submit_contexts = 0; | |
503 | ||
504 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
505 | ||
506 | read_pointer = ring->next_context_status_buffer; | |
507 | write_pointer = status_pointer & 0x07; | |
508 | if (read_pointer > write_pointer) | |
509 | write_pointer += 6; | |
510 | ||
511 | spin_lock(&ring->execlist_lock); | |
512 | ||
513 | while (read_pointer < write_pointer) { | |
514 | read_pointer++; | |
515 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
516 | (read_pointer % 6) * 8); | |
517 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
518 | (read_pointer % 6) * 8 + 4); | |
519 | ||
e1fee72c OM |
520 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
521 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
522 | if (execlists_check_remove_request(ring, status_id)) | |
523 | WARN(1, "Lite Restored request removed from queue\n"); | |
524 | } else | |
525 | WARN(1, "Preemption without Lite Restore\n"); | |
526 | } | |
527 | ||
528 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
529 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
530 | if (execlists_check_remove_request(ring, status_id)) |
531 | submit_contexts++; | |
532 | } | |
533 | } | |
534 | ||
535 | if (submit_contexts != 0) | |
536 | execlists_context_unqueue(ring); | |
537 | ||
538 | spin_unlock(&ring->execlist_lock); | |
539 | ||
540 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
541 | ring->next_context_status_buffer = write_pointer % 6; | |
542 | ||
543 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
544 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
545 | } | |
546 | ||
acdd884a MT |
547 | static int execlists_context_queue(struct intel_engine_cs *ring, |
548 | struct intel_context *to, | |
2d12955a NH |
549 | u32 tail, |
550 | struct drm_i915_gem_request *request) | |
acdd884a | 551 | { |
6d3d8274 | 552 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 553 | int num_elements = 0; |
acdd884a | 554 | |
7ba717cf TD |
555 | if (to != ring->default_context) |
556 | intel_lr_context_pin(ring, to); | |
557 | ||
2d12955a NH |
558 | if (!request) { |
559 | /* | |
560 | * If there isn't a request associated with this submission, | |
561 | * create one as a temporary holder. | |
562 | */ | |
2d12955a NH |
563 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
564 | if (request == NULL) | |
565 | return -ENOMEM; | |
2d12955a | 566 | request->ring = ring; |
6d3d8274 | 567 | request->ctx = to; |
b3a38998 | 568 | kref_init(&request->ref); |
b3a38998 | 569 | i915_gem_context_reference(request->ctx); |
21076372 | 570 | } else { |
b3a38998 | 571 | i915_gem_request_reference(request); |
21076372 | 572 | WARN_ON(to != request->ctx); |
2d12955a | 573 | } |
72f95afa | 574 | request->tail = tail; |
2d12955a | 575 | |
b5eba372 | 576 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 577 | |
f1ad5a1f OM |
578 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
579 | if (++num_elements > 2) | |
580 | break; | |
581 | ||
582 | if (num_elements > 2) { | |
6d3d8274 | 583 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
584 | |
585 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 586 | struct drm_i915_gem_request, |
f1ad5a1f OM |
587 | execlist_link); |
588 | ||
6d3d8274 | 589 | if (to == tail_req->ctx) { |
f1ad5a1f | 590 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 591 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 592 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
593 | list_add_tail(&tail_req->execlist_link, |
594 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
595 | } |
596 | } | |
597 | ||
6d3d8274 | 598 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 599 | if (num_elements == 0) |
acdd884a MT |
600 | execlists_context_unqueue(ring); |
601 | ||
b5eba372 | 602 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
21076372 NH |
607 | static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf, |
608 | struct intel_context *ctx) | |
ba8b7ccb OM |
609 | { |
610 | struct intel_engine_cs *ring = ringbuf->ring; | |
611 | uint32_t flush_domains; | |
612 | int ret; | |
613 | ||
614 | flush_domains = 0; | |
615 | if (ring->gpu_caches_dirty) | |
616 | flush_domains = I915_GEM_GPU_DOMAINS; | |
617 | ||
21076372 NH |
618 | ret = ring->emit_flush(ringbuf, ctx, |
619 | I915_GEM_GPU_DOMAINS, flush_domains); | |
ba8b7ccb OM |
620 | if (ret) |
621 | return ret; | |
622 | ||
623 | ring->gpu_caches_dirty = false; | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, | |
21076372 | 628 | struct intel_context *ctx, |
ba8b7ccb OM |
629 | struct list_head *vmas) |
630 | { | |
631 | struct intel_engine_cs *ring = ringbuf->ring; | |
03ade511 | 632 | const unsigned other_rings = ~intel_ring_flag(ring); |
ba8b7ccb OM |
633 | struct i915_vma *vma; |
634 | uint32_t flush_domains = 0; | |
635 | bool flush_chipset = false; | |
636 | int ret; | |
637 | ||
638 | list_for_each_entry(vma, vmas, exec_list) { | |
639 | struct drm_i915_gem_object *obj = vma->obj; | |
640 | ||
03ade511 CW |
641 | if (obj->active & other_rings) { |
642 | ret = i915_gem_object_sync(obj, ring); | |
643 | if (ret) | |
644 | return ret; | |
645 | } | |
ba8b7ccb OM |
646 | |
647 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
648 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
649 | ||
650 | flush_domains |= obj->base.write_domain; | |
651 | } | |
652 | ||
653 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
654 | wmb(); | |
655 | ||
656 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
657 | * any residual writes from the previous batch. | |
658 | */ | |
21076372 | 659 | return logical_ring_invalidate_all_caches(ringbuf, ctx); |
ba8b7ccb OM |
660 | } |
661 | ||
40e895ce | 662 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 663 | { |
bc0dce3f JH |
664 | int ret; |
665 | ||
40e895ce JH |
666 | if (request->ctx != request->ring->default_context) { |
667 | ret = intel_lr_context_pin(request->ring, request->ctx); | |
6689cb2b | 668 | if (ret) |
bc0dce3f | 669 | return ret; |
bc0dce3f JH |
670 | } |
671 | ||
40e895ce | 672 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
bc0dce3f | 673 | |
bc0dce3f JH |
674 | return 0; |
675 | } | |
676 | ||
595e1eeb CW |
677 | static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, |
678 | struct intel_context *ctx, | |
679 | int bytes) | |
bc0dce3f JH |
680 | { |
681 | struct intel_engine_cs *ring = ringbuf->ring; | |
682 | struct drm_i915_gem_request *request; | |
b4716185 CW |
683 | unsigned space; |
684 | int ret; | |
bc0dce3f | 685 | |
29b1b415 JH |
686 | /* The whole point of reserving space is to not wait! */ |
687 | WARN_ON(ringbuf->reserved_in_use); | |
688 | ||
bc0dce3f JH |
689 | if (intel_ring_space(ringbuf) >= bytes) |
690 | return 0; | |
691 | ||
692 | list_for_each_entry(request, &ring->request_list, list) { | |
693 | /* | |
694 | * The request queue is per-engine, so can contain requests | |
695 | * from multiple ringbuffers. Here, we must ignore any that | |
696 | * aren't from the ringbuffer we're considering. | |
697 | */ | |
b4716185 | 698 | if (request->ringbuf != ringbuf) |
bc0dce3f JH |
699 | continue; |
700 | ||
701 | /* Would completion of this request free enough space? */ | |
b4716185 CW |
702 | space = __intel_ring_space(request->postfix, ringbuf->tail, |
703 | ringbuf->size); | |
704 | if (space >= bytes) | |
bc0dce3f | 705 | break; |
bc0dce3f JH |
706 | } |
707 | ||
595e1eeb | 708 | if (WARN_ON(&request->list == &ring->request_list)) |
bc0dce3f JH |
709 | return -ENOSPC; |
710 | ||
711 | ret = i915_wait_request(request); | |
712 | if (ret) | |
713 | return ret; | |
714 | ||
b4716185 CW |
715 | ringbuf->space = space; |
716 | return 0; | |
bc0dce3f JH |
717 | } |
718 | ||
719 | /* | |
720 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
721 | * @ringbuf: Logical Ringbuffer to advance. | |
722 | * | |
723 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
724 | * really happens during submission is that the context and current tail will be placed | |
725 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
726 | * point, the tail *inside* the context is updated and the ELSP written to. | |
727 | */ | |
728 | static void | |
729 | intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, | |
730 | struct intel_context *ctx, | |
731 | struct drm_i915_gem_request *request) | |
732 | { | |
733 | struct intel_engine_cs *ring = ringbuf->ring; | |
734 | ||
735 | intel_logical_ring_advance(ringbuf); | |
736 | ||
737 | if (intel_ring_stopped(ring)) | |
738 | return; | |
739 | ||
740 | execlists_context_queue(ring, ctx, ringbuf->tail, request); | |
741 | } | |
742 | ||
bc0dce3f JH |
743 | static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, |
744 | struct intel_context *ctx) | |
745 | { | |
746 | uint32_t __iomem *virt; | |
747 | int rem = ringbuf->size - ringbuf->tail; | |
748 | ||
29b1b415 JH |
749 | /* Can't wrap if space has already been reserved! */ |
750 | WARN_ON(ringbuf->reserved_in_use); | |
751 | ||
bc0dce3f JH |
752 | if (ringbuf->space < rem) { |
753 | int ret = logical_ring_wait_for_space(ringbuf, ctx, rem); | |
754 | ||
755 | if (ret) | |
756 | return ret; | |
757 | } | |
758 | ||
759 | virt = ringbuf->virtual_start + ringbuf->tail; | |
760 | rem /= 4; | |
761 | while (rem--) | |
762 | iowrite32(MI_NOOP, virt++); | |
763 | ||
764 | ringbuf->tail = 0; | |
765 | intel_ring_update_space(ringbuf); | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
770 | static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, | |
771 | struct intel_context *ctx, int bytes) | |
772 | { | |
773 | int ret; | |
774 | ||
29b1b415 JH |
775 | /* |
776 | * Add on the reserved size to the request to make sure that after | |
777 | * the intended commands have been emitted, there is guaranteed to | |
778 | * still be enough free space to send them to the hardware. | |
779 | */ | |
780 | if (!ringbuf->reserved_in_use) | |
781 | bytes += ringbuf->reserved_size; | |
782 | ||
bc0dce3f JH |
783 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
784 | ret = logical_ring_wrap_buffer(ringbuf, ctx); | |
785 | if (unlikely(ret)) | |
786 | return ret; | |
29b1b415 JH |
787 | |
788 | if(ringbuf->reserved_size) { | |
789 | uint32_t size = ringbuf->reserved_size; | |
790 | ||
791 | intel_ring_reserved_space_cancel(ringbuf); | |
792 | intel_ring_reserved_space_reserve(ringbuf, size); | |
793 | } | |
bc0dce3f JH |
794 | } |
795 | ||
796 | if (unlikely(ringbuf->space < bytes)) { | |
797 | ret = logical_ring_wait_for_space(ringbuf, ctx, bytes); | |
798 | if (unlikely(ret)) | |
799 | return ret; | |
800 | } | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
805 | /** | |
806 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
807 | * | |
808 | * @ringbuf: Logical ringbuffer. | |
809 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. | |
810 | * | |
811 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
812 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
813 | * and also preallocates a request (every workload submission is still mediated through | |
814 | * requests, same as it did with legacy ringbuffer submission). | |
815 | * | |
816 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
817 | */ | |
818 | static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, | |
819 | struct intel_context *ctx, int num_dwords) | |
820 | { | |
821 | struct intel_engine_cs *ring = ringbuf->ring; | |
822 | struct drm_device *dev = ring->dev; | |
823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
824 | int ret; | |
825 | ||
826 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, | |
827 | dev_priv->mm.interruptible); | |
828 | if (ret) | |
829 | return ret; | |
830 | ||
831 | ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); | |
832 | if (ret) | |
833 | return ret; | |
834 | ||
835 | /* Preallocate the olr before touching the ring */ | |
6689cb2b | 836 | ret = i915_gem_request_alloc(ring, ctx); |
bc0dce3f JH |
837 | if (ret) |
838 | return ret; | |
839 | ||
840 | ringbuf->space -= num_dwords * sizeof(uint32_t); | |
841 | return 0; | |
842 | } | |
843 | ||
73e4d07f OM |
844 | /** |
845 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
846 | * @dev: DRM device. | |
847 | * @file: DRM file. | |
848 | * @ring: Engine Command Streamer to submit to. | |
849 | * @ctx: Context to employ for this submission. | |
850 | * @args: execbuffer call arguments. | |
851 | * @vmas: list of vmas. | |
852 | * @batch_obj: the batchbuffer to submit. | |
853 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 854 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
855 | * |
856 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
857 | * away the submission details of the execbuffer ioctl call. | |
858 | * | |
859 | * Return: non-zero if the submission fails. | |
860 | */ | |
5f19e2bf | 861 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 862 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 863 | struct list_head *vmas) |
454afebd | 864 | { |
5f19e2bf JH |
865 | struct drm_device *dev = params->dev; |
866 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 867 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
868 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
869 | u64 exec_start; | |
ba8b7ccb OM |
870 | int instp_mode; |
871 | u32 instp_mask; | |
872 | int ret; | |
873 | ||
874 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
875 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
876 | switch (instp_mode) { | |
877 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
878 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
879 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
880 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
881 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
885 | if (instp_mode != dev_priv->relative_constants_mode) { | |
886 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
887 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
888 | return -EINVAL; | |
889 | } | |
890 | ||
891 | /* The HW changed the meaning on this bit on gen6 */ | |
892 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
893 | } | |
894 | break; | |
895 | default: | |
896 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
897 | return -EINVAL; | |
898 | } | |
899 | ||
900 | if (args->num_cliprects != 0) { | |
901 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
902 | return -EINVAL; | |
903 | } else { | |
904 | if (args->DR4 == 0xffffffff) { | |
905 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
906 | args->DR4 = 0; | |
907 | } | |
908 | ||
909 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
910 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
911 | return -EINVAL; | |
912 | } | |
913 | } | |
914 | ||
915 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
916 | DRM_DEBUG("sol reset is gen7 only\n"); | |
917 | return -EINVAL; | |
918 | } | |
919 | ||
5f19e2bf | 920 | ret = execlists_move_to_gpu(ringbuf, params->ctx, vmas); |
ba8b7ccb OM |
921 | if (ret) |
922 | return ret; | |
923 | ||
924 | if (ring == &dev_priv->ring[RCS] && | |
925 | instp_mode != dev_priv->relative_constants_mode) { | |
5f19e2bf | 926 | ret = intel_logical_ring_begin(ringbuf, params->ctx, 4); |
ba8b7ccb OM |
927 | if (ret) |
928 | return ret; | |
929 | ||
930 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
931 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
932 | intel_logical_ring_emit(ringbuf, INSTPM); | |
933 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
934 | intel_logical_ring_advance(ringbuf); | |
935 | ||
936 | dev_priv->relative_constants_mode = instp_mode; | |
937 | } | |
938 | ||
5f19e2bf JH |
939 | exec_start = params->batch_obj_vm_offset + |
940 | args->batch_start_offset; | |
941 | ||
942 | ret = ring->emit_bb_start(ringbuf, params->ctx, exec_start, params->dispatch_flags); | |
ba8b7ccb OM |
943 | if (ret) |
944 | return ret; | |
945 | ||
5f19e2bf | 946 | trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), params->dispatch_flags); |
5e4be7bd | 947 | |
ba8b7ccb | 948 | i915_gem_execbuffer_move_to_active(vmas, ring); |
adeca76d | 949 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 950 | |
454afebd OM |
951 | return 0; |
952 | } | |
953 | ||
c86ee3a9 TD |
954 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
955 | { | |
6d3d8274 | 956 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
957 | struct list_head retired_list; |
958 | ||
959 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
960 | if (list_empty(&ring->execlist_retired_req_list)) | |
961 | return; | |
962 | ||
963 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 964 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 965 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 966 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
967 | |
968 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 969 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
970 | struct drm_i915_gem_object *ctx_obj = |
971 | ctx->engine[ring->id].state; | |
972 | ||
973 | if (ctx_obj && (ctx != ring->default_context)) | |
974 | intel_lr_context_unpin(ring, ctx); | |
c86ee3a9 | 975 | list_del(&req->execlist_link); |
f8210795 | 976 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
977 | } |
978 | } | |
979 | ||
454afebd OM |
980 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
981 | { | |
9832b9da OM |
982 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
983 | int ret; | |
984 | ||
985 | if (!intel_ring_initialized(ring)) | |
986 | return; | |
987 | ||
988 | ret = intel_ring_idle(ring); | |
989 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
990 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
991 | ring->name, ret); | |
992 | ||
993 | /* TODO: Is this correct with Execlists enabled? */ | |
994 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
995 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
996 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
997 | return; | |
998 | } | |
999 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
1000 | } |
1001 | ||
21076372 NH |
1002 | int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf, |
1003 | struct intel_context *ctx) | |
48e29f55 OM |
1004 | { |
1005 | struct intel_engine_cs *ring = ringbuf->ring; | |
1006 | int ret; | |
1007 | ||
1008 | if (!ring->gpu_caches_dirty) | |
1009 | return 0; | |
1010 | ||
21076372 | 1011 | ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1012 | if (ret) |
1013 | return ret; | |
1014 | ||
1015 | ring->gpu_caches_dirty = false; | |
1016 | return 0; | |
1017 | } | |
1018 | ||
dcb4c12a OM |
1019 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
1020 | struct intel_context *ctx) | |
1021 | { | |
1022 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1023 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1024 | int ret = 0; |
1025 | ||
1026 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1027 | if (ctx->engine[ring->id].pin_count++ == 0) { |
dcb4c12a OM |
1028 | ret = i915_gem_obj_ggtt_pin(ctx_obj, |
1029 | GEN8_LR_CONTEXT_ALIGN, 0); | |
1030 | if (ret) | |
a7cbedec | 1031 | goto reset_pin_count; |
7ba717cf TD |
1032 | |
1033 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); | |
1034 | if (ret) | |
1035 | goto unpin_ctx_obj; | |
dcb4c12a OM |
1036 | } |
1037 | ||
7ba717cf TD |
1038 | return ret; |
1039 | ||
1040 | unpin_ctx_obj: | |
1041 | i915_gem_object_ggtt_unpin(ctx_obj); | |
a7cbedec MK |
1042 | reset_pin_count: |
1043 | ctx->engine[ring->id].pin_count = 0; | |
7ba717cf | 1044 | |
dcb4c12a OM |
1045 | return ret; |
1046 | } | |
1047 | ||
1048 | void intel_lr_context_unpin(struct intel_engine_cs *ring, | |
1049 | struct intel_context *ctx) | |
1050 | { | |
1051 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1052 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1053 | |
1054 | if (ctx_obj) { | |
1055 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1056 | if (--ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1057 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1058 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1059 | } |
dcb4c12a OM |
1060 | } |
1061 | } | |
1062 | ||
771b9a53 MT |
1063 | static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, |
1064 | struct intel_context *ctx) | |
1065 | { | |
1066 | int ret, i; | |
1067 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1068 | struct drm_device *dev = ring->dev; | |
1069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1071 | ||
e6c1abb7 | 1072 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1073 | return 0; |
1074 | ||
1075 | ring->gpu_caches_dirty = true; | |
21076372 | 1076 | ret = logical_ring_flush_all_caches(ringbuf, ctx); |
771b9a53 MT |
1077 | if (ret) |
1078 | return ret; | |
1079 | ||
21076372 | 1080 | ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2); |
771b9a53 MT |
1081 | if (ret) |
1082 | return ret; | |
1083 | ||
1084 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1085 | for (i = 0; i < w->count; i++) { | |
1086 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1087 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1088 | } | |
1089 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1090 | ||
1091 | intel_logical_ring_advance(ringbuf); | |
1092 | ||
1093 | ring->gpu_caches_dirty = true; | |
21076372 | 1094 | ret = logical_ring_flush_all_caches(ringbuf, ctx); |
771b9a53 MT |
1095 | if (ret) |
1096 | return ret; | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
17ee950d AS |
1101 | #define wa_ctx_emit(batch, cmd) \ |
1102 | do { \ | |
1103 | if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
1104 | return -ENOSPC; \ | |
1105 | } \ | |
1106 | batch[index++] = (cmd); \ | |
1107 | } while (0) | |
1108 | ||
1109 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, | |
1110 | uint32_t offset, | |
1111 | uint32_t start_alignment) | |
1112 | { | |
1113 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1114 | } | |
1115 | ||
1116 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1117 | uint32_t offset, | |
1118 | uint32_t size_alignment) | |
1119 | { | |
1120 | wa_ctx->size = offset - wa_ctx->offset; | |
1121 | ||
1122 | WARN(wa_ctx->size % size_alignment, | |
1123 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1124 | wa_ctx->size, size_alignment); | |
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | /** | |
1129 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1130 | * | |
1131 | * @ring: only applicable for RCS | |
1132 | * @wa_ctx: structure representing wa_ctx | |
1133 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1134 | * with the offset value received as input. | |
1135 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1136 | * @batch: page in which WA are loaded | |
1137 | * @offset: This field specifies the start of the batch, it should be | |
1138 | * cache-aligned otherwise it is adjusted accordingly. | |
1139 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1140 | * initialized at the beginning and shared across all contexts but this field | |
1141 | * helps us to have multiple batches at different offsets and select them based | |
1142 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1143 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1144 | * | |
1145 | * The number of WA applied are not known at the beginning; we use this field | |
1146 | * to return the no of DWORDS written. | |
1147 | ||
1148 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END | |
1149 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1150 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1151 | * makes a complete batch buffer. | |
1152 | * | |
1153 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1154 | */ | |
1155 | ||
1156 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1157 | struct i915_wa_ctx_bb *wa_ctx, | |
1158 | uint32_t *const batch, | |
1159 | uint32_t *offset) | |
1160 | { | |
1161 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1162 | ||
7ad00d1a AS |
1163 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1164 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
17ee950d | 1165 | |
c82435bb AS |
1166 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1167 | if (IS_BROADWELL(ring->dev)) { | |
1168 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
1169 | uint32_t l3sqc4_flush = (I915_READ(GEN8_L3SQCREG4) | | |
1170 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1171 | ||
1172 | wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1)); | |
1173 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1174 | wa_ctx_emit(batch, l3sqc4_flush); | |
1175 | ||
1176 | wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6)); | |
1177 | wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL | | |
1178 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1179 | wa_ctx_emit(batch, 0); | |
1180 | wa_ctx_emit(batch, 0); | |
1181 | wa_ctx_emit(batch, 0); | |
1182 | wa_ctx_emit(batch, 0); | |
1183 | ||
1184 | wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1)); | |
1185 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1186 | wa_ctx_emit(batch, l3sqc4_flush & ~GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1187 | } | |
1188 | ||
17ee950d AS |
1189 | /* Pad to end of cacheline */ |
1190 | while (index % CACHELINE_DWORDS) | |
1191 | wa_ctx_emit(batch, MI_NOOP); | |
1192 | ||
1193 | /* | |
1194 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1195 | * execution depends on the length specified in terms of cache lines | |
1196 | * in the register CTX_RCS_INDIRECT_CTX | |
1197 | */ | |
1198 | ||
1199 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1200 | } | |
1201 | ||
1202 | /** | |
1203 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1204 | * | |
1205 | * @ring: only applicable for RCS | |
1206 | * @wa_ctx: structure representing wa_ctx | |
1207 | * offset: specifies start of the batch, should be cache-aligned. | |
1208 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1209 | * @offset: This field specifies the start of this batch. | |
1210 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1211 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1212 | * | |
1213 | * The number of DWORDS written are returned using this field. | |
1214 | * | |
1215 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1216 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1217 | */ | |
1218 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1219 | struct i915_wa_ctx_bb *wa_ctx, | |
1220 | uint32_t *const batch, | |
1221 | uint32_t *offset) | |
1222 | { | |
1223 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1224 | ||
7ad00d1a AS |
1225 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1226 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1227 | ||
17ee950d AS |
1228 | wa_ctx_emit(batch, MI_BATCH_BUFFER_END); |
1229 | ||
1230 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1231 | } | |
1232 | ||
1233 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) | |
1234 | { | |
1235 | int ret; | |
1236 | ||
1237 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1238 | if (!ring->wa_ctx.obj) { | |
1239 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1240 | return -ENOMEM; | |
1241 | } | |
1242 | ||
1243 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1244 | if (ret) { | |
1245 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1246 | ret); | |
1247 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1248 | return ret; | |
1249 | } | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1255 | { | |
1256 | if (ring->wa_ctx.obj) { | |
1257 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1258 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1259 | ring->wa_ctx.obj = NULL; | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1264 | { | |
1265 | int ret; | |
1266 | uint32_t *batch; | |
1267 | uint32_t offset; | |
1268 | struct page *page; | |
1269 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1270 | ||
1271 | WARN_ON(ring->id != RCS); | |
1272 | ||
c4db7599 AS |
1273 | /* some WA perform writes to scratch page, ensure it is valid */ |
1274 | if (ring->scratch.obj == NULL) { | |
1275 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1276 | return -EINVAL; | |
1277 | } | |
1278 | ||
17ee950d AS |
1279 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1280 | if (ret) { | |
1281 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1286 | batch = kmap_atomic(page); | |
1287 | offset = 0; | |
1288 | ||
1289 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1290 | ret = gen8_init_indirectctx_bb(ring, | |
1291 | &wa_ctx->indirect_ctx, | |
1292 | batch, | |
1293 | &offset); | |
1294 | if (ret) | |
1295 | goto out; | |
1296 | ||
1297 | ret = gen8_init_perctx_bb(ring, | |
1298 | &wa_ctx->per_ctx, | |
1299 | batch, | |
1300 | &offset); | |
1301 | if (ret) | |
1302 | goto out; | |
1303 | } else { | |
1304 | WARN(INTEL_INFO(ring->dev)->gen >= 8, | |
1305 | "WA batch buffer is not initialized for Gen%d\n", | |
1306 | INTEL_INFO(ring->dev)->gen); | |
1307 | lrc_destroy_wa_ctx_obj(ring); | |
1308 | } | |
1309 | ||
1310 | out: | |
1311 | kunmap_atomic(batch); | |
1312 | if (ret) | |
1313 | lrc_destroy_wa_ctx_obj(ring); | |
1314 | ||
1315 | return ret; | |
1316 | } | |
1317 | ||
9b1136d5 OM |
1318 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1319 | { | |
1320 | struct drm_device *dev = ring->dev; | |
1321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1322 | ||
73d477f6 OM |
1323 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1324 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1325 | ||
9b1136d5 OM |
1326 | I915_WRITE(RING_MODE_GEN7(ring), |
1327 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1328 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1329 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1330 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1331 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1332 | ||
1333 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
1338 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1339 | { | |
1340 | struct drm_device *dev = ring->dev; | |
1341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1342 | int ret; | |
1343 | ||
1344 | ret = gen8_init_common_ring(ring); | |
1345 | if (ret) | |
1346 | return ret; | |
1347 | ||
1348 | /* We need to disable the AsyncFlip performance optimisations in order | |
1349 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1350 | * programmed to '1' on all products. | |
1351 | * | |
1352 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1353 | */ | |
1354 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1355 | ||
9b1136d5 OM |
1356 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1357 | ||
771b9a53 | 1358 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1359 | } |
1360 | ||
82ef822e DL |
1361 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1362 | { | |
1363 | int ret; | |
1364 | ||
1365 | ret = gen8_init_common_ring(ring); | |
1366 | if (ret) | |
1367 | return ret; | |
1368 | ||
1369 | return init_workarounds_ring(ring); | |
1370 | } | |
1371 | ||
15648585 | 1372 | static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, |
21076372 | 1373 | struct intel_context *ctx, |
8e004efc | 1374 | u64 offset, unsigned dispatch_flags) |
15648585 | 1375 | { |
8e004efc | 1376 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1377 | int ret; |
1378 | ||
21076372 | 1379 | ret = intel_logical_ring_begin(ringbuf, ctx, 4); |
15648585 OM |
1380 | if (ret) |
1381 | return ret; | |
1382 | ||
1383 | /* FIXME(BDW): Address space and security selectors. */ | |
1384 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); | |
1385 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); | |
1386 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1387 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1388 | intel_logical_ring_advance(ringbuf); | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
73d477f6 OM |
1393 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1394 | { | |
1395 | struct drm_device *dev = ring->dev; | |
1396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1397 | unsigned long flags; | |
1398 | ||
7cd512f1 | 1399 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1400 | return false; |
1401 | ||
1402 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1403 | if (ring->irq_refcount++ == 0) { | |
1404 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1405 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1406 | } | |
1407 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1408 | ||
1409 | return true; | |
1410 | } | |
1411 | ||
1412 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1413 | { | |
1414 | struct drm_device *dev = ring->dev; | |
1415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1416 | unsigned long flags; | |
1417 | ||
1418 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1419 | if (--ring->irq_refcount == 0) { | |
1420 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1421 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1422 | } | |
1423 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1424 | } | |
1425 | ||
4712274c | 1426 | static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, |
21076372 | 1427 | struct intel_context *ctx, |
4712274c OM |
1428 | u32 invalidate_domains, |
1429 | u32 unused) | |
1430 | { | |
1431 | struct intel_engine_cs *ring = ringbuf->ring; | |
1432 | struct drm_device *dev = ring->dev; | |
1433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1434 | uint32_t cmd; | |
1435 | int ret; | |
1436 | ||
21076372 | 1437 | ret = intel_logical_ring_begin(ringbuf, ctx, 4); |
4712274c OM |
1438 | if (ret) |
1439 | return ret; | |
1440 | ||
1441 | cmd = MI_FLUSH_DW + 1; | |
1442 | ||
f0a1fb10 CW |
1443 | /* We always require a command barrier so that subsequent |
1444 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1445 | * wrt the contents of the write cache being flushed to memory | |
1446 | * (and thus being coherent from the CPU). | |
1447 | */ | |
1448 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1449 | ||
1450 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1451 | cmd |= MI_INVALIDATE_TLB; | |
1452 | if (ring == &dev_priv->ring[VCS]) | |
1453 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1454 | } |
1455 | ||
1456 | intel_logical_ring_emit(ringbuf, cmd); | |
1457 | intel_logical_ring_emit(ringbuf, | |
1458 | I915_GEM_HWS_SCRATCH_ADDR | | |
1459 | MI_FLUSH_DW_USE_GTT); | |
1460 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1461 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1462 | intel_logical_ring_advance(ringbuf); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, | |
21076372 | 1468 | struct intel_context *ctx, |
4712274c OM |
1469 | u32 invalidate_domains, |
1470 | u32 flush_domains) | |
1471 | { | |
1472 | struct intel_engine_cs *ring = ringbuf->ring; | |
1473 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1474 | bool vf_flush_wa; |
4712274c OM |
1475 | u32 flags = 0; |
1476 | int ret; | |
1477 | ||
1478 | flags |= PIPE_CONTROL_CS_STALL; | |
1479 | ||
1480 | if (flush_domains) { | |
1481 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1482 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1483 | } | |
1484 | ||
1485 | if (invalidate_domains) { | |
1486 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1487 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1488 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1489 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1490 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1491 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1492 | flags |= PIPE_CONTROL_QW_WRITE; | |
1493 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1494 | } | |
1495 | ||
9647ff36 ID |
1496 | /* |
1497 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1498 | * control. | |
1499 | */ | |
1500 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1501 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1502 | ||
1503 | ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6); | |
4712274c OM |
1504 | if (ret) |
1505 | return ret; | |
1506 | ||
9647ff36 ID |
1507 | if (vf_flush_wa) { |
1508 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1509 | intel_logical_ring_emit(ringbuf, 0); | |
1510 | intel_logical_ring_emit(ringbuf, 0); | |
1511 | intel_logical_ring_emit(ringbuf, 0); | |
1512 | intel_logical_ring_emit(ringbuf, 0); | |
1513 | intel_logical_ring_emit(ringbuf, 0); | |
1514 | } | |
1515 | ||
4712274c OM |
1516 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1517 | intel_logical_ring_emit(ringbuf, flags); | |
1518 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1519 | intel_logical_ring_emit(ringbuf, 0); | |
1520 | intel_logical_ring_emit(ringbuf, 0); | |
1521 | intel_logical_ring_emit(ringbuf, 0); | |
1522 | intel_logical_ring_advance(ringbuf); | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
e94e37ad OM |
1527 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1528 | { | |
1529 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1530 | } | |
1531 | ||
1532 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1533 | { | |
1534 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1535 | } | |
1536 | ||
2d12955a NH |
1537 | static int gen8_emit_request(struct intel_ringbuffer *ringbuf, |
1538 | struct drm_i915_gem_request *request) | |
4da46e1e OM |
1539 | { |
1540 | struct intel_engine_cs *ring = ringbuf->ring; | |
1541 | u32 cmd; | |
1542 | int ret; | |
1543 | ||
53292cdb MT |
1544 | /* |
1545 | * Reserve space for 2 NOOPs at the end of each request to be | |
1546 | * used as a workaround for not being allowed to do lite | |
1547 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1548 | */ | |
1549 | ret = intel_logical_ring_begin(ringbuf, request->ctx, 8); | |
4da46e1e OM |
1550 | if (ret) |
1551 | return ret; | |
1552 | ||
8edfbb8b | 1553 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1554 | cmd |= MI_GLOBAL_GTT; |
1555 | ||
1556 | intel_logical_ring_emit(ringbuf, cmd); | |
1557 | intel_logical_ring_emit(ringbuf, | |
1558 | (ring->status_page.gfx_addr + | |
1559 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1560 | intel_logical_ring_emit(ringbuf, 0); | |
6259cead JH |
1561 | intel_logical_ring_emit(ringbuf, |
1562 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
4da46e1e OM |
1563 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1564 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
21076372 | 1565 | intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request); |
4da46e1e | 1566 | |
53292cdb MT |
1567 | /* |
1568 | * Here we add two extra NOOPs as padding to avoid | |
1569 | * lite restore of a context with HEAD==TAIL. | |
1570 | */ | |
1571 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1572 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1573 | intel_logical_ring_advance(ringbuf); | |
1574 | ||
4da46e1e OM |
1575 | return 0; |
1576 | } | |
1577 | ||
cef437ad DL |
1578 | static int intel_lr_context_render_state_init(struct intel_engine_cs *ring, |
1579 | struct intel_context *ctx) | |
1580 | { | |
1581 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; | |
1582 | struct render_state so; | |
1583 | struct drm_i915_file_private *file_priv = ctx->file_priv; | |
1584 | struct drm_file *file = file_priv ? file_priv->file : NULL; | |
1585 | int ret; | |
1586 | ||
1587 | ret = i915_gem_render_state_prepare(ring, &so); | |
1588 | if (ret) | |
1589 | return ret; | |
1590 | ||
1591 | if (so.rodata == NULL) | |
1592 | return 0; | |
1593 | ||
1594 | ret = ring->emit_bb_start(ringbuf, | |
1595 | ctx, | |
1596 | so.ggtt_offset, | |
1597 | I915_DISPATCH_SECURE); | |
1598 | if (ret) | |
1599 | goto out; | |
1600 | ||
1601 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); | |
1602 | ||
bf7dc5b7 | 1603 | __i915_add_request(ring, file, so.obj); |
cef437ad DL |
1604 | /* intel_logical_ring_add_request moves object to inactive if it |
1605 | * fails */ | |
1606 | out: | |
1607 | i915_gem_render_state_fini(&so); | |
1608 | return ret; | |
1609 | } | |
1610 | ||
e7778be1 TD |
1611 | static int gen8_init_rcs_context(struct intel_engine_cs *ring, |
1612 | struct intel_context *ctx) | |
1613 | { | |
1614 | int ret; | |
1615 | ||
1616 | ret = intel_logical_ring_workarounds_emit(ring, ctx); | |
1617 | if (ret) | |
1618 | return ret; | |
1619 | ||
1620 | return intel_lr_context_render_state_init(ring, ctx); | |
1621 | } | |
1622 | ||
73e4d07f OM |
1623 | /** |
1624 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1625 | * | |
1626 | * @ring: Engine Command Streamer. | |
1627 | * | |
1628 | */ | |
454afebd OM |
1629 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1630 | { | |
6402c330 | 1631 | struct drm_i915_private *dev_priv; |
9832b9da | 1632 | |
48d82387 OM |
1633 | if (!intel_ring_initialized(ring)) |
1634 | return; | |
1635 | ||
6402c330 JH |
1636 | dev_priv = ring->dev->dev_private; |
1637 | ||
9832b9da OM |
1638 | intel_logical_ring_stop(ring); |
1639 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
6259cead | 1640 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
48d82387 OM |
1641 | |
1642 | if (ring->cleanup) | |
1643 | ring->cleanup(ring); | |
1644 | ||
1645 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1646 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1647 | |
1648 | if (ring->status_page.obj) { | |
1649 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1650 | ring->status_page.obj = NULL; | |
1651 | } | |
17ee950d AS |
1652 | |
1653 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1654 | } |
1655 | ||
1656 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1657 | { | |
48d82387 | 1658 | int ret; |
48d82387 OM |
1659 | |
1660 | /* Intentionally left blank. */ | |
1661 | ring->buffer = NULL; | |
1662 | ||
1663 | ring->dev = dev; | |
1664 | INIT_LIST_HEAD(&ring->active_list); | |
1665 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1666 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1667 | init_waitqueue_head(&ring->irq_queue); |
1668 | ||
acdd884a | 1669 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1670 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1671 | spin_lock_init(&ring->execlist_lock); |
1672 | ||
48d82387 OM |
1673 | ret = i915_cmd_parser_init_ring(ring); |
1674 | if (ret) | |
1675 | return ret; | |
1676 | ||
564ddb2f OM |
1677 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1678 | ||
1679 | return ret; | |
454afebd OM |
1680 | } |
1681 | ||
1682 | static int logical_render_ring_init(struct drm_device *dev) | |
1683 | { | |
1684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1685 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1686 | int ret; |
454afebd OM |
1687 | |
1688 | ring->name = "render ring"; | |
1689 | ring->id = RCS; | |
1690 | ring->mmio_base = RENDER_RING_BASE; | |
1691 | ring->irq_enable_mask = | |
1692 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1693 | ring->irq_keep_mask = |
1694 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1695 | if (HAS_L3_DPF(dev)) | |
1696 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1697 | |
82ef822e DL |
1698 | if (INTEL_INFO(dev)->gen >= 9) |
1699 | ring->init_hw = gen9_init_render_ring; | |
1700 | else | |
1701 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1702 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1703 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1704 | ring->get_seqno = gen8_get_seqno; |
1705 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1706 | ring->emit_request = gen8_emit_request; |
4712274c | 1707 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1708 | ring->irq_get = gen8_logical_ring_get_irq; |
1709 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1710 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1711 | |
99be1dfe | 1712 | ring->dev = dev; |
c4db7599 AS |
1713 | |
1714 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1715 | if (ret) |
1716 | return ret; | |
1717 | ||
17ee950d AS |
1718 | ret = intel_init_workaround_bb(ring); |
1719 | if (ret) { | |
1720 | /* | |
1721 | * We continue even if we fail to initialize WA batch | |
1722 | * because we only expect rare glitches but nothing | |
1723 | * critical to prevent us from using GPU | |
1724 | */ | |
1725 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1726 | ret); | |
1727 | } | |
1728 | ||
c4db7599 AS |
1729 | ret = logical_ring_init(dev, ring); |
1730 | if (ret) { | |
17ee950d | 1731 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1732 | } |
17ee950d AS |
1733 | |
1734 | return ret; | |
454afebd OM |
1735 | } |
1736 | ||
1737 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1738 | { | |
1739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1740 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1741 | ||
1742 | ring->name = "bsd ring"; | |
1743 | ring->id = VCS; | |
1744 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1745 | ring->irq_enable_mask = | |
1746 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1747 | ring->irq_keep_mask = |
1748 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1749 | |
ecfe00d8 | 1750 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1751 | ring->get_seqno = gen8_get_seqno; |
1752 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1753 | ring->emit_request = gen8_emit_request; |
4712274c | 1754 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1755 | ring->irq_get = gen8_logical_ring_get_irq; |
1756 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1757 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1758 | |
454afebd OM |
1759 | return logical_ring_init(dev, ring); |
1760 | } | |
1761 | ||
1762 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1763 | { | |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1765 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1766 | ||
1767 | ring->name = "bds2 ring"; | |
1768 | ring->id = VCS2; | |
1769 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1770 | ring->irq_enable_mask = | |
1771 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1772 | ring->irq_keep_mask = |
1773 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1774 | |
ecfe00d8 | 1775 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1776 | ring->get_seqno = gen8_get_seqno; |
1777 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1778 | ring->emit_request = gen8_emit_request; |
4712274c | 1779 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1780 | ring->irq_get = gen8_logical_ring_get_irq; |
1781 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1782 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1783 | |
454afebd OM |
1784 | return logical_ring_init(dev, ring); |
1785 | } | |
1786 | ||
1787 | static int logical_blt_ring_init(struct drm_device *dev) | |
1788 | { | |
1789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1790 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1791 | ||
1792 | ring->name = "blitter ring"; | |
1793 | ring->id = BCS; | |
1794 | ring->mmio_base = BLT_RING_BASE; | |
1795 | ring->irq_enable_mask = | |
1796 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1797 | ring->irq_keep_mask = |
1798 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1799 | |
ecfe00d8 | 1800 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1801 | ring->get_seqno = gen8_get_seqno; |
1802 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1803 | ring->emit_request = gen8_emit_request; |
4712274c | 1804 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1805 | ring->irq_get = gen8_logical_ring_get_irq; |
1806 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1807 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1808 | |
454afebd OM |
1809 | return logical_ring_init(dev, ring); |
1810 | } | |
1811 | ||
1812 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1813 | { | |
1814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1815 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1816 | ||
1817 | ring->name = "video enhancement ring"; | |
1818 | ring->id = VECS; | |
1819 | ring->mmio_base = VEBOX_RING_BASE; | |
1820 | ring->irq_enable_mask = | |
1821 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1822 | ring->irq_keep_mask = |
1823 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1824 | |
ecfe00d8 | 1825 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1826 | ring->get_seqno = gen8_get_seqno; |
1827 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1828 | ring->emit_request = gen8_emit_request; |
4712274c | 1829 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1830 | ring->irq_get = gen8_logical_ring_get_irq; |
1831 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1832 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1833 | |
454afebd OM |
1834 | return logical_ring_init(dev, ring); |
1835 | } | |
1836 | ||
73e4d07f OM |
1837 | /** |
1838 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1839 | * @dev: DRM device. | |
1840 | * | |
1841 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1842 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1843 | * those engines that are present in the hardware. | |
1844 | * | |
1845 | * Return: non-zero if the initialization failed. | |
1846 | */ | |
454afebd OM |
1847 | int intel_logical_rings_init(struct drm_device *dev) |
1848 | { | |
1849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1850 | int ret; | |
1851 | ||
1852 | ret = logical_render_ring_init(dev); | |
1853 | if (ret) | |
1854 | return ret; | |
1855 | ||
1856 | if (HAS_BSD(dev)) { | |
1857 | ret = logical_bsd_ring_init(dev); | |
1858 | if (ret) | |
1859 | goto cleanup_render_ring; | |
1860 | } | |
1861 | ||
1862 | if (HAS_BLT(dev)) { | |
1863 | ret = logical_blt_ring_init(dev); | |
1864 | if (ret) | |
1865 | goto cleanup_bsd_ring; | |
1866 | } | |
1867 | ||
1868 | if (HAS_VEBOX(dev)) { | |
1869 | ret = logical_vebox_ring_init(dev); | |
1870 | if (ret) | |
1871 | goto cleanup_blt_ring; | |
1872 | } | |
1873 | ||
1874 | if (HAS_BSD2(dev)) { | |
1875 | ret = logical_bsd2_ring_init(dev); | |
1876 | if (ret) | |
1877 | goto cleanup_vebox_ring; | |
1878 | } | |
1879 | ||
1880 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1881 | if (ret) | |
1882 | goto cleanup_bsd2_ring; | |
1883 | ||
1884 | return 0; | |
1885 | ||
1886 | cleanup_bsd2_ring: | |
1887 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1888 | cleanup_vebox_ring: | |
1889 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1890 | cleanup_blt_ring: | |
1891 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1892 | cleanup_bsd_ring: | |
1893 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1894 | cleanup_render_ring: | |
1895 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1896 | ||
1897 | return ret; | |
1898 | } | |
1899 | ||
0cea6502 JM |
1900 | static u32 |
1901 | make_rpcs(struct drm_device *dev) | |
1902 | { | |
1903 | u32 rpcs = 0; | |
1904 | ||
1905 | /* | |
1906 | * No explicit RPCS request is needed to ensure full | |
1907 | * slice/subslice/EU enablement prior to Gen9. | |
1908 | */ | |
1909 | if (INTEL_INFO(dev)->gen < 9) | |
1910 | return 0; | |
1911 | ||
1912 | /* | |
1913 | * Starting in Gen9, render power gating can leave | |
1914 | * slice/subslice/EU in a partially enabled state. We | |
1915 | * must make an explicit request through RPCS for full | |
1916 | * enablement. | |
1917 | */ | |
1918 | if (INTEL_INFO(dev)->has_slice_pg) { | |
1919 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
1920 | rpcs |= INTEL_INFO(dev)->slice_total << | |
1921 | GEN8_RPCS_S_CNT_SHIFT; | |
1922 | rpcs |= GEN8_RPCS_ENABLE; | |
1923 | } | |
1924 | ||
1925 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
1926 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
1927 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
1928 | GEN8_RPCS_SS_CNT_SHIFT; | |
1929 | rpcs |= GEN8_RPCS_ENABLE; | |
1930 | } | |
1931 | ||
1932 | if (INTEL_INFO(dev)->has_eu_pg) { | |
1933 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1934 | GEN8_RPCS_EU_MIN_SHIFT; | |
1935 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1936 | GEN8_RPCS_EU_MAX_SHIFT; | |
1937 | rpcs |= GEN8_RPCS_ENABLE; | |
1938 | } | |
1939 | ||
1940 | return rpcs; | |
1941 | } | |
1942 | ||
8670d6f9 OM |
1943 | static int |
1944 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
1945 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
1946 | { | |
2d965536 TD |
1947 | struct drm_device *dev = ring->dev; |
1948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 1949 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
1950 | struct page *page; |
1951 | uint32_t *reg_state; | |
1952 | int ret; | |
1953 | ||
2d965536 TD |
1954 | if (!ppgtt) |
1955 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1956 | ||
8670d6f9 OM |
1957 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1958 | if (ret) { | |
1959 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1960 | return ret; | |
1961 | } | |
1962 | ||
1963 | ret = i915_gem_object_get_pages(ctx_obj); | |
1964 | if (ret) { | |
1965 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
1966 | return ret; | |
1967 | } | |
1968 | ||
1969 | i915_gem_object_pin_pages(ctx_obj); | |
1970 | ||
1971 | /* The second page of the context object contains some fields which must | |
1972 | * be set up prior to the first execution. */ | |
1973 | page = i915_gem_object_get_page(ctx_obj, 1); | |
1974 | reg_state = kmap_atomic(page); | |
1975 | ||
1976 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1977 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1978 | * only for the first context restore: on a subsequent save, the GPU will | |
1979 | * recreate this batchbuffer with new values (including all the missing | |
1980 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
1981 | if (ring->id == RCS) | |
1982 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
1983 | else | |
1984 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
1985 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
1986 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
1987 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 ZW |
1988 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1989 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); | |
8670d6f9 OM |
1990 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
1991 | reg_state[CTX_RING_HEAD+1] = 0; | |
1992 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
1993 | reg_state[CTX_RING_TAIL+1] = 0; | |
1994 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
1995 | /* Ring buffer start address is not known until the buffer is pinned. |
1996 | * It is written to the context image in execlists_update_context() | |
1997 | */ | |
8670d6f9 OM |
1998 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
1999 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
2000 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
2001 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
2002 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
2003 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
2004 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
2005 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
2006 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
2007 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
2008 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
2009 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
2010 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
2011 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
2012 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
2013 | if (ring->id == RCS) { | |
8670d6f9 OM |
2014 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
2015 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
2016 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
2017 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
2018 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
2019 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
2020 | if (ring->wa_ctx.obj) { |
2021 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2022 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2023 | ||
2024 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2025 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2026 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2027 | ||
2028 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2029 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2030 | ||
2031 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2032 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2033 | 0x01; | |
2034 | } | |
8670d6f9 OM |
2035 | } |
2036 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2037 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2038 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2039 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2040 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2041 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2042 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2043 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2044 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2045 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2046 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2047 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d MT |
2048 | |
2049 | /* With dynamic page allocation, PDPs may not be allocated at this point, | |
2050 | * Point the unallocated PDPs to the scratch page | |
e5815a2e MT |
2051 | */ |
2052 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2053 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2054 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2055 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
8670d6f9 OM |
2056 | if (ring->id == RCS) { |
2057 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2058 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2059 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2060 | } |
2061 | ||
2062 | kunmap_atomic(reg_state); | |
2063 | ||
2064 | ctx_obj->dirty = 1; | |
2065 | set_page_dirty(page); | |
2066 | i915_gem_object_unpin_pages(ctx_obj); | |
2067 | ||
2068 | return 0; | |
2069 | } | |
2070 | ||
73e4d07f OM |
2071 | /** |
2072 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2073 | * @ctx: the LR context to free. | |
2074 | * | |
2075 | * The real context freeing is done in i915_gem_context_free: this only | |
2076 | * takes care of the bits that are LRC related: the per-engine backing | |
2077 | * objects and the logical ringbuffer. | |
2078 | */ | |
ede7d42b OM |
2079 | void intel_lr_context_free(struct intel_context *ctx) |
2080 | { | |
8c857917 OM |
2081 | int i; |
2082 | ||
2083 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2084 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2085 | |
8c857917 | 2086 | if (ctx_obj) { |
dcb4c12a OM |
2087 | struct intel_ringbuffer *ringbuf = |
2088 | ctx->engine[i].ringbuf; | |
2089 | struct intel_engine_cs *ring = ringbuf->ring; | |
2090 | ||
7ba717cf TD |
2091 | if (ctx == ring->default_context) { |
2092 | intel_unpin_ringbuffer_obj(ringbuf); | |
2093 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2094 | } | |
a7cbedec | 2095 | WARN_ON(ctx->engine[ring->id].pin_count); |
84c2377f OM |
2096 | intel_destroy_ringbuffer_obj(ringbuf); |
2097 | kfree(ringbuf); | |
8c857917 OM |
2098 | drm_gem_object_unreference(&ctx_obj->base); |
2099 | } | |
2100 | } | |
2101 | } | |
2102 | ||
2103 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2104 | { | |
2105 | int ret = 0; | |
2106 | ||
468c6816 | 2107 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2108 | |
2109 | switch (ring->id) { | |
2110 | case RCS: | |
468c6816 MN |
2111 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2112 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2113 | else | |
2114 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2115 | break; |
2116 | case VCS: | |
2117 | case BCS: | |
2118 | case VECS: | |
2119 | case VCS2: | |
2120 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2121 | break; | |
2122 | } | |
2123 | ||
2124 | return ret; | |
ede7d42b OM |
2125 | } |
2126 | ||
70b0ea86 | 2127 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2128 | struct drm_i915_gem_object *default_ctx_obj) |
2129 | { | |
2130 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2131 | ||
2132 | /* The status page is offset 0 from the default context object | |
2133 | * in LRC mode. */ | |
2134 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
2135 | ring->status_page.page_addr = | |
2136 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1df06b75 TD |
2137 | ring->status_page.obj = default_ctx_obj; |
2138 | ||
2139 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2140 | (u32)ring->status_page.gfx_addr); | |
2141 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2142 | } |
2143 | ||
73e4d07f OM |
2144 | /** |
2145 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
2146 | * @ctx: LR context to create. | |
2147 | * @ring: engine to be used with the context. | |
2148 | * | |
2149 | * This function can be called more than once, with different engines, if we plan | |
2150 | * to use the context with them. The context backing objects and the ringbuffers | |
2151 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2152 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2153 | * a given ring with the context. | |
2154 | * | |
32197aab | 2155 | * Return: non-zero on error. |
73e4d07f | 2156 | */ |
ede7d42b OM |
2157 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
2158 | struct intel_engine_cs *ring) | |
2159 | { | |
dcb4c12a | 2160 | const bool is_global_default_ctx = (ctx == ring->default_context); |
8c857917 OM |
2161 | struct drm_device *dev = ring->dev; |
2162 | struct drm_i915_gem_object *ctx_obj; | |
2163 | uint32_t context_size; | |
84c2377f | 2164 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2165 | int ret; |
2166 | ||
ede7d42b | 2167 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2168 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2169 | |
8c857917 OM |
2170 | context_size = round_up(get_lr_context_size(ring), 4096); |
2171 | ||
149c86e7 | 2172 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2173 | if (!ctx_obj) { |
2174 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2175 | return -ENOMEM; | |
8c857917 OM |
2176 | } |
2177 | ||
dcb4c12a OM |
2178 | if (is_global_default_ctx) { |
2179 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
2180 | if (ret) { | |
2181 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", | |
2182 | ret); | |
2183 | drm_gem_object_unreference(&ctx_obj->base); | |
2184 | return ret; | |
2185 | } | |
8c857917 OM |
2186 | } |
2187 | ||
84c2377f OM |
2188 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
2189 | if (!ringbuf) { | |
2190 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2191 | ring->name); | |
84c2377f | 2192 | ret = -ENOMEM; |
7ba717cf | 2193 | goto error_unpin_ctx; |
84c2377f OM |
2194 | } |
2195 | ||
0c7dd53b | 2196 | ringbuf->ring = ring; |
582d67f0 | 2197 | |
84c2377f OM |
2198 | ringbuf->size = 32 * PAGE_SIZE; |
2199 | ringbuf->effective_size = ringbuf->size; | |
2200 | ringbuf->head = 0; | |
2201 | ringbuf->tail = 0; | |
84c2377f | 2202 | ringbuf->last_retired_head = -1; |
ebd0fd4b | 2203 | intel_ring_update_space(ringbuf); |
84c2377f | 2204 | |
7ba717cf TD |
2205 | if (ringbuf->obj == NULL) { |
2206 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
2207 | if (ret) { | |
2208 | DRM_DEBUG_DRIVER( | |
2209 | "Failed to allocate ringbuffer obj %s: %d\n", | |
84c2377f | 2210 | ring->name, ret); |
7ba717cf TD |
2211 | goto error_free_rbuf; |
2212 | } | |
2213 | ||
2214 | if (is_global_default_ctx) { | |
2215 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
2216 | if (ret) { | |
2217 | DRM_ERROR( | |
2218 | "Failed to pin and map ringbuffer %s: %d\n", | |
2219 | ring->name, ret); | |
2220 | goto error_destroy_rbuf; | |
2221 | } | |
2222 | } | |
2223 | ||
8670d6f9 OM |
2224 | } |
2225 | ||
2226 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2227 | if (ret) { | |
2228 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
8670d6f9 | 2229 | goto error; |
84c2377f OM |
2230 | } |
2231 | ||
2232 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2233 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2234 | |
70b0ea86 DV |
2235 | if (ctx == ring->default_context) |
2236 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
e7778be1 | 2237 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
771b9a53 MT |
2238 | if (ring->init_context) { |
2239 | ret = ring->init_context(ring, ctx); | |
e7778be1 | 2240 | if (ret) { |
771b9a53 | 2241 | DRM_ERROR("ring init context: %d\n", ret); |
e7778be1 TD |
2242 | ctx->engine[ring->id].ringbuf = NULL; |
2243 | ctx->engine[ring->id].state = NULL; | |
2244 | goto error; | |
2245 | } | |
771b9a53 MT |
2246 | } |
2247 | ||
564ddb2f OM |
2248 | ctx->rcs_initialized = true; |
2249 | } | |
2250 | ||
ede7d42b | 2251 | return 0; |
8670d6f9 OM |
2252 | |
2253 | error: | |
7ba717cf TD |
2254 | if (is_global_default_ctx) |
2255 | intel_unpin_ringbuffer_obj(ringbuf); | |
2256 | error_destroy_rbuf: | |
2257 | intel_destroy_ringbuffer_obj(ringbuf); | |
2258 | error_free_rbuf: | |
8670d6f9 | 2259 | kfree(ringbuf); |
7ba717cf | 2260 | error_unpin_ctx: |
dcb4c12a OM |
2261 | if (is_global_default_ctx) |
2262 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8670d6f9 OM |
2263 | drm_gem_object_unreference(&ctx_obj->base); |
2264 | return ret; | |
ede7d42b | 2265 | } |
3e5b6f05 TD |
2266 | |
2267 | void intel_lr_context_reset(struct drm_device *dev, | |
2268 | struct intel_context *ctx) | |
2269 | { | |
2270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2271 | struct intel_engine_cs *ring; | |
2272 | int i; | |
2273 | ||
2274 | for_each_ring(ring, dev_priv, i) { | |
2275 | struct drm_i915_gem_object *ctx_obj = | |
2276 | ctx->engine[ring->id].state; | |
2277 | struct intel_ringbuffer *ringbuf = | |
2278 | ctx->engine[ring->id].ringbuf; | |
2279 | uint32_t *reg_state; | |
2280 | struct page *page; | |
2281 | ||
2282 | if (!ctx_obj) | |
2283 | continue; | |
2284 | ||
2285 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2286 | WARN(1, "Failed get_pages for context obj\n"); | |
2287 | continue; | |
2288 | } | |
2289 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2290 | reg_state = kmap_atomic(page); | |
2291 | ||
2292 | reg_state[CTX_RING_HEAD+1] = 0; | |
2293 | reg_state[CTX_RING_TAIL+1] = 0; | |
2294 | ||
2295 | kunmap_atomic(reg_state); | |
2296 | ||
2297 | ringbuf->head = 0; | |
2298 | ringbuf->tail = 0; | |
2299 | } | |
2300 | } |