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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
3bbaba0c | 138 | #include "intel_mocs.h" |
127f1003 | 139 | |
468c6816 | 140 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
141 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
142 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
143 | ||
e981e7b1 TD |
144 | #define RING_EXECLIST_QFULL (1 << 0x2) |
145 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
146 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
147 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
148 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
149 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
150 | ||
151 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
152 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
153 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
154 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
155 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
156 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
157 | |
158 | #define CTX_LRI_HEADER_0 0x01 | |
159 | #define CTX_CONTEXT_CONTROL 0x02 | |
160 | #define CTX_RING_HEAD 0x04 | |
161 | #define CTX_RING_TAIL 0x06 | |
162 | #define CTX_RING_BUFFER_START 0x08 | |
163 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
164 | #define CTX_BB_HEAD_U 0x0c | |
165 | #define CTX_BB_HEAD_L 0x0e | |
166 | #define CTX_BB_STATE 0x10 | |
167 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
168 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
169 | #define CTX_SECOND_BB_STATE 0x16 | |
170 | #define CTX_BB_PER_CTX_PTR 0x18 | |
171 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
172 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
173 | #define CTX_LRI_HEADER_1 0x21 | |
174 | #define CTX_CTX_TIMESTAMP 0x22 | |
175 | #define CTX_PDP3_UDW 0x24 | |
176 | #define CTX_PDP3_LDW 0x26 | |
177 | #define CTX_PDP2_UDW 0x28 | |
178 | #define CTX_PDP2_LDW 0x2a | |
179 | #define CTX_PDP1_UDW 0x2c | |
180 | #define CTX_PDP1_LDW 0x2e | |
181 | #define CTX_PDP0_UDW 0x30 | |
182 | #define CTX_PDP0_LDW 0x32 | |
183 | #define CTX_LRI_HEADER_2 0x41 | |
184 | #define CTX_R_PWR_CLK_STATE 0x42 | |
185 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
186 | ||
84b790f8 BW |
187 | #define GEN8_CTX_VALID (1<<0) |
188 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
189 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
190 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
191 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 192 | |
0d925ea0 | 193 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 194 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
195 | (reg_state)[(pos)+1] = (val); \ |
196 | } while (0) | |
197 | ||
198 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 199 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
200 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
201 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 202 | } while (0) |
e5815a2e | 203 | |
9244a817 | 204 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
205 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
206 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 207 | } while (0) |
2dba3239 | 208 | |
84b790f8 BW |
209 | enum { |
210 | ADVANCED_CONTEXT = 0, | |
2dba3239 | 211 | LEGACY_32B_CONTEXT, |
84b790f8 BW |
212 | ADVANCED_AD_CONTEXT, |
213 | LEGACY_64B_CONTEXT | |
214 | }; | |
2dba3239 MT |
215 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
216 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ | |
217 | LEGACY_64B_CONTEXT :\ | |
218 | LEGACY_32B_CONTEXT) | |
84b790f8 BW |
219 | enum { |
220 | FAULT_AND_HANG = 0, | |
221 | FAULT_AND_HALT, /* Debug only */ | |
222 | FAULT_AND_STREAM, | |
223 | FAULT_AND_CONTINUE /* Unsupported */ | |
224 | }; | |
225 | #define GEN8_CTX_ID_SHIFT 32 | |
71562919 MT |
226 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
227 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 228 | |
e5292823 TU |
229 | static int intel_lr_context_pin(struct intel_context *ctx, |
230 | struct intel_engine_cs *engine); | |
0bc40be8 TU |
231 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, |
232 | struct drm_i915_gem_object *default_ctx_obj); | |
e84fe803 | 233 | |
7ba717cf | 234 | |
73e4d07f OM |
235 | /** |
236 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
237 | * @dev: DRM device. | |
238 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
239 | * | |
240 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 241 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
242 | * |
243 | * Return: 1 if Execlists is supported and has to be enabled. | |
244 | */ | |
127f1003 OM |
245 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
246 | { | |
bd84b1e9 DV |
247 | WARN_ON(i915.enable_ppgtt == -1); |
248 | ||
a0bd6c31 ZL |
249 | /* On platforms with execlist available, vGPU will only |
250 | * support execlist mode, no ring buffer mode. | |
251 | */ | |
252 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) | |
253 | return 1; | |
254 | ||
70ee45e1 DL |
255 | if (INTEL_INFO(dev)->gen >= 9) |
256 | return 1; | |
257 | ||
127f1003 OM |
258 | if (enable_execlists == 0) |
259 | return 0; | |
260 | ||
14bf993e OM |
261 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
262 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
263 | return 1; |
264 | ||
265 | return 0; | |
266 | } | |
ede7d42b | 267 | |
ca82580c | 268 | static void |
0bc40be8 | 269 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 270 | { |
0bc40be8 | 271 | struct drm_device *dev = engine->dev; |
ca82580c | 272 | |
c6a2ac71 | 273 | if (IS_GEN8(dev) || IS_GEN9(dev)) |
0bc40be8 | 274 | engine->idle_lite_restore_wa = ~0; |
c6a2ac71 | 275 | |
0bc40be8 | 276 | engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
ca82580c | 277 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) && |
0bc40be8 | 278 | (engine->id == VCS || engine->id == VCS2); |
ca82580c | 279 | |
0bc40be8 TU |
280 | engine->ctx_desc_template = GEN8_CTX_VALID; |
281 | engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) << | |
ca82580c TU |
282 | GEN8_CTX_ADDRESSING_MODE_SHIFT; |
283 | if (IS_GEN8(dev)) | |
0bc40be8 TU |
284 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
285 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
286 | |
287 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
288 | * signalling between Command Streamers */ | |
289 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
290 | ||
291 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
292 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
293 | if (engine->disable_lite_restore_wa) |
294 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
295 | } |
296 | ||
73e4d07f | 297 | /** |
ca82580c TU |
298 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
299 | * descriptor for a pinned context | |
73e4d07f | 300 | * |
ca82580c TU |
301 | * @ctx: Context to work on |
302 | * @ring: Engine the descriptor will be used with | |
73e4d07f | 303 | * |
ca82580c TU |
304 | * The context descriptor encodes various attributes of a context, |
305 | * including its GTT address and some flags. Because it's fairly | |
306 | * expensive to calculate, we'll just do it once and cache the result, | |
307 | * which remains valid until the context is unpinned. | |
308 | * | |
309 | * This is what a descriptor looks like, from LSB to MSB: | |
310 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
311 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
312 | * bits 32-51: ctx ID, a globally unique tag (the LRCA again!) | |
313 | * bits 52-63: reserved, may encode the engine ID (for GuC) | |
73e4d07f | 314 | */ |
ca82580c TU |
315 | static void |
316 | intel_lr_context_descriptor_update(struct intel_context *ctx, | |
0bc40be8 | 317 | struct intel_engine_cs *engine) |
84b790f8 | 318 | { |
ca82580c | 319 | uint64_t lrca, desc; |
84b790f8 | 320 | |
0bc40be8 | 321 | lrca = ctx->engine[engine->id].lrc_vma->node.start + |
ca82580c | 322 | LRC_PPHWSP_PN * PAGE_SIZE; |
84b790f8 | 323 | |
0bc40be8 | 324 | desc = engine->ctx_desc_template; /* bits 0-11 */ |
ca82580c TU |
325 | desc |= lrca; /* bits 12-31 */ |
326 | desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */ | |
5af05fef | 327 | |
0bc40be8 | 328 | ctx->engine[engine->id].lrc_desc = desc; |
5af05fef MT |
329 | } |
330 | ||
919f1f55 | 331 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
0bc40be8 | 332 | struct intel_engine_cs *engine) |
84b790f8 | 333 | { |
0bc40be8 | 334 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 335 | } |
203a571b | 336 | |
ca82580c TU |
337 | /** |
338 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
339 | * @ctx: Context to get the ID for | |
340 | * @ring: Engine to get the ID for | |
341 | * | |
342 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
343 | * here: the old context ID we pass to userspace as a handler so that | |
344 | * they can refer to a context, and the new context ID we pass to the | |
345 | * ELSP so that the GPU can inform us of the context status via | |
346 | * interrupts. | |
347 | * | |
348 | * The context ID is a portion of the context descriptor, so we can | |
349 | * just extract the required part from the cached descriptor. | |
350 | * | |
351 | * Return: 20-bits globally unique context ID. | |
352 | */ | |
353 | u32 intel_execlists_ctx_id(struct intel_context *ctx, | |
0bc40be8 | 354 | struct intel_engine_cs *engine) |
ca82580c | 355 | { |
0bc40be8 | 356 | return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT; |
84b790f8 BW |
357 | } |
358 | ||
cc3c4253 MK |
359 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
360 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 361 | { |
cc3c4253 | 362 | |
4a570db5 | 363 | struct intel_engine_cs *engine = rq0->engine; |
e2f80391 | 364 | struct drm_device *dev = engine->dev; |
6e7cc470 | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
1cff8cc3 | 366 | uint64_t desc[2]; |
84b790f8 | 367 | |
1cff8cc3 | 368 | if (rq1) { |
4a570db5 | 369 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine); |
1cff8cc3 MK |
370 | rq1->elsp_submitted++; |
371 | } else { | |
372 | desc[1] = 0; | |
373 | } | |
84b790f8 | 374 | |
4a570db5 | 375 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine); |
1cff8cc3 | 376 | rq0->elsp_submitted++; |
84b790f8 | 377 | |
1cff8cc3 | 378 | /* You must always write both descriptors in the order below. */ |
e2f80391 TU |
379 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1])); |
380 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1])); | |
6daccb0b | 381 | |
e2f80391 | 382 | I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0])); |
84b790f8 | 383 | /* The context is automatically loaded after the following */ |
e2f80391 | 384 | I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0])); |
84b790f8 | 385 | |
1cff8cc3 | 386 | /* ELSP is a wo register, use another nearby reg for posting */ |
e2f80391 | 387 | POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine)); |
84b790f8 BW |
388 | } |
389 | ||
c6a2ac71 TU |
390 | static void |
391 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
392 | { | |
393 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
394 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
395 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
396 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
397 | } | |
398 | ||
399 | static void execlists_update_context(struct drm_i915_gem_request *rq) | |
ae1250b9 | 400 | { |
4a570db5 | 401 | struct intel_engine_cs *engine = rq->engine; |
05d9824b | 402 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
e2f80391 | 403 | uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state; |
ae1250b9 | 404 | |
05d9824b | 405 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 406 | |
c6a2ac71 TU |
407 | /* True 32b PPGTT with dynamic page allocation: update PDP |
408 | * registers and point the unallocated PDPs to scratch page. | |
409 | * PML4 is allocated during ppgtt init, so this is not needed | |
410 | * in 48-bit mode. | |
411 | */ | |
412 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
413 | execlists_update_context_pdps(ppgtt, reg_state); | |
ae1250b9 OM |
414 | } |
415 | ||
d8cb8875 MK |
416 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
417 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 418 | { |
26720ab9 TU |
419 | struct drm_i915_private *dev_priv = rq0->i915; |
420 | ||
421 | /* BUG_ON(!irqs_disabled()); */ | |
422 | ||
05d9824b | 423 | execlists_update_context(rq0); |
d8cb8875 | 424 | |
cc3c4253 | 425 | if (rq1) |
05d9824b | 426 | execlists_update_context(rq1); |
84b790f8 | 427 | |
26720ab9 TU |
428 | spin_lock(&dev_priv->uncore.lock); |
429 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
430 | ||
cc3c4253 | 431 | execlists_elsp_write(rq0, rq1); |
26720ab9 TU |
432 | |
433 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
434 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
435 | } |
436 | ||
26720ab9 | 437 | static void execlists_context_unqueue(struct intel_engine_cs *engine) |
acdd884a | 438 | { |
6d3d8274 | 439 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
c6a2ac71 | 440 | struct drm_i915_gem_request *cursor, *tmp; |
e981e7b1 | 441 | |
0bc40be8 | 442 | assert_spin_locked(&engine->execlist_lock); |
acdd884a | 443 | |
779949f4 PA |
444 | /* |
445 | * If irqs are not active generate a warning as batches that finish | |
446 | * without the irqs may get lost and a GPU Hang may occur. | |
447 | */ | |
0bc40be8 | 448 | WARN_ON(!intel_irqs_enabled(engine->dev->dev_private)); |
779949f4 | 449 | |
acdd884a | 450 | /* Try to read in pairs */ |
0bc40be8 | 451 | list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue, |
acdd884a MT |
452 | execlist_link) { |
453 | if (!req0) { | |
454 | req0 = cursor; | |
6d3d8274 | 455 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
456 | /* Same ctx: ignore first request, as second request |
457 | * will update tail past first request's workload */ | |
e1fee72c | 458 | cursor->elsp_submitted = req0->elsp_submitted; |
7eb08a25 | 459 | list_move_tail(&req0->execlist_link, |
0bc40be8 | 460 | &engine->execlist_retired_req_list); |
acdd884a MT |
461 | req0 = cursor; |
462 | } else { | |
463 | req1 = cursor; | |
c6a2ac71 | 464 | WARN_ON(req1->elsp_submitted); |
acdd884a MT |
465 | break; |
466 | } | |
467 | } | |
468 | ||
c6a2ac71 TU |
469 | if (unlikely(!req0)) |
470 | return; | |
471 | ||
0bc40be8 | 472 | if (req0->elsp_submitted & engine->idle_lite_restore_wa) { |
53292cdb | 473 | /* |
c6a2ac71 TU |
474 | * WaIdleLiteRestore: make sure we never cause a lite restore |
475 | * with HEAD==TAIL. | |
476 | * | |
477 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we | |
478 | * resubmit the request. See gen8_emit_request() for where we | |
479 | * prepare the padding after the end of the request. | |
53292cdb | 480 | */ |
c6a2ac71 | 481 | struct intel_ringbuffer *ringbuf; |
53292cdb | 482 | |
0bc40be8 | 483 | ringbuf = req0->ctx->engine[engine->id].ringbuf; |
c6a2ac71 TU |
484 | req0->tail += 8; |
485 | req0->tail &= ringbuf->size - 1; | |
53292cdb MT |
486 | } |
487 | ||
d8cb8875 | 488 | execlists_submit_requests(req0, req1); |
acdd884a MT |
489 | } |
490 | ||
c6a2ac71 | 491 | static unsigned int |
0bc40be8 | 492 | execlists_check_remove_request(struct intel_engine_cs *engine, u32 request_id) |
e981e7b1 | 493 | { |
6d3d8274 | 494 | struct drm_i915_gem_request *head_req; |
e981e7b1 | 495 | |
0bc40be8 | 496 | assert_spin_locked(&engine->execlist_lock); |
e981e7b1 | 497 | |
0bc40be8 | 498 | head_req = list_first_entry_or_null(&engine->execlist_queue, |
6d3d8274 | 499 | struct drm_i915_gem_request, |
e981e7b1 TD |
500 | execlist_link); |
501 | ||
c6a2ac71 TU |
502 | if (!head_req) |
503 | return 0; | |
e1fee72c | 504 | |
0bc40be8 | 505 | if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) != request_id)) |
c6a2ac71 TU |
506 | return 0; |
507 | ||
508 | WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); | |
509 | ||
510 | if (--head_req->elsp_submitted > 0) | |
511 | return 0; | |
512 | ||
513 | list_move_tail(&head_req->execlist_link, | |
0bc40be8 | 514 | &engine->execlist_retired_req_list); |
e981e7b1 | 515 | |
c6a2ac71 | 516 | return 1; |
e981e7b1 TD |
517 | } |
518 | ||
c6a2ac71 | 519 | static u32 |
0bc40be8 | 520 | get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer, |
c6a2ac71 | 521 | u32 *context_id) |
91a41032 | 522 | { |
0bc40be8 | 523 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
c6a2ac71 | 524 | u32 status; |
91a41032 | 525 | |
c6a2ac71 TU |
526 | read_pointer %= GEN8_CSB_ENTRIES; |
527 | ||
0bc40be8 | 528 | status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer)); |
c6a2ac71 TU |
529 | |
530 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) | |
531 | return 0; | |
91a41032 | 532 | |
0bc40be8 | 533 | *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine, |
c6a2ac71 TU |
534 | read_pointer)); |
535 | ||
536 | return status; | |
91a41032 BW |
537 | } |
538 | ||
73e4d07f | 539 | /** |
3f7531c3 | 540 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
541 | * @ring: Engine Command Streamer to handle. |
542 | * | |
543 | * Check the unread Context Status Buffers and manage the submission of new | |
544 | * contexts to the ELSP accordingly. | |
545 | */ | |
0bc40be8 | 546 | void intel_lrc_irq_handler(struct intel_engine_cs *engine) |
e981e7b1 | 547 | { |
0bc40be8 | 548 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
e981e7b1 | 549 | u32 status_pointer; |
c6a2ac71 | 550 | unsigned int read_pointer, write_pointer; |
26720ab9 TU |
551 | u32 csb[GEN8_CSB_ENTRIES][2]; |
552 | unsigned int csb_read = 0, i; | |
c6a2ac71 TU |
553 | unsigned int submit_contexts = 0; |
554 | ||
c6a2ac71 TU |
555 | spin_lock(&dev_priv->uncore.lock); |
556 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
557 | ||
0bc40be8 | 558 | status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine)); |
e981e7b1 | 559 | |
0bc40be8 | 560 | read_pointer = engine->next_context_status_buffer; |
5590a5f0 | 561 | write_pointer = GEN8_CSB_WRITE_PTR(status_pointer); |
e981e7b1 | 562 | if (read_pointer > write_pointer) |
dfc53c5e | 563 | write_pointer += GEN8_CSB_ENTRIES; |
e981e7b1 | 564 | |
e981e7b1 | 565 | while (read_pointer < write_pointer) { |
26720ab9 TU |
566 | if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES)) |
567 | break; | |
568 | csb[csb_read][0] = get_context_status(engine, ++read_pointer, | |
569 | &csb[csb_read][1]); | |
570 | csb_read++; | |
571 | } | |
91a41032 | 572 | |
26720ab9 TU |
573 | engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; |
574 | ||
575 | /* Update the read pointer to the old write pointer. Manual ringbuffer | |
576 | * management ftw </sarcasm> */ | |
577 | I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine), | |
578 | _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, | |
579 | engine->next_context_status_buffer << 8)); | |
580 | ||
581 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
582 | spin_unlock(&dev_priv->uncore.lock); | |
583 | ||
584 | spin_lock(&engine->execlist_lock); | |
585 | ||
586 | for (i = 0; i < csb_read; i++) { | |
587 | if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) { | |
588 | if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) { | |
589 | if (execlists_check_remove_request(engine, csb[i][1])) | |
e1fee72c OM |
590 | WARN(1, "Lite Restored request removed from queue\n"); |
591 | } else | |
592 | WARN(1, "Preemption without Lite Restore\n"); | |
593 | } | |
594 | ||
26720ab9 | 595 | if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE | |
c6a2ac71 TU |
596 | GEN8_CTX_STATUS_ELEMENT_SWITCH)) |
597 | submit_contexts += | |
26720ab9 | 598 | execlists_check_remove_request(engine, csb[i][1]); |
e981e7b1 TD |
599 | } |
600 | ||
c6a2ac71 | 601 | if (submit_contexts) { |
0bc40be8 | 602 | if (!engine->disable_lite_restore_wa || |
26720ab9 TU |
603 | (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE)) |
604 | execlists_context_unqueue(engine); | |
5af05fef | 605 | } |
e981e7b1 | 606 | |
0bc40be8 | 607 | spin_unlock(&engine->execlist_lock); |
c6a2ac71 TU |
608 | |
609 | if (unlikely(submit_contexts > 2)) | |
610 | DRM_ERROR("More than two context complete events?\n"); | |
e981e7b1 TD |
611 | } |
612 | ||
c6a2ac71 | 613 | static void execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 614 | { |
4a570db5 | 615 | struct intel_engine_cs *engine = request->engine; |
6d3d8274 | 616 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 617 | int num_elements = 0; |
acdd884a | 618 | |
ed54c1a1 | 619 | if (request->ctx != request->i915->kernel_context) |
e2f80391 | 620 | intel_lr_context_pin(request->ctx, engine); |
af3302b9 | 621 | |
9bb1af44 JH |
622 | i915_gem_request_reference(request); |
623 | ||
e2f80391 | 624 | spin_lock_irq(&engine->execlist_lock); |
acdd884a | 625 | |
e2f80391 | 626 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) |
f1ad5a1f OM |
627 | if (++num_elements > 2) |
628 | break; | |
629 | ||
630 | if (num_elements > 2) { | |
6d3d8274 | 631 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f | 632 | |
e2f80391 | 633 | tail_req = list_last_entry(&engine->execlist_queue, |
6d3d8274 | 634 | struct drm_i915_gem_request, |
f1ad5a1f OM |
635 | execlist_link); |
636 | ||
ae70797d | 637 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 638 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 639 | "More than 2 already-submitted reqs queued\n"); |
7eb08a25 | 640 | list_move_tail(&tail_req->execlist_link, |
e2f80391 | 641 | &engine->execlist_retired_req_list); |
f1ad5a1f OM |
642 | } |
643 | } | |
644 | ||
e2f80391 | 645 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
f1ad5a1f | 646 | if (num_elements == 0) |
e2f80391 | 647 | execlists_context_unqueue(engine); |
acdd884a | 648 | |
e2f80391 | 649 | spin_unlock_irq(&engine->execlist_lock); |
acdd884a MT |
650 | } |
651 | ||
2f20055d | 652 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 653 | { |
4a570db5 | 654 | struct intel_engine_cs *engine = req->engine; |
ba8b7ccb OM |
655 | uint32_t flush_domains; |
656 | int ret; | |
657 | ||
658 | flush_domains = 0; | |
e2f80391 | 659 | if (engine->gpu_caches_dirty) |
ba8b7ccb OM |
660 | flush_domains = I915_GEM_GPU_DOMAINS; |
661 | ||
e2f80391 | 662 | ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
663 | if (ret) |
664 | return ret; | |
665 | ||
e2f80391 | 666 | engine->gpu_caches_dirty = false; |
ba8b7ccb OM |
667 | return 0; |
668 | } | |
669 | ||
535fbe82 | 670 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
671 | struct list_head *vmas) |
672 | { | |
666796da | 673 | const unsigned other_rings = ~intel_engine_flag(req->engine); |
ba8b7ccb OM |
674 | struct i915_vma *vma; |
675 | uint32_t flush_domains = 0; | |
676 | bool flush_chipset = false; | |
677 | int ret; | |
678 | ||
679 | list_for_each_entry(vma, vmas, exec_list) { | |
680 | struct drm_i915_gem_object *obj = vma->obj; | |
681 | ||
03ade511 | 682 | if (obj->active & other_rings) { |
4a570db5 | 683 | ret = i915_gem_object_sync(obj, req->engine, &req); |
03ade511 CW |
684 | if (ret) |
685 | return ret; | |
686 | } | |
ba8b7ccb OM |
687 | |
688 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
689 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
690 | ||
691 | flush_domains |= obj->base.write_domain; | |
692 | } | |
693 | ||
694 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
695 | wmb(); | |
696 | ||
697 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
698 | * any residual writes from the previous batch. | |
699 | */ | |
2f20055d | 700 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
701 | } |
702 | ||
40e895ce | 703 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 704 | { |
e28e404c | 705 | int ret = 0; |
bc0dce3f | 706 | |
4a570db5 | 707 | request->ringbuf = request->ctx->engine[request->engine->id].ringbuf; |
f3cc01f0 | 708 | |
a7e02199 AD |
709 | if (i915.enable_guc_submission) { |
710 | /* | |
711 | * Check that the GuC has space for the request before | |
712 | * going any further, as the i915_add_request() call | |
713 | * later on mustn't fail ... | |
714 | */ | |
715 | struct intel_guc *guc = &request->i915->guc; | |
716 | ||
717 | ret = i915_guc_wq_check_space(guc->execbuf_client); | |
718 | if (ret) | |
719 | return ret; | |
720 | } | |
721 | ||
e28e404c | 722 | if (request->ctx != request->i915->kernel_context) |
4a570db5 | 723 | ret = intel_lr_context_pin(request->ctx, request->engine); |
e28e404c DG |
724 | |
725 | return ret; | |
bc0dce3f JH |
726 | } |
727 | ||
ae70797d | 728 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 729 | int bytes) |
bc0dce3f | 730 | { |
ae70797d | 731 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
4a570db5 | 732 | struct intel_engine_cs *engine = req->engine; |
ae70797d | 733 | struct drm_i915_gem_request *target; |
b4716185 CW |
734 | unsigned space; |
735 | int ret; | |
bc0dce3f JH |
736 | |
737 | if (intel_ring_space(ringbuf) >= bytes) | |
738 | return 0; | |
739 | ||
79bbcc29 JH |
740 | /* The whole point of reserving space is to not wait! */ |
741 | WARN_ON(ringbuf->reserved_in_use); | |
742 | ||
e2f80391 | 743 | list_for_each_entry(target, &engine->request_list, list) { |
bc0dce3f JH |
744 | /* |
745 | * The request queue is per-engine, so can contain requests | |
746 | * from multiple ringbuffers. Here, we must ignore any that | |
747 | * aren't from the ringbuffer we're considering. | |
748 | */ | |
ae70797d | 749 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
750 | continue; |
751 | ||
752 | /* Would completion of this request free enough space? */ | |
ae70797d | 753 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
754 | ringbuf->size); |
755 | if (space >= bytes) | |
bc0dce3f | 756 | break; |
bc0dce3f JH |
757 | } |
758 | ||
e2f80391 | 759 | if (WARN_ON(&target->list == &engine->request_list)) |
bc0dce3f JH |
760 | return -ENOSPC; |
761 | ||
ae70797d | 762 | ret = i915_wait_request(target); |
bc0dce3f JH |
763 | if (ret) |
764 | return ret; | |
765 | ||
b4716185 CW |
766 | ringbuf->space = space; |
767 | return 0; | |
bc0dce3f JH |
768 | } |
769 | ||
770 | /* | |
771 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 772 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
773 | * |
774 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
775 | * really happens during submission is that the context and current tail will be placed | |
776 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
777 | * point, the tail *inside* the context is updated and the ELSP written to. | |
778 | */ | |
7c17d377 | 779 | static int |
ae70797d | 780 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 781 | { |
7c17d377 | 782 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
d1675198 | 783 | struct drm_i915_private *dev_priv = request->i915; |
4a570db5 | 784 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 785 | |
7c17d377 CW |
786 | intel_logical_ring_advance(ringbuf); |
787 | request->tail = ringbuf->tail; | |
bc0dce3f | 788 | |
7c17d377 CW |
789 | /* |
790 | * Here we add two extra NOOPs as padding to avoid | |
791 | * lite restore of a context with HEAD==TAIL. | |
792 | * | |
793 | * Caller must reserve WA_TAIL_DWORDS for us! | |
794 | */ | |
795 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
796 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
797 | intel_logical_ring_advance(ringbuf); | |
d1675198 | 798 | |
117897f4 | 799 | if (intel_engine_stopped(engine)) |
7c17d377 | 800 | return 0; |
bc0dce3f | 801 | |
f4e2dece TU |
802 | if (engine->last_context != request->ctx) { |
803 | if (engine->last_context) | |
804 | intel_lr_context_unpin(engine->last_context, engine); | |
805 | if (request->ctx != request->i915->kernel_context) { | |
806 | intel_lr_context_pin(request->ctx, engine); | |
807 | engine->last_context = request->ctx; | |
808 | } else { | |
809 | engine->last_context = NULL; | |
810 | } | |
811 | } | |
812 | ||
d1675198 AD |
813 | if (dev_priv->guc.execbuf_client) |
814 | i915_guc_submit(dev_priv->guc.execbuf_client, request); | |
815 | else | |
816 | execlists_context_queue(request); | |
7c17d377 CW |
817 | |
818 | return 0; | |
bc0dce3f JH |
819 | } |
820 | ||
79bbcc29 | 821 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
822 | { |
823 | uint32_t __iomem *virt; | |
824 | int rem = ringbuf->size - ringbuf->tail; | |
825 | ||
bc0dce3f JH |
826 | virt = ringbuf->virtual_start + ringbuf->tail; |
827 | rem /= 4; | |
828 | while (rem--) | |
829 | iowrite32(MI_NOOP, virt++); | |
830 | ||
831 | ringbuf->tail = 0; | |
832 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
833 | } |
834 | ||
ae70797d | 835 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 836 | { |
ae70797d | 837 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
838 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
839 | int remain_actual = ringbuf->size - ringbuf->tail; | |
840 | int ret, total_bytes, wait_bytes = 0; | |
841 | bool need_wrap = false; | |
29b1b415 | 842 | |
79bbcc29 JH |
843 | if (ringbuf->reserved_in_use) |
844 | total_bytes = bytes; | |
845 | else | |
846 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 847 | |
79bbcc29 JH |
848 | if (unlikely(bytes > remain_usable)) { |
849 | /* | |
850 | * Not enough space for the basic request. So need to flush | |
851 | * out the remainder and then wait for base + reserved. | |
852 | */ | |
853 | wait_bytes = remain_actual + total_bytes; | |
854 | need_wrap = true; | |
855 | } else { | |
856 | if (unlikely(total_bytes > remain_usable)) { | |
857 | /* | |
858 | * The base request will fit but the reserved space | |
859 | * falls off the end. So only need to to wait for the | |
860 | * reserved size after flushing out the remainder. | |
861 | */ | |
862 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
863 | need_wrap = true; | |
864 | } else if (total_bytes > ringbuf->space) { | |
865 | /* No wrapping required, just waiting. */ | |
866 | wait_bytes = total_bytes; | |
29b1b415 | 867 | } |
bc0dce3f JH |
868 | } |
869 | ||
79bbcc29 JH |
870 | if (wait_bytes) { |
871 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
872 | if (unlikely(ret)) |
873 | return ret; | |
79bbcc29 JH |
874 | |
875 | if (need_wrap) | |
876 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
877 | } |
878 | ||
879 | return 0; | |
880 | } | |
881 | ||
882 | /** | |
883 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
884 | * | |
374887ba | 885 | * @req: The request to start some new work for |
bc0dce3f JH |
886 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
887 | * | |
888 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
889 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
890 | * and also preallocates a request (every workload submission is still mediated through | |
891 | * requests, same as it did with legacy ringbuffer submission). | |
892 | * | |
893 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
894 | */ | |
3bbaba0c | 895 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
bc0dce3f | 896 | { |
4d616a29 | 897 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
898 | int ret; |
899 | ||
4d616a29 | 900 | WARN_ON(req == NULL); |
39dabecd | 901 | dev_priv = req->i915; |
4d616a29 | 902 | |
bc0dce3f JH |
903 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
904 | dev_priv->mm.interruptible); | |
905 | if (ret) | |
906 | return ret; | |
907 | ||
ae70797d | 908 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
909 | if (ret) |
910 | return ret; | |
911 | ||
4d616a29 | 912 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
913 | return 0; |
914 | } | |
915 | ||
ccd98fe4 JH |
916 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
917 | { | |
918 | /* | |
919 | * The first call merely notes the reserve request and is common for | |
920 | * all back ends. The subsequent localised _begin() call actually | |
921 | * ensures that the reservation is available. Without the begin, if | |
922 | * the request creator immediately submitted the request without | |
923 | * adding any commands to it then there might not actually be | |
924 | * sufficient room for the submission commands. | |
925 | */ | |
926 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
927 | ||
928 | return intel_logical_ring_begin(request, 0); | |
929 | } | |
930 | ||
73e4d07f OM |
931 | /** |
932 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
933 | * @dev: DRM device. | |
934 | * @file: DRM file. | |
935 | * @ring: Engine Command Streamer to submit to. | |
936 | * @ctx: Context to employ for this submission. | |
937 | * @args: execbuffer call arguments. | |
938 | * @vmas: list of vmas. | |
939 | * @batch_obj: the batchbuffer to submit. | |
940 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 941 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
942 | * |
943 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
944 | * away the submission details of the execbuffer ioctl call. | |
945 | * | |
946 | * Return: non-zero if the submission fails. | |
947 | */ | |
5f19e2bf | 948 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 949 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 950 | struct list_head *vmas) |
454afebd | 951 | { |
5f19e2bf | 952 | struct drm_device *dev = params->dev; |
4a570db5 | 953 | struct intel_engine_cs *engine = params->engine; |
ba8b7ccb | 954 | struct drm_i915_private *dev_priv = dev->dev_private; |
e2f80391 | 955 | struct intel_ringbuffer *ringbuf = params->ctx->engine[engine->id].ringbuf; |
5f19e2bf | 956 | u64 exec_start; |
ba8b7ccb OM |
957 | int instp_mode; |
958 | u32 instp_mask; | |
959 | int ret; | |
960 | ||
961 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
962 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
963 | switch (instp_mode) { | |
964 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
965 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
966 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
4a570db5 | 967 | if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) { |
ba8b7ccb OM |
968 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); |
969 | return -EINVAL; | |
970 | } | |
971 | ||
972 | if (instp_mode != dev_priv->relative_constants_mode) { | |
973 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
974 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
975 | return -EINVAL; | |
976 | } | |
977 | ||
978 | /* The HW changed the meaning on this bit on gen6 */ | |
979 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
980 | } | |
981 | break; | |
982 | default: | |
983 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
984 | return -EINVAL; | |
985 | } | |
986 | ||
ba8b7ccb OM |
987 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { |
988 | DRM_DEBUG("sol reset is gen7 only\n"); | |
989 | return -EINVAL; | |
990 | } | |
991 | ||
535fbe82 | 992 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
993 | if (ret) |
994 | return ret; | |
995 | ||
4a570db5 | 996 | if (engine == &dev_priv->engine[RCS] && |
ba8b7ccb | 997 | instp_mode != dev_priv->relative_constants_mode) { |
4d616a29 | 998 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
999 | if (ret) |
1000 | return ret; | |
1001 | ||
1002 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1003 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 1004 | intel_logical_ring_emit_reg(ringbuf, INSTPM); |
ba8b7ccb OM |
1005 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); |
1006 | intel_logical_ring_advance(ringbuf); | |
1007 | ||
1008 | dev_priv->relative_constants_mode = instp_mode; | |
1009 | } | |
1010 | ||
5f19e2bf JH |
1011 | exec_start = params->batch_obj_vm_offset + |
1012 | args->batch_start_offset; | |
1013 | ||
e2f80391 | 1014 | ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
1015 | if (ret) |
1016 | return ret; | |
1017 | ||
95c24161 | 1018 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 1019 | |
8a8edb59 | 1020 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 1021 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 1022 | |
454afebd OM |
1023 | return 0; |
1024 | } | |
1025 | ||
0bc40be8 | 1026 | void intel_execlists_retire_requests(struct intel_engine_cs *engine) |
c86ee3a9 | 1027 | { |
6d3d8274 | 1028 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
1029 | struct list_head retired_list; |
1030 | ||
0bc40be8 TU |
1031 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
1032 | if (list_empty(&engine->execlist_retired_req_list)) | |
c86ee3a9 TD |
1033 | return; |
1034 | ||
1035 | INIT_LIST_HEAD(&retired_list); | |
0bc40be8 TU |
1036 | spin_lock_irq(&engine->execlist_lock); |
1037 | list_replace_init(&engine->execlist_retired_req_list, &retired_list); | |
1038 | spin_unlock_irq(&engine->execlist_lock); | |
c86ee3a9 TD |
1039 | |
1040 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
af3302b9 DV |
1041 | struct intel_context *ctx = req->ctx; |
1042 | struct drm_i915_gem_object *ctx_obj = | |
0bc40be8 | 1043 | ctx->engine[engine->id].state; |
af3302b9 | 1044 | |
ed54c1a1 | 1045 | if (ctx_obj && (ctx != req->i915->kernel_context)) |
0bc40be8 | 1046 | intel_lr_context_unpin(ctx, engine); |
e5292823 | 1047 | |
c86ee3a9 | 1048 | list_del(&req->execlist_link); |
f8210795 | 1049 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
1050 | } |
1051 | } | |
1052 | ||
0bc40be8 | 1053 | void intel_logical_ring_stop(struct intel_engine_cs *engine) |
454afebd | 1054 | { |
0bc40be8 | 1055 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
9832b9da OM |
1056 | int ret; |
1057 | ||
117897f4 | 1058 | if (!intel_engine_initialized(engine)) |
9832b9da OM |
1059 | return; |
1060 | ||
666796da | 1061 | ret = intel_engine_idle(engine); |
0bc40be8 | 1062 | if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error)) |
9832b9da | 1063 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
0bc40be8 | 1064 | engine->name, ret); |
9832b9da OM |
1065 | |
1066 | /* TODO: Is this correct with Execlists enabled? */ | |
0bc40be8 TU |
1067 | I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); |
1068 | if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) { | |
1069 | DRM_ERROR("%s :timed out trying to stop ring\n", engine->name); | |
9832b9da OM |
1070 | return; |
1071 | } | |
0bc40be8 | 1072 | I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); |
454afebd OM |
1073 | } |
1074 | ||
4866d729 | 1075 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 1076 | { |
4a570db5 | 1077 | struct intel_engine_cs *engine = req->engine; |
48e29f55 OM |
1078 | int ret; |
1079 | ||
e2f80391 | 1080 | if (!engine->gpu_caches_dirty) |
48e29f55 OM |
1081 | return 0; |
1082 | ||
e2f80391 | 1083 | ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1084 | if (ret) |
1085 | return ret; | |
1086 | ||
e2f80391 | 1087 | engine->gpu_caches_dirty = false; |
48e29f55 OM |
1088 | return 0; |
1089 | } | |
1090 | ||
e5292823 | 1091 | static int intel_lr_context_do_pin(struct intel_context *ctx, |
0bc40be8 | 1092 | struct intel_engine_cs *engine) |
dcb4c12a | 1093 | { |
0bc40be8 | 1094 | struct drm_device *dev = engine->dev; |
e84fe803 | 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
0bc40be8 TU |
1096 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
1097 | struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf; | |
82352e90 | 1098 | struct page *lrc_state_page; |
77b04a04 | 1099 | uint32_t *lrc_reg_state; |
ca82580c | 1100 | int ret; |
dcb4c12a | 1101 | |
0bc40be8 | 1102 | WARN_ON(!mutex_is_locked(&engine->dev->struct_mutex)); |
ca82580c | 1103 | |
e84fe803 NH |
1104 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
1105 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
1106 | if (ret) | |
1107 | return ret; | |
7ba717cf | 1108 | |
82352e90 TU |
1109 | lrc_state_page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
1110 | if (WARN_ON(!lrc_state_page)) { | |
1111 | ret = -ENODEV; | |
1112 | goto unpin_ctx_obj; | |
1113 | } | |
1114 | ||
0bc40be8 | 1115 | ret = intel_pin_and_map_ringbuffer_obj(engine->dev, ringbuf); |
e84fe803 NH |
1116 | if (ret) |
1117 | goto unpin_ctx_obj; | |
d1675198 | 1118 | |
0bc40be8 TU |
1119 | ctx->engine[engine->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj); |
1120 | intel_lr_context_descriptor_update(ctx, engine); | |
77b04a04 TU |
1121 | lrc_reg_state = kmap(lrc_state_page); |
1122 | lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start; | |
0bc40be8 | 1123 | ctx->engine[engine->id].lrc_reg_state = lrc_reg_state; |
e84fe803 | 1124 | ctx_obj->dirty = true; |
e93c28f3 | 1125 | |
e84fe803 NH |
1126 | /* Invalidate GuC TLB. */ |
1127 | if (i915.enable_guc_submission) | |
1128 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a | 1129 | |
7ba717cf TD |
1130 | return ret; |
1131 | ||
1132 | unpin_ctx_obj: | |
1133 | i915_gem_object_ggtt_unpin(ctx_obj); | |
e84fe803 NH |
1134 | |
1135 | return ret; | |
1136 | } | |
1137 | ||
e5292823 TU |
1138 | static int intel_lr_context_pin(struct intel_context *ctx, |
1139 | struct intel_engine_cs *engine) | |
e84fe803 NH |
1140 | { |
1141 | int ret = 0; | |
e84fe803 | 1142 | |
e5292823 TU |
1143 | if (ctx->engine[engine->id].pin_count++ == 0) { |
1144 | ret = intel_lr_context_do_pin(ctx, engine); | |
e84fe803 NH |
1145 | if (ret) |
1146 | goto reset_pin_count; | |
321fe304 TU |
1147 | |
1148 | i915_gem_context_reference(ctx); | |
e84fe803 NH |
1149 | } |
1150 | return ret; | |
1151 | ||
a7cbedec | 1152 | reset_pin_count: |
e5292823 | 1153 | ctx->engine[engine->id].pin_count = 0; |
dcb4c12a OM |
1154 | return ret; |
1155 | } | |
1156 | ||
e5292823 TU |
1157 | void intel_lr_context_unpin(struct intel_context *ctx, |
1158 | struct intel_engine_cs *engine) | |
dcb4c12a | 1159 | { |
e5292823 | 1160 | struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state; |
af3302b9 | 1161 | |
f4e2dece | 1162 | WARN_ON(!mutex_is_locked(&ctx->i915->dev->struct_mutex)); |
e5292823 TU |
1163 | if (--ctx->engine[engine->id].pin_count == 0) { |
1164 | kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state)); | |
1165 | intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf); | |
82352e90 | 1166 | i915_gem_object_ggtt_unpin(ctx_obj); |
e5292823 TU |
1167 | ctx->engine[engine->id].lrc_vma = NULL; |
1168 | ctx->engine[engine->id].lrc_desc = 0; | |
1169 | ctx->engine[engine->id].lrc_reg_state = NULL; | |
321fe304 TU |
1170 | |
1171 | i915_gem_context_unreference(ctx); | |
dcb4c12a OM |
1172 | } |
1173 | } | |
1174 | ||
e2be4faf | 1175 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1176 | { |
1177 | int ret, i; | |
4a570db5 | 1178 | struct intel_engine_cs *engine = req->engine; |
e2be4faf | 1179 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
e2f80391 | 1180 | struct drm_device *dev = engine->dev; |
771b9a53 MT |
1181 | struct drm_i915_private *dev_priv = dev->dev_private; |
1182 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1183 | ||
cd7feaaa | 1184 | if (w->count == 0) |
771b9a53 MT |
1185 | return 0; |
1186 | ||
e2f80391 | 1187 | engine->gpu_caches_dirty = true; |
4866d729 | 1188 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1189 | if (ret) |
1190 | return ret; | |
1191 | ||
4d616a29 | 1192 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1193 | if (ret) |
1194 | return ret; | |
1195 | ||
1196 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1197 | for (i = 0; i < w->count; i++) { | |
f92a9162 | 1198 | intel_logical_ring_emit_reg(ringbuf, w->reg[i].addr); |
771b9a53 MT |
1199 | intel_logical_ring_emit(ringbuf, w->reg[i].value); |
1200 | } | |
1201 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1202 | ||
1203 | intel_logical_ring_advance(ringbuf); | |
1204 | ||
e2f80391 | 1205 | engine->gpu_caches_dirty = true; |
4866d729 | 1206 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1207 | if (ret) |
1208 | return ret; | |
1209 | ||
1210 | return 0; | |
1211 | } | |
1212 | ||
83b8a982 | 1213 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1214 | do { \ |
83b8a982 AS |
1215 | int __index = (index)++; \ |
1216 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1217 | return -ENOSPC; \ |
1218 | } \ | |
83b8a982 | 1219 | batch[__index] = (cmd); \ |
17ee950d AS |
1220 | } while (0) |
1221 | ||
8f40db77 | 1222 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 1223 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
1224 | |
1225 | /* | |
1226 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1227 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1228 | * but there is a slight complication as this is applied in WA batch where the | |
1229 | * values are only initialized once so we cannot take register value at the | |
1230 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1231 | * constant value with bit21 set and then we restore it back with the saved value. | |
1232 | * To simplify the WA, a constant value is formed by using the default value | |
1233 | * of this register. This shouldn't be a problem because we are only modifying | |
1234 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1235 | * use additional instructions that read the actual value of the register | |
1236 | * at that time and set our bit of interest but it makes the WA complicated. | |
1237 | * | |
1238 | * This WA is also required for Gen9 so extracting as a function avoids | |
1239 | * code duplication. | |
1240 | */ | |
0bc40be8 | 1241 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
9e000847 AS |
1242 | uint32_t *const batch, |
1243 | uint32_t index) | |
1244 | { | |
1245 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1246 | ||
a4106a78 AS |
1247 | /* |
1248 | * WaDisableLSQCROPERFforOCL:skl | |
1249 | * This WA is implemented in skl_init_clock_gating() but since | |
1250 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1251 | * set this bit here to retain the WA during flush. | |
1252 | */ | |
0bc40be8 | 1253 | if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0)) |
a4106a78 AS |
1254 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
1255 | ||
f1afe24f | 1256 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 1257 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1258 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1259 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 AS |
1260 | wa_ctx_emit(batch, index, 0); |
1261 | ||
1262 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 1263 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
1264 | wa_ctx_emit(batch, index, l3sqc4_flush); |
1265 | ||
1266 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1267 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1268 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1269 | wa_ctx_emit(batch, index, 0); | |
1270 | wa_ctx_emit(batch, index, 0); | |
1271 | wa_ctx_emit(batch, index, 0); | |
1272 | wa_ctx_emit(batch, index, 0); | |
1273 | ||
f1afe24f | 1274 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 1275 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 1276 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
0bc40be8 | 1277 | wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256); |
83b8a982 | 1278 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
1279 | |
1280 | return index; | |
1281 | } | |
1282 | ||
17ee950d AS |
1283 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1284 | uint32_t offset, | |
1285 | uint32_t start_alignment) | |
1286 | { | |
1287 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1288 | } | |
1289 | ||
1290 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1291 | uint32_t offset, | |
1292 | uint32_t size_alignment) | |
1293 | { | |
1294 | wa_ctx->size = offset - wa_ctx->offset; | |
1295 | ||
1296 | WARN(wa_ctx->size % size_alignment, | |
1297 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1298 | wa_ctx->size, size_alignment); | |
1299 | return 0; | |
1300 | } | |
1301 | ||
1302 | /** | |
1303 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1304 | * | |
1305 | * @ring: only applicable for RCS | |
1306 | * @wa_ctx: structure representing wa_ctx | |
1307 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1308 | * with the offset value received as input. | |
1309 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1310 | * @batch: page in which WA are loaded | |
1311 | * @offset: This field specifies the start of the batch, it should be | |
1312 | * cache-aligned otherwise it is adjusted accordingly. | |
1313 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1314 | * initialized at the beginning and shared across all contexts but this field | |
1315 | * helps us to have multiple batches at different offsets and select them based | |
1316 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1317 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1318 | * | |
1319 | * The number of WA applied are not known at the beginning; we use this field | |
1320 | * to return the no of DWORDS written. | |
4d78c8dc | 1321 | * |
17ee950d AS |
1322 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1323 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1324 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1325 | * makes a complete batch buffer. | |
1326 | * | |
1327 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1328 | */ | |
1329 | ||
0bc40be8 | 1330 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1331 | struct i915_wa_ctx_bb *wa_ctx, |
1332 | uint32_t *const batch, | |
1333 | uint32_t *offset) | |
1334 | { | |
0160f055 | 1335 | uint32_t scratch_addr; |
17ee950d AS |
1336 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1337 | ||
7ad00d1a | 1338 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1339 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1340 | |
c82435bb | 1341 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
0bc40be8 TU |
1342 | if (IS_BROADWELL(engine->dev)) { |
1343 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); | |
604ef734 AH |
1344 | if (rc < 0) |
1345 | return rc; | |
1346 | index = rc; | |
c82435bb AS |
1347 | } |
1348 | ||
0160f055 AS |
1349 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1350 | /* Actual scratch location is at 128 bytes offset */ | |
0bc40be8 | 1351 | scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES; |
0160f055 | 1352 | |
83b8a982 AS |
1353 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1354 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1355 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1356 | PIPE_CONTROL_CS_STALL | | |
1357 | PIPE_CONTROL_QW_WRITE)); | |
1358 | wa_ctx_emit(batch, index, scratch_addr); | |
1359 | wa_ctx_emit(batch, index, 0); | |
1360 | wa_ctx_emit(batch, index, 0); | |
1361 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1362 | |
17ee950d AS |
1363 | /* Pad to end of cacheline */ |
1364 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1365 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1366 | |
1367 | /* | |
1368 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1369 | * execution depends on the length specified in terms of cache lines | |
1370 | * in the register CTX_RCS_INDIRECT_CTX | |
1371 | */ | |
1372 | ||
1373 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1374 | } | |
1375 | ||
1376 | /** | |
1377 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1378 | * | |
1379 | * @ring: only applicable for RCS | |
1380 | * @wa_ctx: structure representing wa_ctx | |
1381 | * offset: specifies start of the batch, should be cache-aligned. | |
1382 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1383 | * @batch: page in which WA are loaded |
17ee950d AS |
1384 | * @offset: This field specifies the start of this batch. |
1385 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1386 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1387 | * | |
1388 | * The number of DWORDS written are returned using this field. | |
1389 | * | |
1390 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1391 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1392 | */ | |
0bc40be8 | 1393 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d AS |
1394 | struct i915_wa_ctx_bb *wa_ctx, |
1395 | uint32_t *const batch, | |
1396 | uint32_t *offset) | |
1397 | { | |
1398 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1399 | ||
7ad00d1a | 1400 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1401 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1402 | |
83b8a982 | 1403 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1404 | |
1405 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1406 | } | |
1407 | ||
0bc40be8 | 1408 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1409 | struct i915_wa_ctx_bb *wa_ctx, |
1410 | uint32_t *const batch, | |
1411 | uint32_t *offset) | |
1412 | { | |
a4106a78 | 1413 | int ret; |
0bc40be8 | 1414 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1415 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1416 | ||
0907c8f7 | 1417 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1418 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1419 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 | 1420 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1421 | |
a4106a78 | 1422 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1423 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1424 | if (ret < 0) |
1425 | return ret; | |
1426 | index = ret; | |
1427 | ||
0504cffc AS |
1428 | /* Pad to end of cacheline */ |
1429 | while (index % CACHELINE_DWORDS) | |
1430 | wa_ctx_emit(batch, index, MI_NOOP); | |
1431 | ||
1432 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1433 | } | |
1434 | ||
0bc40be8 | 1435 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc AS |
1436 | struct i915_wa_ctx_bb *wa_ctx, |
1437 | uint32_t *const batch, | |
1438 | uint32_t *offset) | |
1439 | { | |
0bc40be8 | 1440 | struct drm_device *dev = engine->dev; |
0504cffc AS |
1441 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1442 | ||
9b01435d | 1443 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
e87a005d | 1444 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) || |
cbdc12a9 | 1445 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
9b01435d | 1446 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1447 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1448 | wa_ctx_emit(batch, index, |
1449 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1450 | wa_ctx_emit(batch, index, MI_NOOP); | |
1451 | } | |
1452 | ||
0907c8f7 | 1453 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
e87a005d | 1454 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
cbdc12a9 | 1455 | IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
0907c8f7 AS |
1456 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1457 | ||
0504cffc AS |
1458 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1459 | ||
1460 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1461 | } | |
1462 | ||
0bc40be8 | 1463 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d AS |
1464 | { |
1465 | int ret; | |
1466 | ||
0bc40be8 TU |
1467 | engine->wa_ctx.obj = i915_gem_alloc_object(engine->dev, |
1468 | PAGE_ALIGN(size)); | |
1469 | if (!engine->wa_ctx.obj) { | |
17ee950d AS |
1470 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); |
1471 | return -ENOMEM; | |
1472 | } | |
1473 | ||
0bc40be8 | 1474 | ret = i915_gem_obj_ggtt_pin(engine->wa_ctx.obj, PAGE_SIZE, 0); |
17ee950d AS |
1475 | if (ret) { |
1476 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1477 | ret); | |
0bc40be8 | 1478 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); |
17ee950d AS |
1479 | return ret; |
1480 | } | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
0bc40be8 | 1485 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1486 | { |
0bc40be8 TU |
1487 | if (engine->wa_ctx.obj) { |
1488 | i915_gem_object_ggtt_unpin(engine->wa_ctx.obj); | |
1489 | drm_gem_object_unreference(&engine->wa_ctx.obj->base); | |
1490 | engine->wa_ctx.obj = NULL; | |
17ee950d AS |
1491 | } |
1492 | } | |
1493 | ||
0bc40be8 | 1494 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d AS |
1495 | { |
1496 | int ret; | |
1497 | uint32_t *batch; | |
1498 | uint32_t offset; | |
1499 | struct page *page; | |
0bc40be8 | 1500 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d | 1501 | |
0bc40be8 | 1502 | WARN_ON(engine->id != RCS); |
17ee950d | 1503 | |
5e60d790 | 1504 | /* update this when WA for higher Gen are added */ |
0bc40be8 | 1505 | if (INTEL_INFO(engine->dev)->gen > 9) { |
0504cffc | 1506 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
0bc40be8 | 1507 | INTEL_INFO(engine->dev)->gen); |
5e60d790 | 1508 | return 0; |
0504cffc | 1509 | } |
5e60d790 | 1510 | |
c4db7599 | 1511 | /* some WA perform writes to scratch page, ensure it is valid */ |
0bc40be8 TU |
1512 | if (engine->scratch.obj == NULL) { |
1513 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); | |
c4db7599 AS |
1514 | return -EINVAL; |
1515 | } | |
1516 | ||
0bc40be8 | 1517 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1518 | if (ret) { |
1519 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1520 | return ret; | |
1521 | } | |
1522 | ||
033908ae | 1523 | page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0); |
17ee950d AS |
1524 | batch = kmap_atomic(page); |
1525 | offset = 0; | |
1526 | ||
0bc40be8 TU |
1527 | if (INTEL_INFO(engine->dev)->gen == 8) { |
1528 | ret = gen8_init_indirectctx_bb(engine, | |
17ee950d AS |
1529 | &wa_ctx->indirect_ctx, |
1530 | batch, | |
1531 | &offset); | |
1532 | if (ret) | |
1533 | goto out; | |
1534 | ||
0bc40be8 | 1535 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1536 | &wa_ctx->per_ctx, |
1537 | batch, | |
1538 | &offset); | |
1539 | if (ret) | |
1540 | goto out; | |
0bc40be8 TU |
1541 | } else if (INTEL_INFO(engine->dev)->gen == 9) { |
1542 | ret = gen9_init_indirectctx_bb(engine, | |
0504cffc AS |
1543 | &wa_ctx->indirect_ctx, |
1544 | batch, | |
1545 | &offset); | |
1546 | if (ret) | |
1547 | goto out; | |
1548 | ||
0bc40be8 | 1549 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1550 | &wa_ctx->per_ctx, |
1551 | batch, | |
1552 | &offset); | |
1553 | if (ret) | |
1554 | goto out; | |
17ee950d AS |
1555 | } |
1556 | ||
1557 | out: | |
1558 | kunmap_atomic(batch); | |
1559 | if (ret) | |
0bc40be8 | 1560 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1561 | |
1562 | return ret; | |
1563 | } | |
1564 | ||
0bc40be8 | 1565 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1566 | { |
0bc40be8 | 1567 | struct drm_device *dev = engine->dev; |
9b1136d5 | 1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
c6a2ac71 | 1569 | unsigned int next_context_status_buffer_hw; |
9b1136d5 | 1570 | |
0bc40be8 TU |
1571 | lrc_setup_hardware_status_page(engine, |
1572 | dev_priv->kernel_context->engine[engine->id].state); | |
e84fe803 | 1573 | |
0bc40be8 TU |
1574 | I915_WRITE_IMR(engine, |
1575 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1576 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); | |
73d477f6 | 1577 | |
0bc40be8 | 1578 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1579 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1580 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
0bc40be8 | 1581 | POSTING_READ(RING_MODE_GEN7(engine)); |
dfc53c5e MT |
1582 | |
1583 | /* | |
1584 | * Instead of resetting the Context Status Buffer (CSB) read pointer to | |
1585 | * zero, we need to read the write pointer from hardware and use its | |
1586 | * value because "this register is power context save restored". | |
1587 | * Effectively, these states have been observed: | |
1588 | * | |
1589 | * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | | |
1590 | * BDW | CSB regs not reset | CSB regs reset | | |
1591 | * CHT | CSB regs not reset | CSB regs not reset | | |
5590a5f0 BW |
1592 | * SKL | ? | ? | |
1593 | * BXT | ? | ? | | |
dfc53c5e | 1594 | */ |
5590a5f0 | 1595 | next_context_status_buffer_hw = |
0bc40be8 | 1596 | GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))); |
dfc53c5e MT |
1597 | |
1598 | /* | |
1599 | * When the CSB registers are reset (also after power-up / gpu reset), | |
1600 | * CSB write pointer is set to all 1's, which is not valid, use '5' in | |
1601 | * this special case, so the first element read is CSB[0]. | |
1602 | */ | |
1603 | if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) | |
1604 | next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); | |
1605 | ||
0bc40be8 TU |
1606 | engine->next_context_status_buffer = next_context_status_buffer_hw; |
1607 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); | |
9b1136d5 | 1608 | |
fc0768ce | 1609 | intel_engine_init_hangcheck(engine); |
9b1136d5 OM |
1610 | |
1611 | return 0; | |
1612 | } | |
1613 | ||
0bc40be8 | 1614 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1615 | { |
0bc40be8 | 1616 | struct drm_device *dev = engine->dev; |
9b1136d5 OM |
1617 | struct drm_i915_private *dev_priv = dev->dev_private; |
1618 | int ret; | |
1619 | ||
0bc40be8 | 1620 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1621 | if (ret) |
1622 | return ret; | |
1623 | ||
1624 | /* We need to disable the AsyncFlip performance optimisations in order | |
1625 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1626 | * programmed to '1' on all products. | |
1627 | * | |
1628 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1629 | */ | |
1630 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1631 | ||
9b1136d5 OM |
1632 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1633 | ||
0bc40be8 | 1634 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1635 | } |
1636 | ||
0bc40be8 | 1637 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1638 | { |
1639 | int ret; | |
1640 | ||
0bc40be8 | 1641 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1642 | if (ret) |
1643 | return ret; | |
1644 | ||
0bc40be8 | 1645 | return init_workarounds_ring(engine); |
82ef822e DL |
1646 | } |
1647 | ||
7a01a0a2 MT |
1648 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1649 | { | |
1650 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1651 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1652 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
1653 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1654 | int i, ret; | |
1655 | ||
1656 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1657 | if (ret) | |
1658 | return ret; | |
1659 | ||
1660 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1661 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1662 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1663 | ||
e2f80391 TU |
1664 | intel_logical_ring_emit_reg(ringbuf, |
1665 | GEN8_RING_PDP_UDW(engine, i)); | |
7a01a0a2 | 1666 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); |
e2f80391 TU |
1667 | intel_logical_ring_emit_reg(ringbuf, |
1668 | GEN8_RING_PDP_LDW(engine, i)); | |
7a01a0a2 MT |
1669 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); |
1670 | } | |
1671 | ||
1672 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1673 | intel_logical_ring_advance(ringbuf); | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
be795fc1 | 1678 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1679 | u64 offset, unsigned dispatch_flags) |
15648585 | 1680 | { |
be795fc1 | 1681 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1682 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1683 | int ret; |
1684 | ||
7a01a0a2 MT |
1685 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1686 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1687 | * but we can't. Force Restore would be a second option, but | |
1688 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1689 | * not idle). PML4 is allocated during ppgtt init so this is |
1690 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1691 | if (req->ctx->ppgtt && |
666796da | 1692 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 ZL |
1693 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
1694 | !intel_vgpu_active(req->i915->dev)) { | |
2dba3239 MT |
1695 | ret = intel_logical_ring_emit_pdps(req); |
1696 | if (ret) | |
1697 | return ret; | |
1698 | } | |
7a01a0a2 | 1699 | |
666796da | 1700 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1701 | } |
1702 | ||
4d616a29 | 1703 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1704 | if (ret) |
1705 | return ret; | |
1706 | ||
1707 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1708 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1709 | (ppgtt<<8) | | |
1710 | (dispatch_flags & I915_DISPATCH_RS ? | |
1711 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1712 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1713 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1714 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1715 | intel_logical_ring_advance(ringbuf); | |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | ||
0bc40be8 | 1720 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine) |
73d477f6 | 1721 | { |
0bc40be8 | 1722 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1723 | struct drm_i915_private *dev_priv = dev->dev_private; |
1724 | unsigned long flags; | |
1725 | ||
7cd512f1 | 1726 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1727 | return false; |
1728 | ||
1729 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1730 | if (engine->irq_refcount++ == 0) { |
1731 | I915_WRITE_IMR(engine, | |
1732 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1733 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1734 | } |
1735 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1736 | ||
1737 | return true; | |
1738 | } | |
1739 | ||
0bc40be8 | 1740 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine) |
73d477f6 | 1741 | { |
0bc40be8 | 1742 | struct drm_device *dev = engine->dev; |
73d477f6 OM |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; |
1744 | unsigned long flags; | |
1745 | ||
1746 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
0bc40be8 TU |
1747 | if (--engine->irq_refcount == 0) { |
1748 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); | |
1749 | POSTING_READ(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1750 | } |
1751 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1752 | } | |
1753 | ||
7deb4d39 | 1754 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1755 | u32 invalidate_domains, |
1756 | u32 unused) | |
1757 | { | |
7deb4d39 | 1758 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1759 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1760 | struct drm_device *dev = engine->dev; |
4712274c OM |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; |
1762 | uint32_t cmd; | |
1763 | int ret; | |
1764 | ||
4d616a29 | 1765 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1766 | if (ret) |
1767 | return ret; | |
1768 | ||
1769 | cmd = MI_FLUSH_DW + 1; | |
1770 | ||
f0a1fb10 CW |
1771 | /* We always require a command barrier so that subsequent |
1772 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1773 | * wrt the contents of the write cache being flushed to memory | |
1774 | * (and thus being coherent from the CPU). | |
1775 | */ | |
1776 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1777 | ||
1778 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1779 | cmd |= MI_INVALIDATE_TLB; | |
4a570db5 | 1780 | if (engine == &dev_priv->engine[VCS]) |
f0a1fb10 | 1781 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1782 | } |
1783 | ||
1784 | intel_logical_ring_emit(ringbuf, cmd); | |
1785 | intel_logical_ring_emit(ringbuf, | |
1786 | I915_GEM_HWS_SCRATCH_ADDR | | |
1787 | MI_FLUSH_DW_USE_GTT); | |
1788 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1789 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1790 | intel_logical_ring_advance(ringbuf); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
7deb4d39 | 1795 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1796 | u32 invalidate_domains, |
1797 | u32 flush_domains) | |
1798 | { | |
7deb4d39 | 1799 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4a570db5 | 1800 | struct intel_engine_cs *engine = ringbuf->engine; |
e2f80391 | 1801 | u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
1a5a9ce7 | 1802 | bool vf_flush_wa = false; |
4712274c OM |
1803 | u32 flags = 0; |
1804 | int ret; | |
1805 | ||
1806 | flags |= PIPE_CONTROL_CS_STALL; | |
1807 | ||
1808 | if (flush_domains) { | |
1809 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1810 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1811 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1812 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1813 | } |
1814 | ||
1815 | if (invalidate_domains) { | |
1816 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1817 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1818 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1819 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1820 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1821 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1822 | flags |= PIPE_CONTROL_QW_WRITE; | |
1823 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1824 | |
1a5a9ce7 BW |
1825 | /* |
1826 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1827 | * pipe control. | |
1828 | */ | |
e2f80391 | 1829 | if (IS_GEN9(engine->dev)) |
1a5a9ce7 BW |
1830 | vf_flush_wa = true; |
1831 | } | |
9647ff36 | 1832 | |
4d616a29 | 1833 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1834 | if (ret) |
1835 | return ret; | |
1836 | ||
9647ff36 ID |
1837 | if (vf_flush_wa) { |
1838 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1839 | intel_logical_ring_emit(ringbuf, 0); | |
1840 | intel_logical_ring_emit(ringbuf, 0); | |
1841 | intel_logical_ring_emit(ringbuf, 0); | |
1842 | intel_logical_ring_emit(ringbuf, 0); | |
1843 | intel_logical_ring_emit(ringbuf, 0); | |
1844 | } | |
1845 | ||
4712274c OM |
1846 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1847 | intel_logical_ring_emit(ringbuf, flags); | |
1848 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1849 | intel_logical_ring_emit(ringbuf, 0); | |
1850 | intel_logical_ring_emit(ringbuf, 0); | |
1851 | intel_logical_ring_emit(ringbuf, 0); | |
1852 | intel_logical_ring_advance(ringbuf); | |
1853 | ||
1854 | return 0; | |
1855 | } | |
1856 | ||
0bc40be8 | 1857 | static u32 gen8_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency) |
e94e37ad | 1858 | { |
0bc40be8 | 1859 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
e94e37ad OM |
1860 | } |
1861 | ||
0bc40be8 | 1862 | static void gen8_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
e94e37ad | 1863 | { |
0bc40be8 | 1864 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
e94e37ad OM |
1865 | } |
1866 | ||
0bc40be8 TU |
1867 | static u32 bxt_a_get_seqno(struct intel_engine_cs *engine, |
1868 | bool lazy_coherency) | |
319404df ID |
1869 | { |
1870 | ||
1871 | /* | |
1872 | * On BXT A steppings there is a HW coherency issue whereby the | |
1873 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1874 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1875 | * clflushing the corresponding cacheline whenever the caller wants | |
1876 | * the coherency to be guaranteed. Note that this cacheline is known | |
1877 | * to be clean at this point, since we only write it in | |
1878 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1879 | * this clflush in practice becomes an invalidate operation. | |
1880 | */ | |
1881 | ||
1882 | if (!lazy_coherency) | |
0bc40be8 | 1883 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df | 1884 | |
0bc40be8 | 1885 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1886 | } |
1887 | ||
0bc40be8 | 1888 | static void bxt_a_set_seqno(struct intel_engine_cs *engine, u32 seqno) |
319404df | 1889 | { |
0bc40be8 | 1890 | intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); |
319404df ID |
1891 | |
1892 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ | |
0bc40be8 | 1893 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1894 | } |
1895 | ||
7c17d377 CW |
1896 | /* |
1897 | * Reserve space for 2 NOOPs at the end of each request to be | |
1898 | * used as a workaround for not being allowed to do lite | |
1899 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1900 | */ | |
1901 | #define WA_TAIL_DWORDS 2 | |
1902 | ||
1903 | static inline u32 hws_seqno_address(struct intel_engine_cs *engine) | |
1904 | { | |
1905 | return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; | |
1906 | } | |
1907 | ||
c4e76638 | 1908 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1909 | { |
c4e76638 | 1910 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1911 | int ret; |
1912 | ||
7c17d377 | 1913 | ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1914 | if (ret) |
1915 | return ret; | |
1916 | ||
7c17d377 CW |
1917 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1918 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1919 | |
4da46e1e | 1920 | intel_logical_ring_emit(ringbuf, |
7c17d377 CW |
1921 | (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1922 | intel_logical_ring_emit(ringbuf, | |
4a570db5 | 1923 | hws_seqno_address(request->engine) | |
7c17d377 | 1924 | MI_FLUSH_DW_USE_GTT); |
4da46e1e | 1925 | intel_logical_ring_emit(ringbuf, 0); |
c4e76638 | 1926 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1927 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1928 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
7c17d377 CW |
1929 | return intel_logical_ring_advance_and_submit(request); |
1930 | } | |
4da46e1e | 1931 | |
7c17d377 CW |
1932 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1933 | { | |
1934 | struct intel_ringbuffer *ringbuf = request->ringbuf; | |
1935 | int ret; | |
53292cdb | 1936 | |
7c17d377 CW |
1937 | ret = intel_logical_ring_begin(request, 6 + WA_TAIL_DWORDS); |
1938 | if (ret) | |
1939 | return ret; | |
1940 | ||
1941 | /* w/a for post sync ops following a GPGPU operation we | |
1942 | * need a prior CS_STALL, which is emitted by the flush | |
1943 | * following the batch. | |
1944 | */ | |
1945 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5)); | |
1946 | intel_logical_ring_emit(ringbuf, | |
1947 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1948 | PIPE_CONTROL_CS_STALL | | |
1949 | PIPE_CONTROL_QW_WRITE)); | |
4a570db5 | 1950 | intel_logical_ring_emit(ringbuf, hws_seqno_address(request->engine)); |
7c17d377 CW |
1951 | intel_logical_ring_emit(ringbuf, 0); |
1952 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); | |
1953 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); | |
1954 | return intel_logical_ring_advance_and_submit(request); | |
4da46e1e OM |
1955 | } |
1956 | ||
be01363f | 1957 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1958 | { |
cef437ad | 1959 | struct render_state so; |
cef437ad DL |
1960 | int ret; |
1961 | ||
4a570db5 | 1962 | ret = i915_gem_render_state_prepare(req->engine, &so); |
cef437ad DL |
1963 | if (ret) |
1964 | return ret; | |
1965 | ||
1966 | if (so.rodata == NULL) | |
1967 | return 0; | |
1968 | ||
4a570db5 | 1969 | ret = req->engine->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1970 | I915_DISPATCH_SECURE); |
cef437ad DL |
1971 | if (ret) |
1972 | goto out; | |
1973 | ||
4a570db5 | 1974 | ret = req->engine->emit_bb_start(req, |
84e81020 AS |
1975 | (so.ggtt_offset + so.aux_batch_offset), |
1976 | I915_DISPATCH_SECURE); | |
1977 | if (ret) | |
1978 | goto out; | |
1979 | ||
b2af0376 | 1980 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1981 | |
cef437ad DL |
1982 | out: |
1983 | i915_gem_render_state_fini(&so); | |
1984 | return ret; | |
1985 | } | |
1986 | ||
8753181e | 1987 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1988 | { |
1989 | int ret; | |
1990 | ||
e2be4faf | 1991 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1992 | if (ret) |
1993 | return ret; | |
1994 | ||
3bbaba0c PA |
1995 | ret = intel_rcs_context_init_mocs(req); |
1996 | /* | |
1997 | * Failing to program the MOCS is non-fatal.The system will not | |
1998 | * run at peak performance. So generate an error and carry on. | |
1999 | */ | |
2000 | if (ret) | |
2001 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
2002 | ||
be01363f | 2003 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
2004 | } |
2005 | ||
73e4d07f OM |
2006 | /** |
2007 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
2008 | * | |
2009 | * @ring: Engine Command Streamer. | |
2010 | * | |
2011 | */ | |
0bc40be8 | 2012 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 2013 | { |
6402c330 | 2014 | struct drm_i915_private *dev_priv; |
9832b9da | 2015 | |
117897f4 | 2016 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
2017 | return; |
2018 | ||
0bc40be8 | 2019 | dev_priv = engine->dev->dev_private; |
6402c330 | 2020 | |
0bc40be8 TU |
2021 | if (engine->buffer) { |
2022 | intel_logical_ring_stop(engine); | |
2023 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); | |
b0366a54 | 2024 | } |
48d82387 | 2025 | |
0bc40be8 TU |
2026 | if (engine->cleanup) |
2027 | engine->cleanup(engine); | |
48d82387 | 2028 | |
0bc40be8 TU |
2029 | i915_cmd_parser_fini_ring(engine); |
2030 | i915_gem_batch_pool_fini(&engine->batch_pool); | |
48d82387 | 2031 | |
0bc40be8 TU |
2032 | if (engine->status_page.obj) { |
2033 | kunmap(sg_page(engine->status_page.obj->pages->sgl)); | |
2034 | engine->status_page.obj = NULL; | |
48d82387 | 2035 | } |
17ee950d | 2036 | |
0bc40be8 TU |
2037 | engine->idle_lite_restore_wa = 0; |
2038 | engine->disable_lite_restore_wa = false; | |
2039 | engine->ctx_desc_template = 0; | |
ca82580c | 2040 | |
0bc40be8 TU |
2041 | lrc_destroy_wa_ctx_obj(engine); |
2042 | engine->dev = NULL; | |
454afebd OM |
2043 | } |
2044 | ||
c9cacf93 TU |
2045 | static void |
2046 | logical_ring_default_vfuncs(struct drm_device *dev, | |
0bc40be8 | 2047 | struct intel_engine_cs *engine) |
c9cacf93 TU |
2048 | { |
2049 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 TU |
2050 | engine->init_hw = gen8_init_common_ring; |
2051 | engine->emit_request = gen8_emit_request; | |
2052 | engine->emit_flush = gen8_emit_flush; | |
2053 | engine->irq_get = gen8_logical_ring_get_irq; | |
2054 | engine->irq_put = gen8_logical_ring_put_irq; | |
2055 | engine->emit_bb_start = gen8_emit_bb_start; | |
c9cacf93 | 2056 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
0bc40be8 TU |
2057 | engine->get_seqno = bxt_a_get_seqno; |
2058 | engine->set_seqno = bxt_a_set_seqno; | |
c9cacf93 | 2059 | } else { |
0bc40be8 TU |
2060 | engine->get_seqno = gen8_get_seqno; |
2061 | engine->set_seqno = gen8_set_seqno; | |
c9cacf93 TU |
2062 | } |
2063 | } | |
2064 | ||
d9f3af96 | 2065 | static inline void |
0bc40be8 | 2066 | logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) |
d9f3af96 | 2067 | { |
0bc40be8 TU |
2068 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
2069 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
2070 | } |
2071 | ||
c9cacf93 | 2072 | static int |
0bc40be8 | 2073 | logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) |
454afebd | 2074 | { |
ed54c1a1 | 2075 | struct intel_context *dctx = to_i915(dev)->kernel_context; |
48d82387 | 2076 | int ret; |
48d82387 OM |
2077 | |
2078 | /* Intentionally left blank. */ | |
0bc40be8 | 2079 | engine->buffer = NULL; |
48d82387 | 2080 | |
0bc40be8 TU |
2081 | engine->dev = dev; |
2082 | INIT_LIST_HEAD(&engine->active_list); | |
2083 | INIT_LIST_HEAD(&engine->request_list); | |
2084 | i915_gem_batch_pool_init(dev, &engine->batch_pool); | |
2085 | init_waitqueue_head(&engine->irq_queue); | |
48d82387 | 2086 | |
0bc40be8 TU |
2087 | INIT_LIST_HEAD(&engine->buffers); |
2088 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2089 | INIT_LIST_HEAD(&engine->execlist_retired_req_list); | |
2090 | spin_lock_init(&engine->execlist_lock); | |
acdd884a | 2091 | |
0bc40be8 | 2092 | logical_ring_init_platform_invariants(engine); |
ca82580c | 2093 | |
0bc40be8 | 2094 | ret = i915_cmd_parser_init_ring(engine); |
48d82387 | 2095 | if (ret) |
b0366a54 | 2096 | goto error; |
48d82387 | 2097 | |
0bc40be8 | 2098 | ret = intel_lr_context_deferred_alloc(dctx, engine); |
e84fe803 | 2099 | if (ret) |
b0366a54 | 2100 | goto error; |
e84fe803 NH |
2101 | |
2102 | /* As this is the default context, always pin it */ | |
0bc40be8 | 2103 | ret = intel_lr_context_do_pin(dctx, engine); |
e84fe803 NH |
2104 | if (ret) { |
2105 | DRM_ERROR( | |
2106 | "Failed to pin and map ringbuffer %s: %d\n", | |
0bc40be8 | 2107 | engine->name, ret); |
b0366a54 | 2108 | goto error; |
e84fe803 | 2109 | } |
564ddb2f | 2110 | |
b0366a54 DG |
2111 | return 0; |
2112 | ||
2113 | error: | |
0bc40be8 | 2114 | intel_logical_ring_cleanup(engine); |
564ddb2f | 2115 | return ret; |
454afebd OM |
2116 | } |
2117 | ||
2118 | static int logical_render_ring_init(struct drm_device *dev) | |
2119 | { | |
2120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2121 | struct intel_engine_cs *engine = &dev_priv->engine[RCS]; |
99be1dfe | 2122 | int ret; |
454afebd | 2123 | |
e2f80391 TU |
2124 | engine->name = "render ring"; |
2125 | engine->id = RCS; | |
2126 | engine->exec_id = I915_EXEC_RENDER; | |
2127 | engine->guc_id = GUC_RENDER_ENGINE; | |
2128 | engine->mmio_base = RENDER_RING_BASE; | |
d9f3af96 | 2129 | |
e2f80391 | 2130 | logical_ring_default_irqs(engine, GEN8_RCS_IRQ_SHIFT); |
73d477f6 | 2131 | if (HAS_L3_DPF(dev)) |
e2f80391 | 2132 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; |
454afebd | 2133 | |
e2f80391 | 2134 | logical_ring_default_vfuncs(dev, engine); |
c9cacf93 TU |
2135 | |
2136 | /* Override some for render ring. */ | |
82ef822e | 2137 | if (INTEL_INFO(dev)->gen >= 9) |
e2f80391 | 2138 | engine->init_hw = gen9_init_render_ring; |
82ef822e | 2139 | else |
e2f80391 TU |
2140 | engine->init_hw = gen8_init_render_ring; |
2141 | engine->init_context = gen8_init_rcs_context; | |
2142 | engine->cleanup = intel_fini_pipe_control; | |
2143 | engine->emit_flush = gen8_emit_flush_render; | |
2144 | engine->emit_request = gen8_emit_request_render; | |
9b1136d5 | 2145 | |
e2f80391 | 2146 | engine->dev = dev; |
c4db7599 | 2147 | |
e2f80391 | 2148 | ret = intel_init_pipe_control(engine); |
99be1dfe DV |
2149 | if (ret) |
2150 | return ret; | |
2151 | ||
e2f80391 | 2152 | ret = intel_init_workaround_bb(engine); |
17ee950d AS |
2153 | if (ret) { |
2154 | /* | |
2155 | * We continue even if we fail to initialize WA batch | |
2156 | * because we only expect rare glitches but nothing | |
2157 | * critical to prevent us from using GPU | |
2158 | */ | |
2159 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
2160 | ret); | |
2161 | } | |
2162 | ||
e2f80391 | 2163 | ret = logical_ring_init(dev, engine); |
c4db7599 | 2164 | if (ret) { |
e2f80391 | 2165 | lrc_destroy_wa_ctx_obj(engine); |
c4db7599 | 2166 | } |
17ee950d AS |
2167 | |
2168 | return ret; | |
454afebd OM |
2169 | } |
2170 | ||
2171 | static int logical_bsd_ring_init(struct drm_device *dev) | |
2172 | { | |
2173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2174 | struct intel_engine_cs *engine = &dev_priv->engine[VCS]; |
454afebd | 2175 | |
e2f80391 TU |
2176 | engine->name = "bsd ring"; |
2177 | engine->id = VCS; | |
2178 | engine->exec_id = I915_EXEC_BSD; | |
2179 | engine->guc_id = GUC_VIDEO_ENGINE; | |
2180 | engine->mmio_base = GEN6_BSD_RING_BASE; | |
454afebd | 2181 | |
e2f80391 TU |
2182 | logical_ring_default_irqs(engine, GEN8_VCS1_IRQ_SHIFT); |
2183 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2184 | |
e2f80391 | 2185 | return logical_ring_init(dev, engine); |
454afebd OM |
2186 | } |
2187 | ||
2188 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
2189 | { | |
2190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2191 | struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; |
454afebd | 2192 | |
e2f80391 TU |
2193 | engine->name = "bsd2 ring"; |
2194 | engine->id = VCS2; | |
2195 | engine->exec_id = I915_EXEC_BSD; | |
2196 | engine->guc_id = GUC_VIDEO_ENGINE2; | |
2197 | engine->mmio_base = GEN8_BSD2_RING_BASE; | |
454afebd | 2198 | |
e2f80391 TU |
2199 | logical_ring_default_irqs(engine, GEN8_VCS2_IRQ_SHIFT); |
2200 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2201 | |
e2f80391 | 2202 | return logical_ring_init(dev, engine); |
454afebd OM |
2203 | } |
2204 | ||
2205 | static int logical_blt_ring_init(struct drm_device *dev) | |
2206 | { | |
2207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2208 | struct intel_engine_cs *engine = &dev_priv->engine[BCS]; |
454afebd | 2209 | |
e2f80391 TU |
2210 | engine->name = "blitter ring"; |
2211 | engine->id = BCS; | |
2212 | engine->exec_id = I915_EXEC_BLT; | |
2213 | engine->guc_id = GUC_BLITTER_ENGINE; | |
2214 | engine->mmio_base = BLT_RING_BASE; | |
454afebd | 2215 | |
e2f80391 TU |
2216 | logical_ring_default_irqs(engine, GEN8_BCS_IRQ_SHIFT); |
2217 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2218 | |
e2f80391 | 2219 | return logical_ring_init(dev, engine); |
454afebd OM |
2220 | } |
2221 | ||
2222 | static int logical_vebox_ring_init(struct drm_device *dev) | |
2223 | { | |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a570db5 | 2225 | struct intel_engine_cs *engine = &dev_priv->engine[VECS]; |
454afebd | 2226 | |
e2f80391 TU |
2227 | engine->name = "video enhancement ring"; |
2228 | engine->id = VECS; | |
2229 | engine->exec_id = I915_EXEC_VEBOX; | |
2230 | engine->guc_id = GUC_VIDEOENHANCE_ENGINE; | |
2231 | engine->mmio_base = VEBOX_RING_BASE; | |
454afebd | 2232 | |
e2f80391 TU |
2233 | logical_ring_default_irqs(engine, GEN8_VECS_IRQ_SHIFT); |
2234 | logical_ring_default_vfuncs(dev, engine); | |
9b1136d5 | 2235 | |
e2f80391 | 2236 | return logical_ring_init(dev, engine); |
454afebd OM |
2237 | } |
2238 | ||
73e4d07f OM |
2239 | /** |
2240 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2241 | * @dev: DRM device. | |
2242 | * | |
2243 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
117897f4 | 2244 | * legacy ringbuffer submission world would be i915_gem_init_engines). It does it only for |
73e4d07f OM |
2245 | * those engines that are present in the hardware. |
2246 | * | |
2247 | * Return: non-zero if the initialization failed. | |
2248 | */ | |
454afebd OM |
2249 | int intel_logical_rings_init(struct drm_device *dev) |
2250 | { | |
2251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2252 | int ret; | |
2253 | ||
2254 | ret = logical_render_ring_init(dev); | |
2255 | if (ret) | |
2256 | return ret; | |
2257 | ||
2258 | if (HAS_BSD(dev)) { | |
2259 | ret = logical_bsd_ring_init(dev); | |
2260 | if (ret) | |
2261 | goto cleanup_render_ring; | |
2262 | } | |
2263 | ||
2264 | if (HAS_BLT(dev)) { | |
2265 | ret = logical_blt_ring_init(dev); | |
2266 | if (ret) | |
2267 | goto cleanup_bsd_ring; | |
2268 | } | |
2269 | ||
2270 | if (HAS_VEBOX(dev)) { | |
2271 | ret = logical_vebox_ring_init(dev); | |
2272 | if (ret) | |
2273 | goto cleanup_blt_ring; | |
2274 | } | |
2275 | ||
2276 | if (HAS_BSD2(dev)) { | |
2277 | ret = logical_bsd2_ring_init(dev); | |
2278 | if (ret) | |
2279 | goto cleanup_vebox_ring; | |
2280 | } | |
2281 | ||
454afebd OM |
2282 | return 0; |
2283 | ||
454afebd | 2284 | cleanup_vebox_ring: |
4a570db5 | 2285 | intel_logical_ring_cleanup(&dev_priv->engine[VECS]); |
454afebd | 2286 | cleanup_blt_ring: |
4a570db5 | 2287 | intel_logical_ring_cleanup(&dev_priv->engine[BCS]); |
454afebd | 2288 | cleanup_bsd_ring: |
4a570db5 | 2289 | intel_logical_ring_cleanup(&dev_priv->engine[VCS]); |
454afebd | 2290 | cleanup_render_ring: |
4a570db5 | 2291 | intel_logical_ring_cleanup(&dev_priv->engine[RCS]); |
454afebd OM |
2292 | |
2293 | return ret; | |
2294 | } | |
2295 | ||
0cea6502 JM |
2296 | static u32 |
2297 | make_rpcs(struct drm_device *dev) | |
2298 | { | |
2299 | u32 rpcs = 0; | |
2300 | ||
2301 | /* | |
2302 | * No explicit RPCS request is needed to ensure full | |
2303 | * slice/subslice/EU enablement prior to Gen9. | |
2304 | */ | |
2305 | if (INTEL_INFO(dev)->gen < 9) | |
2306 | return 0; | |
2307 | ||
2308 | /* | |
2309 | * Starting in Gen9, render power gating can leave | |
2310 | * slice/subslice/EU in a partially enabled state. We | |
2311 | * must make an explicit request through RPCS for full | |
2312 | * enablement. | |
2313 | */ | |
2314 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2315 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2316 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2317 | GEN8_RPCS_S_CNT_SHIFT; | |
2318 | rpcs |= GEN8_RPCS_ENABLE; | |
2319 | } | |
2320 | ||
2321 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2322 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2323 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2324 | GEN8_RPCS_SS_CNT_SHIFT; | |
2325 | rpcs |= GEN8_RPCS_ENABLE; | |
2326 | } | |
2327 | ||
2328 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2329 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2330 | GEN8_RPCS_EU_MIN_SHIFT; | |
2331 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2332 | GEN8_RPCS_EU_MAX_SHIFT; | |
2333 | rpcs |= GEN8_RPCS_ENABLE; | |
2334 | } | |
2335 | ||
2336 | return rpcs; | |
2337 | } | |
2338 | ||
0bc40be8 | 2339 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2340 | { |
2341 | u32 indirect_ctx_offset; | |
2342 | ||
0bc40be8 | 2343 | switch (INTEL_INFO(engine->dev)->gen) { |
71562919 | 2344 | default: |
0bc40be8 | 2345 | MISSING_CASE(INTEL_INFO(engine->dev)->gen); |
71562919 MT |
2346 | /* fall through */ |
2347 | case 9: | |
2348 | indirect_ctx_offset = | |
2349 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2350 | break; | |
2351 | case 8: | |
2352 | indirect_ctx_offset = | |
2353 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2354 | break; | |
2355 | } | |
2356 | ||
2357 | return indirect_ctx_offset; | |
2358 | } | |
2359 | ||
8670d6f9 OM |
2360 | static int |
2361 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
0bc40be8 TU |
2362 | struct intel_engine_cs *engine, |
2363 | struct intel_ringbuffer *ringbuf) | |
8670d6f9 | 2364 | { |
0bc40be8 | 2365 | struct drm_device *dev = engine->dev; |
2d965536 | 2366 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae6c4806 | 2367 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2368 | struct page *page; |
2369 | uint32_t *reg_state; | |
2370 | int ret; | |
2371 | ||
2d965536 TD |
2372 | if (!ppgtt) |
2373 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2374 | ||
8670d6f9 OM |
2375 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2376 | if (ret) { | |
2377 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2378 | return ret; | |
2379 | } | |
2380 | ||
2381 | ret = i915_gem_object_get_pages(ctx_obj); | |
2382 | if (ret) { | |
2383 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2384 | return ret; | |
2385 | } | |
2386 | ||
2387 | i915_gem_object_pin_pages(ctx_obj); | |
2388 | ||
2389 | /* The second page of the context object contains some fields which must | |
2390 | * be set up prior to the first execution. */ | |
033908ae | 2391 | page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
8670d6f9 OM |
2392 | reg_state = kmap_atomic(page); |
2393 | ||
2394 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2395 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2396 | * only for the first context restore: on a subsequent save, the GPU will | |
2397 | * recreate this batchbuffer with new values (including all the missing | |
2398 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 2399 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
2400 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
2401 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
2402 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
2403 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
2404 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
99cf8ea1 MT |
2405 | (HAS_RESOURCE_STREAMER(dev) ? |
2406 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
0bc40be8 TU |
2407 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
2408 | 0); | |
2409 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
2410 | 0); | |
7ba717cf TD |
2411 | /* Ring buffer start address is not known until the buffer is pinned. |
2412 | * It is written to the context image in execlists_update_context() | |
2413 | */ | |
0bc40be8 TU |
2414 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
2415 | RING_START(engine->mmio_base), 0); | |
2416 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
2417 | RING_CTL(engine->mmio_base), | |
0d925ea0 | 2418 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
2419 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
2420 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
2421 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
2422 | RING_BBADDR(engine->mmio_base), 0); | |
2423 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
2424 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 2425 | RING_BB_PPGTT); |
0bc40be8 TU |
2426 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
2427 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
2428 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
2429 | RING_SBBADDR(engine->mmio_base), 0); | |
2430 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
2431 | RING_SBBSTATE(engine->mmio_base), 0); | |
2432 | if (engine->id == RCS) { | |
2433 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
2434 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
2435 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
2436 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
2437 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2438 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
2439 | if (engine->wa_ctx.obj) { | |
2440 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; | |
17ee950d AS |
2441 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); |
2442 | ||
2443 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2444 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2445 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2446 | ||
2447 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 2448 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
2449 | |
2450 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2451 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2452 | 0x01; | |
2453 | } | |
8670d6f9 | 2454 | } |
0d925ea0 | 2455 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
2456 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
2457 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 2458 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
2459 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
2460 | 0); | |
2461 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
2462 | 0); | |
2463 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
2464 | 0); | |
2465 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2466 | 0); | |
2467 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2468 | 0); | |
2469 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2470 | 0); | |
2471 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2472 | 0); | |
2473 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2474 | 0); | |
d7b2633d | 2475 | |
2dba3239 MT |
2476 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2477 | /* 64b PPGTT (48bit canonical) | |
2478 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2479 | * other PDP Descriptors are ignored. | |
2480 | */ | |
2481 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2482 | } else { | |
2483 | /* 32b PPGTT | |
2484 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2485 | * With dynamic page allocation, PDPs may not be allocated at | |
2486 | * this point. Point the unallocated PDPs to the scratch page | |
2487 | */ | |
c6a2ac71 | 2488 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2489 | } |
2490 | ||
0bc40be8 | 2491 | if (engine->id == RCS) { |
8670d6f9 | 2492 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 VS |
2493 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
2494 | make_rpcs(dev)); | |
8670d6f9 OM |
2495 | } |
2496 | ||
2497 | kunmap_atomic(reg_state); | |
8670d6f9 OM |
2498 | i915_gem_object_unpin_pages(ctx_obj); |
2499 | ||
2500 | return 0; | |
2501 | } | |
2502 | ||
73e4d07f OM |
2503 | /** |
2504 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2505 | * @ctx: the LR context to free. | |
2506 | * | |
2507 | * The real context freeing is done in i915_gem_context_free: this only | |
2508 | * takes care of the bits that are LRC related: the per-engine backing | |
2509 | * objects and the logical ringbuffer. | |
2510 | */ | |
ede7d42b OM |
2511 | void intel_lr_context_free(struct intel_context *ctx) |
2512 | { | |
8c857917 OM |
2513 | int i; |
2514 | ||
666796da | 2515 | for (i = I915_NUM_ENGINES; --i >= 0; ) { |
e28e404c | 2516 | struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; |
8c857917 | 2517 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; |
84c2377f | 2518 | |
e28e404c DG |
2519 | if (!ctx_obj) |
2520 | continue; | |
dcb4c12a | 2521 | |
e28e404c DG |
2522 | if (ctx == ctx->i915->kernel_context) { |
2523 | intel_unpin_ringbuffer_obj(ringbuf); | |
2524 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8c857917 | 2525 | } |
e28e404c DG |
2526 | |
2527 | WARN_ON(ctx->engine[i].pin_count); | |
2528 | intel_ringbuffer_free(ringbuf); | |
2529 | drm_gem_object_unreference(&ctx_obj->base); | |
8c857917 OM |
2530 | } |
2531 | } | |
2532 | ||
c5d46ee2 DG |
2533 | /** |
2534 | * intel_lr_context_size() - return the size of the context for an engine | |
2535 | * @ring: which engine to find the context size for | |
2536 | * | |
2537 | * Each engine may require a different amount of space for a context image, | |
2538 | * so when allocating (or copying) an image, this function can be used to | |
2539 | * find the right size for the specific engine. | |
2540 | * | |
2541 | * Return: size (in bytes) of an engine-specific context image | |
2542 | * | |
2543 | * Note: this size includes the HWSP, which is part of the context image | |
2544 | * in LRC mode, but does not include the "shared data page" used with | |
2545 | * GuC submission. The caller should account for this if using the GuC. | |
2546 | */ | |
0bc40be8 | 2547 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2548 | { |
2549 | int ret = 0; | |
2550 | ||
0bc40be8 | 2551 | WARN_ON(INTEL_INFO(engine->dev)->gen < 8); |
8c857917 | 2552 | |
0bc40be8 | 2553 | switch (engine->id) { |
8c857917 | 2554 | case RCS: |
0bc40be8 | 2555 | if (INTEL_INFO(engine->dev)->gen >= 9) |
468c6816 MN |
2556 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2557 | else | |
2558 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2559 | break; |
2560 | case VCS: | |
2561 | case BCS: | |
2562 | case VECS: | |
2563 | case VCS2: | |
2564 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2565 | break; | |
2566 | } | |
2567 | ||
2568 | return ret; | |
ede7d42b OM |
2569 | } |
2570 | ||
0bc40be8 TU |
2571 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *engine, |
2572 | struct drm_i915_gem_object *default_ctx_obj) | |
1df06b75 | 2573 | { |
0bc40be8 | 2574 | struct drm_i915_private *dev_priv = engine->dev->dev_private; |
d1675198 | 2575 | struct page *page; |
1df06b75 | 2576 | |
d1675198 | 2577 | /* The HWSP is part of the default context object in LRC mode. */ |
0bc40be8 | 2578 | engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) |
d1675198 AD |
2579 | + LRC_PPHWSP_PN * PAGE_SIZE; |
2580 | page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); | |
0bc40be8 TU |
2581 | engine->status_page.page_addr = kmap(page); |
2582 | engine->status_page.obj = default_ctx_obj; | |
1df06b75 | 2583 | |
0bc40be8 TU |
2584 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
2585 | (u32)engine->status_page.gfx_addr); | |
2586 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
1df06b75 TD |
2587 | } |
2588 | ||
73e4d07f | 2589 | /** |
e84fe803 | 2590 | * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
73e4d07f OM |
2591 | * @ctx: LR context to create. |
2592 | * @ring: engine to be used with the context. | |
2593 | * | |
2594 | * This function can be called more than once, with different engines, if we plan | |
2595 | * to use the context with them. The context backing objects and the ringbuffers | |
2596 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2597 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2598 | * a given ring with the context. | |
2599 | * | |
32197aab | 2600 | * Return: non-zero on error. |
73e4d07f | 2601 | */ |
e84fe803 NH |
2602 | |
2603 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, | |
0bc40be8 | 2604 | struct intel_engine_cs *engine) |
ede7d42b | 2605 | { |
0bc40be8 | 2606 | struct drm_device *dev = engine->dev; |
8c857917 OM |
2607 | struct drm_i915_gem_object *ctx_obj; |
2608 | uint32_t context_size; | |
84c2377f | 2609 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2610 | int ret; |
2611 | ||
ede7d42b | 2612 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
0bc40be8 | 2613 | WARN_ON(ctx->engine[engine->id].state); |
ede7d42b | 2614 | |
0bc40be8 | 2615 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2616 | |
d1675198 AD |
2617 | /* One extra page as the sharing data between driver and GuC */ |
2618 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2619 | ||
149c86e7 | 2620 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2621 | if (!ctx_obj) { |
2622 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2623 | return -ENOMEM; | |
8c857917 OM |
2624 | } |
2625 | ||
0bc40be8 | 2626 | ringbuf = intel_engine_create_ringbuffer(engine, 4 * PAGE_SIZE); |
01101fa7 CW |
2627 | if (IS_ERR(ringbuf)) { |
2628 | ret = PTR_ERR(ringbuf); | |
e84fe803 | 2629 | goto error_deref_obj; |
8670d6f9 OM |
2630 | } |
2631 | ||
0bc40be8 | 2632 | ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf); |
8670d6f9 OM |
2633 | if (ret) { |
2634 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
e84fe803 | 2635 | goto error_ringbuf; |
84c2377f OM |
2636 | } |
2637 | ||
0bc40be8 TU |
2638 | ctx->engine[engine->id].ringbuf = ringbuf; |
2639 | ctx->engine[engine->id].state = ctx_obj; | |
ede7d42b | 2640 | |
0bc40be8 | 2641 | if (ctx != ctx->i915->kernel_context && engine->init_context) { |
e84fe803 | 2642 | struct drm_i915_gem_request *req; |
76c39168 | 2643 | |
0bc40be8 | 2644 | req = i915_gem_request_alloc(engine, ctx); |
26827088 DG |
2645 | if (IS_ERR(req)) { |
2646 | ret = PTR_ERR(req); | |
2647 | DRM_ERROR("ring create req: %d\n", ret); | |
e84fe803 | 2648 | goto error_ringbuf; |
771b9a53 MT |
2649 | } |
2650 | ||
0bc40be8 | 2651 | ret = engine->init_context(req); |
e84fe803 NH |
2652 | if (ret) { |
2653 | DRM_ERROR("ring init context: %d\n", | |
2654 | ret); | |
2655 | i915_gem_request_cancel(req); | |
2656 | goto error_ringbuf; | |
2657 | } | |
2658 | i915_add_request_no_flush(req); | |
564ddb2f | 2659 | } |
ede7d42b | 2660 | return 0; |
8670d6f9 | 2661 | |
01101fa7 CW |
2662 | error_ringbuf: |
2663 | intel_ringbuffer_free(ringbuf); | |
e84fe803 | 2664 | error_deref_obj: |
8670d6f9 | 2665 | drm_gem_object_unreference(&ctx_obj->base); |
0bc40be8 TU |
2666 | ctx->engine[engine->id].ringbuf = NULL; |
2667 | ctx->engine[engine->id].state = NULL; | |
8670d6f9 | 2668 | return ret; |
ede7d42b | 2669 | } |
3e5b6f05 TD |
2670 | |
2671 | void intel_lr_context_reset(struct drm_device *dev, | |
2672 | struct intel_context *ctx) | |
2673 | { | |
2674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2f80391 | 2675 | struct intel_engine_cs *engine; |
3e5b6f05 TD |
2676 | int i; |
2677 | ||
666796da | 2678 | for_each_engine(engine, dev_priv, i) { |
3e5b6f05 | 2679 | struct drm_i915_gem_object *ctx_obj = |
e2f80391 | 2680 | ctx->engine[engine->id].state; |
3e5b6f05 | 2681 | struct intel_ringbuffer *ringbuf = |
e2f80391 | 2682 | ctx->engine[engine->id].ringbuf; |
3e5b6f05 TD |
2683 | uint32_t *reg_state; |
2684 | struct page *page; | |
2685 | ||
2686 | if (!ctx_obj) | |
2687 | continue; | |
2688 | ||
2689 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2690 | WARN(1, "Failed get_pages for context obj\n"); | |
2691 | continue; | |
2692 | } | |
033908ae | 2693 | page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN); |
3e5b6f05 TD |
2694 | reg_state = kmap_atomic(page); |
2695 | ||
2696 | reg_state[CTX_RING_HEAD+1] = 0; | |
2697 | reg_state[CTX_RING_TAIL+1] = 0; | |
2698 | ||
2699 | kunmap_atomic(reg_state); | |
2700 | ||
2701 | ringbuf->head = 0; | |
2702 | ringbuf->tail = 0; | |
2703 | } | |
2704 | } |