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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
127f1003 | 138 | |
468c6816 | 139 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
140 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
141 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
142 | ||
e981e7b1 TD |
143 | #define RING_EXECLIST_QFULL (1 << 0x2) |
144 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
145 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
146 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
147 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
148 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
149 | ||
150 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
151 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
152 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
153 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
154 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
155 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
156 | |
157 | #define CTX_LRI_HEADER_0 0x01 | |
158 | #define CTX_CONTEXT_CONTROL 0x02 | |
159 | #define CTX_RING_HEAD 0x04 | |
160 | #define CTX_RING_TAIL 0x06 | |
161 | #define CTX_RING_BUFFER_START 0x08 | |
162 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
163 | #define CTX_BB_HEAD_U 0x0c | |
164 | #define CTX_BB_HEAD_L 0x0e | |
165 | #define CTX_BB_STATE 0x10 | |
166 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
167 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
168 | #define CTX_SECOND_BB_STATE 0x16 | |
169 | #define CTX_BB_PER_CTX_PTR 0x18 | |
170 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
171 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
172 | #define CTX_LRI_HEADER_1 0x21 | |
173 | #define CTX_CTX_TIMESTAMP 0x22 | |
174 | #define CTX_PDP3_UDW 0x24 | |
175 | #define CTX_PDP3_LDW 0x26 | |
176 | #define CTX_PDP2_UDW 0x28 | |
177 | #define CTX_PDP2_LDW 0x2a | |
178 | #define CTX_PDP1_UDW 0x2c | |
179 | #define CTX_PDP1_LDW 0x2e | |
180 | #define CTX_PDP0_UDW 0x30 | |
181 | #define CTX_PDP0_LDW 0x32 | |
182 | #define CTX_LRI_HEADER_2 0x41 | |
183 | #define CTX_R_PWR_CLK_STATE 0x42 | |
184 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
185 | ||
84b790f8 BW |
186 | #define GEN8_CTX_VALID (1<<0) |
187 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
188 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
189 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
190 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
191 | |
192 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d852c7bf | 193 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
194 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
195 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
196 | } | |
197 | ||
84b790f8 BW |
198 | enum { |
199 | ADVANCED_CONTEXT = 0, | |
200 | LEGACY_CONTEXT, | |
201 | ADVANCED_AD_CONTEXT, | |
202 | LEGACY_64B_CONTEXT | |
203 | }; | |
204 | #define GEN8_CTX_MODE_SHIFT 3 | |
205 | enum { | |
206 | FAULT_AND_HANG = 0, | |
207 | FAULT_AND_HALT, /* Debug only */ | |
208 | FAULT_AND_STREAM, | |
209 | FAULT_AND_CONTINUE /* Unsupported */ | |
210 | }; | |
211 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 212 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 213 | |
7ba717cf TD |
214 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
215 | struct intel_context *ctx); | |
216 | ||
73e4d07f OM |
217 | /** |
218 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
219 | * @dev: DRM device. | |
220 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
221 | * | |
222 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 223 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
224 | * |
225 | * Return: 1 if Execlists is supported and has to be enabled. | |
226 | */ | |
127f1003 OM |
227 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
228 | { | |
bd84b1e9 DV |
229 | WARN_ON(i915.enable_ppgtt == -1); |
230 | ||
70ee45e1 DL |
231 | if (INTEL_INFO(dev)->gen >= 9) |
232 | return 1; | |
233 | ||
127f1003 OM |
234 | if (enable_execlists == 0) |
235 | return 0; | |
236 | ||
14bf993e OM |
237 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
238 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
239 | return 1; |
240 | ||
241 | return 0; | |
242 | } | |
ede7d42b | 243 | |
73e4d07f OM |
244 | /** |
245 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
246 | * @ctx_obj: Logical Ring Context backing object. | |
247 | * | |
248 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
249 | * here: the old context ID we pass to userspace as a handler so that | |
250 | * they can refer to a context, and the new context ID we pass to the | |
251 | * ELSP so that the GPU can inform us of the context status via | |
252 | * interrupts. | |
253 | * | |
254 | * Return: 20-bits globally unique context ID. | |
255 | */ | |
84b790f8 BW |
256 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
257 | { | |
258 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
259 | ||
260 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
261 | * are globally unique */ | |
262 | return lrca >> 12; | |
263 | } | |
264 | ||
203a571b NH |
265 | static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, |
266 | struct drm_i915_gem_object *ctx_obj) | |
84b790f8 | 267 | { |
203a571b | 268 | struct drm_device *dev = ring->dev; |
84b790f8 BW |
269 | uint64_t desc; |
270 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); | |
acdd884a MT |
271 | |
272 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
273 | |
274 | desc = GEN8_CTX_VALID; | |
275 | desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; | |
51847fb9 AS |
276 | if (IS_GEN8(ctx_obj->base.dev)) |
277 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
278 | desc |= GEN8_CTX_PRIVILEGE; |
279 | desc |= lrca; | |
280 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
281 | ||
282 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
283 | * signalling between Command Streamers */ | |
284 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
285 | ||
203a571b NH |
286 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
287 | if (IS_GEN9(dev) && | |
288 | INTEL_REVID(dev) <= SKL_REVID_B0 && | |
289 | (ring->id == BCS || ring->id == VCS || | |
290 | ring->id == VECS || ring->id == VCS2)) | |
291 | desc |= GEN8_CTX_FORCE_RESTORE; | |
292 | ||
84b790f8 BW |
293 | return desc; |
294 | } | |
295 | ||
296 | static void execlists_elsp_write(struct intel_engine_cs *ring, | |
297 | struct drm_i915_gem_object *ctx_obj0, | |
298 | struct drm_i915_gem_object *ctx_obj1) | |
299 | { | |
6e7cc470 TU |
300 | struct drm_device *dev = ring->dev; |
301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
84b790f8 BW |
302 | uint64_t temp = 0; |
303 | uint32_t desc[4]; | |
304 | ||
305 | /* XXX: You must always write both descriptors in the order below. */ | |
306 | if (ctx_obj1) | |
203a571b | 307 | temp = execlists_ctx_descriptor(ring, ctx_obj1); |
84b790f8 BW |
308 | else |
309 | temp = 0; | |
310 | desc[1] = (u32)(temp >> 32); | |
311 | desc[0] = (u32)temp; | |
312 | ||
203a571b | 313 | temp = execlists_ctx_descriptor(ring, ctx_obj0); |
84b790f8 BW |
314 | desc[3] = (u32)(temp >> 32); |
315 | desc[2] = (u32)temp; | |
316 | ||
a6111f7b CW |
317 | spin_lock(&dev_priv->uncore.lock); |
318 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
319 | I915_WRITE_FW(RING_ELSP(ring), desc[1]); | |
320 | I915_WRITE_FW(RING_ELSP(ring), desc[0]); | |
321 | I915_WRITE_FW(RING_ELSP(ring), desc[3]); | |
6daccb0b | 322 | |
84b790f8 | 323 | /* The context is automatically loaded after the following */ |
a6111f7b | 324 | I915_WRITE_FW(RING_ELSP(ring), desc[2]); |
84b790f8 BW |
325 | |
326 | /* ELSP is a wo register, so use another nearby reg for posting instead */ | |
a6111f7b CW |
327 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
328 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
329 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
330 | } |
331 | ||
05d9824b | 332 | static int execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 333 | { |
05d9824b MK |
334 | struct intel_engine_cs *ring = rq->ring; |
335 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; | |
336 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
337 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; | |
ae1250b9 OM |
338 | struct page *page; |
339 | uint32_t *reg_state; | |
340 | ||
05d9824b MK |
341 | BUG_ON(!ctx_obj); |
342 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); | |
343 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); | |
344 | ||
ae1250b9 OM |
345 | page = i915_gem_object_get_page(ctx_obj, 1); |
346 | reg_state = kmap_atomic(page); | |
347 | ||
05d9824b MK |
348 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
349 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); | |
ae1250b9 | 350 | |
d7b2633d MT |
351 | /* True PPGTT with dynamic page allocation: update PDP registers and |
352 | * point the unallocated PDPs to the scratch page | |
353 | */ | |
354 | if (ppgtt) { | |
355 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
356 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
357 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
358 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
359 | } | |
360 | ||
ae1250b9 OM |
361 | kunmap_atomic(reg_state); |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
d8cb8875 MK |
366 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
367 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 368 | { |
d8cb8875 MK |
369 | struct intel_engine_cs *ring = rq0->ring; |
370 | struct drm_i915_gem_object *ctx_obj0 = rq0->ctx->engine[ring->id].state; | |
84b790f8 BW |
371 | struct drm_i915_gem_object *ctx_obj1 = NULL; |
372 | ||
05d9824b | 373 | execlists_update_context(rq0); |
d8cb8875 MK |
374 | |
375 | if (rq1) { | |
05d9824b | 376 | execlists_update_context(rq1); |
d8cb8875 | 377 | ctx_obj1 = rq1->ctx->engine[ring->id].state; |
84b790f8 BW |
378 | } |
379 | ||
380 | execlists_elsp_write(ring, ctx_obj0, ctx_obj1); | |
84b790f8 BW |
381 | } |
382 | ||
acdd884a MT |
383 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
384 | { | |
6d3d8274 NH |
385 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
386 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
387 | |
388 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 389 | |
779949f4 PA |
390 | /* |
391 | * If irqs are not active generate a warning as batches that finish | |
392 | * without the irqs may get lost and a GPU Hang may occur. | |
393 | */ | |
394 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
395 | ||
acdd884a MT |
396 | if (list_empty(&ring->execlist_queue)) |
397 | return; | |
398 | ||
399 | /* Try to read in pairs */ | |
400 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
401 | execlist_link) { | |
402 | if (!req0) { | |
403 | req0 = cursor; | |
6d3d8274 | 404 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
405 | /* Same ctx: ignore first request, as second request |
406 | * will update tail past first request's workload */ | |
e1fee72c | 407 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 408 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
409 | list_add_tail(&req0->execlist_link, |
410 | &ring->execlist_retired_req_list); | |
acdd884a MT |
411 | req0 = cursor; |
412 | } else { | |
413 | req1 = cursor; | |
414 | break; | |
415 | } | |
416 | } | |
417 | ||
53292cdb MT |
418 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
419 | /* | |
420 | * WaIdleLiteRestore: make sure we never cause a lite | |
421 | * restore with HEAD==TAIL | |
422 | */ | |
d63f820f | 423 | if (req0->elsp_submitted) { |
53292cdb MT |
424 | /* |
425 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
426 | * as we resubmit the request. See gen8_emit_request() | |
427 | * for where we prepare the padding after the end of the | |
428 | * request. | |
429 | */ | |
430 | struct intel_ringbuffer *ringbuf; | |
431 | ||
432 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
433 | req0->tail += 8; | |
434 | req0->tail &= ringbuf->size - 1; | |
435 | } | |
436 | } | |
437 | ||
e1fee72c OM |
438 | WARN_ON(req1 && req1->elsp_submitted); |
439 | ||
d8cb8875 | 440 | execlists_submit_requests(req0, req1); |
e1fee72c OM |
441 | |
442 | req0->elsp_submitted++; | |
443 | if (req1) | |
444 | req1->elsp_submitted++; | |
acdd884a MT |
445 | } |
446 | ||
e981e7b1 TD |
447 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
448 | u32 request_id) | |
449 | { | |
6d3d8274 | 450 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
451 | |
452 | assert_spin_locked(&ring->execlist_lock); | |
453 | ||
454 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 455 | struct drm_i915_gem_request, |
e981e7b1 TD |
456 | execlist_link); |
457 | ||
458 | if (head_req != NULL) { | |
459 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 460 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 461 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
462 | WARN(head_req->elsp_submitted == 0, |
463 | "Never submitted head request\n"); | |
464 | ||
465 | if (--head_req->elsp_submitted <= 0) { | |
466 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
467 | list_add_tail(&head_req->execlist_link, |
468 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
469 | return true; |
470 | } | |
e981e7b1 TD |
471 | } |
472 | } | |
473 | ||
474 | return false; | |
475 | } | |
476 | ||
73e4d07f | 477 | /** |
3f7531c3 | 478 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
479 | * @ring: Engine Command Streamer to handle. |
480 | * | |
481 | * Check the unread Context Status Buffers and manage the submission of new | |
482 | * contexts to the ELSP accordingly. | |
483 | */ | |
3f7531c3 | 484 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
485 | { |
486 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
487 | u32 status_pointer; | |
488 | u8 read_pointer; | |
489 | u8 write_pointer; | |
490 | u32 status; | |
491 | u32 status_id; | |
492 | u32 submit_contexts = 0; | |
493 | ||
494 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
495 | ||
496 | read_pointer = ring->next_context_status_buffer; | |
497 | write_pointer = status_pointer & 0x07; | |
498 | if (read_pointer > write_pointer) | |
499 | write_pointer += 6; | |
500 | ||
501 | spin_lock(&ring->execlist_lock); | |
502 | ||
503 | while (read_pointer < write_pointer) { | |
504 | read_pointer++; | |
505 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
506 | (read_pointer % 6) * 8); | |
507 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
508 | (read_pointer % 6) * 8 + 4); | |
509 | ||
e1fee72c OM |
510 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
511 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
512 | if (execlists_check_remove_request(ring, status_id)) | |
513 | WARN(1, "Lite Restored request removed from queue\n"); | |
514 | } else | |
515 | WARN(1, "Preemption without Lite Restore\n"); | |
516 | } | |
517 | ||
518 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
519 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
520 | if (execlists_check_remove_request(ring, status_id)) |
521 | submit_contexts++; | |
522 | } | |
523 | } | |
524 | ||
525 | if (submit_contexts != 0) | |
526 | execlists_context_unqueue(ring); | |
527 | ||
528 | spin_unlock(&ring->execlist_lock); | |
529 | ||
530 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
531 | ring->next_context_status_buffer = write_pointer % 6; | |
532 | ||
533 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
534 | ((u32)ring->next_context_status_buffer & 0x07) << 8); | |
535 | } | |
536 | ||
ae70797d | 537 | static int execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 538 | { |
ae70797d | 539 | struct intel_engine_cs *ring = request->ring; |
6d3d8274 | 540 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 541 | int num_elements = 0; |
acdd884a | 542 | |
ae70797d JH |
543 | if (request->ctx != ring->default_context) |
544 | intel_lr_context_pin(ring, request->ctx); | |
9bb1af44 JH |
545 | |
546 | i915_gem_request_reference(request); | |
547 | ||
ae70797d | 548 | request->tail = request->ringbuf->tail; |
2d12955a | 549 | |
b5eba372 | 550 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 551 | |
f1ad5a1f OM |
552 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
553 | if (++num_elements > 2) | |
554 | break; | |
555 | ||
556 | if (num_elements > 2) { | |
6d3d8274 | 557 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
558 | |
559 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 560 | struct drm_i915_gem_request, |
f1ad5a1f OM |
561 | execlist_link); |
562 | ||
ae70797d | 563 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 564 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 565 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 566 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
567 | list_add_tail(&tail_req->execlist_link, |
568 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
569 | } |
570 | } | |
571 | ||
6d3d8274 | 572 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 573 | if (num_elements == 0) |
acdd884a MT |
574 | execlists_context_unqueue(ring); |
575 | ||
b5eba372 | 576 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
577 | |
578 | return 0; | |
579 | } | |
580 | ||
2f20055d | 581 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 582 | { |
2f20055d | 583 | struct intel_engine_cs *ring = req->ring; |
ba8b7ccb OM |
584 | uint32_t flush_domains; |
585 | int ret; | |
586 | ||
587 | flush_domains = 0; | |
588 | if (ring->gpu_caches_dirty) | |
589 | flush_domains = I915_GEM_GPU_DOMAINS; | |
590 | ||
7deb4d39 | 591 | ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
592 | if (ret) |
593 | return ret; | |
594 | ||
595 | ring->gpu_caches_dirty = false; | |
596 | return 0; | |
597 | } | |
598 | ||
535fbe82 | 599 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
600 | struct list_head *vmas) |
601 | { | |
535fbe82 | 602 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
ba8b7ccb OM |
603 | struct i915_vma *vma; |
604 | uint32_t flush_domains = 0; | |
605 | bool flush_chipset = false; | |
606 | int ret; | |
607 | ||
608 | list_for_each_entry(vma, vmas, exec_list) { | |
609 | struct drm_i915_gem_object *obj = vma->obj; | |
610 | ||
03ade511 | 611 | if (obj->active & other_rings) { |
91af127f | 612 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
613 | if (ret) |
614 | return ret; | |
615 | } | |
ba8b7ccb OM |
616 | |
617 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
618 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
619 | ||
620 | flush_domains |= obj->base.write_domain; | |
621 | } | |
622 | ||
623 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
624 | wmb(); | |
625 | ||
626 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
627 | * any residual writes from the previous batch. | |
628 | */ | |
2f20055d | 629 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
630 | } |
631 | ||
40e895ce | 632 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 633 | { |
bc0dce3f JH |
634 | int ret; |
635 | ||
f3cc01f0 MK |
636 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
637 | ||
40e895ce JH |
638 | if (request->ctx != request->ring->default_context) { |
639 | ret = intel_lr_context_pin(request->ring, request->ctx); | |
6689cb2b | 640 | if (ret) |
bc0dce3f | 641 | return ret; |
bc0dce3f JH |
642 | } |
643 | ||
bc0dce3f JH |
644 | return 0; |
645 | } | |
646 | ||
ae70797d | 647 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 648 | int bytes) |
bc0dce3f | 649 | { |
ae70797d JH |
650 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
651 | struct intel_engine_cs *ring = req->ring; | |
652 | struct drm_i915_gem_request *target; | |
b4716185 CW |
653 | unsigned space; |
654 | int ret; | |
bc0dce3f JH |
655 | |
656 | if (intel_ring_space(ringbuf) >= bytes) | |
657 | return 0; | |
658 | ||
79bbcc29 JH |
659 | /* The whole point of reserving space is to not wait! */ |
660 | WARN_ON(ringbuf->reserved_in_use); | |
661 | ||
ae70797d | 662 | list_for_each_entry(target, &ring->request_list, list) { |
bc0dce3f JH |
663 | /* |
664 | * The request queue is per-engine, so can contain requests | |
665 | * from multiple ringbuffers. Here, we must ignore any that | |
666 | * aren't from the ringbuffer we're considering. | |
667 | */ | |
ae70797d | 668 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
669 | continue; |
670 | ||
671 | /* Would completion of this request free enough space? */ | |
ae70797d | 672 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
673 | ringbuf->size); |
674 | if (space >= bytes) | |
bc0dce3f | 675 | break; |
bc0dce3f JH |
676 | } |
677 | ||
ae70797d | 678 | if (WARN_ON(&target->list == &ring->request_list)) |
bc0dce3f JH |
679 | return -ENOSPC; |
680 | ||
ae70797d | 681 | ret = i915_wait_request(target); |
bc0dce3f JH |
682 | if (ret) |
683 | return ret; | |
684 | ||
b4716185 CW |
685 | ringbuf->space = space; |
686 | return 0; | |
bc0dce3f JH |
687 | } |
688 | ||
689 | /* | |
690 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 691 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
692 | * |
693 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
694 | * really happens during submission is that the context and current tail will be placed | |
695 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
696 | * point, the tail *inside* the context is updated and the ELSP written to. | |
697 | */ | |
698 | static void | |
ae70797d | 699 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 700 | { |
ae70797d | 701 | struct intel_engine_cs *ring = request->ring; |
bc0dce3f | 702 | |
ae70797d | 703 | intel_logical_ring_advance(request->ringbuf); |
bc0dce3f JH |
704 | |
705 | if (intel_ring_stopped(ring)) | |
706 | return; | |
707 | ||
ae70797d | 708 | execlists_context_queue(request); |
bc0dce3f JH |
709 | } |
710 | ||
79bbcc29 | 711 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
712 | { |
713 | uint32_t __iomem *virt; | |
714 | int rem = ringbuf->size - ringbuf->tail; | |
715 | ||
bc0dce3f JH |
716 | virt = ringbuf->virtual_start + ringbuf->tail; |
717 | rem /= 4; | |
718 | while (rem--) | |
719 | iowrite32(MI_NOOP, virt++); | |
720 | ||
721 | ringbuf->tail = 0; | |
722 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
723 | } |
724 | ||
ae70797d | 725 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 726 | { |
ae70797d | 727 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
728 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
729 | int remain_actual = ringbuf->size - ringbuf->tail; | |
730 | int ret, total_bytes, wait_bytes = 0; | |
731 | bool need_wrap = false; | |
29b1b415 | 732 | |
79bbcc29 JH |
733 | if (ringbuf->reserved_in_use) |
734 | total_bytes = bytes; | |
735 | else | |
736 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 737 | |
79bbcc29 JH |
738 | if (unlikely(bytes > remain_usable)) { |
739 | /* | |
740 | * Not enough space for the basic request. So need to flush | |
741 | * out the remainder and then wait for base + reserved. | |
742 | */ | |
743 | wait_bytes = remain_actual + total_bytes; | |
744 | need_wrap = true; | |
745 | } else { | |
746 | if (unlikely(total_bytes > remain_usable)) { | |
747 | /* | |
748 | * The base request will fit but the reserved space | |
749 | * falls off the end. So only need to to wait for the | |
750 | * reserved size after flushing out the remainder. | |
751 | */ | |
752 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
753 | need_wrap = true; | |
754 | } else if (total_bytes > ringbuf->space) { | |
755 | /* No wrapping required, just waiting. */ | |
756 | wait_bytes = total_bytes; | |
29b1b415 | 757 | } |
bc0dce3f JH |
758 | } |
759 | ||
79bbcc29 JH |
760 | if (wait_bytes) { |
761 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
762 | if (unlikely(ret)) |
763 | return ret; | |
79bbcc29 JH |
764 | |
765 | if (need_wrap) | |
766 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
767 | } |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
772 | /** | |
773 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
774 | * | |
4d616a29 | 775 | * @request: The request to start some new work for |
4d78c8dc | 776 | * @ctx: Logical ring context whose ringbuffer is being prepared. |
bc0dce3f JH |
777 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
778 | * | |
779 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
780 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
781 | * and also preallocates a request (every workload submission is still mediated through | |
782 | * requests, same as it did with legacy ringbuffer submission). | |
783 | * | |
784 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
785 | */ | |
4d616a29 JH |
786 | static int intel_logical_ring_begin(struct drm_i915_gem_request *req, |
787 | int num_dwords) | |
bc0dce3f | 788 | { |
4d616a29 | 789 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
790 | int ret; |
791 | ||
4d616a29 JH |
792 | WARN_ON(req == NULL); |
793 | dev_priv = req->ring->dev->dev_private; | |
794 | ||
bc0dce3f JH |
795 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
796 | dev_priv->mm.interruptible); | |
797 | if (ret) | |
798 | return ret; | |
799 | ||
ae70797d | 800 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
801 | if (ret) |
802 | return ret; | |
803 | ||
4d616a29 | 804 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
805 | return 0; |
806 | } | |
807 | ||
ccd98fe4 JH |
808 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
809 | { | |
810 | /* | |
811 | * The first call merely notes the reserve request and is common for | |
812 | * all back ends. The subsequent localised _begin() call actually | |
813 | * ensures that the reservation is available. Without the begin, if | |
814 | * the request creator immediately submitted the request without | |
815 | * adding any commands to it then there might not actually be | |
816 | * sufficient room for the submission commands. | |
817 | */ | |
818 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
819 | ||
820 | return intel_logical_ring_begin(request, 0); | |
821 | } | |
822 | ||
73e4d07f OM |
823 | /** |
824 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
825 | * @dev: DRM device. | |
826 | * @file: DRM file. | |
827 | * @ring: Engine Command Streamer to submit to. | |
828 | * @ctx: Context to employ for this submission. | |
829 | * @args: execbuffer call arguments. | |
830 | * @vmas: list of vmas. | |
831 | * @batch_obj: the batchbuffer to submit. | |
832 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 833 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
834 | * |
835 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
836 | * away the submission details of the execbuffer ioctl call. | |
837 | * | |
838 | * Return: non-zero if the submission fails. | |
839 | */ | |
5f19e2bf | 840 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 841 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 842 | struct list_head *vmas) |
454afebd | 843 | { |
5f19e2bf JH |
844 | struct drm_device *dev = params->dev; |
845 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 846 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
847 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
848 | u64 exec_start; | |
ba8b7ccb OM |
849 | int instp_mode; |
850 | u32 instp_mask; | |
851 | int ret; | |
852 | ||
853 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
854 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
855 | switch (instp_mode) { | |
856 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
857 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
858 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
859 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
860 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
864 | if (instp_mode != dev_priv->relative_constants_mode) { | |
865 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
866 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
867 | return -EINVAL; | |
868 | } | |
869 | ||
870 | /* The HW changed the meaning on this bit on gen6 */ | |
871 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
872 | } | |
873 | break; | |
874 | default: | |
875 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
876 | return -EINVAL; | |
877 | } | |
878 | ||
879 | if (args->num_cliprects != 0) { | |
880 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
881 | return -EINVAL; | |
882 | } else { | |
883 | if (args->DR4 == 0xffffffff) { | |
884 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
885 | args->DR4 = 0; | |
886 | } | |
887 | ||
888 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
889 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
890 | return -EINVAL; | |
891 | } | |
892 | } | |
893 | ||
894 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
895 | DRM_DEBUG("sol reset is gen7 only\n"); | |
896 | return -EINVAL; | |
897 | } | |
898 | ||
535fbe82 | 899 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
900 | if (ret) |
901 | return ret; | |
902 | ||
903 | if (ring == &dev_priv->ring[RCS] && | |
904 | instp_mode != dev_priv->relative_constants_mode) { | |
4d616a29 | 905 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
906 | if (ret) |
907 | return ret; | |
908 | ||
909 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
910 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
911 | intel_logical_ring_emit(ringbuf, INSTPM); | |
912 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
913 | intel_logical_ring_advance(ringbuf); | |
914 | ||
915 | dev_priv->relative_constants_mode = instp_mode; | |
916 | } | |
917 | ||
5f19e2bf JH |
918 | exec_start = params->batch_obj_vm_offset + |
919 | args->batch_start_offset; | |
920 | ||
be795fc1 | 921 | ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
922 | if (ret) |
923 | return ret; | |
924 | ||
95c24161 | 925 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 926 | |
8a8edb59 | 927 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 928 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 929 | |
454afebd OM |
930 | return 0; |
931 | } | |
932 | ||
c86ee3a9 TD |
933 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
934 | { | |
6d3d8274 | 935 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
936 | struct list_head retired_list; |
937 | ||
938 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
939 | if (list_empty(&ring->execlist_retired_req_list)) | |
940 | return; | |
941 | ||
942 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 943 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 944 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 945 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
946 | |
947 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 948 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
949 | struct drm_i915_gem_object *ctx_obj = |
950 | ctx->engine[ring->id].state; | |
951 | ||
952 | if (ctx_obj && (ctx != ring->default_context)) | |
953 | intel_lr_context_unpin(ring, ctx); | |
c86ee3a9 | 954 | list_del(&req->execlist_link); |
f8210795 | 955 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
956 | } |
957 | } | |
958 | ||
454afebd OM |
959 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
960 | { | |
9832b9da OM |
961 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
962 | int ret; | |
963 | ||
964 | if (!intel_ring_initialized(ring)) | |
965 | return; | |
966 | ||
967 | ret = intel_ring_idle(ring); | |
968 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
969 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
970 | ring->name, ret); | |
971 | ||
972 | /* TODO: Is this correct with Execlists enabled? */ | |
973 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
974 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
975 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
976 | return; | |
977 | } | |
978 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
979 | } |
980 | ||
4866d729 | 981 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 982 | { |
4866d729 | 983 | struct intel_engine_cs *ring = req->ring; |
48e29f55 OM |
984 | int ret; |
985 | ||
986 | if (!ring->gpu_caches_dirty) | |
987 | return 0; | |
988 | ||
7deb4d39 | 989 | ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
990 | if (ret) |
991 | return ret; | |
992 | ||
993 | ring->gpu_caches_dirty = false; | |
994 | return 0; | |
995 | } | |
996 | ||
dcb4c12a OM |
997 | static int intel_lr_context_pin(struct intel_engine_cs *ring, |
998 | struct intel_context *ctx) | |
999 | { | |
1000 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1001 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1002 | int ret = 0; |
1003 | ||
1004 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1005 | if (ctx->engine[ring->id].pin_count++ == 0) { |
dcb4c12a OM |
1006 | ret = i915_gem_obj_ggtt_pin(ctx_obj, |
1007 | GEN8_LR_CONTEXT_ALIGN, 0); | |
1008 | if (ret) | |
a7cbedec | 1009 | goto reset_pin_count; |
7ba717cf TD |
1010 | |
1011 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); | |
1012 | if (ret) | |
1013 | goto unpin_ctx_obj; | |
dcb4c12a OM |
1014 | } |
1015 | ||
7ba717cf TD |
1016 | return ret; |
1017 | ||
1018 | unpin_ctx_obj: | |
1019 | i915_gem_object_ggtt_unpin(ctx_obj); | |
a7cbedec MK |
1020 | reset_pin_count: |
1021 | ctx->engine[ring->id].pin_count = 0; | |
7ba717cf | 1022 | |
dcb4c12a OM |
1023 | return ret; |
1024 | } | |
1025 | ||
1026 | void intel_lr_context_unpin(struct intel_engine_cs *ring, | |
1027 | struct intel_context *ctx) | |
1028 | { | |
1029 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; | |
7ba717cf | 1030 | struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; |
dcb4c12a OM |
1031 | |
1032 | if (ctx_obj) { | |
1033 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
a7cbedec | 1034 | if (--ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1035 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1036 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1037 | } |
dcb4c12a OM |
1038 | } |
1039 | } | |
1040 | ||
e2be4faf | 1041 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1042 | { |
1043 | int ret, i; | |
e2be4faf JH |
1044 | struct intel_engine_cs *ring = req->ring; |
1045 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
771b9a53 MT |
1046 | struct drm_device *dev = ring->dev; |
1047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1048 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1049 | ||
e6c1abb7 | 1050 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1051 | return 0; |
1052 | ||
1053 | ring->gpu_caches_dirty = true; | |
4866d729 | 1054 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1055 | if (ret) |
1056 | return ret; | |
1057 | ||
4d616a29 | 1058 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1059 | if (ret) |
1060 | return ret; | |
1061 | ||
1062 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1063 | for (i = 0; i < w->count; i++) { | |
1064 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1065 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1066 | } | |
1067 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1068 | ||
1069 | intel_logical_ring_advance(ringbuf); | |
1070 | ||
1071 | ring->gpu_caches_dirty = true; | |
4866d729 | 1072 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1073 | if (ret) |
1074 | return ret; | |
1075 | ||
1076 | return 0; | |
1077 | } | |
1078 | ||
17ee950d AS |
1079 | #define wa_ctx_emit(batch, cmd) \ |
1080 | do { \ | |
1081 | if (WARN_ON(index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
1082 | return -ENOSPC; \ | |
1083 | } \ | |
1084 | batch[index++] = (cmd); \ | |
1085 | } while (0) | |
1086 | ||
9e000847 AS |
1087 | |
1088 | /* | |
1089 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1090 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1091 | * but there is a slight complication as this is applied in WA batch where the | |
1092 | * values are only initialized once so we cannot take register value at the | |
1093 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1094 | * constant value with bit21 set and then we restore it back with the saved value. | |
1095 | * To simplify the WA, a constant value is formed by using the default value | |
1096 | * of this register. This shouldn't be a problem because we are only modifying | |
1097 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1098 | * use additional instructions that read the actual value of the register | |
1099 | * at that time and set our bit of interest but it makes the WA complicated. | |
1100 | * | |
1101 | * This WA is also required for Gen9 so extracting as a function avoids | |
1102 | * code duplication. | |
1103 | */ | |
1104 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, | |
1105 | uint32_t *const batch, | |
1106 | uint32_t index) | |
1107 | { | |
1108 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1109 | ||
1110 | wa_ctx_emit(batch, (MI_STORE_REGISTER_MEM_GEN8(1) | | |
1111 | MI_SRM_LRM_GLOBAL_GTT)); | |
1112 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1113 | wa_ctx_emit(batch, ring->scratch.gtt_offset + 256); | |
1114 | wa_ctx_emit(batch, 0); | |
1115 | ||
1116 | wa_ctx_emit(batch, MI_LOAD_REGISTER_IMM(1)); | |
1117 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1118 | wa_ctx_emit(batch, l3sqc4_flush); | |
1119 | ||
1120 | wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6)); | |
1121 | wa_ctx_emit(batch, (PIPE_CONTROL_CS_STALL | | |
1122 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1123 | wa_ctx_emit(batch, 0); | |
1124 | wa_ctx_emit(batch, 0); | |
1125 | wa_ctx_emit(batch, 0); | |
1126 | wa_ctx_emit(batch, 0); | |
1127 | ||
1128 | wa_ctx_emit(batch, (MI_LOAD_REGISTER_MEM_GEN8(1) | | |
1129 | MI_SRM_LRM_GLOBAL_GTT)); | |
1130 | wa_ctx_emit(batch, GEN8_L3SQCREG4); | |
1131 | wa_ctx_emit(batch, ring->scratch.gtt_offset + 256); | |
1132 | wa_ctx_emit(batch, 0); | |
1133 | ||
1134 | return index; | |
1135 | } | |
1136 | ||
17ee950d AS |
1137 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1138 | uint32_t offset, | |
1139 | uint32_t start_alignment) | |
1140 | { | |
1141 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1142 | } | |
1143 | ||
1144 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1145 | uint32_t offset, | |
1146 | uint32_t size_alignment) | |
1147 | { | |
1148 | wa_ctx->size = offset - wa_ctx->offset; | |
1149 | ||
1150 | WARN(wa_ctx->size % size_alignment, | |
1151 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1152 | wa_ctx->size, size_alignment); | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | /** | |
1157 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1158 | * | |
1159 | * @ring: only applicable for RCS | |
1160 | * @wa_ctx: structure representing wa_ctx | |
1161 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1162 | * with the offset value received as input. | |
1163 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1164 | * @batch: page in which WA are loaded | |
1165 | * @offset: This field specifies the start of the batch, it should be | |
1166 | * cache-aligned otherwise it is adjusted accordingly. | |
1167 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1168 | * initialized at the beginning and shared across all contexts but this field | |
1169 | * helps us to have multiple batches at different offsets and select them based | |
1170 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1171 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1172 | * | |
1173 | * The number of WA applied are not known at the beginning; we use this field | |
1174 | * to return the no of DWORDS written. | |
4d78c8dc | 1175 | * |
17ee950d AS |
1176 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1177 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1178 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1179 | * makes a complete batch buffer. | |
1180 | * | |
1181 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1182 | */ | |
1183 | ||
1184 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1185 | struct i915_wa_ctx_bb *wa_ctx, | |
1186 | uint32_t *const batch, | |
1187 | uint32_t *offset) | |
1188 | { | |
0160f055 | 1189 | uint32_t scratch_addr; |
17ee950d AS |
1190 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1191 | ||
7ad00d1a AS |
1192 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1193 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
17ee950d | 1194 | |
c82435bb AS |
1195 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1196 | if (IS_BROADWELL(ring->dev)) { | |
9e000847 AS |
1197 | index = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
1198 | if (index < 0) | |
1199 | return index; | |
c82435bb AS |
1200 | } |
1201 | ||
0160f055 AS |
1202 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1203 | /* Actual scratch location is at 128 bytes offset */ | |
1204 | scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; | |
1205 | ||
1206 | wa_ctx_emit(batch, GFX_OP_PIPE_CONTROL(6)); | |
1207 | wa_ctx_emit(batch, (PIPE_CONTROL_FLUSH_L3 | | |
1208 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1209 | PIPE_CONTROL_CS_STALL | | |
1210 | PIPE_CONTROL_QW_WRITE)); | |
1211 | wa_ctx_emit(batch, scratch_addr); | |
1212 | wa_ctx_emit(batch, 0); | |
1213 | wa_ctx_emit(batch, 0); | |
1214 | wa_ctx_emit(batch, 0); | |
1215 | ||
17ee950d AS |
1216 | /* Pad to end of cacheline */ |
1217 | while (index % CACHELINE_DWORDS) | |
1218 | wa_ctx_emit(batch, MI_NOOP); | |
1219 | ||
1220 | /* | |
1221 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1222 | * execution depends on the length specified in terms of cache lines | |
1223 | * in the register CTX_RCS_INDIRECT_CTX | |
1224 | */ | |
1225 | ||
1226 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1227 | } | |
1228 | ||
1229 | /** | |
1230 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1231 | * | |
1232 | * @ring: only applicable for RCS | |
1233 | * @wa_ctx: structure representing wa_ctx | |
1234 | * offset: specifies start of the batch, should be cache-aligned. | |
1235 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1236 | * @batch: page in which WA are loaded |
17ee950d AS |
1237 | * @offset: This field specifies the start of this batch. |
1238 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1239 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1240 | * | |
1241 | * The number of DWORDS written are returned using this field. | |
1242 | * | |
1243 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1244 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1245 | */ | |
1246 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1247 | struct i915_wa_ctx_bb *wa_ctx, | |
1248 | uint32_t *const batch, | |
1249 | uint32_t *offset) | |
1250 | { | |
1251 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1252 | ||
7ad00d1a AS |
1253 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
1254 | wa_ctx_emit(batch, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1255 | ||
17ee950d AS |
1256 | wa_ctx_emit(batch, MI_BATCH_BUFFER_END); |
1257 | ||
1258 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1259 | } | |
1260 | ||
1261 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) | |
1262 | { | |
1263 | int ret; | |
1264 | ||
1265 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1266 | if (!ring->wa_ctx.obj) { | |
1267 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1268 | return -ENOMEM; | |
1269 | } | |
1270 | ||
1271 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1272 | if (ret) { | |
1273 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1274 | ret); | |
1275 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1283 | { | |
1284 | if (ring->wa_ctx.obj) { | |
1285 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1286 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1287 | ring->wa_ctx.obj = NULL; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1292 | { | |
1293 | int ret; | |
1294 | uint32_t *batch; | |
1295 | uint32_t offset; | |
1296 | struct page *page; | |
1297 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1298 | ||
1299 | WARN_ON(ring->id != RCS); | |
1300 | ||
5e60d790 AS |
1301 | /* update this when WA for higher Gen are added */ |
1302 | if (WARN(INTEL_INFO(ring->dev)->gen > 8, | |
1303 | "WA batch buffer is not initialized for Gen%d\n", | |
1304 | INTEL_INFO(ring->dev)->gen)) | |
1305 | return 0; | |
1306 | ||
c4db7599 AS |
1307 | /* some WA perform writes to scratch page, ensure it is valid */ |
1308 | if (ring->scratch.obj == NULL) { | |
1309 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1310 | return -EINVAL; | |
1311 | } | |
1312 | ||
17ee950d AS |
1313 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1314 | if (ret) { | |
1315 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1320 | batch = kmap_atomic(page); | |
1321 | offset = 0; | |
1322 | ||
1323 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1324 | ret = gen8_init_indirectctx_bb(ring, | |
1325 | &wa_ctx->indirect_ctx, | |
1326 | batch, | |
1327 | &offset); | |
1328 | if (ret) | |
1329 | goto out; | |
1330 | ||
1331 | ret = gen8_init_perctx_bb(ring, | |
1332 | &wa_ctx->per_ctx, | |
1333 | batch, | |
1334 | &offset); | |
1335 | if (ret) | |
1336 | goto out; | |
17ee950d AS |
1337 | } |
1338 | ||
1339 | out: | |
1340 | kunmap_atomic(batch); | |
1341 | if (ret) | |
1342 | lrc_destroy_wa_ctx_obj(ring); | |
1343 | ||
1344 | return ret; | |
1345 | } | |
1346 | ||
9b1136d5 OM |
1347 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1348 | { | |
1349 | struct drm_device *dev = ring->dev; | |
1350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1351 | ||
73d477f6 OM |
1352 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1353 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1354 | ||
9b1136d5 OM |
1355 | I915_WRITE(RING_MODE_GEN7(ring), |
1356 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1357 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1358 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1359 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1360 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1361 | ||
1362 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1368 | { | |
1369 | struct drm_device *dev = ring->dev; | |
1370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1371 | int ret; | |
1372 | ||
1373 | ret = gen8_init_common_ring(ring); | |
1374 | if (ret) | |
1375 | return ret; | |
1376 | ||
1377 | /* We need to disable the AsyncFlip performance optimisations in order | |
1378 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1379 | * programmed to '1' on all products. | |
1380 | * | |
1381 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1382 | */ | |
1383 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1384 | ||
9b1136d5 OM |
1385 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1386 | ||
771b9a53 | 1387 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1388 | } |
1389 | ||
82ef822e DL |
1390 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1391 | { | |
1392 | int ret; | |
1393 | ||
1394 | ret = gen8_init_common_ring(ring); | |
1395 | if (ret) | |
1396 | return ret; | |
1397 | ||
1398 | return init_workarounds_ring(ring); | |
1399 | } | |
1400 | ||
7a01a0a2 MT |
1401 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1402 | { | |
1403 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
1404 | struct intel_engine_cs *ring = req->ring; | |
1405 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
1406 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1407 | int i, ret; | |
1408 | ||
1409 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1410 | if (ret) | |
1411 | return ret; | |
1412 | ||
1413 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1414 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1415 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1416 | ||
1417 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); | |
1418 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); | |
1419 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); | |
1420 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); | |
1421 | } | |
1422 | ||
1423 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1424 | intel_logical_ring_advance(ringbuf); | |
1425 | ||
1426 | return 0; | |
1427 | } | |
1428 | ||
be795fc1 | 1429 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1430 | u64 offset, unsigned dispatch_flags) |
15648585 | 1431 | { |
be795fc1 | 1432 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1433 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1434 | int ret; |
1435 | ||
7a01a0a2 MT |
1436 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1437 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1438 | * but we can't. Force Restore would be a second option, but | |
1439 | * it is unsafe in case of lite-restore (because the ctx is | |
1440 | * not idle). */ | |
1441 | if (req->ctx->ppgtt && | |
1442 | (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { | |
1443 | ret = intel_logical_ring_emit_pdps(req); | |
1444 | if (ret) | |
1445 | return ret; | |
1446 | ||
1447 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); | |
1448 | } | |
1449 | ||
4d616a29 | 1450 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1451 | if (ret) |
1452 | return ret; | |
1453 | ||
1454 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1455 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1456 | (ppgtt<<8) | | |
1457 | (dispatch_flags & I915_DISPATCH_RS ? | |
1458 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1459 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1460 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1461 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1462 | intel_logical_ring_advance(ringbuf); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
73d477f6 OM |
1467 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1468 | { | |
1469 | struct drm_device *dev = ring->dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1471 | unsigned long flags; | |
1472 | ||
7cd512f1 | 1473 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1474 | return false; |
1475 | ||
1476 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1477 | if (ring->irq_refcount++ == 0) { | |
1478 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1479 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1480 | } | |
1481 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1482 | ||
1483 | return true; | |
1484 | } | |
1485 | ||
1486 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1487 | { | |
1488 | struct drm_device *dev = ring->dev; | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | unsigned long flags; | |
1491 | ||
1492 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1493 | if (--ring->irq_refcount == 0) { | |
1494 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1495 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1496 | } | |
1497 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1498 | } | |
1499 | ||
7deb4d39 | 1500 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1501 | u32 invalidate_domains, |
1502 | u32 unused) | |
1503 | { | |
7deb4d39 | 1504 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1505 | struct intel_engine_cs *ring = ringbuf->ring; |
1506 | struct drm_device *dev = ring->dev; | |
1507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1508 | uint32_t cmd; | |
1509 | int ret; | |
1510 | ||
4d616a29 | 1511 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1512 | if (ret) |
1513 | return ret; | |
1514 | ||
1515 | cmd = MI_FLUSH_DW + 1; | |
1516 | ||
f0a1fb10 CW |
1517 | /* We always require a command barrier so that subsequent |
1518 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1519 | * wrt the contents of the write cache being flushed to memory | |
1520 | * (and thus being coherent from the CPU). | |
1521 | */ | |
1522 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1523 | ||
1524 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1525 | cmd |= MI_INVALIDATE_TLB; | |
1526 | if (ring == &dev_priv->ring[VCS]) | |
1527 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1528 | } |
1529 | ||
1530 | intel_logical_ring_emit(ringbuf, cmd); | |
1531 | intel_logical_ring_emit(ringbuf, | |
1532 | I915_GEM_HWS_SCRATCH_ADDR | | |
1533 | MI_FLUSH_DW_USE_GTT); | |
1534 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1535 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1536 | intel_logical_ring_advance(ringbuf); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
7deb4d39 | 1541 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1542 | u32 invalidate_domains, |
1543 | u32 flush_domains) | |
1544 | { | |
7deb4d39 | 1545 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1546 | struct intel_engine_cs *ring = ringbuf->ring; |
1547 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1548 | bool vf_flush_wa; |
4712274c OM |
1549 | u32 flags = 0; |
1550 | int ret; | |
1551 | ||
1552 | flags |= PIPE_CONTROL_CS_STALL; | |
1553 | ||
1554 | if (flush_domains) { | |
1555 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1556 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1557 | } | |
1558 | ||
1559 | if (invalidate_domains) { | |
1560 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1561 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1562 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1563 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1564 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1565 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1566 | flags |= PIPE_CONTROL_QW_WRITE; | |
1567 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1568 | } | |
1569 | ||
9647ff36 ID |
1570 | /* |
1571 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1572 | * control. | |
1573 | */ | |
1574 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1575 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1576 | ||
4d616a29 | 1577 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1578 | if (ret) |
1579 | return ret; | |
1580 | ||
9647ff36 ID |
1581 | if (vf_flush_wa) { |
1582 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1583 | intel_logical_ring_emit(ringbuf, 0); | |
1584 | intel_logical_ring_emit(ringbuf, 0); | |
1585 | intel_logical_ring_emit(ringbuf, 0); | |
1586 | intel_logical_ring_emit(ringbuf, 0); | |
1587 | intel_logical_ring_emit(ringbuf, 0); | |
1588 | } | |
1589 | ||
4712274c OM |
1590 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1591 | intel_logical_ring_emit(ringbuf, flags); | |
1592 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1593 | intel_logical_ring_emit(ringbuf, 0); | |
1594 | intel_logical_ring_emit(ringbuf, 0); | |
1595 | intel_logical_ring_emit(ringbuf, 0); | |
1596 | intel_logical_ring_advance(ringbuf); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
e94e37ad OM |
1601 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1602 | { | |
1603 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1604 | } | |
1605 | ||
1606 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1607 | { | |
1608 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1609 | } | |
1610 | ||
c4e76638 | 1611 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1612 | { |
c4e76638 | 1613 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1614 | struct intel_engine_cs *ring = ringbuf->ring; |
1615 | u32 cmd; | |
1616 | int ret; | |
1617 | ||
53292cdb MT |
1618 | /* |
1619 | * Reserve space for 2 NOOPs at the end of each request to be | |
1620 | * used as a workaround for not being allowed to do lite | |
1621 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1622 | */ | |
4d616a29 | 1623 | ret = intel_logical_ring_begin(request, 8); |
4da46e1e OM |
1624 | if (ret) |
1625 | return ret; | |
1626 | ||
8edfbb8b | 1627 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1628 | cmd |= MI_GLOBAL_GTT; |
1629 | ||
1630 | intel_logical_ring_emit(ringbuf, cmd); | |
1631 | intel_logical_ring_emit(ringbuf, | |
1632 | (ring->status_page.gfx_addr + | |
1633 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1634 | intel_logical_ring_emit(ringbuf, 0); | |
c4e76638 | 1635 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1636 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1637 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
ae70797d | 1638 | intel_logical_ring_advance_and_submit(request); |
4da46e1e | 1639 | |
53292cdb MT |
1640 | /* |
1641 | * Here we add two extra NOOPs as padding to avoid | |
1642 | * lite restore of a context with HEAD==TAIL. | |
1643 | */ | |
1644 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1645 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1646 | intel_logical_ring_advance(ringbuf); | |
1647 | ||
4da46e1e OM |
1648 | return 0; |
1649 | } | |
1650 | ||
be01363f | 1651 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1652 | { |
cef437ad | 1653 | struct render_state so; |
cef437ad DL |
1654 | int ret; |
1655 | ||
be01363f | 1656 | ret = i915_gem_render_state_prepare(req->ring, &so); |
cef437ad DL |
1657 | if (ret) |
1658 | return ret; | |
1659 | ||
1660 | if (so.rodata == NULL) | |
1661 | return 0; | |
1662 | ||
be795fc1 | 1663 | ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1664 | I915_DISPATCH_SECURE); |
cef437ad DL |
1665 | if (ret) |
1666 | goto out; | |
1667 | ||
b2af0376 | 1668 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1669 | |
cef437ad DL |
1670 | out: |
1671 | i915_gem_render_state_fini(&so); | |
1672 | return ret; | |
1673 | } | |
1674 | ||
8753181e | 1675 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1676 | { |
1677 | int ret; | |
1678 | ||
e2be4faf | 1679 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1680 | if (ret) |
1681 | return ret; | |
1682 | ||
be01363f | 1683 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1684 | } |
1685 | ||
73e4d07f OM |
1686 | /** |
1687 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1688 | * | |
1689 | * @ring: Engine Command Streamer. | |
1690 | * | |
1691 | */ | |
454afebd OM |
1692 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1693 | { | |
6402c330 | 1694 | struct drm_i915_private *dev_priv; |
9832b9da | 1695 | |
48d82387 OM |
1696 | if (!intel_ring_initialized(ring)) |
1697 | return; | |
1698 | ||
6402c330 JH |
1699 | dev_priv = ring->dev->dev_private; |
1700 | ||
9832b9da OM |
1701 | intel_logical_ring_stop(ring); |
1702 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1703 | |
1704 | if (ring->cleanup) | |
1705 | ring->cleanup(ring); | |
1706 | ||
1707 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1708 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1709 | |
1710 | if (ring->status_page.obj) { | |
1711 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1712 | ring->status_page.obj = NULL; | |
1713 | } | |
17ee950d AS |
1714 | |
1715 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1716 | } |
1717 | ||
1718 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1719 | { | |
48d82387 | 1720 | int ret; |
48d82387 OM |
1721 | |
1722 | /* Intentionally left blank. */ | |
1723 | ring->buffer = NULL; | |
1724 | ||
1725 | ring->dev = dev; | |
1726 | INIT_LIST_HEAD(&ring->active_list); | |
1727 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1728 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1729 | init_waitqueue_head(&ring->irq_queue); |
1730 | ||
acdd884a | 1731 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1732 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1733 | spin_lock_init(&ring->execlist_lock); |
1734 | ||
48d82387 OM |
1735 | ret = i915_cmd_parser_init_ring(ring); |
1736 | if (ret) | |
1737 | return ret; | |
1738 | ||
564ddb2f OM |
1739 | ret = intel_lr_context_deferred_create(ring->default_context, ring); |
1740 | ||
1741 | return ret; | |
454afebd OM |
1742 | } |
1743 | ||
1744 | static int logical_render_ring_init(struct drm_device *dev) | |
1745 | { | |
1746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1747 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1748 | int ret; |
454afebd OM |
1749 | |
1750 | ring->name = "render ring"; | |
1751 | ring->id = RCS; | |
1752 | ring->mmio_base = RENDER_RING_BASE; | |
1753 | ring->irq_enable_mask = | |
1754 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1755 | ring->irq_keep_mask = |
1756 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1757 | if (HAS_L3_DPF(dev)) | |
1758 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1759 | |
82ef822e DL |
1760 | if (INTEL_INFO(dev)->gen >= 9) |
1761 | ring->init_hw = gen9_init_render_ring; | |
1762 | else | |
1763 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1764 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1765 | ring->cleanup = intel_fini_pipe_control; |
e94e37ad OM |
1766 | ring->get_seqno = gen8_get_seqno; |
1767 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1768 | ring->emit_request = gen8_emit_request; |
4712274c | 1769 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1770 | ring->irq_get = gen8_logical_ring_get_irq; |
1771 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1772 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1773 | |
99be1dfe | 1774 | ring->dev = dev; |
c4db7599 AS |
1775 | |
1776 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1777 | if (ret) |
1778 | return ret; | |
1779 | ||
17ee950d AS |
1780 | ret = intel_init_workaround_bb(ring); |
1781 | if (ret) { | |
1782 | /* | |
1783 | * We continue even if we fail to initialize WA batch | |
1784 | * because we only expect rare glitches but nothing | |
1785 | * critical to prevent us from using GPU | |
1786 | */ | |
1787 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1788 | ret); | |
1789 | } | |
1790 | ||
c4db7599 AS |
1791 | ret = logical_ring_init(dev, ring); |
1792 | if (ret) { | |
17ee950d | 1793 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1794 | } |
17ee950d AS |
1795 | |
1796 | return ret; | |
454afebd OM |
1797 | } |
1798 | ||
1799 | static int logical_bsd_ring_init(struct drm_device *dev) | |
1800 | { | |
1801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1802 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
1803 | ||
1804 | ring->name = "bsd ring"; | |
1805 | ring->id = VCS; | |
1806 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
1807 | ring->irq_enable_mask = | |
1808 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
1809 | ring->irq_keep_mask = |
1810 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 1811 | |
ecfe00d8 | 1812 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1813 | ring->get_seqno = gen8_get_seqno; |
1814 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1815 | ring->emit_request = gen8_emit_request; |
4712274c | 1816 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1817 | ring->irq_get = gen8_logical_ring_get_irq; |
1818 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1819 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1820 | |
454afebd OM |
1821 | return logical_ring_init(dev, ring); |
1822 | } | |
1823 | ||
1824 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
1825 | { | |
1826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1827 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
1828 | ||
1829 | ring->name = "bds2 ring"; | |
1830 | ring->id = VCS2; | |
1831 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
1832 | ring->irq_enable_mask = | |
1833 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
1834 | ring->irq_keep_mask = |
1835 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 1836 | |
ecfe00d8 | 1837 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1838 | ring->get_seqno = gen8_get_seqno; |
1839 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1840 | ring->emit_request = gen8_emit_request; |
4712274c | 1841 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1842 | ring->irq_get = gen8_logical_ring_get_irq; |
1843 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1844 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1845 | |
454afebd OM |
1846 | return logical_ring_init(dev, ring); |
1847 | } | |
1848 | ||
1849 | static int logical_blt_ring_init(struct drm_device *dev) | |
1850 | { | |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1852 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
1853 | ||
1854 | ring->name = "blitter ring"; | |
1855 | ring->id = BCS; | |
1856 | ring->mmio_base = BLT_RING_BASE; | |
1857 | ring->irq_enable_mask = | |
1858 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
1859 | ring->irq_keep_mask = |
1860 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 1861 | |
ecfe00d8 | 1862 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1863 | ring->get_seqno = gen8_get_seqno; |
1864 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1865 | ring->emit_request = gen8_emit_request; |
4712274c | 1866 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1867 | ring->irq_get = gen8_logical_ring_get_irq; |
1868 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1869 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1870 | |
454afebd OM |
1871 | return logical_ring_init(dev, ring); |
1872 | } | |
1873 | ||
1874 | static int logical_vebox_ring_init(struct drm_device *dev) | |
1875 | { | |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1877 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
1878 | ||
1879 | ring->name = "video enhancement ring"; | |
1880 | ring->id = VECS; | |
1881 | ring->mmio_base = VEBOX_RING_BASE; | |
1882 | ring->irq_enable_mask = | |
1883 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
1884 | ring->irq_keep_mask = |
1885 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 1886 | |
ecfe00d8 | 1887 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
1888 | ring->get_seqno = gen8_get_seqno; |
1889 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 1890 | ring->emit_request = gen8_emit_request; |
4712274c | 1891 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
1892 | ring->irq_get = gen8_logical_ring_get_irq; |
1893 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1894 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1895 | |
454afebd OM |
1896 | return logical_ring_init(dev, ring); |
1897 | } | |
1898 | ||
73e4d07f OM |
1899 | /** |
1900 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
1901 | * @dev: DRM device. | |
1902 | * | |
1903 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
1904 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
1905 | * those engines that are present in the hardware. | |
1906 | * | |
1907 | * Return: non-zero if the initialization failed. | |
1908 | */ | |
454afebd OM |
1909 | int intel_logical_rings_init(struct drm_device *dev) |
1910 | { | |
1911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1912 | int ret; | |
1913 | ||
1914 | ret = logical_render_ring_init(dev); | |
1915 | if (ret) | |
1916 | return ret; | |
1917 | ||
1918 | if (HAS_BSD(dev)) { | |
1919 | ret = logical_bsd_ring_init(dev); | |
1920 | if (ret) | |
1921 | goto cleanup_render_ring; | |
1922 | } | |
1923 | ||
1924 | if (HAS_BLT(dev)) { | |
1925 | ret = logical_blt_ring_init(dev); | |
1926 | if (ret) | |
1927 | goto cleanup_bsd_ring; | |
1928 | } | |
1929 | ||
1930 | if (HAS_VEBOX(dev)) { | |
1931 | ret = logical_vebox_ring_init(dev); | |
1932 | if (ret) | |
1933 | goto cleanup_blt_ring; | |
1934 | } | |
1935 | ||
1936 | if (HAS_BSD2(dev)) { | |
1937 | ret = logical_bsd2_ring_init(dev); | |
1938 | if (ret) | |
1939 | goto cleanup_vebox_ring; | |
1940 | } | |
1941 | ||
1942 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); | |
1943 | if (ret) | |
1944 | goto cleanup_bsd2_ring; | |
1945 | ||
1946 | return 0; | |
1947 | ||
1948 | cleanup_bsd2_ring: | |
1949 | intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); | |
1950 | cleanup_vebox_ring: | |
1951 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
1952 | cleanup_blt_ring: | |
1953 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
1954 | cleanup_bsd_ring: | |
1955 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
1956 | cleanup_render_ring: | |
1957 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
1958 | ||
1959 | return ret; | |
1960 | } | |
1961 | ||
0cea6502 JM |
1962 | static u32 |
1963 | make_rpcs(struct drm_device *dev) | |
1964 | { | |
1965 | u32 rpcs = 0; | |
1966 | ||
1967 | /* | |
1968 | * No explicit RPCS request is needed to ensure full | |
1969 | * slice/subslice/EU enablement prior to Gen9. | |
1970 | */ | |
1971 | if (INTEL_INFO(dev)->gen < 9) | |
1972 | return 0; | |
1973 | ||
1974 | /* | |
1975 | * Starting in Gen9, render power gating can leave | |
1976 | * slice/subslice/EU in a partially enabled state. We | |
1977 | * must make an explicit request through RPCS for full | |
1978 | * enablement. | |
1979 | */ | |
1980 | if (INTEL_INFO(dev)->has_slice_pg) { | |
1981 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
1982 | rpcs |= INTEL_INFO(dev)->slice_total << | |
1983 | GEN8_RPCS_S_CNT_SHIFT; | |
1984 | rpcs |= GEN8_RPCS_ENABLE; | |
1985 | } | |
1986 | ||
1987 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
1988 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
1989 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
1990 | GEN8_RPCS_SS_CNT_SHIFT; | |
1991 | rpcs |= GEN8_RPCS_ENABLE; | |
1992 | } | |
1993 | ||
1994 | if (INTEL_INFO(dev)->has_eu_pg) { | |
1995 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1996 | GEN8_RPCS_EU_MIN_SHIFT; | |
1997 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
1998 | GEN8_RPCS_EU_MAX_SHIFT; | |
1999 | rpcs |= GEN8_RPCS_ENABLE; | |
2000 | } | |
2001 | ||
2002 | return rpcs; | |
2003 | } | |
2004 | ||
8670d6f9 OM |
2005 | static int |
2006 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
2007 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
2008 | { | |
2d965536 TD |
2009 | struct drm_device *dev = ring->dev; |
2010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 2011 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2012 | struct page *page; |
2013 | uint32_t *reg_state; | |
2014 | int ret; | |
2015 | ||
2d965536 TD |
2016 | if (!ppgtt) |
2017 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2018 | ||
8670d6f9 OM |
2019 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2020 | if (ret) { | |
2021 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2022 | return ret; | |
2023 | } | |
2024 | ||
2025 | ret = i915_gem_object_get_pages(ctx_obj); | |
2026 | if (ret) { | |
2027 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2028 | return ret; | |
2029 | } | |
2030 | ||
2031 | i915_gem_object_pin_pages(ctx_obj); | |
2032 | ||
2033 | /* The second page of the context object contains some fields which must | |
2034 | * be set up prior to the first execution. */ | |
2035 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2036 | reg_state = kmap_atomic(page); | |
2037 | ||
2038 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2039 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2040 | * only for the first context restore: on a subsequent save, the GPU will | |
2041 | * recreate this batchbuffer with new values (including all the missing | |
2042 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
2043 | if (ring->id == RCS) | |
2044 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
2045 | else | |
2046 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
2047 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
2048 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
2049 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 | 2050 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
6922528a AJ |
2051 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
2052 | CTX_CTRL_RS_CTX_ENABLE); | |
8670d6f9 OM |
2053 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
2054 | reg_state[CTX_RING_HEAD+1] = 0; | |
2055 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
2056 | reg_state[CTX_RING_TAIL+1] = 0; | |
2057 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
2058 | /* Ring buffer start address is not known until the buffer is pinned. |
2059 | * It is written to the context image in execlists_update_context() | |
2060 | */ | |
8670d6f9 OM |
2061 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
2062 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
2063 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
2064 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
2065 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
2066 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
2067 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
2068 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
2069 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
2070 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
2071 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
2072 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
2073 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
2074 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
2075 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
2076 | if (ring->id == RCS) { | |
8670d6f9 OM |
2077 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
2078 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
2079 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
2080 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
2081 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
2082 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
2083 | if (ring->wa_ctx.obj) { |
2084 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2085 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2086 | ||
2087 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2088 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2089 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2090 | ||
2091 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2092 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2093 | ||
2094 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2095 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2096 | 0x01; | |
2097 | } | |
8670d6f9 OM |
2098 | } |
2099 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2100 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2101 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2102 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2103 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2104 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2105 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2106 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2107 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2108 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2109 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2110 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d MT |
2111 | |
2112 | /* With dynamic page allocation, PDPs may not be allocated at this point, | |
2113 | * Point the unallocated PDPs to the scratch page | |
e5815a2e MT |
2114 | */ |
2115 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2116 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2117 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2118 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
8670d6f9 OM |
2119 | if (ring->id == RCS) { |
2120 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2121 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2122 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2123 | } |
2124 | ||
2125 | kunmap_atomic(reg_state); | |
2126 | ||
2127 | ctx_obj->dirty = 1; | |
2128 | set_page_dirty(page); | |
2129 | i915_gem_object_unpin_pages(ctx_obj); | |
2130 | ||
2131 | return 0; | |
2132 | } | |
2133 | ||
73e4d07f OM |
2134 | /** |
2135 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2136 | * @ctx: the LR context to free. | |
2137 | * | |
2138 | * The real context freeing is done in i915_gem_context_free: this only | |
2139 | * takes care of the bits that are LRC related: the per-engine backing | |
2140 | * objects and the logical ringbuffer. | |
2141 | */ | |
ede7d42b OM |
2142 | void intel_lr_context_free(struct intel_context *ctx) |
2143 | { | |
8c857917 OM |
2144 | int i; |
2145 | ||
2146 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2147 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2148 | |
8c857917 | 2149 | if (ctx_obj) { |
dcb4c12a OM |
2150 | struct intel_ringbuffer *ringbuf = |
2151 | ctx->engine[i].ringbuf; | |
2152 | struct intel_engine_cs *ring = ringbuf->ring; | |
2153 | ||
7ba717cf TD |
2154 | if (ctx == ring->default_context) { |
2155 | intel_unpin_ringbuffer_obj(ringbuf); | |
2156 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2157 | } | |
a7cbedec | 2158 | WARN_ON(ctx->engine[ring->id].pin_count); |
84c2377f OM |
2159 | intel_destroy_ringbuffer_obj(ringbuf); |
2160 | kfree(ringbuf); | |
8c857917 OM |
2161 | drm_gem_object_unreference(&ctx_obj->base); |
2162 | } | |
2163 | } | |
2164 | } | |
2165 | ||
2166 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2167 | { | |
2168 | int ret = 0; | |
2169 | ||
468c6816 | 2170 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2171 | |
2172 | switch (ring->id) { | |
2173 | case RCS: | |
468c6816 MN |
2174 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2175 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2176 | else | |
2177 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2178 | break; |
2179 | case VCS: | |
2180 | case BCS: | |
2181 | case VECS: | |
2182 | case VCS2: | |
2183 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2184 | break; | |
2185 | } | |
2186 | ||
2187 | return ret; | |
ede7d42b OM |
2188 | } |
2189 | ||
70b0ea86 | 2190 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2191 | struct drm_i915_gem_object *default_ctx_obj) |
2192 | { | |
2193 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
2194 | ||
2195 | /* The status page is offset 0 from the default context object | |
2196 | * in LRC mode. */ | |
2197 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); | |
2198 | ring->status_page.page_addr = | |
2199 | kmap(sg_page(default_ctx_obj->pages->sgl)); | |
1df06b75 TD |
2200 | ring->status_page.obj = default_ctx_obj; |
2201 | ||
2202 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2203 | (u32)ring->status_page.gfx_addr); | |
2204 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2205 | } |
2206 | ||
73e4d07f OM |
2207 | /** |
2208 | * intel_lr_context_deferred_create() - create the LRC specific bits of a context | |
2209 | * @ctx: LR context to create. | |
2210 | * @ring: engine to be used with the context. | |
2211 | * | |
2212 | * This function can be called more than once, with different engines, if we plan | |
2213 | * to use the context with them. The context backing objects and the ringbuffers | |
2214 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2215 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2216 | * a given ring with the context. | |
2217 | * | |
32197aab | 2218 | * Return: non-zero on error. |
73e4d07f | 2219 | */ |
ede7d42b OM |
2220 | int intel_lr_context_deferred_create(struct intel_context *ctx, |
2221 | struct intel_engine_cs *ring) | |
2222 | { | |
dcb4c12a | 2223 | const bool is_global_default_ctx = (ctx == ring->default_context); |
8c857917 OM |
2224 | struct drm_device *dev = ring->dev; |
2225 | struct drm_i915_gem_object *ctx_obj; | |
2226 | uint32_t context_size; | |
84c2377f | 2227 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2228 | int ret; |
2229 | ||
ede7d42b | 2230 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2231 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2232 | |
8c857917 OM |
2233 | context_size = round_up(get_lr_context_size(ring), 4096); |
2234 | ||
149c86e7 | 2235 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2236 | if (!ctx_obj) { |
2237 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2238 | return -ENOMEM; | |
8c857917 OM |
2239 | } |
2240 | ||
dcb4c12a OM |
2241 | if (is_global_default_ctx) { |
2242 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); | |
2243 | if (ret) { | |
2244 | DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", | |
2245 | ret); | |
2246 | drm_gem_object_unreference(&ctx_obj->base); | |
2247 | return ret; | |
2248 | } | |
8c857917 OM |
2249 | } |
2250 | ||
84c2377f OM |
2251 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); |
2252 | if (!ringbuf) { | |
2253 | DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", | |
2254 | ring->name); | |
84c2377f | 2255 | ret = -ENOMEM; |
7ba717cf | 2256 | goto error_unpin_ctx; |
84c2377f OM |
2257 | } |
2258 | ||
0c7dd53b | 2259 | ringbuf->ring = ring; |
582d67f0 | 2260 | |
84c2377f OM |
2261 | ringbuf->size = 32 * PAGE_SIZE; |
2262 | ringbuf->effective_size = ringbuf->size; | |
2263 | ringbuf->head = 0; | |
2264 | ringbuf->tail = 0; | |
84c2377f | 2265 | ringbuf->last_retired_head = -1; |
ebd0fd4b | 2266 | intel_ring_update_space(ringbuf); |
84c2377f | 2267 | |
7ba717cf TD |
2268 | if (ringbuf->obj == NULL) { |
2269 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); | |
2270 | if (ret) { | |
2271 | DRM_DEBUG_DRIVER( | |
2272 | "Failed to allocate ringbuffer obj %s: %d\n", | |
84c2377f | 2273 | ring->name, ret); |
7ba717cf TD |
2274 | goto error_free_rbuf; |
2275 | } | |
2276 | ||
2277 | if (is_global_default_ctx) { | |
2278 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
2279 | if (ret) { | |
2280 | DRM_ERROR( | |
2281 | "Failed to pin and map ringbuffer %s: %d\n", | |
2282 | ring->name, ret); | |
2283 | goto error_destroy_rbuf; | |
2284 | } | |
2285 | } | |
2286 | ||
8670d6f9 OM |
2287 | } |
2288 | ||
2289 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2290 | if (ret) { | |
2291 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
8670d6f9 | 2292 | goto error; |
84c2377f OM |
2293 | } |
2294 | ||
2295 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2296 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2297 | |
70b0ea86 DV |
2298 | if (ctx == ring->default_context) |
2299 | lrc_setup_hardware_status_page(ring, ctx_obj); | |
e7778be1 | 2300 | else if (ring->id == RCS && !ctx->rcs_initialized) { |
771b9a53 | 2301 | if (ring->init_context) { |
76c39168 JH |
2302 | struct drm_i915_gem_request *req; |
2303 | ||
2304 | ret = i915_gem_request_alloc(ring, ctx, &req); | |
2305 | if (ret) | |
2306 | return ret; | |
2307 | ||
8753181e | 2308 | ret = ring->init_context(req); |
e7778be1 | 2309 | if (ret) { |
771b9a53 | 2310 | DRM_ERROR("ring init context: %d\n", ret); |
76c39168 | 2311 | i915_gem_request_cancel(req); |
e7778be1 TD |
2312 | ctx->engine[ring->id].ringbuf = NULL; |
2313 | ctx->engine[ring->id].state = NULL; | |
2314 | goto error; | |
2315 | } | |
76c39168 | 2316 | |
75289874 | 2317 | i915_add_request_no_flush(req); |
771b9a53 MT |
2318 | } |
2319 | ||
564ddb2f OM |
2320 | ctx->rcs_initialized = true; |
2321 | } | |
2322 | ||
ede7d42b | 2323 | return 0; |
8670d6f9 OM |
2324 | |
2325 | error: | |
7ba717cf TD |
2326 | if (is_global_default_ctx) |
2327 | intel_unpin_ringbuffer_obj(ringbuf); | |
2328 | error_destroy_rbuf: | |
2329 | intel_destroy_ringbuffer_obj(ringbuf); | |
2330 | error_free_rbuf: | |
8670d6f9 | 2331 | kfree(ringbuf); |
7ba717cf | 2332 | error_unpin_ctx: |
dcb4c12a OM |
2333 | if (is_global_default_ctx) |
2334 | i915_gem_object_ggtt_unpin(ctx_obj); | |
8670d6f9 OM |
2335 | drm_gem_object_unreference(&ctx_obj->base); |
2336 | return ret; | |
ede7d42b | 2337 | } |
3e5b6f05 TD |
2338 | |
2339 | void intel_lr_context_reset(struct drm_device *dev, | |
2340 | struct intel_context *ctx) | |
2341 | { | |
2342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2343 | struct intel_engine_cs *ring; | |
2344 | int i; | |
2345 | ||
2346 | for_each_ring(ring, dev_priv, i) { | |
2347 | struct drm_i915_gem_object *ctx_obj = | |
2348 | ctx->engine[ring->id].state; | |
2349 | struct intel_ringbuffer *ringbuf = | |
2350 | ctx->engine[ring->id].ringbuf; | |
2351 | uint32_t *reg_state; | |
2352 | struct page *page; | |
2353 | ||
2354 | if (!ctx_obj) | |
2355 | continue; | |
2356 | ||
2357 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2358 | WARN(1, "Failed get_pages for context obj\n"); | |
2359 | continue; | |
2360 | } | |
2361 | page = i915_gem_object_get_page(ctx_obj, 1); | |
2362 | reg_state = kmap_atomic(page); | |
2363 | ||
2364 | reg_state[CTX_RING_HEAD+1] = 0; | |
2365 | reg_state[CTX_RING_TAIL+1] = 0; | |
2366 | ||
2367 | kunmap_atomic(reg_state); | |
2368 | ||
2369 | ringbuf->head = 0; | |
2370 | ringbuf->tail = 0; | |
2371 | } | |
2372 | } |