[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lrc.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_

#include "intel_ringbuffer.h"

#define GEN8_LR_CONTEXT_ALIGN 4096

/* Execlists regs */
#define RING_ELSP(ring)				_MMIO((ring)->mmio_base + 0x230)
#define RING_EXECLIST_STATUS_LO(ring)		_MMIO((ring)->mmio_base + 0x234)
#define RING_EXECLIST_STATUS_HI(ring)		_MMIO((ring)->mmio_base + 0x234 + 4)
#define RING_CONTEXT_CONTROL(ring)		_MMIO((ring)->mmio_base + 0x244)
#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)
#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
#define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
#define RING_CONTEXT_STATUS_BUF_BASE(ring)	_MMIO((ring)->mmio_base + 0x370)
#define RING_CONTEXT_STATUS_BUF_LO(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8)
#define RING_CONTEXT_STATUS_BUF_HI(ring, i)	_MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
#define RING_CONTEXT_STATUS_PTR(ring)		_MMIO((ring)->mmio_base + 0x3a0)

/* The docs specify that the write pointer wraps around after 5h, "After status
 * is written out to the last available status QW at offset 5h, this pointer
 * wraps to 0."
 *
 * Therefore, one must infer than even though there are 3 bits available, 6 and
 * 7 appear to be * reserved.
 */
#define GEN8_CSB_ENTRIES 6
#define GEN8_CSB_PTR_MASK 0x7
#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
#define GEN8_CSB_WRITE_PTR(csb_status) \
	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
#define GEN8_CSB_READ_PTR(csb_status) \
	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)

/* Logical Rings */
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
void intel_logical_ring_stop(struct intel_engine_cs *engine);
void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
int intel_logical_rings_init(struct drm_device *dev);

int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
/**
 * intel_logical_ring_advance() - advance the ringbuffer tail
 * @ringbuf: Ringbuffer to advance.
 *
 * The tail is only updated in our logical ringbuffer struct.
 */
static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
{
	ringbuf->tail &= ringbuf->size - 1;
}
/**
 * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
 * @ringbuf: Ringbuffer to write to.
 * @data: DWORD to write.
 */
static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
					   u32 data)
{
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
					       i915_reg_t reg)
{
	intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
}

/* Logical Ring Contexts */

/* One extra page is added before LRC for GuC as shared data */
#define LRC_GUCSHR_PN	(0)
#define LRC_PPHWSP_PN	(LRC_GUCSHR_PN + 1)
#define LRC_STATE_PN	(LRC_PPHWSP_PN + 1)

struct i915_gem_context;

uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
void intel_lr_context_unpin(struct i915_gem_context *ctx,
			    struct intel_engine_cs *engine);

struct drm_i915_private;

void intel_lr_context_reset(struct drm_i915_private *dev_priv,
			    struct i915_gem_context *ctx);
uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
				     struct intel_engine_cs *engine);

/* Execlists */
int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
				    int enable_execlists);
struct i915_execbuffer_params;
int intel_execlists_submission(struct i915_execbuffer_params *params,
			       struct drm_i915_gem_execbuffer2 *args,
			       struct list_head *vmas);

void intel_execlists_cancel_requests(struct intel_engine_cs *engine);

#endif /* _INTEL_LRC_H_ */
Commit	Line	Data
b20385f1 OM	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#ifndef _INTEL_LRC_H_
	25	#define _INTEL_LRC_H_
	26
e73bdd20 CW	27	#include "intel_ringbuffer.h"
e73bdd20 CW	28
dcb4c12a OM	29	#define GEN8_LR_CONTEXT_ALIGN 4096
dcb4c12a OM	30
4ba70e44	31	/* Execlists regs */
f0f59a00 VS	32	#define RING_ELSP(ring) _MMIO((ring)->mmio_base + 0x230)
	33	#define RING_EXECLIST_STATUS_LO(ring) _MMIO((ring)->mmio_base + 0x234)
	34	#define RING_EXECLIST_STATUS_HI(ring) _MMIO((ring)->mmio_base + 0x234 + 4)
	35	#define RING_CONTEXT_CONTROL(ring) _MMIO((ring)->mmio_base + 0x244)
5baa22c5 ZW	36	#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
5baa22c5 ZW	37	#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
6922528a	38	#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
3756685a	39	#define RING_CONTEXT_STATUS_BUF_BASE(ring) _MMIO((ring)->mmio_base + 0x370)
f0f59a00 VS	40	#define RING_CONTEXT_STATUS_BUF_LO(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8)
	41	#define RING_CONTEXT_STATUS_BUF_HI(ring, i) _MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
	42	#define RING_CONTEXT_STATUS_PTR(ring) _MMIO((ring)->mmio_base + 0x3a0)
4ba70e44	43
5590a5f0 BW	44	/* The docs specify that the write pointer wraps around after 5h, "After status
	45	* is written out to the last available status QW at offset 5h, this pointer
	46	* wraps to 0."
	47	*
	48	* Therefore, one must infer than even though there are 3 bits available, 6 and
	49	* 7 appear to be * reserved.
	50	*/
	51	#define GEN8_CSB_ENTRIES 6
	52	#define GEN8_CSB_PTR_MASK 0x7
	53	#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
	54	#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
	55	#define GEN8_CSB_WRITE_PTR(csb_status) \
	56	(((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
	57	#define GEN8_CSB_READ_PTR(csb_status) \
	58	(((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
	59
454afebd	60	/* Logical Rings */
40e895ce	61	int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
ccd98fe4	62	int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
0bc40be8 TU	63	void intel_logical_ring_stop(struct intel_engine_cs *engine);
0bc40be8 TU	64	void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
454afebd OM	65	int intel_logical_rings_init(struct drm_device *dev);
454afebd OM	66
4866d729	67	int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
73e4d07f OM	68	/**
	69	* intel_logical_ring_advance() - advance the ringbuffer tail
	70	* @ringbuf: Ringbuffer to advance.
	71	*
	72	* The tail is only updated in our logical ringbuffer struct.
	73	*/
82e104cc OM	74	static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
	75	{
	76	ringbuf->tail &= ringbuf->size - 1;
	77	}
73e4d07f OM	78	/**
	79	* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
	80	* @ringbuf: Ringbuffer to write to.
	81	* @data: DWORD to write.
	82	*/
82e104cc OM	83	static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
	84	u32 data)
	85	{
	86	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	87	ringbuf->tail += 4;
	88	}
f92a9162	89	static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
f0f59a00	90	i915_reg_t reg)
f92a9162	91	{
f0f59a00	92	intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
f92a9162	93	}
82e104cc	94
ede7d42b	95	/* Logical Ring Contexts */
d1675198 AD	96
	97	/* One extra page is added before LRC for GuC as shared data */
	98	#define LRC_GUCSHR_PN (0)
	99	#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
	100	#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
	101
e2efd130 CW	102	struct i915_gem_context;
e2efd130 CW	103
0bc40be8	104	uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
e2efd130	105	void intel_lr_context_unpin(struct i915_gem_context *ctx,
e5292823	106	struct intel_engine_cs *engine);
7d774cac TU	107
	108	struct drm_i915_private;
	109
	110	void intel_lr_context_reset(struct drm_i915_private *dev_priv,
e2efd130 CW	111	struct i915_gem_context *ctx);
e2efd130 CW	112	uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
0bc40be8	113	struct intel_engine_cs *engine);
ede7d42b	114
127f1003	115	/* Execlists */
c033666a CW	116	int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
c033666a CW	117	int enable_execlists);
5f19e2bf JH	118	struct i915_execbuffer_params;
5f19e2bf JH	119	int intel_execlists_submission(struct i915_execbuffer_params *params,
454afebd	120	struct drm_i915_gem_execbuffer2 *args,
5f19e2bf	121	struct list_head *vmas);
127f1003	122
e39d42fa	123	void intel_execlists_cancel_requests(struct intel_engine_cs *engine);
e981e7b1	124
b20385f1	125	#endif /* _INTEL_LRC_H_ */