[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lrc.h

/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_

/* Execlists regs */
#define RING_ELSP(ring)			((ring)->mmio_base+0x230)
#define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)
#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)
#define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)
#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)

/* Logical Rings */
void intel_logical_ring_stop(struct intel_engine_cs *ring);
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
int intel_logical_rings_init(struct drm_device *dev);

int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf);
void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf);
/**
 * intel_logical_ring_advance() - advance the ringbuffer tail
 * @ringbuf: Ringbuffer to advance.
 *
 * The tail is only updated in our logical ringbuffer struct.
 */
static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
{
	ringbuf->tail &= ringbuf->size - 1;
}
/**
 * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
 * @ringbuf: Ringbuffer to write to.
 * @data: DWORD to write.
 */
static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
					   u32 data)
{
	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	ringbuf->tail += 4;
}
int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords);

/* Logical Ring Contexts */
int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
				       struct intel_context *ctx);
void intel_lr_context_free(struct intel_context *ctx);
int intel_lr_context_deferred_create(struct intel_context *ctx,
				     struct intel_engine_cs *ring);

/* Execlists */
int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
			       struct intel_engine_cs *ring,
			       struct intel_context *ctx,
			       struct drm_i915_gem_execbuffer2 *args,
			       struct list_head *vmas,
			       struct drm_i915_gem_object *batch_obj,
			       u64 exec_start, u32 flags);
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);

/**
 * struct intel_ctx_submit_request - queued context submission request
 * @ctx: Context to submit to the ELSP.
 * @ring: Engine to submit it to.
 * @tail: how far in the context's ringbuffer this request goes to.
 * @execlist_link: link in the submission queue.
 * @work: workqueue for processing this request in a bottom half.
 * @elsp_submitted: no. of times this request has been sent to the ELSP.
 *
 * The ELSP only accepts two elements at a time, so we queue context/tail
 * pairs on a given queue (ring->execlist_queue) until the hardware is
 * available. The queue serves a double purpose: we also use it to keep track
 * of the up to 2 contexts currently in the hardware (usually one in execution
 * and the other queued up by the GPU): We only remove elements from the head
 * of the queue when the hardware informs us that an element has been
 * completed.
 *
 * All accesses to the queue are mediated by a spinlock (ring->execlist_lock).
 */
struct intel_ctx_submit_request {
	struct intel_context *ctx;
	struct intel_engine_cs *ring;
	u32 tail;

	struct list_head execlist_link;

	int elsp_submitted;
};

void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring);
void intel_execlists_retire_requests(struct intel_engine_cs *ring);

#endif /* _INTEL_LRC_H_ */
Commit	Line	Data
b20385f1 OM	1	/*
	2	* Copyright © 2014 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#ifndef _INTEL_LRC_H_
	25	#define _INTEL_LRC_H_
	26
4ba70e44 OM	27	/* Execlists regs */
	28	#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
	29	#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
	30	#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
	31	#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
	32	#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
	33
454afebd OM	34	/* Logical Rings */
	35	void intel_logical_ring_stop(struct intel_engine_cs *ring);
	36	void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
	37	int intel_logical_rings_init(struct drm_device *dev);
	38
48e29f55	39	int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf);
82e104cc	40	void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf);
73e4d07f OM	41	/**
	42	* intel_logical_ring_advance() - advance the ringbuffer tail
	43	* @ringbuf: Ringbuffer to advance.
	44	*
	45	* The tail is only updated in our logical ringbuffer struct.
	46	*/
82e104cc OM	47	static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
	48	{
	49	ringbuf->tail &= ringbuf->size - 1;
	50	}
73e4d07f OM	51	/**
	52	* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
	53	* @ringbuf: Ringbuffer to write to.
	54	* @data: DWORD to write.
	55	*/
82e104cc OM	56	static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
	57	u32 data)
	58	{
	59	iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
	60	ringbuf->tail += 4;
	61	}
	62	int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords);
	63
ede7d42b	64	/* Logical Ring Contexts */
564ddb2f OM	65	int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
564ddb2f OM	66	struct intel_context *ctx);
ede7d42b OM	67	void intel_lr_context_free(struct intel_context *ctx);
	68	int intel_lr_context_deferred_create(struct intel_context *ctx,
	69	struct intel_engine_cs *ring);
	70
127f1003 OM	71	/* Execlists */
127f1003 OM	72	int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
454afebd OM	73	int intel_execlists_submission(struct drm_device dev, struct drm_file file,
	74	struct intel_engine_cs *ring,
	75	struct intel_context *ctx,
	76	struct drm_i915_gem_execbuffer2 *args,
	77	struct list_head *vmas,
	78	struct drm_i915_gem_object *batch_obj,
	79	u64 exec_start, u32 flags);
84b790f8	80	u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
127f1003	81
73e4d07f OM	82	/**
	83	* struct intel_ctx_submit_request - queued context submission request
	84	* @ctx: Context to submit to the ELSP.
	85	* @ring: Engine to submit it to.
	86	* @tail: how far in the context's ringbuffer this request goes to.
	87	* @execlist_link: link in the submission queue.
	88	* @work: workqueue for processing this request in a bottom half.
	89	* @elsp_submitted: no. of times this request has been sent to the ELSP.
	90	*
	91	* The ELSP only accepts two elements at a time, so we queue context/tail
	92	* pairs on a given queue (ring->execlist_queue) until the hardware is
	93	* available. The queue serves a double purpose: we also use it to keep track
	94	* of the up to 2 contexts currently in the hardware (usually one in execution
	95	* and the other queued up by the GPU): We only remove elements from the head
	96	* of the queue when the hardware informs us that an element has been
	97	* completed.
	98	*
	99	* All accesses to the queue are mediated by a spinlock (ring->execlist_lock).
	100	*/
acdd884a MT	101	struct intel_ctx_submit_request {
	102	struct intel_context *ctx;
	103	struct intel_engine_cs *ring;
	104	u32 tail;
	105
	106	struct list_head execlist_link;
e1fee72c OM	107
e1fee72c OM	108	int elsp_submitted;
acdd884a MT	109	};
acdd884a MT	110
e981e7b1	111	void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring);
c86ee3a9	112	void intel_execlists_retire_requests(struct intel_engine_cs *ring);
e981e7b1	113
b20385f1	114	#endif /* _INTEL_LRC_H_ */