Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
3fbe18d6 ZY |
52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | |
13c7d870 | 54 | bool is_dual_link; |
7dec0606 | 55 | u32 reg; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
76 | u32 tmp; | |
b1dc332c | 77 | |
7dec0606 | 78 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
79 | |
80 | if (!(tmp & LVDS_PORT_EN)) | |
81 | return false; | |
82 | ||
83 | if (HAS_PCH_CPT(dev)) | |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
85 | else | |
86 | *pipe = PORT_TO_PIPE(tmp); | |
87 | ||
88 | return true; | |
89 | } | |
90 | ||
fc683091 DV |
91 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
92 | * This is an exception to the general rule that mode_set doesn't turn | |
93 | * things on. | |
94 | */ | |
95 | static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |
96 | { | |
97 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
98 | struct drm_device *dev = encoder->base.dev; | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
101 | struct drm_display_mode *fixed_mode = | |
102 | lvds_encoder->attached_connector->base.panel.fixed_mode; | |
103 | int pipe = intel_crtc->pipe; | |
104 | u32 temp; | |
105 | ||
fc683091 DV |
106 | temp = I915_READ(lvds_encoder->reg); |
107 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
108 | |
109 | if (HAS_PCH_CPT(dev)) { | |
110 | temp &= ~PORT_TRANS_SEL_MASK; | |
111 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 112 | } else { |
62810e5a DV |
113 | if (pipe == 1) { |
114 | temp |= LVDS_PIPEB_SELECT; | |
115 | } else { | |
116 | temp &= ~LVDS_PIPEB_SELECT; | |
117 | } | |
fc683091 | 118 | } |
62810e5a | 119 | |
fc683091 DV |
120 | /* set the corresponsding LVDS_BORDER bit */ |
121 | temp |= dev_priv->lvds_border_bits; | |
122 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
123 | * set the DPLLs for dual-channel mode or not. | |
124 | */ | |
125 | if (lvds_encoder->is_dual_link) | |
126 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
127 | else | |
128 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
129 | ||
130 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
131 | * appropriately here, but we need to look more thoroughly into how | |
132 | * panels behave in the two modes. | |
133 | */ | |
62810e5a DV |
134 | |
135 | /* Set the dithering flag on LVDS as needed, note that there is no | |
136 | * special lvds dither control bit on pch-split platforms, dithering is | |
137 | * only controlled through the PIPECONF reg. */ | |
138 | if (INTEL_INFO(dev)->gen == 4) { | |
fc683091 DV |
139 | if (dev_priv->lvds_dither) |
140 | temp |= LVDS_ENABLE_DITHER; | |
141 | else | |
142 | temp &= ~LVDS_ENABLE_DITHER; | |
143 | } | |
144 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
145 | if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
146 | temp |= LVDS_HSYNC_POLARITY; | |
147 | if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
148 | temp |= LVDS_VSYNC_POLARITY; | |
149 | ||
150 | I915_WRITE(lvds_encoder->reg, temp); | |
151 | } | |
152 | ||
9d6d9f19 MK |
153 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
154 | { | |
155 | struct drm_device *dev = encoder->base.dev; | |
156 | struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | ||
159 | if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) | |
160 | return; | |
161 | ||
e29a18fa DV |
162 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
163 | assert_pipe_disabled(dev_priv, to_intel_crtc(encoder->base.crtc)->pipe); | |
164 | ||
9d6d9f19 MK |
165 | /* |
166 | * Enable automatic panel scaling so that non-native modes | |
167 | * fill the screen. The panel fitter should only be | |
168 | * adjusted whilst the pipe is disabled, according to | |
169 | * register description and PRM. | |
170 | */ | |
171 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
172 | enc->pfit_control, | |
173 | enc->pfit_pgm_ratios); | |
174 | ||
175 | I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); | |
176 | I915_WRITE(PFIT_CONTROL, enc->pfit_control); | |
177 | } | |
178 | ||
79e53945 JB |
179 | /** |
180 | * Sets the power state for the panel. | |
181 | */ | |
c22834ec | 182 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 183 | { |
c22834ec | 184 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 185 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 186 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 187 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 188 | u32 ctl_reg, stat_reg; |
541998a1 | 189 | |
c619eed4 | 190 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 191 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 192 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
193 | } else { |
194 | ctl_reg = PP_CONTROL; | |
de842eff | 195 | stat_reg = PP_STATUS; |
541998a1 | 196 | } |
79e53945 | 197 | |
7dec0606 | 198 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 199 | |
2a1292fd | 200 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 201 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
202 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
203 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 204 | |
24ded204 | 205 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
206 | } |
207 | ||
c22834ec | 208 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 209 | { |
c22834ec | 210 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 211 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 213 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
214 | |
215 | if (HAS_PCH_SPLIT(dev)) { | |
216 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 217 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
218 | } else { |
219 | ctl_reg = PP_CONTROL; | |
de842eff | 220 | stat_reg = PP_STATUS; |
2a1292fd CW |
221 | } |
222 | ||
47356eb6 | 223 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
224 | |
225 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
226 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
227 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 228 | |
7dec0606 DV |
229 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
230 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
231 | } |
232 | ||
79e53945 JB |
233 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
234 | struct drm_display_mode *mode) | |
235 | { | |
dd06f90e JN |
236 | struct intel_connector *intel_connector = to_intel_connector(connector); |
237 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 238 | |
788319d4 CW |
239 | if (mode->hdisplay > fixed_mode->hdisplay) |
240 | return MODE_PANEL; | |
241 | if (mode->vdisplay > fixed_mode->vdisplay) | |
242 | return MODE_PANEL; | |
79e53945 JB |
243 | |
244 | return MODE_OK; | |
245 | } | |
246 | ||
49be663f CW |
247 | static void |
248 | centre_horizontally(struct drm_display_mode *mode, | |
249 | int width) | |
250 | { | |
251 | u32 border, sync_pos, blank_width, sync_width; | |
252 | ||
253 | /* keep the hsync and hblank widths constant */ | |
254 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
255 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
256 | sync_pos = (blank_width - sync_width + 1) / 2; | |
257 | ||
258 | border = (mode->hdisplay - width + 1) / 2; | |
259 | border += border & 1; /* make the border even */ | |
260 | ||
261 | mode->crtc_hdisplay = width; | |
262 | mode->crtc_hblank_start = width + border; | |
263 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
264 | ||
265 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
266 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
267 | } | |
268 | ||
269 | static void | |
270 | centre_vertically(struct drm_display_mode *mode, | |
271 | int height) | |
272 | { | |
273 | u32 border, sync_pos, blank_width, sync_width; | |
274 | ||
275 | /* keep the vsync and vblank widths constant */ | |
276 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
277 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
278 | sync_pos = (blank_width - sync_width + 1) / 2; | |
279 | ||
280 | border = (mode->vdisplay - height + 1) / 2; | |
281 | ||
282 | mode->crtc_vdisplay = height; | |
283 | mode->crtc_vblank_start = height + border; | |
284 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
285 | ||
286 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
287 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
288 | } | |
289 | ||
290 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
291 | { | |
292 | /* | |
293 | * Floating point operation is not supported. So the FACTOR | |
294 | * is defined, which can avoid the floating point computation | |
295 | * when calculating the panel ratio. | |
296 | */ | |
297 | #define ACCURACY 12 | |
298 | #define FACTOR (1 << ACCURACY) | |
299 | u32 ratio = source * FACTOR / target; | |
300 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
301 | } | |
302 | ||
7ae89233 DV |
303 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
304 | struct intel_crtc_config *pipe_config) | |
79e53945 | 305 | { |
7ae89233 | 306 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 307 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
308 | struct intel_lvds_encoder *lvds_encoder = |
309 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
310 | struct intel_connector *intel_connector = |
311 | &lvds_encoder->attached_connector->base; | |
7ae89233 DV |
312 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
313 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
29b99b48 | 314 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
49be663f | 315 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
4e53c2e0 | 316 | unsigned int lvds_bpp; |
9db4a9c7 | 317 | int pipe; |
79e53945 JB |
318 | |
319 | /* Should never happen!! */ | |
a6c45cf0 | 320 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 321 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
322 | return false; |
323 | } | |
324 | ||
29b99b48 | 325 | if (intel_encoder_check_is_cloned(&lvds_encoder->base)) |
e24c5c29 | 326 | return false; |
1d8e1c75 | 327 | |
4e53c2e0 DV |
328 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
329 | LVDS_A3_POWER_UP) | |
330 | lvds_bpp = 8*3; | |
331 | else | |
332 | lvds_bpp = 6*3; | |
333 | ||
334 | if (lvds_bpp != pipe_config->pipe_bpp) { | |
335 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", | |
336 | pipe_config->pipe_bpp, lvds_bpp); | |
337 | pipe_config->pipe_bpp = lvds_bpp; | |
338 | } | |
79e53945 | 339 | /* |
71677043 | 340 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
341 | * to the adjusted mode. The CRTC will be set up for this mode, |
342 | * with the panel scaling set up to source from the H/VDisplay | |
343 | * of the original mode. | |
344 | */ | |
4d891523 | 345 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 346 | adjusted_mode); |
1d8e1c75 CW |
347 | |
348 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
349 | pipe_config->has_pch_encoder = true; |
350 | ||
4d891523 JN |
351 | intel_pch_panel_fitting(dev, |
352 | intel_connector->panel.fitting_mode, | |
1d8e1c75 CW |
353 | mode, adjusted_mode); |
354 | return true; | |
355 | } | |
79e53945 | 356 | |
3fbe18d6 ZY |
357 | /* Native modes don't need fitting */ |
358 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 359 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 360 | goto out; |
3fbe18d6 ZY |
361 | |
362 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 363 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
364 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
365 | PFIT_FILTER_FUZZY); | |
366 | ||
3fbe18d6 ZY |
367 | /* |
368 | * Enable automatic panel scaling for non-native modes so that they fill | |
369 | * the screen. Should be enabled before the pipe is enabled, according | |
370 | * to register description and PRM. | |
371 | * Change the value here to see the borders for debugging | |
372 | */ | |
9db4a9c7 JB |
373 | for_each_pipe(pipe) |
374 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 375 | |
f9bef081 | 376 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
7ae89233 | 377 | pipe_config->timings_set = true; |
f9bef081 | 378 | |
4d891523 | 379 | switch (intel_connector->panel.fitting_mode) { |
53bd8389 | 380 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
381 | /* |
382 | * For centered modes, we have to calculate border widths & | |
383 | * heights and modify the values programmed into the CRTC. | |
384 | */ | |
49be663f CW |
385 | centre_horizontally(adjusted_mode, mode->hdisplay); |
386 | centre_vertically(adjusted_mode, mode->vdisplay); | |
387 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 388 | break; |
49be663f | 389 | |
3fbe18d6 | 390 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 391 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 392 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
393 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
394 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
395 | ||
3fbe18d6 | 396 | /* 965+ is easy, it does everything in hw */ |
49be663f | 397 | if (scaled_width > scaled_height) |
257e48f1 | 398 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 399 | else if (scaled_width < scaled_height) |
257e48f1 CW |
400 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
401 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
402 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 403 | } else { |
49be663f CW |
404 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
405 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
406 | /* |
407 | * For earlier chips we have to calculate the scaling | |
408 | * ratio by hand and program it into the | |
409 | * PFIT_PGM_RATIO register | |
410 | */ | |
49be663f CW |
411 | if (scaled_width > scaled_height) { /* pillar */ |
412 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
413 | ||
414 | border = LVDS_BORDER_ENABLE; | |
415 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
416 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
417 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
418 | bits << PFIT_VERT_SCALE_SHIFT); | |
419 | pfit_control |= (PFIT_ENABLE | | |
420 | VERT_INTERP_BILINEAR | | |
421 | HORIZ_INTERP_BILINEAR); | |
422 | } | |
423 | } else if (scaled_width < scaled_height) { /* letter */ | |
424 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
425 | ||
426 | border = LVDS_BORDER_ENABLE; | |
427 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
428 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
429 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
430 | bits << PFIT_VERT_SCALE_SHIFT); | |
431 | pfit_control |= (PFIT_ENABLE | | |
432 | VERT_INTERP_BILINEAR | | |
433 | HORIZ_INTERP_BILINEAR); | |
434 | } | |
435 | } else | |
436 | /* Aspects match, Let hw scale both directions */ | |
437 | pfit_control |= (PFIT_ENABLE | | |
438 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
439 | VERT_INTERP_BILINEAR | |
440 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
441 | } |
442 | break; | |
443 | ||
444 | case DRM_MODE_SCALE_FULLSCREEN: | |
445 | /* | |
446 | * Full scaling, even if it changes the aspect ratio. | |
447 | * Fortunately this is all done for us in hw. | |
448 | */ | |
257e48f1 CW |
449 | if (mode->vdisplay != adjusted_mode->vdisplay || |
450 | mode->hdisplay != adjusted_mode->hdisplay) { | |
451 | pfit_control |= PFIT_ENABLE; | |
452 | if (INTEL_INFO(dev)->gen >= 4) | |
453 | pfit_control |= PFIT_SCALING_AUTO; | |
454 | else | |
455 | pfit_control |= (VERT_AUTO_SCALE | | |
456 | VERT_INTERP_BILINEAR | | |
457 | HORIZ_AUTO_SCALE | | |
458 | HORIZ_INTERP_BILINEAR); | |
459 | } | |
3fbe18d6 | 460 | break; |
49be663f | 461 | |
3fbe18d6 ZY |
462 | default: |
463 | break; | |
464 | } | |
465 | ||
466 | out: | |
72389a33 | 467 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
468 | if ((pfit_control & PFIT_ENABLE) == 0) { |
469 | pfit_control = 0; | |
470 | pfit_pgm_ratios = 0; | |
471 | } | |
72389a33 CW |
472 | |
473 | /* Make sure pre-965 set dither correctly */ | |
474 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
475 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
476 | ||
29b99b48 JN |
477 | if (pfit_control != lvds_encoder->pfit_control || |
478 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | |
479 | lvds_encoder->pfit_control = pfit_control; | |
480 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | |
e9e331a8 | 481 | } |
49be663f CW |
482 | dev_priv->lvds_border_bits = border; |
483 | ||
79e53945 JB |
484 | /* |
485 | * XXX: It would be nice to support lower refresh rates on the | |
486 | * panels to reduce power consumption, and perhaps match the | |
487 | * user's requested refresh rate. | |
488 | */ | |
489 | ||
490 | return true; | |
491 | } | |
492 | ||
79e53945 JB |
493 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
494 | struct drm_display_mode *mode, | |
495 | struct drm_display_mode *adjusted_mode) | |
496 | { | |
79e53945 JB |
497 | /* |
498 | * The LVDS pin pair will already have been turned on in the | |
499 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
500 | * settings. | |
501 | */ | |
79e53945 JB |
502 | } |
503 | ||
504 | /** | |
505 | * Detect the LVDS connection. | |
506 | * | |
b42d4c5c JB |
507 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
508 | * connected and closed means disconnected. We also send hotplug events as | |
509 | * needed, using lid status notification from the input layer. | |
79e53945 | 510 | */ |
7b334fcb | 511 | static enum drm_connector_status |
930a9e28 | 512 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 513 | { |
7b9c5abe | 514 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 515 | enum drm_connector_status status; |
b42d4c5c | 516 | |
fe16d949 CW |
517 | status = intel_panel_detect(dev); |
518 | if (status != connector_status_unknown) | |
519 | return status; | |
01fe9dbd | 520 | |
6ee3b5a1 | 521 | return connector_status_connected; |
79e53945 JB |
522 | } |
523 | ||
524 | /** | |
525 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
526 | */ | |
527 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
528 | { | |
62165e0d | 529 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 530 | struct drm_device *dev = connector->dev; |
788319d4 | 531 | struct drm_display_mode *mode; |
79e53945 | 532 | |
9cd300e0 | 533 | /* use cached edid if we have one */ |
2aa4f099 | 534 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 535 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 536 | |
dd06f90e | 537 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 538 | if (mode == NULL) |
788319d4 | 539 | return 0; |
79e53945 | 540 | |
788319d4 CW |
541 | drm_mode_probed_add(connector, mode); |
542 | return 1; | |
79e53945 JB |
543 | } |
544 | ||
0544edfd TB |
545 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
546 | { | |
bc0daf48 | 547 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
548 | return 1; |
549 | } | |
550 | ||
551 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
552 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
553 | { | |
554 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
555 | .ident = "Toshiba Tecra A11", | |
556 | .matches = { | |
557 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
558 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
559 | }, | |
560 | }, | |
561 | ||
562 | { } /* terminating entry */ | |
563 | }; | |
564 | ||
c9354c85 | 565 | /* |
b8efb17b ZR |
566 | * Lid events. Note the use of 'modeset': |
567 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
568 | * and set it to MODESET_DONE on open | |
c9354c85 | 569 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
570 | * duplicate events where it was already properly set) |
571 | * - the suspend/resume paths will set it to | |
572 | * MODESET_SUSPENDED and ignore the lid open event, | |
573 | * because they restore the mode ("lid open"). | |
c9354c85 | 574 | */ |
c1c7af60 JB |
575 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
576 | void *unused) | |
577 | { | |
db1740a0 JN |
578 | struct intel_lvds_connector *lvds_connector = |
579 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
580 | struct drm_connector *connector = &lvds_connector->base.base; | |
581 | struct drm_device *dev = connector->dev; | |
582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 583 | |
2fb4e61d AW |
584 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
585 | return NOTIFY_OK; | |
586 | ||
b8efb17b ZR |
587 | mutex_lock(&dev_priv->modeset_restore_lock); |
588 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
589 | goto exit; | |
a2565377 ZY |
590 | /* |
591 | * check and update the status of LVDS connector after receiving | |
592 | * the LID nofication event. | |
593 | */ | |
db1740a0 | 594 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 595 | |
0544edfd TB |
596 | /* Don't force modeset on machines where it causes a GPU lockup */ |
597 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 598 | goto exit; |
c9354c85 | 599 | if (!acpi_lid_open()) { |
b8efb17b ZR |
600 | /* do modeset on next lid open event */ |
601 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
602 | goto exit; | |
06891e27 | 603 | } |
c1c7af60 | 604 | |
b8efb17b ZR |
605 | if (dev_priv->modeset_restore == MODESET_DONE) |
606 | goto exit; | |
c9354c85 | 607 | |
a0e99e68 | 608 | drm_modeset_lock_all(dev); |
45e2b5f6 | 609 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 610 | drm_modeset_unlock_all(dev); |
06324194 | 611 | |
b8efb17b ZR |
612 | dev_priv->modeset_restore = MODESET_DONE; |
613 | ||
614 | exit: | |
615 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
616 | return NOTIFY_OK; |
617 | } | |
618 | ||
79e53945 JB |
619 | /** |
620 | * intel_lvds_destroy - unregister and free LVDS structures | |
621 | * @connector: connector to free | |
622 | * | |
623 | * Unregister the DDC bus for this connector then free the driver private | |
624 | * structure. | |
625 | */ | |
626 | static void intel_lvds_destroy(struct drm_connector *connector) | |
627 | { | |
db1740a0 JN |
628 | struct intel_lvds_connector *lvds_connector = |
629 | to_lvds_connector(connector); | |
79e53945 | 630 | |
db1740a0 JN |
631 | if (lvds_connector->lid_notifier.notifier_call) |
632 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 633 | |
9cd300e0 JN |
634 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
635 | kfree(lvds_connector->base.edid); | |
636 | ||
1d508706 | 637 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 638 | |
79e53945 JB |
639 | drm_sysfs_connector_remove(connector); |
640 | drm_connector_cleanup(connector); | |
641 | kfree(connector); | |
642 | } | |
643 | ||
335041ed JB |
644 | static int intel_lvds_set_property(struct drm_connector *connector, |
645 | struct drm_property *property, | |
646 | uint64_t value) | |
647 | { | |
4d891523 | 648 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 649 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 650 | |
788319d4 | 651 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 652 | struct drm_crtc *crtc; |
bb8a3560 | 653 | |
53bd8389 JB |
654 | if (value == DRM_MODE_SCALE_NONE) { |
655 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 656 | return -EINVAL; |
3fbe18d6 | 657 | } |
788319d4 | 658 | |
4d891523 | 659 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
660 | /* the LVDS scaling property is not changed */ |
661 | return 0; | |
662 | } | |
4d891523 | 663 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
664 | |
665 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
666 | if (crtc && crtc->enabled) { |
667 | /* | |
668 | * If the CRTC is enabled, the display will be changed | |
669 | * according to the new panel fitting mode. | |
670 | */ | |
c0c36b94 | 671 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
672 | } |
673 | } | |
674 | ||
335041ed JB |
675 | return 0; |
676 | } | |
677 | ||
79e53945 | 678 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 679 | .mode_set = intel_lvds_mode_set, |
79e53945 JB |
680 | }; |
681 | ||
682 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
683 | .get_modes = intel_lvds_get_modes, | |
684 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 685 | .best_encoder = intel_best_encoder, |
79e53945 JB |
686 | }; |
687 | ||
688 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 689 | .dpms = intel_connector_dpms, |
79e53945 JB |
690 | .detect = intel_lvds_detect, |
691 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 692 | .set_property = intel_lvds_set_property, |
79e53945 JB |
693 | .destroy = intel_lvds_destroy, |
694 | }; | |
695 | ||
79e53945 | 696 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 697 | .destroy = intel_encoder_destroy, |
79e53945 JB |
698 | }; |
699 | ||
425d244c JW |
700 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
701 | { | |
bc0daf48 | 702 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
703 | return 1; |
704 | } | |
79e53945 | 705 | |
425d244c | 706 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 707 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
708 | { |
709 | .callback = intel_no_lvds_dmi_callback, | |
710 | .ident = "Apple Mac Mini (Core series)", | |
711 | .matches = { | |
98acd46f | 712 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
713 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
714 | }, | |
715 | }, | |
716 | { | |
717 | .callback = intel_no_lvds_dmi_callback, | |
718 | .ident = "Apple Mac Mini (Core 2 series)", | |
719 | .matches = { | |
98acd46f | 720 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
721 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
722 | }, | |
723 | }, | |
724 | { | |
725 | .callback = intel_no_lvds_dmi_callback, | |
726 | .ident = "MSI IM-945GSE-A", | |
727 | .matches = { | |
728 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
729 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
730 | }, | |
731 | }, | |
732 | { | |
733 | .callback = intel_no_lvds_dmi_callback, | |
734 | .ident = "Dell Studio Hybrid", | |
735 | .matches = { | |
736 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
737 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
738 | }, | |
739 | }, | |
70aa96ca JW |
740 | { |
741 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
742 | .ident = "Dell OptiPlex FX170", |
743 | .matches = { | |
744 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
745 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
746 | }, | |
747 | }, | |
748 | { | |
749 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
750 | .ident = "AOpen Mini PC", |
751 | .matches = { | |
752 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
753 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
754 | }, | |
755 | }, | |
ed8c754b TV |
756 | { |
757 | .callback = intel_no_lvds_dmi_callback, | |
758 | .ident = "AOpen Mini PC MP915", | |
759 | .matches = { | |
760 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
761 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
762 | }, | |
763 | }, | |
22ab70d3 KP |
764 | { |
765 | .callback = intel_no_lvds_dmi_callback, | |
766 | .ident = "AOpen i915GMm-HFS", | |
767 | .matches = { | |
768 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
769 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
770 | }, | |
771 | }, | |
e57b6886 DV |
772 | { |
773 | .callback = intel_no_lvds_dmi_callback, | |
774 | .ident = "AOpen i45GMx-I", | |
775 | .matches = { | |
776 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
777 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
778 | }, | |
779 | }, | |
fa0864b2 MC |
780 | { |
781 | .callback = intel_no_lvds_dmi_callback, | |
782 | .ident = "Aopen i945GTt-VFA", | |
783 | .matches = { | |
784 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
785 | }, | |
786 | }, | |
9875557e SB |
787 | { |
788 | .callback = intel_no_lvds_dmi_callback, | |
789 | .ident = "Clientron U800", | |
790 | .matches = { | |
791 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
792 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
793 | }, | |
794 | }, | |
6a574b5b | 795 | { |
44306ab3 JS |
796 | .callback = intel_no_lvds_dmi_callback, |
797 | .ident = "Clientron E830", | |
798 | .matches = { | |
799 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
800 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
801 | }, | |
802 | }, | |
803 | { | |
6a574b5b HG |
804 | .callback = intel_no_lvds_dmi_callback, |
805 | .ident = "Asus EeeBox PC EB1007", | |
806 | .matches = { | |
807 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
808 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
809 | }, | |
810 | }, | |
0999bbe0 AJ |
811 | { |
812 | .callback = intel_no_lvds_dmi_callback, | |
813 | .ident = "Asus AT5NM10T-I", | |
814 | .matches = { | |
815 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
816 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
817 | }, | |
818 | }, | |
33471119 JBG |
819 | { |
820 | .callback = intel_no_lvds_dmi_callback, | |
821 | .ident = "Hewlett-Packard HP t5740e Thin Client", | |
822 | .matches = { | |
823 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
824 | DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"), | |
825 | }, | |
826 | }, | |
f5b8a7ed MG |
827 | { |
828 | .callback = intel_no_lvds_dmi_callback, | |
829 | .ident = "Hewlett-Packard t5745", | |
830 | .matches = { | |
831 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 832 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
833 | }, |
834 | }, | |
835 | { | |
836 | .callback = intel_no_lvds_dmi_callback, | |
837 | .ident = "Hewlett-Packard st5747", | |
838 | .matches = { | |
839 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 840 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
841 | }, |
842 | }, | |
97effadb AA |
843 | { |
844 | .callback = intel_no_lvds_dmi_callback, | |
845 | .ident = "MSI Wind Box DC500", | |
846 | .matches = { | |
847 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
848 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
849 | }, | |
850 | }, | |
a51d4ed0 CW |
851 | { |
852 | .callback = intel_no_lvds_dmi_callback, | |
853 | .ident = "Gigabyte GA-D525TUD", | |
854 | .matches = { | |
855 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
856 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
857 | }, | |
858 | }, | |
c31407a3 CW |
859 | { |
860 | .callback = intel_no_lvds_dmi_callback, | |
861 | .ident = "Supermicro X7SPA-H", | |
862 | .matches = { | |
863 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
864 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
865 | }, | |
866 | }, | |
9e9dd0e8 CL |
867 | { |
868 | .callback = intel_no_lvds_dmi_callback, | |
869 | .ident = "Fujitsu Esprimo Q900", | |
870 | .matches = { | |
871 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
872 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
873 | }, | |
874 | }, | |
425d244c JW |
875 | |
876 | { } /* terminating entry */ | |
877 | }; | |
79e53945 | 878 | |
18f9ed12 ZY |
879 | /** |
880 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
881 | * @dev: drm device | |
882 | * @connector: LVDS connector | |
883 | * | |
884 | * Find the reduced downclock for LVDS in EDID. | |
885 | */ | |
886 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
887 | struct drm_display_mode *fixed_mode, |
888 | struct drm_connector *connector) | |
18f9ed12 ZY |
889 | { |
890 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 891 | struct drm_display_mode *scan; |
18f9ed12 ZY |
892 | int temp_downclock; |
893 | ||
788319d4 | 894 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
895 | list_for_each_entry(scan, &connector->probed_modes, head) { |
896 | /* | |
897 | * If one mode has the same resolution with the fixed_panel | |
898 | * mode while they have the different refresh rate, it means | |
899 | * that the reduced downclock is found for the LVDS. In such | |
900 | * case we can set the different FPx0/1 to dynamically select | |
901 | * between low and high frequency. | |
902 | */ | |
788319d4 CW |
903 | if (scan->hdisplay == fixed_mode->hdisplay && |
904 | scan->hsync_start == fixed_mode->hsync_start && | |
905 | scan->hsync_end == fixed_mode->hsync_end && | |
906 | scan->htotal == fixed_mode->htotal && | |
907 | scan->vdisplay == fixed_mode->vdisplay && | |
908 | scan->vsync_start == fixed_mode->vsync_start && | |
909 | scan->vsync_end == fixed_mode->vsync_end && | |
910 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
911 | if (scan->clock < temp_downclock) { |
912 | /* | |
913 | * The downclock is already found. But we | |
914 | * expect to find the lower downclock. | |
915 | */ | |
916 | temp_downclock = scan->clock; | |
917 | } | |
918 | } | |
919 | } | |
788319d4 | 920 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
921 | /* We found the downclock for LVDS. */ |
922 | dev_priv->lvds_downclock_avail = 1; | |
923 | dev_priv->lvds_downclock = temp_downclock; | |
924 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
925 | "Normal clock %dKhz, downclock %dKhz\n", |
926 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 927 | } |
18f9ed12 ZY |
928 | } |
929 | ||
7cf4f69d ZY |
930 | /* |
931 | * Enumerate the child dev array parsed from VBT to check whether | |
932 | * the LVDS is present. | |
933 | * If it is present, return 1. | |
934 | * If it is not present, return false. | |
935 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 936 | */ |
270eea0f CW |
937 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
938 | u8 *i2c_pin) | |
7cf4f69d ZY |
939 | { |
940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 941 | int i; |
7cf4f69d ZY |
942 | |
943 | if (!dev_priv->child_dev_num) | |
425904dd | 944 | return true; |
7cf4f69d | 945 | |
7cf4f69d | 946 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
947 | struct child_device_config *child = dev_priv->child_dev + i; |
948 | ||
949 | /* If the device type is not LFP, continue. | |
950 | * We have to check both the new identifiers as well as the | |
951 | * old for compatibility with some BIOSes. | |
7cf4f69d | 952 | */ |
425904dd CW |
953 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
954 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
955 | continue; |
956 | ||
3bd7d909 DK |
957 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
958 | *i2c_pin = child->i2c_pin; | |
270eea0f | 959 | |
425904dd CW |
960 | /* However, we cannot trust the BIOS writers to populate |
961 | * the VBT correctly. Since LVDS requires additional | |
962 | * information from AIM blocks, a non-zero addin offset is | |
963 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 964 | */ |
425904dd CW |
965 | if (child->addin_offset) |
966 | return true; | |
967 | ||
968 | /* But even then some BIOS writers perform some black magic | |
969 | * and instantiate the device without reference to any | |
970 | * additional data. Trust that if the VBT was written into | |
971 | * the OpRegion then they have validated the LVDS's existence. | |
972 | */ | |
973 | if (dev_priv->opregion.vbt) | |
974 | return true; | |
7cf4f69d | 975 | } |
425904dd CW |
976 | |
977 | return false; | |
7cf4f69d ZY |
978 | } |
979 | ||
1974cad0 DV |
980 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
981 | { | |
982 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
983 | return 1; | |
984 | } | |
985 | ||
986 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
987 | { | |
988 | .callback = intel_dual_link_lvds_callback, | |
989 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
990 | .matches = { | |
991 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
992 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
993 | }, | |
994 | }, | |
995 | { } /* terminating entry */ | |
996 | }; | |
997 | ||
998 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
999 | { |
1000 | struct intel_encoder *encoder; | |
1001 | struct intel_lvds_encoder *lvds_encoder; | |
1002 | ||
1003 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
1004 | base.head) { | |
1005 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
1006 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
1007 | ||
1008 | return lvds_encoder->is_dual_link; | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | return false; | |
1013 | } | |
1014 | ||
7dec0606 | 1015 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 1016 | { |
7dec0606 | 1017 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
1018 | unsigned int val; |
1019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
1020 | |
1021 | /* use the module option value if specified */ | |
1022 | if (i915_lvds_channel_mode > 0) | |
1023 | return i915_lvds_channel_mode == 2; | |
1024 | ||
1025 | if (dmi_check_system(intel_dual_link_lvds)) | |
1026 | return true; | |
1027 | ||
13c7d870 DV |
1028 | /* BIOS should set the proper LVDS register value at boot, but |
1029 | * in reality, it doesn't set the value when the lid is closed; | |
1030 | * we need to check "the value to be set" in VBT when LVDS | |
1031 | * register is uninitialized. | |
1032 | */ | |
7dec0606 | 1033 | val = I915_READ(lvds_encoder->reg); |
13c7d870 DV |
1034 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
1035 | val = dev_priv->bios_lvds_val; | |
1036 | ||
1974cad0 DV |
1037 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
1038 | } | |
1039 | ||
f3cfcba6 CW |
1040 | static bool intel_lvds_supported(struct drm_device *dev) |
1041 | { | |
1042 | /* With the introduction of the PCH we gained a dedicated | |
1043 | * LVDS presence pin, use it. */ | |
311e359c | 1044 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
1045 | return true; |
1046 | ||
1047 | /* Otherwise LVDS was only attached to mobile products, | |
1048 | * except for the inglorious 830gm */ | |
311e359c PZ |
1049 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
1050 | return true; | |
1051 | ||
1052 | return false; | |
f3cfcba6 CW |
1053 | } |
1054 | ||
79e53945 JB |
1055 | /** |
1056 | * intel_lvds_init - setup LVDS connectors on this device | |
1057 | * @dev: drm device | |
1058 | * | |
1059 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
1060 | * modes we can display on the LVDS panel (if present). | |
1061 | */ | |
c5d1b51d | 1062 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
1063 | { |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 1065 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 1066 | struct intel_encoder *intel_encoder; |
c7362c4d | 1067 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 1068 | struct intel_connector *intel_connector; |
79e53945 JB |
1069 | struct drm_connector *connector; |
1070 | struct drm_encoder *encoder; | |
1071 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 1072 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 1073 | struct edid *edid; |
79e53945 JB |
1074 | struct drm_crtc *crtc; |
1075 | u32 lvds; | |
270eea0f CW |
1076 | int pipe; |
1077 | u8 pin; | |
79e53945 | 1078 | |
f3cfcba6 CW |
1079 | if (!intel_lvds_supported(dev)) |
1080 | return false; | |
1081 | ||
425d244c JW |
1082 | /* Skip init on machines we know falsely report LVDS */ |
1083 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 1084 | return false; |
565dcd46 | 1085 | |
270eea0f CW |
1086 | pin = GMBUS_PORT_PANEL; |
1087 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 1088 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 1089 | return false; |
38b3037e | 1090 | } |
e99da35f | 1091 | |
c619eed4 | 1092 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1093 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 1094 | return false; |
5ceb0f9b | 1095 | if (dev_priv->edp.support) { |
28c97730 | 1096 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 1097 | return false; |
32f9d658 | 1098 | } |
541998a1 ZW |
1099 | } |
1100 | ||
29b99b48 JN |
1101 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
1102 | if (!lvds_encoder) | |
c5d1b51d | 1103 | return false; |
79e53945 | 1104 | |
c7362c4d JN |
1105 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
1106 | if (!lvds_connector) { | |
29b99b48 | 1107 | kfree(lvds_encoder); |
c5d1b51d | 1108 | return false; |
bb8a3560 ZW |
1109 | } |
1110 | ||
62165e0d JN |
1111 | lvds_encoder->attached_connector = lvds_connector; |
1112 | ||
e9e331a8 | 1113 | if (!HAS_PCH_SPLIT(dev)) { |
29b99b48 | 1114 | lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); |
e9e331a8 CW |
1115 | } |
1116 | ||
29b99b48 | 1117 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1118 | encoder = &intel_encoder->base; |
c7362c4d | 1119 | intel_connector = &lvds_connector->base; |
ea5b213a | 1120 | connector = &intel_connector->base; |
bb8a3560 | 1121 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1122 | DRM_MODE_CONNECTOR_LVDS); |
1123 | ||
4ef69c7a | 1124 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
1125 | DRM_MODE_ENCODER_LVDS); |
1126 | ||
c22834ec | 1127 | intel_encoder->enable = intel_enable_lvds; |
9d6d9f19 | 1128 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
fc683091 | 1129 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
7ae89233 | 1130 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 1131 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c DV |
1132 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
1133 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
c22834ec | 1134 | |
df0e9248 | 1135 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1136 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1137 | |
66a9278e | 1138 | intel_encoder->cloneable = false; |
27f8227b JB |
1139 | if (HAS_PCH_SPLIT(dev)) |
1140 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1141 | else if (IS_GEN4(dev)) |
1142 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1143 | else |
1144 | intel_encoder->crtc_mask = (1 << 1); | |
1145 | ||
79e53945 JB |
1146 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1147 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1148 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1149 | connector->interlace_allowed = false; | |
1150 | connector->doublescan_allowed = false; | |
1151 | ||
7dec0606 DV |
1152 | if (HAS_PCH_SPLIT(dev)) { |
1153 | lvds_encoder->reg = PCH_LVDS; | |
1154 | } else { | |
1155 | lvds_encoder->reg = LVDS; | |
1156 | } | |
1157 | ||
3fbe18d6 ZY |
1158 | /* create the scaling mode property */ |
1159 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1160 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1161 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1162 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1163 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1164 | /* |
1165 | * LVDS discovery: | |
1166 | * 1) check for EDID on DDC | |
1167 | * 2) check for VBT data | |
1168 | * 3) check to see if LVDS is already on | |
1169 | * if none of the above, no panel | |
1170 | * 4) make sure lid is open | |
1171 | * if closed, act like it's not there for now | |
1172 | */ | |
1173 | ||
79e53945 JB |
1174 | /* |
1175 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1176 | * preferred mode is the right one. | |
1177 | */ | |
9cd300e0 JN |
1178 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1179 | if (edid) { | |
1180 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1181 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1182 | edid); |
3f8ff0e7 | 1183 | } else { |
9cd300e0 JN |
1184 | kfree(edid); |
1185 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1186 | } |
9cd300e0 JN |
1187 | } else { |
1188 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1189 | } |
9cd300e0 JN |
1190 | lvds_connector->base.edid = edid; |
1191 | ||
1192 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1193 | /* Didn't get an EDID, so |
1194 | * Set wide sync ranges so we get all modes | |
1195 | * handed to valid_mode for checking | |
1196 | */ | |
1197 | connector->display_info.min_vfreq = 0; | |
1198 | connector->display_info.max_vfreq = 200; | |
1199 | connector->display_info.min_hfreq = 0; | |
1200 | connector->display_info.max_hfreq = 200; | |
1201 | } | |
79e53945 JB |
1202 | |
1203 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1204 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1205 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1206 | drm_mode_debug_printmodeline(scan); | |
1207 | ||
dd06f90e | 1208 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1209 | if (fixed_mode) { |
1210 | intel_find_lvds_downclock(dev, fixed_mode, | |
1211 | connector); | |
1212 | goto out; | |
1213 | } | |
79e53945 | 1214 | } |
79e53945 JB |
1215 | } |
1216 | ||
1217 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1218 | if (dev_priv->lfp_lvds_vbt_mode) { |
6a9d51b7 CW |
1219 | DRM_DEBUG_KMS("using mode from VBT: "); |
1220 | drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); | |
1221 | ||
dd06f90e JN |
1222 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
1223 | if (fixed_mode) { | |
1224 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1225 | goto out; |
1226 | } | |
79e53945 JB |
1227 | } |
1228 | ||
1229 | /* | |
1230 | * If we didn't get EDID, try checking if the panel is already turned | |
1231 | * on. If so, assume that whatever is currently programmed is the | |
1232 | * correct mode. | |
1233 | */ | |
541998a1 | 1234 | |
f2b115e6 | 1235 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1236 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1237 | goto failed; |
1238 | ||
79e53945 JB |
1239 | lvds = I915_READ(LVDS); |
1240 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1241 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1242 | |
1243 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1244 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1245 | if (fixed_mode) { | |
6a9d51b7 CW |
1246 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1247 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1248 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1249 | goto out; |
79e53945 JB |
1250 | } |
1251 | } | |
1252 | ||
1253 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1254 | if (!fixed_mode) |
79e53945 JB |
1255 | goto failed; |
1256 | ||
79e53945 | 1257 | out: |
7dec0606 | 1258 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1259 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1260 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1261 | ||
24ded204 DV |
1262 | /* |
1263 | * Unlock registers and just | |
1264 | * leave them unlocked | |
1265 | */ | |
c619eed4 | 1266 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1267 | I915_WRITE(PCH_PP_CONTROL, |
1268 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1269 | } else { | |
ed10fca9 KP |
1270 | I915_WRITE(PP_CONTROL, |
1271 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1272 | } |
db1740a0 JN |
1273 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1274 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1275 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1276 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1277 | } |
79e53945 | 1278 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1279 | |
dd06f90e | 1280 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1281 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1282 | |
c5d1b51d | 1283 | return true; |
79e53945 JB |
1284 | |
1285 | failed: | |
8a4c47f3 | 1286 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1287 | drm_connector_cleanup(connector); |
1991bdfa | 1288 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1289 | if (fixed_mode) |
1290 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1291 | kfree(lvds_encoder); |
c7362c4d | 1292 | kfree(lvds_connector); |
c5d1b51d | 1293 | return false; |
79e53945 | 1294 | } |