Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
4eddaeec | 34 | #include <linux/vga_switcheroo.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_edid.h> | |
79e53945 | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
79e53945 | 41 | #include "i915_drv.h" |
e99da35f | 42 | #include <linux/acpi.h> |
79e53945 | 43 | |
3fbe18d6 | 44 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
45 | struct intel_lvds_connector { |
46 | struct intel_connector base; | |
788319d4 | 47 | |
db1740a0 | 48 | struct notifier_block lid_notifier; |
c7362c4d JN |
49 | }; |
50 | ||
ed6143b8 ID |
51 | struct intel_lvds_pps { |
52 | /* 100us units */ | |
53 | int t1_t2; | |
54 | int t3; | |
55 | int t4; | |
56 | int t5; | |
57 | int tx; | |
58 | ||
59 | int divider; | |
60 | ||
61 | int port; | |
62 | bool powerdown_on_reset; | |
63 | }; | |
64 | ||
29b99b48 | 65 | struct intel_lvds_encoder { |
ea5b213a | 66 | struct intel_encoder base; |
788319d4 | 67 | |
13c7d870 | 68 | bool is_dual_link; |
f0f59a00 | 69 | i915_reg_t reg; |
1f835a77 | 70 | u32 a3_power; |
788319d4 | 71 | |
ed6143b8 ID |
72 | struct intel_lvds_pps init_pps; |
73 | u32 init_lvds_val; | |
74 | ||
62165e0d | 75 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
76 | }; |
77 | ||
29b99b48 | 78 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 79 | { |
29b99b48 | 80 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
81 | } |
82 | ||
c7362c4d | 83 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 84 | { |
c7362c4d | 85 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
86 | } |
87 | ||
b1dc332c DV |
88 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
89 | enum pipe *pipe) | |
90 | { | |
91 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 92 | struct drm_i915_private *dev_priv = to_i915(dev); |
7dec0606 | 93 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 94 | enum intel_display_power_domain power_domain; |
7dec0606 | 95 | u32 tmp; |
ecb24482 | 96 | bool ret; |
b1dc332c | 97 | |
34a6c70f | 98 | power_domain = intel_display_port_power_domain(encoder); |
ecb24482 | 99 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
34a6c70f PZ |
100 | return false; |
101 | ||
ecb24482 ID |
102 | ret = false; |
103 | ||
7dec0606 | 104 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
105 | |
106 | if (!(tmp & LVDS_PORT_EN)) | |
ecb24482 | 107 | goto out; |
b1dc332c DV |
108 | |
109 | if (HAS_PCH_CPT(dev)) | |
110 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
111 | else | |
112 | *pipe = PORT_TO_PIPE(tmp); | |
113 | ||
ecb24482 ID |
114 | ret = true; |
115 | ||
116 | out: | |
117 | intel_display_power_put(dev_priv, power_domain); | |
118 | ||
119 | return ret; | |
b1dc332c DV |
120 | } |
121 | ||
045ac3b5 | 122 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
5cec258b | 123 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
124 | { |
125 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 126 | struct drm_i915_private *dev_priv = to_i915(dev); |
d0669d00 VS |
127 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
128 | u32 tmp, flags = 0; | |
045ac3b5 | 129 | |
d0669d00 | 130 | tmp = I915_READ(lvds_encoder->reg); |
045ac3b5 JB |
131 | if (tmp & LVDS_HSYNC_POLARITY) |
132 | flags |= DRM_MODE_FLAG_NHSYNC; | |
133 | else | |
134 | flags |= DRM_MODE_FLAG_PHSYNC; | |
135 | if (tmp & LVDS_VSYNC_POLARITY) | |
136 | flags |= DRM_MODE_FLAG_NVSYNC; | |
137 | else | |
138 | flags |= DRM_MODE_FLAG_PVSYNC; | |
139 | ||
2d112de7 | 140 | pipe_config->base.adjusted_mode.flags |= flags; |
06922821 | 141 | |
a0cbe6a3 JN |
142 | if (INTEL_INFO(dev)->gen < 5) |
143 | pipe_config->gmch_pfit.lvds_border_bits = | |
144 | tmp & LVDS_BORDER_ENABLE; | |
145 | ||
6b89cdde DV |
146 | /* gen2/3 store dither state in pfit control, needs to match */ |
147 | if (INTEL_INFO(dev)->gen < 4) { | |
148 | tmp = I915_READ(PFIT_CONTROL); | |
149 | ||
150 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
151 | } | |
152 | ||
e3b247da | 153 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
154 | } |
155 | ||
ed6143b8 ID |
156 | static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, |
157 | struct intel_lvds_pps *pps) | |
158 | { | |
159 | u32 val; | |
160 | ||
161 | pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; | |
162 | ||
163 | val = I915_READ(PP_ON_DELAYS(0)); | |
164 | pps->port = (val & PANEL_PORT_SELECT_MASK) >> | |
165 | PANEL_PORT_SELECT_SHIFT; | |
166 | pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> | |
167 | PANEL_POWER_UP_DELAY_SHIFT; | |
168 | pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> | |
169 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
170 | ||
171 | val = I915_READ(PP_OFF_DELAYS(0)); | |
172 | pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> | |
173 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
174 | pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
175 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
176 | ||
177 | val = I915_READ(PP_DIVISOR(0)); | |
178 | pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> | |
179 | PP_REFERENCE_DIVIDER_SHIFT; | |
180 | val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
181 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
182 | /* | |
183 | * Remove the BSpec specified +1 (100ms) offset that accounts for a | |
184 | * too short power-cycle delay due to the asynchronous programming of | |
185 | * the register. | |
186 | */ | |
187 | if (val) | |
188 | val--; | |
189 | /* Convert from 100ms to 100us units */ | |
190 | pps->t4 = val * 1000; | |
191 | ||
192 | if (INTEL_INFO(dev_priv)->gen <= 4 && | |
193 | pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { | |
194 | DRM_DEBUG_KMS("Panel power timings uninitialized, " | |
195 | "setting defaults\n"); | |
196 | /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ | |
197 | pps->t1_t2 = 40 * 10; | |
198 | pps->t5 = 200 * 10; | |
199 | /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ | |
200 | pps->t3 = 35 * 10; | |
201 | pps->tx = 200 * 10; | |
202 | } | |
203 | ||
204 | DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " | |
205 | "divider %d port %d powerdown_on_reset %d\n", | |
206 | pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, | |
207 | pps->divider, pps->port, pps->powerdown_on_reset); | |
208 | } | |
209 | ||
210 | static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, | |
211 | struct intel_lvds_pps *pps) | |
212 | { | |
213 | u32 val; | |
214 | ||
215 | val = I915_READ(PP_CONTROL(0)); | |
216 | WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); | |
217 | if (pps->powerdown_on_reset) | |
218 | val |= PANEL_POWER_RESET; | |
219 | I915_WRITE(PP_CONTROL(0), val); | |
220 | ||
221 | I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | | |
222 | (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | | |
223 | (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); | |
224 | I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | | |
225 | (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); | |
226 | ||
227 | val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; | |
228 | val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << | |
229 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
230 | I915_WRITE(PP_DIVISOR(0), val); | |
231 | } | |
232 | ||
f6736a1a | 233 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
234 | { |
235 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
236 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 237 | struct drm_i915_private *dev_priv = to_i915(dev); |
55607e8a | 238 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
124abe07 | 239 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
55607e8a | 240 | int pipe = crtc->pipe; |
fc683091 DV |
241 | u32 temp; |
242 | ||
55607e8a DV |
243 | if (HAS_PCH_SPLIT(dev)) { |
244 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
245 | assert_shared_dpll_disabled(dev_priv, | |
8106ddbd | 246 | crtc->config->shared_dpll); |
55607e8a DV |
247 | } else { |
248 | assert_pll_disabled(dev_priv, pipe); | |
249 | } | |
250 | ||
ed6143b8 ID |
251 | intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); |
252 | ||
253 | temp = lvds_encoder->init_lvds_val; | |
fc683091 | 254 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
62810e5a DV |
255 | |
256 | if (HAS_PCH_CPT(dev)) { | |
257 | temp &= ~PORT_TRANS_SEL_MASK; | |
258 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 259 | } else { |
62810e5a DV |
260 | if (pipe == 1) { |
261 | temp |= LVDS_PIPEB_SELECT; | |
262 | } else { | |
263 | temp &= ~LVDS_PIPEB_SELECT; | |
264 | } | |
fc683091 | 265 | } |
62810e5a | 266 | |
fc683091 | 267 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 268 | temp &= ~LVDS_BORDER_ENABLE; |
6e3c9717 | 269 | temp |= crtc->config->gmch_pfit.lvds_border_bits; |
fc683091 DV |
270 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
271 | * set the DPLLs for dual-channel mode or not. | |
272 | */ | |
273 | if (lvds_encoder->is_dual_link) | |
274 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
275 | else | |
276 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
277 | ||
278 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
279 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
280 | * panels behave in the two modes. For now, let's just maintain the |
281 | * value we got from the BIOS. | |
fc683091 | 282 | */ |
f1fda745 CW |
283 | temp &= ~LVDS_A3_POWER_MASK; |
284 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
285 | |
286 | /* Set the dithering flag on LVDS as needed, note that there is no | |
287 | * special lvds dither control bit on pch-split platforms, dithering is | |
288 | * only controlled through the PIPECONF reg. */ | |
7e22dbbb | 289 | if (IS_GEN4(dev_priv)) { |
d8b32247 DV |
290 | /* Bspec wording suggests that LVDS port dithering only exists |
291 | * for 18bpp panels. */ | |
6e3c9717 | 292 | if (crtc->config->dither && crtc->config->pipe_bpp == 18) |
fc683091 DV |
293 | temp |= LVDS_ENABLE_DITHER; |
294 | else | |
295 | temp &= ~LVDS_ENABLE_DITHER; | |
296 | } | |
297 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 298 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 299 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 300 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
301 | temp |= LVDS_VSYNC_POLARITY; |
302 | ||
303 | I915_WRITE(lvds_encoder->reg, temp); | |
304 | } | |
305 | ||
79e53945 JB |
306 | /** |
307 | * Sets the power state for the panel. | |
308 | */ | |
c22834ec | 309 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 310 | { |
c22834ec | 311 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 312 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
313 | struct intel_connector *intel_connector = |
314 | &lvds_encoder->attached_connector->base; | |
fac5e23e | 315 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 316 | |
7dec0606 | 317 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 318 | |
5a162e22 | 319 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); |
7dec0606 | 320 | POSTING_READ(lvds_encoder->reg); |
44cb734c | 321 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) |
de842eff | 322 | DRM_ERROR("timed out waiting for panel to power on\n"); |
2a1292fd | 323 | |
752aa88a | 324 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
325 | } |
326 | ||
c22834ec | 327 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 328 | { |
c22834ec | 329 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 330 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
fac5e23e | 331 | struct drm_i915_private *dev_priv = to_i915(dev); |
2a1292fd | 332 | |
5a162e22 | 333 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); |
44cb734c | 334 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) |
de842eff | 335 | DRM_ERROR("timed out waiting for panel to power off\n"); |
2a1292fd | 336 | |
7dec0606 DV |
337 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
338 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
339 | } |
340 | ||
d26a5b6e VS |
341 | static void gmch_disable_lvds(struct intel_encoder *encoder) |
342 | { | |
343 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
344 | struct intel_connector *intel_connector = | |
345 | &lvds_encoder->attached_connector->base; | |
346 | ||
347 | intel_panel_disable_backlight(intel_connector); | |
348 | ||
349 | intel_disable_lvds(encoder); | |
350 | } | |
351 | ||
352 | static void pch_disable_lvds(struct intel_encoder *encoder) | |
353 | { | |
354 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
355 | struct intel_connector *intel_connector = | |
356 | &lvds_encoder->attached_connector->base; | |
357 | ||
358 | intel_panel_disable_backlight(intel_connector); | |
359 | } | |
360 | ||
361 | static void pch_post_disable_lvds(struct intel_encoder *encoder) | |
362 | { | |
363 | intel_disable_lvds(encoder); | |
364 | } | |
365 | ||
c19de8eb DL |
366 | static enum drm_mode_status |
367 | intel_lvds_mode_valid(struct drm_connector *connector, | |
368 | struct drm_display_mode *mode) | |
79e53945 | 369 | { |
dd06f90e JN |
370 | struct intel_connector *intel_connector = to_intel_connector(connector); |
371 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
7f7b58cc | 372 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; |
79e53945 | 373 | |
788319d4 CW |
374 | if (mode->hdisplay > fixed_mode->hdisplay) |
375 | return MODE_PANEL; | |
376 | if (mode->vdisplay > fixed_mode->vdisplay) | |
377 | return MODE_PANEL; | |
7f7b58cc MK |
378 | if (fixed_mode->clock > max_pixclk) |
379 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
380 | |
381 | return MODE_OK; | |
382 | } | |
383 | ||
7ae89233 | 384 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
5cec258b | 385 | struct intel_crtc_state *pipe_config) |
79e53945 | 386 | { |
7ae89233 | 387 | struct drm_device *dev = intel_encoder->base.dev; |
7ae89233 DV |
388 | struct intel_lvds_encoder *lvds_encoder = |
389 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
390 | struct intel_connector *intel_connector = |
391 | &lvds_encoder->attached_connector->base; | |
2d112de7 | 392 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d21bd67b | 393 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e53c2e0 | 394 | unsigned int lvds_bpp; |
79e53945 JB |
395 | |
396 | /* Should never happen!! */ | |
a6c45cf0 | 397 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 398 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
399 | return false; |
400 | } | |
401 | ||
1f835a77 | 402 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
403 | lvds_bpp = 8*3; |
404 | else | |
405 | lvds_bpp = 6*3; | |
406 | ||
e29c22c0 | 407 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
408 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
409 | pipe_config->pipe_bpp, lvds_bpp); | |
410 | pipe_config->pipe_bpp = lvds_bpp; | |
411 | } | |
d8b32247 | 412 | |
79e53945 | 413 | /* |
71677043 | 414 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
415 | * to the adjusted mode. The CRTC will be set up for this mode, |
416 | * with the panel scaling set up to source from the H/VDisplay | |
417 | * of the original mode. | |
418 | */ | |
4d891523 | 419 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 420 | adjusted_mode); |
1d8e1c75 CW |
421 | |
422 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
423 | pipe_config->has_pch_encoder = true; |
424 | ||
b074cec8 JB |
425 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
426 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
427 | } else { |
428 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
429 | intel_connector->panel.fitting_mode); | |
79e53945 | 430 | |
21d8a475 | 431 | } |
f9bef081 | 432 | |
79e53945 JB |
433 | /* |
434 | * XXX: It would be nice to support lower refresh rates on the | |
435 | * panels to reduce power consumption, and perhaps match the | |
436 | * user's requested refresh rate. | |
437 | */ | |
438 | ||
439 | return true; | |
440 | } | |
441 | ||
79e53945 JB |
442 | /** |
443 | * Detect the LVDS connection. | |
444 | * | |
b42d4c5c JB |
445 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
446 | * connected and closed means disconnected. We also send hotplug events as | |
447 | * needed, using lid status notification from the input layer. | |
79e53945 | 448 | */ |
7b334fcb | 449 | static enum drm_connector_status |
930a9e28 | 450 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 451 | { |
7b9c5abe | 452 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 453 | enum drm_connector_status status; |
b42d4c5c | 454 | |
164c8598 | 455 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 456 | connector->base.id, connector->name); |
164c8598 | 457 | |
fe16d949 CW |
458 | status = intel_panel_detect(dev); |
459 | if (status != connector_status_unknown) | |
460 | return status; | |
01fe9dbd | 461 | |
6ee3b5a1 | 462 | return connector_status_connected; |
79e53945 JB |
463 | } |
464 | ||
465 | /** | |
466 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
467 | */ | |
468 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
469 | { | |
62165e0d | 470 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 471 | struct drm_device *dev = connector->dev; |
788319d4 | 472 | struct drm_display_mode *mode; |
79e53945 | 473 | |
9cd300e0 | 474 | /* use cached edid if we have one */ |
2aa4f099 | 475 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 476 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 477 | |
dd06f90e | 478 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 479 | if (mode == NULL) |
788319d4 | 480 | return 0; |
79e53945 | 481 | |
788319d4 CW |
482 | drm_mode_probed_add(connector, mode); |
483 | return 1; | |
79e53945 JB |
484 | } |
485 | ||
0544edfd TB |
486 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
487 | { | |
bc0daf48 | 488 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
489 | return 1; |
490 | } | |
491 | ||
492 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
493 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
494 | { | |
495 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
496 | .ident = "Toshiba Tecra A11", | |
497 | .matches = { | |
498 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
499 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
500 | }, | |
501 | }, | |
502 | ||
503 | { } /* terminating entry */ | |
504 | }; | |
505 | ||
c9354c85 | 506 | /* |
b8efb17b ZR |
507 | * Lid events. Note the use of 'modeset': |
508 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
509 | * and set it to MODESET_DONE on open | |
c9354c85 | 510 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
511 | * duplicate events where it was already properly set) |
512 | * - the suspend/resume paths will set it to | |
513 | * MODESET_SUSPENDED and ignore the lid open event, | |
514 | * because they restore the mode ("lid open"). | |
c9354c85 | 515 | */ |
c1c7af60 JB |
516 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
517 | void *unused) | |
518 | { | |
db1740a0 JN |
519 | struct intel_lvds_connector *lvds_connector = |
520 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
521 | struct drm_connector *connector = &lvds_connector->base.base; | |
522 | struct drm_device *dev = connector->dev; | |
fac5e23e | 523 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1c7af60 | 524 | |
2fb4e61d AW |
525 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
526 | return NOTIFY_OK; | |
527 | ||
b8efb17b ZR |
528 | mutex_lock(&dev_priv->modeset_restore_lock); |
529 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
530 | goto exit; | |
a2565377 ZY |
531 | /* |
532 | * check and update the status of LVDS connector after receiving | |
533 | * the LID nofication event. | |
534 | */ | |
db1740a0 | 535 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 536 | |
0544edfd TB |
537 | /* Don't force modeset on machines where it causes a GPU lockup */ |
538 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 539 | goto exit; |
c9354c85 | 540 | if (!acpi_lid_open()) { |
b8efb17b ZR |
541 | /* do modeset on next lid open event */ |
542 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
543 | goto exit; | |
06891e27 | 544 | } |
c1c7af60 | 545 | |
b8efb17b ZR |
546 | if (dev_priv->modeset_restore == MODESET_DONE) |
547 | goto exit; | |
c9354c85 | 548 | |
5be19d91 DV |
549 | /* |
550 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
551 | * We try to detect this here and undo any damage. The split for PCH | |
552 | * platforms is rather conservative and a bit arbitrary expect that on | |
553 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
554 | * and as part of the cleanup in the hw state restore we also redisable | |
555 | * the vga plane. | |
556 | */ | |
9f54d4bd | 557 | if (!HAS_PCH_SPLIT(dev)) |
043e9bda | 558 | intel_display_resume(dev); |
06324194 | 559 | |
b8efb17b ZR |
560 | dev_priv->modeset_restore = MODESET_DONE; |
561 | ||
562 | exit: | |
563 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
564 | return NOTIFY_OK; |
565 | } | |
566 | ||
79e53945 JB |
567 | /** |
568 | * intel_lvds_destroy - unregister and free LVDS structures | |
569 | * @connector: connector to free | |
570 | * | |
571 | * Unregister the DDC bus for this connector then free the driver private | |
572 | * structure. | |
573 | */ | |
574 | static void intel_lvds_destroy(struct drm_connector *connector) | |
575 | { | |
db1740a0 JN |
576 | struct intel_lvds_connector *lvds_connector = |
577 | to_lvds_connector(connector); | |
79e53945 | 578 | |
db1740a0 JN |
579 | if (lvds_connector->lid_notifier.notifier_call) |
580 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 581 | |
9cd300e0 JN |
582 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
583 | kfree(lvds_connector->base.edid); | |
584 | ||
1d508706 | 585 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 586 | |
79e53945 JB |
587 | drm_connector_cleanup(connector); |
588 | kfree(connector); | |
589 | } | |
590 | ||
335041ed JB |
591 | static int intel_lvds_set_property(struct drm_connector *connector, |
592 | struct drm_property *property, | |
593 | uint64_t value) | |
594 | { | |
4d891523 | 595 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 596 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 597 | |
788319d4 | 598 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 599 | struct drm_crtc *crtc; |
bb8a3560 | 600 | |
53bd8389 JB |
601 | if (value == DRM_MODE_SCALE_NONE) { |
602 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 603 | return -EINVAL; |
3fbe18d6 | 604 | } |
788319d4 | 605 | |
4d891523 | 606 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
607 | /* the LVDS scaling property is not changed */ |
608 | return 0; | |
609 | } | |
4d891523 | 610 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
611 | |
612 | crtc = intel_attached_encoder(connector)->base.crtc; | |
83d65738 | 613 | if (crtc && crtc->state->enable) { |
3fbe18d6 ZY |
614 | /* |
615 | * If the CRTC is enabled, the display will be changed | |
616 | * according to the new panel fitting mode. | |
617 | */ | |
c0c36b94 | 618 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
619 | } |
620 | } | |
621 | ||
335041ed JB |
622 | return 0; |
623 | } | |
624 | ||
79e53945 JB |
625 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
626 | .get_modes = intel_lvds_get_modes, | |
627 | .mode_valid = intel_lvds_mode_valid, | |
79e53945 JB |
628 | }; |
629 | ||
630 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
4d688a2a | 631 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
632 | .detect = intel_lvds_detect, |
633 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 634 | .set_property = intel_lvds_set_property, |
2545e4a6 | 635 | .atomic_get_property = intel_connector_atomic_get_property, |
1ebaa0b9 | 636 | .late_register = intel_connector_register, |
c191eca1 | 637 | .early_unregister = intel_connector_unregister, |
79e53945 | 638 | .destroy = intel_lvds_destroy, |
c6f95f27 | 639 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 640 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
641 | }; |
642 | ||
79e53945 | 643 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 644 | .destroy = intel_encoder_destroy, |
79e53945 JB |
645 | }; |
646 | ||
bbe1c274 | 647 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 648 | { |
bc0daf48 | 649 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
650 | return 1; |
651 | } | |
79e53945 | 652 | |
425d244c | 653 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 654 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
655 | { |
656 | .callback = intel_no_lvds_dmi_callback, | |
657 | .ident = "Apple Mac Mini (Core series)", | |
658 | .matches = { | |
98acd46f | 659 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
660 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
661 | }, | |
662 | }, | |
663 | { | |
664 | .callback = intel_no_lvds_dmi_callback, | |
665 | .ident = "Apple Mac Mini (Core 2 series)", | |
666 | .matches = { | |
98acd46f | 667 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
668 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
669 | }, | |
670 | }, | |
671 | { | |
672 | .callback = intel_no_lvds_dmi_callback, | |
673 | .ident = "MSI IM-945GSE-A", | |
674 | .matches = { | |
675 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
676 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
677 | }, | |
678 | }, | |
679 | { | |
680 | .callback = intel_no_lvds_dmi_callback, | |
681 | .ident = "Dell Studio Hybrid", | |
682 | .matches = { | |
683 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
684 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
685 | }, | |
686 | }, | |
70aa96ca JW |
687 | { |
688 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
689 | .ident = "Dell OptiPlex FX170", |
690 | .matches = { | |
691 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
692 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
693 | }, | |
694 | }, | |
695 | { | |
696 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
697 | .ident = "AOpen Mini PC", |
698 | .matches = { | |
699 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
700 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
701 | }, | |
702 | }, | |
ed8c754b TV |
703 | { |
704 | .callback = intel_no_lvds_dmi_callback, | |
705 | .ident = "AOpen Mini PC MP915", | |
706 | .matches = { | |
707 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
708 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
709 | }, | |
710 | }, | |
22ab70d3 KP |
711 | { |
712 | .callback = intel_no_lvds_dmi_callback, | |
713 | .ident = "AOpen i915GMm-HFS", | |
714 | .matches = { | |
715 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
716 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
717 | }, | |
718 | }, | |
e57b6886 DV |
719 | { |
720 | .callback = intel_no_lvds_dmi_callback, | |
721 | .ident = "AOpen i45GMx-I", | |
722 | .matches = { | |
723 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
724 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
725 | }, | |
726 | }, | |
fa0864b2 MC |
727 | { |
728 | .callback = intel_no_lvds_dmi_callback, | |
729 | .ident = "Aopen i945GTt-VFA", | |
730 | .matches = { | |
731 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
732 | }, | |
733 | }, | |
9875557e SB |
734 | { |
735 | .callback = intel_no_lvds_dmi_callback, | |
736 | .ident = "Clientron U800", | |
737 | .matches = { | |
738 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
739 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
740 | }, | |
741 | }, | |
6a574b5b | 742 | { |
44306ab3 JS |
743 | .callback = intel_no_lvds_dmi_callback, |
744 | .ident = "Clientron E830", | |
745 | .matches = { | |
746 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
747 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
748 | }, | |
749 | }, | |
750 | { | |
6a574b5b HG |
751 | .callback = intel_no_lvds_dmi_callback, |
752 | .ident = "Asus EeeBox PC EB1007", | |
753 | .matches = { | |
754 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
755 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
756 | }, | |
757 | }, | |
0999bbe0 AJ |
758 | { |
759 | .callback = intel_no_lvds_dmi_callback, | |
760 | .ident = "Asus AT5NM10T-I", | |
761 | .matches = { | |
762 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
763 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
764 | }, | |
765 | }, | |
33471119 JBG |
766 | { |
767 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 768 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
769 | .matches = { |
770 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 771 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
772 | }, |
773 | }, | |
f5b8a7ed MG |
774 | { |
775 | .callback = intel_no_lvds_dmi_callback, | |
776 | .ident = "Hewlett-Packard t5745", | |
777 | .matches = { | |
778 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 779 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
780 | }, |
781 | }, | |
782 | { | |
783 | .callback = intel_no_lvds_dmi_callback, | |
784 | .ident = "Hewlett-Packard st5747", | |
785 | .matches = { | |
786 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 787 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
788 | }, |
789 | }, | |
97effadb AA |
790 | { |
791 | .callback = intel_no_lvds_dmi_callback, | |
792 | .ident = "MSI Wind Box DC500", | |
793 | .matches = { | |
794 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
795 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
796 | }, | |
797 | }, | |
a51d4ed0 CW |
798 | { |
799 | .callback = intel_no_lvds_dmi_callback, | |
800 | .ident = "Gigabyte GA-D525TUD", | |
801 | .matches = { | |
802 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
803 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
804 | }, | |
805 | }, | |
c31407a3 CW |
806 | { |
807 | .callback = intel_no_lvds_dmi_callback, | |
808 | .ident = "Supermicro X7SPA-H", | |
809 | .matches = { | |
810 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
811 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
812 | }, | |
813 | }, | |
9e9dd0e8 CL |
814 | { |
815 | .callback = intel_no_lvds_dmi_callback, | |
816 | .ident = "Fujitsu Esprimo Q900", | |
817 | .matches = { | |
818 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
819 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
820 | }, | |
821 | }, | |
645378d8 RP |
822 | { |
823 | .callback = intel_no_lvds_dmi_callback, | |
824 | .ident = "Intel D410PT", | |
825 | .matches = { | |
826 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
827 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
828 | }, | |
829 | }, | |
830 | { | |
831 | .callback = intel_no_lvds_dmi_callback, | |
832 | .ident = "Intel D425KT", | |
833 | .matches = { | |
834 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
835 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
836 | }, | |
837 | }, | |
e5614f0c CW |
838 | { |
839 | .callback = intel_no_lvds_dmi_callback, | |
840 | .ident = "Intel D510MO", | |
841 | .matches = { | |
842 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
843 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
844 | }, | |
845 | }, | |
dcf6d294 JN |
846 | { |
847 | .callback = intel_no_lvds_dmi_callback, | |
848 | .ident = "Intel D525MW", | |
849 | .matches = { | |
850 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
851 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
852 | }, | |
853 | }, | |
425d244c JW |
854 | |
855 | { } /* terminating entry */ | |
856 | }; | |
79e53945 | 857 | |
1974cad0 DV |
858 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
859 | { | |
860 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
861 | return 1; | |
862 | } | |
863 | ||
864 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
865 | { | |
866 | .callback = intel_dual_link_lvds_callback, | |
3916e3fd LW |
867 | .ident = "Apple MacBook Pro 15\" (2010)", |
868 | .matches = { | |
869 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
870 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
871 | }, | |
872 | }, | |
873 | { | |
874 | .callback = intel_dual_link_lvds_callback, | |
875 | .ident = "Apple MacBook Pro 15\" (2011)", | |
1974cad0 DV |
876 | .matches = { |
877 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
878 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
879 | }, | |
880 | }, | |
3916e3fd LW |
881 | { |
882 | .callback = intel_dual_link_lvds_callback, | |
883 | .ident = "Apple MacBook Pro 15\" (2012)", | |
884 | .matches = { | |
885 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
886 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
887 | }, | |
888 | }, | |
1974cad0 DV |
889 | { } /* terminating entry */ |
890 | }; | |
891 | ||
97a824e1 | 892 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) |
13c7d870 | 893 | { |
97a824e1 | 894 | struct intel_encoder *intel_encoder; |
13c7d870 | 895 | |
97a824e1 ID |
896 | for_each_intel_encoder(dev, intel_encoder) |
897 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
898 | return intel_encoder; | |
13c7d870 | 899 | |
97a824e1 ID |
900 | return NULL; |
901 | } | |
902 | ||
903 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
904 | { | |
905 | struct intel_encoder *encoder = intel_get_lvds_encoder(dev); | |
13c7d870 | 906 | |
97a824e1 | 907 | return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; |
13c7d870 DV |
908 | } |
909 | ||
7dec0606 | 910 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 911 | { |
7dec0606 | 912 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 | 913 | unsigned int val; |
fac5e23e | 914 | struct drm_i915_private *dev_priv = to_i915(dev); |
1974cad0 DV |
915 | |
916 | /* use the module option value if specified */ | |
d330a953 JN |
917 | if (i915.lvds_channel_mode > 0) |
918 | return i915.lvds_channel_mode == 2; | |
1974cad0 | 919 | |
6f317cfe LW |
920 | /* single channel LVDS is limited to 112 MHz */ |
921 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
922 | > 112999) | |
923 | return true; | |
924 | ||
1974cad0 DV |
925 | if (dmi_check_system(intel_dual_link_lvds)) |
926 | return true; | |
927 | ||
13c7d870 DV |
928 | /* BIOS should set the proper LVDS register value at boot, but |
929 | * in reality, it doesn't set the value when the lid is closed; | |
930 | * we need to check "the value to be set" in VBT when LVDS | |
931 | * register is uninitialized. | |
932 | */ | |
7dec0606 | 933 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 934 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 935 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 936 | |
1974cad0 DV |
937 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
938 | } | |
939 | ||
f3cfcba6 CW |
940 | static bool intel_lvds_supported(struct drm_device *dev) |
941 | { | |
942 | /* With the introduction of the PCH we gained a dedicated | |
943 | * LVDS presence pin, use it. */ | |
311e359c | 944 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
945 | return true; |
946 | ||
947 | /* Otherwise LVDS was only attached to mobile products, | |
948 | * except for the inglorious 830gm */ | |
311e359c PZ |
949 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
950 | return true; | |
951 | ||
952 | return false; | |
f3cfcba6 CW |
953 | } |
954 | ||
79e53945 JB |
955 | /** |
956 | * intel_lvds_init - setup LVDS connectors on this device | |
957 | * @dev: drm device | |
958 | * | |
959 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
960 | * modes we can display on the LVDS panel (if present). | |
961 | */ | |
c9093354 | 962 | void intel_lvds_init(struct drm_device *dev) |
79e53945 | 963 | { |
fac5e23e | 964 | struct drm_i915_private *dev_priv = to_i915(dev); |
29b99b48 | 965 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 966 | struct intel_encoder *intel_encoder; |
c7362c4d | 967 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 968 | struct intel_connector *intel_connector; |
79e53945 JB |
969 | struct drm_connector *connector; |
970 | struct drm_encoder *encoder; | |
971 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 972 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 973 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 974 | struct edid *edid; |
79e53945 | 975 | struct drm_crtc *crtc; |
f0f59a00 | 976 | i915_reg_t lvds_reg; |
79e53945 | 977 | u32 lvds; |
270eea0f CW |
978 | int pipe; |
979 | u8 pin; | |
79e53945 | 980 | |
f3cfcba6 | 981 | if (!intel_lvds_supported(dev)) |
c9093354 | 982 | return; |
f3cfcba6 | 983 | |
425d244c JW |
984 | /* Skip init on machines we know falsely report LVDS */ |
985 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 986 | return; |
565dcd46 | 987 | |
d0669d00 VS |
988 | if (HAS_PCH_SPLIT(dev)) |
989 | lvds_reg = PCH_LVDS; | |
990 | else | |
991 | lvds_reg = LVDS; | |
992 | ||
993 | lvds = I915_READ(lvds_reg); | |
994 | ||
c619eed4 | 995 | if (HAS_PCH_SPLIT(dev)) { |
d0669d00 | 996 | if ((lvds & LVDS_DETECTED) == 0) |
c9093354 | 997 | return; |
6aa23e65 | 998 | if (dev_priv->vbt.edp.support) { |
28c97730 | 999 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 1000 | return; |
32f9d658 | 1001 | } |
541998a1 ZW |
1002 | } |
1003 | ||
eebaed64 | 1004 | pin = GMBUS_PIN_PANEL; |
5a69d13d | 1005 | if (!intel_bios_is_lvds_present(dev_priv, &pin)) { |
d0669d00 | 1006 | if ((lvds & LVDS_PORT_EN) == 0) { |
eebaed64 CW |
1007 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
1008 | return; | |
1009 | } | |
1010 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); | |
1011 | } | |
1012 | ||
b14c5679 | 1013 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 1014 | if (!lvds_encoder) |
c9093354 | 1015 | return; |
79e53945 | 1016 | |
b14c5679 | 1017 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 1018 | if (!lvds_connector) { |
29b99b48 | 1019 | kfree(lvds_encoder); |
c9093354 | 1020 | return; |
bb8a3560 ZW |
1021 | } |
1022 | ||
9bdbd0b9 ACO |
1023 | if (intel_connector_init(&lvds_connector->base) < 0) { |
1024 | kfree(lvds_connector); | |
1025 | kfree(lvds_encoder); | |
1026 | return; | |
1027 | } | |
1028 | ||
62165e0d JN |
1029 | lvds_encoder->attached_connector = lvds_connector; |
1030 | ||
29b99b48 | 1031 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1032 | encoder = &intel_encoder->base; |
c7362c4d | 1033 | intel_connector = &lvds_connector->base; |
ea5b213a | 1034 | connector = &intel_connector->base; |
bb8a3560 | 1035 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1036 | DRM_MODE_CONNECTOR_LVDS); |
1037 | ||
4ef69c7a | 1038 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
580d8ed5 | 1039 | DRM_MODE_ENCODER_LVDS, "LVDS"); |
79e53945 | 1040 | |
c22834ec | 1041 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 1042 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 1043 | intel_encoder->compute_config = intel_lvds_compute_config; |
d26a5b6e VS |
1044 | if (HAS_PCH_SPLIT(dev_priv)) { |
1045 | intel_encoder->disable = pch_disable_lvds; | |
1046 | intel_encoder->post_disable = pch_post_disable_lvds; | |
1047 | } else { | |
1048 | intel_encoder->disable = gmch_disable_lvds; | |
1049 | } | |
b1dc332c | 1050 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 1051 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 1052 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
c22834ec | 1053 | |
df0e9248 | 1054 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1055 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1056 | |
bc079e8b | 1057 | intel_encoder->cloneable = 0; |
27f8227b JB |
1058 | if (HAS_PCH_SPLIT(dev)) |
1059 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1060 | else if (IS_GEN4(dev)) |
1061 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1062 | else |
1063 | intel_encoder->crtc_mask = (1 << 1); | |
1064 | ||
79e53945 JB |
1065 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1066 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1067 | connector->interlace_allowed = false; | |
1068 | connector->doublescan_allowed = false; | |
1069 | ||
d0669d00 | 1070 | lvds_encoder->reg = lvds_reg; |
7dec0606 | 1071 | |
3fbe18d6 ZY |
1072 | /* create the scaling mode property */ |
1073 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1074 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1075 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1076 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1077 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
ed6143b8 ID |
1078 | |
1079 | intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); | |
1080 | lvds_encoder->init_lvds_val = lvds; | |
1081 | ||
79e53945 JB |
1082 | /* |
1083 | * LVDS discovery: | |
1084 | * 1) check for EDID on DDC | |
1085 | * 2) check for VBT data | |
1086 | * 3) check to see if LVDS is already on | |
1087 | * if none of the above, no panel | |
1088 | * 4) make sure lid is open | |
1089 | * if closed, act like it's not there for now | |
1090 | */ | |
1091 | ||
79e53945 JB |
1092 | /* |
1093 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1094 | * preferred mode is the right one. | |
1095 | */ | |
4da98541 | 1096 | mutex_lock(&dev->mode_config.mutex); |
4eddaeec LW |
1097 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) |
1098 | edid = drm_get_edid_switcheroo(connector, | |
1099 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1100 | else | |
1101 | edid = drm_get_edid(connector, | |
1102 | intel_gmbus_get_adapter(dev_priv, pin)); | |
9cd300e0 JN |
1103 | if (edid) { |
1104 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1105 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1106 | edid); |
3f8ff0e7 | 1107 | } else { |
9cd300e0 JN |
1108 | kfree(edid); |
1109 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1110 | } |
9cd300e0 JN |
1111 | } else { |
1112 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1113 | } |
9cd300e0 JN |
1114 | lvds_connector->base.edid = edid; |
1115 | ||
1116 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1117 | /* Didn't get an EDID, so |
1118 | * Set wide sync ranges so we get all modes | |
1119 | * handed to valid_mode for checking | |
1120 | */ | |
1121 | connector->display_info.min_vfreq = 0; | |
1122 | connector->display_info.max_vfreq = 200; | |
1123 | connector->display_info.min_hfreq = 0; | |
1124 | connector->display_info.max_hfreq = 200; | |
1125 | } | |
79e53945 JB |
1126 | |
1127 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1128 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1129 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1130 | drm_mode_debug_printmodeline(scan); | |
1131 | ||
dd06f90e | 1132 | fixed_mode = drm_mode_duplicate(dev, scan); |
c329a4ec | 1133 | if (fixed_mode) |
6a9d51b7 | 1134 | goto out; |
79e53945 | 1135 | } |
79e53945 JB |
1136 | } |
1137 | ||
1138 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1139 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1140 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1141 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1142 | |
41aa3448 | 1143 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1144 | if (fixed_mode) { |
1145 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
df457245 VS |
1146 | connector->display_info.width_mm = fixed_mode->width_mm; |
1147 | connector->display_info.height_mm = fixed_mode->height_mm; | |
e285f3cd JB |
1148 | goto out; |
1149 | } | |
79e53945 JB |
1150 | } |
1151 | ||
1152 | /* | |
1153 | * If we didn't get EDID, try checking if the panel is already turned | |
1154 | * on. If so, assume that whatever is currently programmed is the | |
1155 | * correct mode. | |
1156 | */ | |
541998a1 | 1157 | |
f2b115e6 | 1158 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1159 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1160 | goto failed; |
1161 | ||
79e53945 | 1162 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
f875c15a | 1163 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1164 | |
1165 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1166 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1167 | if (fixed_mode) { | |
6a9d51b7 CW |
1168 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1169 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1170 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1171 | goto out; |
79e53945 JB |
1172 | } |
1173 | } | |
1174 | ||
1175 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1176 | if (!fixed_mode) |
79e53945 JB |
1177 | goto failed; |
1178 | ||
79e53945 | 1179 | out: |
4da98541 DV |
1180 | mutex_unlock(&dev->mode_config.mutex); |
1181 | ||
6f317cfe | 1182 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
fda9ee98 | 1183 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
6f317cfe | 1184 | |
7dec0606 | 1185 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1186 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1187 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1188 | ||
af9b9c19 | 1189 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
1f835a77 | 1190 | |
db1740a0 JN |
1191 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1192 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1193 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1194 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1195 | } |
aaa6fd2a | 1196 | |
c9093354 | 1197 | return; |
79e53945 JB |
1198 | |
1199 | failed: | |
4da98541 DV |
1200 | mutex_unlock(&dev->mode_config.mutex); |
1201 | ||
8a4c47f3 | 1202 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1203 | drm_connector_cleanup(connector); |
1991bdfa | 1204 | drm_encoder_cleanup(encoder); |
29b99b48 | 1205 | kfree(lvds_encoder); |
c7362c4d | 1206 | kfree(lvds_connector); |
c9093354 | 1207 | return; |
79e53945 | 1208 | } |