drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
045ac3b5
JB
89static void intel_lvds_get_config(struct intel_encoder *encoder,
90 struct intel_crtc_config *pipe_config)
91{
92 struct drm_device *dev = encoder->base.dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 u32 lvds_reg, tmp, flags = 0;
95
96 if (HAS_PCH_SPLIT(dev))
97 lvds_reg = PCH_LVDS;
98 else
99 lvds_reg = LVDS;
100
101 tmp = I915_READ(lvds_reg);
102 if (tmp & LVDS_HSYNC_POLARITY)
103 flags |= DRM_MODE_FLAG_NHSYNC;
104 else
105 flags |= DRM_MODE_FLAG_PHSYNC;
106 if (tmp & LVDS_VSYNC_POLARITY)
107 flags |= DRM_MODE_FLAG_NVSYNC;
108 else
109 flags |= DRM_MODE_FLAG_PVSYNC;
110
111 pipe_config->adjusted_mode.flags |= flags;
06922821
DV
112
113 /* gen2/3 store dither state in pfit control, needs to match */
114 if (INTEL_INFO(dev)->gen < 4) {
115 tmp = I915_READ(PFIT_CONTROL);
116
117 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
118 }
045ac3b5
JB
119}
120
fc683091
DV
121/* The LVDS pin pair needs to be on before the DPLLs are enabled.
122 * This is an exception to the general rule that mode_set doesn't turn
123 * things on.
124 */
f6736a1a 125static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
126{
127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
128 struct drm_device *dev = encoder->base.dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 130 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4c6df4b4
VS
131 const struct drm_display_mode *adjusted_mode =
132 &crtc->config.adjusted_mode;
55607e8a 133 int pipe = crtc->pipe;
fc683091
DV
134 u32 temp;
135
55607e8a
DV
136 if (HAS_PCH_SPLIT(dev)) {
137 assert_fdi_rx_pll_disabled(dev_priv, pipe);
138 assert_shared_dpll_disabled(dev_priv,
139 intel_crtc_to_shared_dpll(crtc));
140 } else {
141 assert_pll_disabled(dev_priv, pipe);
142 }
143
fc683091
DV
144 temp = I915_READ(lvds_encoder->reg);
145 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
146
147 if (HAS_PCH_CPT(dev)) {
148 temp &= ~PORT_TRANS_SEL_MASK;
149 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 150 } else {
62810e5a
DV
151 if (pipe == 1) {
152 temp |= LVDS_PIPEB_SELECT;
153 } else {
154 temp &= ~LVDS_PIPEB_SELECT;
155 }
fc683091 156 }
62810e5a 157
fc683091 158 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 159 temp &= ~LVDS_BORDER_ENABLE;
55607e8a 160 temp |= crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
161 /* Set the B0-B3 data pairs corresponding to whether we're going to
162 * set the DPLLs for dual-channel mode or not.
163 */
164 if (lvds_encoder->is_dual_link)
165 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
166 else
167 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
168
169 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
170 * appropriately here, but we need to look more thoroughly into how
171 * panels behave in the two modes.
172 */
62810e5a
DV
173
174 /* Set the dithering flag on LVDS as needed, note that there is no
175 * special lvds dither control bit on pch-split platforms, dithering is
176 * only controlled through the PIPECONF reg. */
177 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
178 /* Bspec wording suggests that LVDS port dithering only exists
179 * for 18bpp panels. */
55607e8a 180 if (crtc->config.dither && crtc->config.pipe_bpp == 18)
fc683091
DV
181 temp |= LVDS_ENABLE_DITHER;
182 else
183 temp &= ~LVDS_ENABLE_DITHER;
184 }
185 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 186 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 187 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 188 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
189 temp |= LVDS_VSYNC_POLARITY;
190
191 I915_WRITE(lvds_encoder->reg, temp);
192}
193
79e53945
JB
194/**
195 * Sets the power state for the panel.
196 */
c22834ec 197static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 198{
c22834ec 199 struct drm_device *dev = encoder->base.dev;
29b99b48 200 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 201 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 202 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 203 u32 ctl_reg, stat_reg;
541998a1 204
c619eed4 205 if (HAS_PCH_SPLIT(dev)) {
541998a1 206 ctl_reg = PCH_PP_CONTROL;
de842eff 207 stat_reg = PCH_PP_STATUS;
541998a1
ZW
208 } else {
209 ctl_reg = PP_CONTROL;
de842eff 210 stat_reg = PP_STATUS;
541998a1 211 }
79e53945 212
7dec0606 213 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 214
2a1292fd 215 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 216 POSTING_READ(lvds_encoder->reg);
de842eff
KP
217 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
218 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 219
24ded204 220 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
221}
222
c22834ec 223static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 224{
c22834ec 225 struct drm_device *dev = encoder->base.dev;
29b99b48 226 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 227 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 228 u32 ctl_reg, stat_reg;
2a1292fd
CW
229
230 if (HAS_PCH_SPLIT(dev)) {
231 ctl_reg = PCH_PP_CONTROL;
de842eff 232 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
233 } else {
234 ctl_reg = PP_CONTROL;
de842eff 235 stat_reg = PP_STATUS;
2a1292fd
CW
236 }
237
47356eb6 238 intel_panel_disable_backlight(dev);
2a1292fd
CW
239
240 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
241 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
242 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 243
7dec0606
DV
244 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
245 POSTING_READ(lvds_encoder->reg);
79e53945
JB
246}
247
79e53945
JB
248static int intel_lvds_mode_valid(struct drm_connector *connector,
249 struct drm_display_mode *mode)
250{
dd06f90e
JN
251 struct intel_connector *intel_connector = to_intel_connector(connector);
252 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 253
788319d4
CW
254 if (mode->hdisplay > fixed_mode->hdisplay)
255 return MODE_PANEL;
256 if (mode->vdisplay > fixed_mode->vdisplay)
257 return MODE_PANEL;
79e53945
JB
258
259 return MODE_OK;
260}
261
7ae89233
DV
262static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
263 struct intel_crtc_config *pipe_config)
79e53945 264{
7ae89233 265 struct drm_device *dev = intel_encoder->base.dev;
79e53945 266 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
267 struct intel_lvds_encoder *lvds_encoder =
268 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
269 struct intel_connector *intel_connector =
270 &lvds_encoder->attached_connector->base;
7ae89233 271 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 272 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 273 unsigned int lvds_bpp;
79e53945
JB
274
275 /* Should never happen!! */
a6c45cf0 276 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 277 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
278 return false;
279 }
280
4e53c2e0
DV
281 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
282 LVDS_A3_POWER_UP)
283 lvds_bpp = 8*3;
284 else
285 lvds_bpp = 6*3;
286
e29c22c0 287 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
288 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
289 pipe_config->pipe_bpp, lvds_bpp);
290 pipe_config->pipe_bpp = lvds_bpp;
291 }
d8b32247 292
79e53945 293 /*
71677043 294 * We have timings from the BIOS for the panel, put them in
79e53945
JB
295 * to the adjusted mode. The CRTC will be set up for this mode,
296 * with the panel scaling set up to source from the H/VDisplay
297 * of the original mode.
298 */
4d891523 299 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 300 adjusted_mode);
1d8e1c75
CW
301
302 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
303 pipe_config->has_pch_encoder = true;
304
b074cec8
JB
305 intel_pch_panel_fitting(intel_crtc, pipe_config,
306 intel_connector->panel.fitting_mode);
2dd24552
JB
307 } else {
308 intel_gmch_panel_fitting(intel_crtc, pipe_config,
309 intel_connector->panel.fitting_mode);
79e53945 310
21d8a475 311 }
f9bef081 312
79e53945
JB
313 /*
314 * XXX: It would be nice to support lower refresh rates on the
315 * panels to reduce power consumption, and perhaps match the
316 * user's requested refresh rate.
317 */
318
319 return true;
320}
321
66df24d9 322static void intel_lvds_mode_set(struct intel_encoder *encoder)
79e53945 323{
79e53945 324 /*
66df24d9
DV
325 * We don't do anything here, the LVDS port is fully set up in the pre
326 * enable hook - the ordering constraints for enabling the lvds port vs.
327 * enabling the display pll are too strict.
79e53945 328 */
79e53945
JB
329}
330
331/**
332 * Detect the LVDS connection.
333 *
b42d4c5c
JB
334 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
335 * connected and closed means disconnected. We also send hotplug events as
336 * needed, using lid status notification from the input layer.
79e53945 337 */
7b334fcb 338static enum drm_connector_status
930a9e28 339intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 340{
7b9c5abe 341 struct drm_device *dev = connector->dev;
6ee3b5a1 342 enum drm_connector_status status;
b42d4c5c 343
164c8598
CW
344 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
345 connector->base.id, drm_get_connector_name(connector));
346
fe16d949
CW
347 status = intel_panel_detect(dev);
348 if (status != connector_status_unknown)
349 return status;
01fe9dbd 350
6ee3b5a1 351 return connector_status_connected;
79e53945
JB
352}
353
354/**
355 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
356 */
357static int intel_lvds_get_modes(struct drm_connector *connector)
358{
62165e0d 359 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 360 struct drm_device *dev = connector->dev;
788319d4 361 struct drm_display_mode *mode;
79e53945 362
9cd300e0 363 /* use cached edid if we have one */
2aa4f099 364 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 365 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 366
dd06f90e 367 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 368 if (mode == NULL)
788319d4 369 return 0;
79e53945 370
788319d4
CW
371 drm_mode_probed_add(connector, mode);
372 return 1;
79e53945
JB
373}
374
0544edfd
TB
375static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
376{
bc0daf48 377 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
378 return 1;
379}
380
381/* The GPU hangs up on these systems if modeset is performed on LID open */
382static const struct dmi_system_id intel_no_modeset_on_lid[] = {
383 {
384 .callback = intel_no_modeset_on_lid_dmi_callback,
385 .ident = "Toshiba Tecra A11",
386 .matches = {
387 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
388 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
389 },
390 },
391
392 { } /* terminating entry */
393};
394
c9354c85 395/*
b8efb17b
ZR
396 * Lid events. Note the use of 'modeset':
397 * - we set it to MODESET_ON_LID_OPEN on lid close,
398 * and set it to MODESET_DONE on open
c9354c85 399 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
400 * duplicate events where it was already properly set)
401 * - the suspend/resume paths will set it to
402 * MODESET_SUSPENDED and ignore the lid open event,
403 * because they restore the mode ("lid open").
c9354c85 404 */
c1c7af60
JB
405static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
406 void *unused)
407{
db1740a0
JN
408 struct intel_lvds_connector *lvds_connector =
409 container_of(nb, struct intel_lvds_connector, lid_notifier);
410 struct drm_connector *connector = &lvds_connector->base.base;
411 struct drm_device *dev = connector->dev;
412 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 413
2fb4e61d
AW
414 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
415 return NOTIFY_OK;
416
b8efb17b
ZR
417 mutex_lock(&dev_priv->modeset_restore_lock);
418 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
419 goto exit;
a2565377
ZY
420 /*
421 * check and update the status of LVDS connector after receiving
422 * the LID nofication event.
423 */
db1740a0 424 connector->status = connector->funcs->detect(connector, false);
7b334fcb 425
0544edfd
TB
426 /* Don't force modeset on machines where it causes a GPU lockup */
427 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 428 goto exit;
c9354c85 429 if (!acpi_lid_open()) {
b8efb17b
ZR
430 /* do modeset on next lid open event */
431 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
432 goto exit;
06891e27 433 }
c1c7af60 434
b8efb17b
ZR
435 if (dev_priv->modeset_restore == MODESET_DONE)
436 goto exit;
c9354c85 437
a0e99e68 438 drm_modeset_lock_all(dev);
45e2b5f6 439 intel_modeset_setup_hw_state(dev, true);
a0e99e68 440 drm_modeset_unlock_all(dev);
06324194 441
b8efb17b
ZR
442 dev_priv->modeset_restore = MODESET_DONE;
443
444exit:
445 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
446 return NOTIFY_OK;
447}
448
79e53945
JB
449/**
450 * intel_lvds_destroy - unregister and free LVDS structures
451 * @connector: connector to free
452 *
453 * Unregister the DDC bus for this connector then free the driver private
454 * structure.
455 */
456static void intel_lvds_destroy(struct drm_connector *connector)
457{
db1740a0
JN
458 struct intel_lvds_connector *lvds_connector =
459 to_lvds_connector(connector);
79e53945 460
db1740a0
JN
461 if (lvds_connector->lid_notifier.notifier_call)
462 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 463
9cd300e0
JN
464 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
465 kfree(lvds_connector->base.edid);
466
1d508706 467 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 468
79e53945
JB
469 drm_sysfs_connector_remove(connector);
470 drm_connector_cleanup(connector);
471 kfree(connector);
472}
473
335041ed
JB
474static int intel_lvds_set_property(struct drm_connector *connector,
475 struct drm_property *property,
476 uint64_t value)
477{
4d891523 478 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 479 struct drm_device *dev = connector->dev;
3fbe18d6 480
788319d4 481 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 482 struct drm_crtc *crtc;
bb8a3560 483
53bd8389
JB
484 if (value == DRM_MODE_SCALE_NONE) {
485 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 486 return -EINVAL;
3fbe18d6 487 }
788319d4 488
4d891523 489 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
490 /* the LVDS scaling property is not changed */
491 return 0;
492 }
4d891523 493 intel_connector->panel.fitting_mode = value;
62165e0d
JN
494
495 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
496 if (crtc && crtc->enabled) {
497 /*
498 * If the CRTC is enabled, the display will be changed
499 * according to the new panel fitting mode.
500 */
c0c36b94 501 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
502 }
503 }
504
335041ed
JB
505 return 0;
506}
507
79e53945
JB
508static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
509 .get_modes = intel_lvds_get_modes,
510 .mode_valid = intel_lvds_mode_valid,
df0e9248 511 .best_encoder = intel_best_encoder,
79e53945
JB
512};
513
514static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 515 .dpms = intel_connector_dpms,
79e53945
JB
516 .detect = intel_lvds_detect,
517 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 518 .set_property = intel_lvds_set_property,
79e53945
JB
519 .destroy = intel_lvds_destroy,
520};
521
79e53945 522static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 523 .destroy = intel_encoder_destroy,
79e53945
JB
524};
525
425d244c
JW
526static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
527{
bc0daf48 528 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
529 return 1;
530}
79e53945 531
425d244c 532/* These systems claim to have LVDS, but really don't */
93c05f22 533static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
534 {
535 .callback = intel_no_lvds_dmi_callback,
536 .ident = "Apple Mac Mini (Core series)",
537 .matches = {
98acd46f 538 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
539 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
540 },
541 },
542 {
543 .callback = intel_no_lvds_dmi_callback,
544 .ident = "Apple Mac Mini (Core 2 series)",
545 .matches = {
98acd46f 546 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
547 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
548 },
549 },
550 {
551 .callback = intel_no_lvds_dmi_callback,
552 .ident = "MSI IM-945GSE-A",
553 .matches = {
554 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
555 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
556 },
557 },
558 {
559 .callback = intel_no_lvds_dmi_callback,
560 .ident = "Dell Studio Hybrid",
561 .matches = {
562 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
563 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
564 },
565 },
70aa96ca
JW
566 {
567 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
568 .ident = "Dell OptiPlex FX170",
569 .matches = {
570 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
571 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
572 },
573 },
574 {
575 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
576 .ident = "AOpen Mini PC",
577 .matches = {
578 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
579 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
580 },
581 },
ed8c754b
TV
582 {
583 .callback = intel_no_lvds_dmi_callback,
584 .ident = "AOpen Mini PC MP915",
585 .matches = {
586 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
587 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
588 },
589 },
22ab70d3
KP
590 {
591 .callback = intel_no_lvds_dmi_callback,
592 .ident = "AOpen i915GMm-HFS",
593 .matches = {
594 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
595 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
596 },
597 },
e57b6886
DV
598 {
599 .callback = intel_no_lvds_dmi_callback,
600 .ident = "AOpen i45GMx-I",
601 .matches = {
602 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
603 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
604 },
605 },
fa0864b2
MC
606 {
607 .callback = intel_no_lvds_dmi_callback,
608 .ident = "Aopen i945GTt-VFA",
609 .matches = {
610 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
611 },
612 },
9875557e
SB
613 {
614 .callback = intel_no_lvds_dmi_callback,
615 .ident = "Clientron U800",
616 .matches = {
617 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
618 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
619 },
620 },
6a574b5b 621 {
44306ab3
JS
622 .callback = intel_no_lvds_dmi_callback,
623 .ident = "Clientron E830",
624 .matches = {
625 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
626 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
627 },
628 },
629 {
6a574b5b
HG
630 .callback = intel_no_lvds_dmi_callback,
631 .ident = "Asus EeeBox PC EB1007",
632 .matches = {
633 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
634 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
635 },
636 },
0999bbe0
AJ
637 {
638 .callback = intel_no_lvds_dmi_callback,
639 .ident = "Asus AT5NM10T-I",
640 .matches = {
641 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
642 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
643 },
644 },
33471119
JBG
645 {
646 .callback = intel_no_lvds_dmi_callback,
45a211d7 647 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
648 .matches = {
649 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 650 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
651 },
652 },
f5b8a7ed
MG
653 {
654 .callback = intel_no_lvds_dmi_callback,
655 .ident = "Hewlett-Packard t5745",
656 .matches = {
657 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 658 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
659 },
660 },
661 {
662 .callback = intel_no_lvds_dmi_callback,
663 .ident = "Hewlett-Packard st5747",
664 .matches = {
665 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 666 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
667 },
668 },
97effadb
AA
669 {
670 .callback = intel_no_lvds_dmi_callback,
671 .ident = "MSI Wind Box DC500",
672 .matches = {
673 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
674 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
675 },
676 },
a51d4ed0
CW
677 {
678 .callback = intel_no_lvds_dmi_callback,
679 .ident = "Gigabyte GA-D525TUD",
680 .matches = {
681 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
682 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
683 },
684 },
c31407a3
CW
685 {
686 .callback = intel_no_lvds_dmi_callback,
687 .ident = "Supermicro X7SPA-H",
688 .matches = {
689 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
690 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
691 },
692 },
9e9dd0e8
CL
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "Fujitsu Esprimo Q900",
696 .matches = {
697 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
698 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
699 },
700 },
e5614f0c
CW
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Intel D510MO",
704 .matches = {
705 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
706 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
707 },
708 },
dcf6d294
JN
709 {
710 .callback = intel_no_lvds_dmi_callback,
711 .ident = "Intel D525MW",
712 .matches = {
713 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
714 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
715 },
716 },
425d244c
JW
717
718 { } /* terminating entry */
719};
79e53945 720
18f9ed12
ZY
721/**
722 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
723 * @dev: drm device
724 * @connector: LVDS connector
725 *
726 * Find the reduced downclock for LVDS in EDID.
727 */
728static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
729 struct drm_display_mode *fixed_mode,
730 struct drm_connector *connector)
18f9ed12
ZY
731{
732 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 733 struct drm_display_mode *scan;
18f9ed12
ZY
734 int temp_downclock;
735
788319d4 736 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
737 list_for_each_entry(scan, &connector->probed_modes, head) {
738 /*
739 * If one mode has the same resolution with the fixed_panel
740 * mode while they have the different refresh rate, it means
741 * that the reduced downclock is found for the LVDS. In such
742 * case we can set the different FPx0/1 to dynamically select
743 * between low and high frequency.
744 */
788319d4
CW
745 if (scan->hdisplay == fixed_mode->hdisplay &&
746 scan->hsync_start == fixed_mode->hsync_start &&
747 scan->hsync_end == fixed_mode->hsync_end &&
748 scan->htotal == fixed_mode->htotal &&
749 scan->vdisplay == fixed_mode->vdisplay &&
750 scan->vsync_start == fixed_mode->vsync_start &&
751 scan->vsync_end == fixed_mode->vsync_end &&
752 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
753 if (scan->clock < temp_downclock) {
754 /*
755 * The downclock is already found. But we
756 * expect to find the lower downclock.
757 */
758 temp_downclock = scan->clock;
759 }
760 }
761 }
788319d4 762 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
763 /* We found the downclock for LVDS. */
764 dev_priv->lvds_downclock_avail = 1;
765 dev_priv->lvds_downclock = temp_downclock;
766 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
767 "Normal clock %dKhz, downclock %dKhz\n",
768 fixed_mode->clock, temp_downclock);
18f9ed12 769 }
18f9ed12
ZY
770}
771
7cf4f69d
ZY
772/*
773 * Enumerate the child dev array parsed from VBT to check whether
774 * the LVDS is present.
775 * If it is present, return 1.
776 * If it is not present, return false.
777 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 778 */
270eea0f
CW
779static bool lvds_is_present_in_vbt(struct drm_device *dev,
780 u8 *i2c_pin)
7cf4f69d
ZY
781{
782 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 783 int i;
7cf4f69d 784
41aa3448 785 if (!dev_priv->vbt.child_dev_num)
425904dd 786 return true;
7cf4f69d 787
41aa3448
RV
788 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
789 struct child_device_config *child = dev_priv->vbt.child_dev + i;
425904dd
CW
790
791 /* If the device type is not LFP, continue.
792 * We have to check both the new identifiers as well as the
793 * old for compatibility with some BIOSes.
7cf4f69d 794 */
425904dd
CW
795 if (child->device_type != DEVICE_TYPE_INT_LFP &&
796 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
797 continue;
798
3bd7d909
DK
799 if (intel_gmbus_is_port_valid(child->i2c_pin))
800 *i2c_pin = child->i2c_pin;
270eea0f 801
425904dd
CW
802 /* However, we cannot trust the BIOS writers to populate
803 * the VBT correctly. Since LVDS requires additional
804 * information from AIM blocks, a non-zero addin offset is
805 * a good indicator that the LVDS is actually present.
7cf4f69d 806 */
425904dd
CW
807 if (child->addin_offset)
808 return true;
809
810 /* But even then some BIOS writers perform some black magic
811 * and instantiate the device without reference to any
812 * additional data. Trust that if the VBT was written into
813 * the OpRegion then they have validated the LVDS's existence.
814 */
815 if (dev_priv->opregion.vbt)
816 return true;
7cf4f69d 817 }
425904dd
CW
818
819 return false;
7cf4f69d
ZY
820}
821
1974cad0
DV
822static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
823{
824 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
825 return 1;
826}
827
828static const struct dmi_system_id intel_dual_link_lvds[] = {
829 {
830 .callback = intel_dual_link_lvds_callback,
831 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
832 .matches = {
833 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
834 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
835 },
836 },
837 { } /* terminating entry */
838};
839
840bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
841{
842 struct intel_encoder *encoder;
843 struct intel_lvds_encoder *lvds_encoder;
844
845 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
846 base.head) {
847 if (encoder->type == INTEL_OUTPUT_LVDS) {
848 lvds_encoder = to_lvds_encoder(&encoder->base);
849
850 return lvds_encoder->is_dual_link;
851 }
852 }
853
854 return false;
855}
856
7dec0606 857static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 858{
7dec0606 859 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
860 unsigned int val;
861 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
862
863 /* use the module option value if specified */
864 if (i915_lvds_channel_mode > 0)
865 return i915_lvds_channel_mode == 2;
866
867 if (dmi_check_system(intel_dual_link_lvds))
868 return true;
869
13c7d870
DV
870 /* BIOS should set the proper LVDS register value at boot, but
871 * in reality, it doesn't set the value when the lid is closed;
872 * we need to check "the value to be set" in VBT when LVDS
873 * register is uninitialized.
874 */
7dec0606 875 val = I915_READ(lvds_encoder->reg);
13c7d870 876 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 877 val = dev_priv->vbt.bios_lvds_val;
13c7d870 878
1974cad0
DV
879 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
880}
881
f3cfcba6
CW
882static bool intel_lvds_supported(struct drm_device *dev)
883{
884 /* With the introduction of the PCH we gained a dedicated
885 * LVDS presence pin, use it. */
311e359c 886 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
887 return true;
888
889 /* Otherwise LVDS was only attached to mobile products,
890 * except for the inglorious 830gm */
311e359c
PZ
891 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
892 return true;
893
894 return false;
f3cfcba6
CW
895}
896
79e53945
JB
897/**
898 * intel_lvds_init - setup LVDS connectors on this device
899 * @dev: drm device
900 *
901 * Create the connector, register the LVDS DDC bus, and try to figure out what
902 * modes we can display on the LVDS panel (if present).
903 */
c9093354 904void intel_lvds_init(struct drm_device *dev)
79e53945
JB
905{
906 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 907 struct intel_lvds_encoder *lvds_encoder;
21d40d37 908 struct intel_encoder *intel_encoder;
c7362c4d 909 struct intel_lvds_connector *lvds_connector;
bb8a3560 910 struct intel_connector *intel_connector;
79e53945
JB
911 struct drm_connector *connector;
912 struct drm_encoder *encoder;
913 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 914 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 915 struct edid *edid;
79e53945
JB
916 struct drm_crtc *crtc;
917 u32 lvds;
270eea0f
CW
918 int pipe;
919 u8 pin;
79e53945 920
f3cfcba6 921 if (!intel_lvds_supported(dev))
c9093354 922 return;
f3cfcba6 923
425d244c
JW
924 /* Skip init on machines we know falsely report LVDS */
925 if (dmi_check_system(intel_no_lvds))
c9093354 926 return;
565dcd46 927
270eea0f
CW
928 pin = GMBUS_PORT_PANEL;
929 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 930 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c9093354 931 return;
38b3037e 932 }
e99da35f 933
c619eed4 934 if (HAS_PCH_SPLIT(dev)) {
541998a1 935 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 936 return;
41aa3448 937 if (dev_priv->vbt.edp_support) {
28c97730 938 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 939 return;
32f9d658 940 }
541998a1
ZW
941 }
942
29b99b48
JN
943 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
944 if (!lvds_encoder)
c9093354 945 return;
79e53945 946
c7362c4d
JN
947 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
948 if (!lvds_connector) {
29b99b48 949 kfree(lvds_encoder);
c9093354 950 return;
bb8a3560
ZW
951 }
952
62165e0d
JN
953 lvds_encoder->attached_connector = lvds_connector;
954
29b99b48 955 intel_encoder = &lvds_encoder->base;
4ef69c7a 956 encoder = &intel_encoder->base;
c7362c4d 957 intel_connector = &lvds_connector->base;
ea5b213a 958 connector = &intel_connector->base;
bb8a3560 959 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
960 DRM_MODE_CONNECTOR_LVDS);
961
4ef69c7a 962 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
963 DRM_MODE_ENCODER_LVDS);
964
c22834ec 965 intel_encoder->enable = intel_enable_lvds;
f6736a1a 966 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 967 intel_encoder->compute_config = intel_lvds_compute_config;
66df24d9 968 intel_encoder->mode_set = intel_lvds_mode_set;
c22834ec 969 intel_encoder->disable = intel_disable_lvds;
b1dc332c 970 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 971 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 972 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 973
df0e9248 974 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 975 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 976
66a9278e 977 intel_encoder->cloneable = false;
27f8227b
JB
978 if (HAS_PCH_SPLIT(dev))
979 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
980 else if (IS_GEN4(dev))
981 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
982 else
983 intel_encoder->crtc_mask = (1 << 1);
984
79e53945
JB
985 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
986 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
987 connector->interlace_allowed = false;
988 connector->doublescan_allowed = false;
989
7dec0606
DV
990 if (HAS_PCH_SPLIT(dev)) {
991 lvds_encoder->reg = PCH_LVDS;
992 } else {
993 lvds_encoder->reg = LVDS;
994 }
995
3fbe18d6
ZY
996 /* create the scaling mode property */
997 drm_mode_create_scaling_mode_property(dev);
662595df 998 drm_object_attach_property(&connector->base,
3fbe18d6 999 dev->mode_config.scaling_mode_property,
dd1ea37d 1000 DRM_MODE_SCALE_ASPECT);
4d891523 1001 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1002 /*
1003 * LVDS discovery:
1004 * 1) check for EDID on DDC
1005 * 2) check for VBT data
1006 * 3) check to see if LVDS is already on
1007 * if none of the above, no panel
1008 * 4) make sure lid is open
1009 * if closed, act like it's not there for now
1010 */
1011
79e53945
JB
1012 /*
1013 * Attempt to get the fixed panel mode from DDC. Assume that the
1014 * preferred mode is the right one.
1015 */
9cd300e0
JN
1016 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1017 if (edid) {
1018 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1019 drm_mode_connector_update_edid_property(connector,
9cd300e0 1020 edid);
3f8ff0e7 1021 } else {
9cd300e0
JN
1022 kfree(edid);
1023 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1024 }
9cd300e0
JN
1025 } else {
1026 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1027 }
9cd300e0
JN
1028 lvds_connector->base.edid = edid;
1029
1030 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1031 /* Didn't get an EDID, so
1032 * Set wide sync ranges so we get all modes
1033 * handed to valid_mode for checking
1034 */
1035 connector->display_info.min_vfreq = 0;
1036 connector->display_info.max_vfreq = 200;
1037 connector->display_info.min_hfreq = 0;
1038 connector->display_info.max_hfreq = 200;
1039 }
79e53945
JB
1040
1041 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1042 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1043 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1044 drm_mode_debug_printmodeline(scan);
1045
dd06f90e 1046 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1047 if (fixed_mode) {
1048 intel_find_lvds_downclock(dev, fixed_mode,
1049 connector);
1050 goto out;
1051 }
79e53945 1052 }
79e53945
JB
1053 }
1054
1055 /* Failed to get EDID, what about VBT? */
41aa3448 1056 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1057 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1058 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1059
41aa3448 1060 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1061 if (fixed_mode) {
1062 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1063 goto out;
1064 }
79e53945
JB
1065 }
1066
1067 /*
1068 * If we didn't get EDID, try checking if the panel is already turned
1069 * on. If so, assume that whatever is currently programmed is the
1070 * correct mode.
1071 */
541998a1 1072
f2b115e6 1073 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1074 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1075 goto failed;
1076
79e53945
JB
1077 lvds = I915_READ(LVDS);
1078 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1079 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1080
1081 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1082 fixed_mode = intel_crtc_mode_get(dev, crtc);
1083 if (fixed_mode) {
6a9d51b7
CW
1084 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1085 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1086 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1087 goto out;
79e53945
JB
1088 }
1089 }
1090
1091 /* If we still don't have a mode after all that, give up. */
dd06f90e 1092 if (!fixed_mode)
79e53945
JB
1093 goto failed;
1094
79e53945 1095out:
7dec0606 1096 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1097 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1098 lvds_encoder->is_dual_link ? "dual" : "single");
1099
24ded204
DV
1100 /*
1101 * Unlock registers and just
1102 * leave them unlocked
1103 */
c619eed4 1104 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1105 I915_WRITE(PCH_PP_CONTROL,
1106 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1107 } else {
ed10fca9
KP
1108 I915_WRITE(PP_CONTROL,
1109 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1110 }
db1740a0
JN
1111 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1112 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1113 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1114 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1115 }
79e53945 1116 drm_sysfs_connector_add(connector);
aaa6fd2a 1117
dd06f90e 1118 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1119 intel_panel_setup_backlight(connector);
aaa6fd2a 1120
c9093354 1121 return;
79e53945
JB
1122
1123failed:
8a4c47f3 1124 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1125 drm_connector_cleanup(connector);
1991bdfa 1126 drm_encoder_cleanup(encoder);
dd06f90e
JN
1127 if (fixed_mode)
1128 drm_mode_destroy(dev, fixed_mode);
29b99b48 1129 kfree(lvds_encoder);
c7362c4d 1130 kfree(lvds_connector);
c9093354 1131 return;
79e53945 1132}
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