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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
788319d4 | 46 | |
219adae1 | 47 | struct edid *edid; |
788319d4 | 48 | |
3fbe18d6 ZY |
49 | int fitting_mode; |
50 | u32 pfit_control; | |
51 | u32 pfit_pgm_ratios; | |
e9e331a8 | 52 | bool pfit_dirty; |
788319d4 CW |
53 | |
54 | struct drm_display_mode *fixed_mode; | |
3fbe18d6 ZY |
55 | }; |
56 | ||
788319d4 | 57 | static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
60 | } |
61 | ||
788319d4 CW |
62 | static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_lvds, base); | |
66 | } | |
67 | ||
79e53945 JB |
68 | /** |
69 | * Sets the power state for the panel. | |
70 | */ | |
e9e331a8 | 71 | static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on) |
79e53945 | 72 | { |
e9e331a8 | 73 | struct drm_device *dev = intel_lvds->base.base.dev; |
79e53945 | 74 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9e331a8 | 75 | u32 ctl_reg, lvds_reg; |
541998a1 | 76 | |
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 78 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 79 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
80 | } else { |
81 | ctl_reg = PP_CONTROL; | |
469d1296 | 82 | lvds_reg = LVDS; |
541998a1 | 83 | } |
79e53945 JB |
84 | |
85 | if (on) { | |
469d1296 | 86 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
77d07fd9 | 87 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
a9573556 | 88 | intel_panel_set_backlight(dev, dev_priv->backlight_level); |
79e53945 | 89 | } else { |
e9e331a8 CW |
90 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
91 | ||
a9573556 | 92 | intel_panel_set_backlight(dev, 0); |
77d07fd9 | 93 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
e9e331a8 CW |
94 | |
95 | if (intel_lvds->pfit_control) { | |
96 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) | |
97 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
98 | I915_WRITE(PFIT_CONTROL, 0); | |
99 | intel_lvds->pfit_control = 0; | |
100 | } | |
101 | ||
469d1296 | 102 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); |
79e53945 | 103 | } |
c9f9ccc1 | 104 | POSTING_READ(lvds_reg); |
79e53945 JB |
105 | } |
106 | ||
107 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
108 | { | |
788319d4 | 109 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
110 | |
111 | if (mode == DRM_MODE_DPMS_ON) | |
e9e331a8 | 112 | intel_lvds_set_power(intel_lvds, true); |
79e53945 | 113 | else |
e9e331a8 | 114 | intel_lvds_set_power(intel_lvds, false); |
79e53945 JB |
115 | |
116 | /* XXX: We never power down the LVDS pairs. */ | |
117 | } | |
118 | ||
79e53945 JB |
119 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
120 | struct drm_display_mode *mode) | |
121 | { | |
788319d4 CW |
122 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
123 | struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; | |
79e53945 | 124 | |
788319d4 CW |
125 | if (mode->hdisplay > fixed_mode->hdisplay) |
126 | return MODE_PANEL; | |
127 | if (mode->vdisplay > fixed_mode->vdisplay) | |
128 | return MODE_PANEL; | |
79e53945 JB |
129 | |
130 | return MODE_OK; | |
131 | } | |
132 | ||
49be663f CW |
133 | static void |
134 | centre_horizontally(struct drm_display_mode *mode, | |
135 | int width) | |
136 | { | |
137 | u32 border, sync_pos, blank_width, sync_width; | |
138 | ||
139 | /* keep the hsync and hblank widths constant */ | |
140 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
141 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
142 | sync_pos = (blank_width - sync_width + 1) / 2; | |
143 | ||
144 | border = (mode->hdisplay - width + 1) / 2; | |
145 | border += border & 1; /* make the border even */ | |
146 | ||
147 | mode->crtc_hdisplay = width; | |
148 | mode->crtc_hblank_start = width + border; | |
149 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
150 | ||
151 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
152 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
153 | } | |
154 | ||
155 | static void | |
156 | centre_vertically(struct drm_display_mode *mode, | |
157 | int height) | |
158 | { | |
159 | u32 border, sync_pos, blank_width, sync_width; | |
160 | ||
161 | /* keep the vsync and vblank widths constant */ | |
162 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
163 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
164 | sync_pos = (blank_width - sync_width + 1) / 2; | |
165 | ||
166 | border = (mode->vdisplay - height + 1) / 2; | |
167 | ||
168 | mode->crtc_vdisplay = height; | |
169 | mode->crtc_vblank_start = height + border; | |
170 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
171 | ||
172 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
173 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
174 | } | |
175 | ||
176 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
177 | { | |
178 | /* | |
179 | * Floating point operation is not supported. So the FACTOR | |
180 | * is defined, which can avoid the floating point computation | |
181 | * when calculating the panel ratio. | |
182 | */ | |
183 | #define ACCURACY 12 | |
184 | #define FACTOR (1 << ACCURACY) | |
185 | u32 ratio = source * FACTOR / target; | |
186 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
187 | } | |
188 | ||
79e53945 JB |
189 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
190 | struct drm_display_mode *mode, | |
191 | struct drm_display_mode *adjusted_mode) | |
192 | { | |
193 | struct drm_device *dev = encoder->dev; | |
194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
195 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
788319d4 | 196 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 197 | struct drm_encoder *tmp_encoder; |
49be663f | 198 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
79e53945 JB |
199 | |
200 | /* Should never happen!! */ | |
201 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
1ae8c0a5 | 202 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
203 | return false; |
204 | } | |
205 | ||
206 | /* Should never happen!! */ | |
207 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
208 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 209 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
210 | "encoder on the same pipe\n"); |
211 | return false; | |
212 | } | |
213 | } | |
1d8e1c75 | 214 | |
79e53945 | 215 | /* |
71677043 | 216 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
217 | * to the adjusted mode. The CRTC will be set up for this mode, |
218 | * with the panel scaling set up to source from the H/VDisplay | |
219 | * of the original mode. | |
220 | */ | |
788319d4 | 221 | intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); |
1d8e1c75 CW |
222 | |
223 | if (HAS_PCH_SPLIT(dev)) { | |
224 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
225 | mode, adjusted_mode); | |
226 | return true; | |
227 | } | |
79e53945 | 228 | |
3fbe18d6 ZY |
229 | /* Make sure pre-965s set dither correctly */ |
230 | if (!IS_I965G(dev)) { | |
231 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) | |
232 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
233 | } | |
234 | ||
235 | /* Native modes don't need fitting */ | |
236 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 237 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 238 | goto out; |
3fbe18d6 ZY |
239 | |
240 | /* 965+ wants fuzzy fitting */ | |
241 | if (IS_I965G(dev)) | |
49be663f CW |
242 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
243 | PFIT_FILTER_FUZZY); | |
244 | ||
3fbe18d6 ZY |
245 | /* |
246 | * Enable automatic panel scaling for non-native modes so that they fill | |
247 | * the screen. Should be enabled before the pipe is enabled, according | |
248 | * to register description and PRM. | |
249 | * Change the value here to see the borders for debugging | |
250 | */ | |
1d8e1c75 CW |
251 | I915_WRITE(BCLRPAT_A, 0); |
252 | I915_WRITE(BCLRPAT_B, 0); | |
3fbe18d6 | 253 | |
ea5b213a | 254 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 255 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
256 | /* |
257 | * For centered modes, we have to calculate border widths & | |
258 | * heights and modify the values programmed into the CRTC. | |
259 | */ | |
49be663f CW |
260 | centre_horizontally(adjusted_mode, mode->hdisplay); |
261 | centre_vertically(adjusted_mode, mode->vdisplay); | |
262 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 263 | break; |
49be663f | 264 | |
3fbe18d6 | 265 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 266 | /* Scale but preserve the aspect ratio */ |
3fbe18d6 | 267 | if (IS_I965G(dev)) { |
49be663f CW |
268 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
269 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
270 | ||
271 | pfit_control |= PFIT_ENABLE; | |
3fbe18d6 | 272 | /* 965+ is easy, it does everything in hw */ |
49be663f | 273 | if (scaled_width > scaled_height) |
3fbe18d6 | 274 | pfit_control |= PFIT_SCALING_PILLAR; |
49be663f | 275 | else if (scaled_width < scaled_height) |
3fbe18d6 ZY |
276 | pfit_control |= PFIT_SCALING_LETTER; |
277 | else | |
278 | pfit_control |= PFIT_SCALING_AUTO; | |
279 | } else { | |
49be663f CW |
280 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
281 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
282 | /* |
283 | * For earlier chips we have to calculate the scaling | |
284 | * ratio by hand and program it into the | |
285 | * PFIT_PGM_RATIO register | |
286 | */ | |
49be663f CW |
287 | if (scaled_width > scaled_height) { /* pillar */ |
288 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
289 | ||
290 | border = LVDS_BORDER_ENABLE; | |
291 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
292 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
293 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
294 | bits << PFIT_VERT_SCALE_SHIFT); | |
295 | pfit_control |= (PFIT_ENABLE | | |
296 | VERT_INTERP_BILINEAR | | |
297 | HORIZ_INTERP_BILINEAR); | |
298 | } | |
299 | } else if (scaled_width < scaled_height) { /* letter */ | |
300 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
301 | ||
302 | border = LVDS_BORDER_ENABLE; | |
303 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
304 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
305 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
306 | bits << PFIT_VERT_SCALE_SHIFT); | |
307 | pfit_control |= (PFIT_ENABLE | | |
308 | VERT_INTERP_BILINEAR | | |
309 | HORIZ_INTERP_BILINEAR); | |
310 | } | |
311 | } else | |
312 | /* Aspects match, Let hw scale both directions */ | |
313 | pfit_control |= (PFIT_ENABLE | | |
314 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
315 | VERT_INTERP_BILINEAR | |
316 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
317 | } |
318 | break; | |
319 | ||
320 | case DRM_MODE_SCALE_FULLSCREEN: | |
321 | /* | |
322 | * Full scaling, even if it changes the aspect ratio. | |
323 | * Fortunately this is all done for us in hw. | |
324 | */ | |
325 | pfit_control |= PFIT_ENABLE; | |
326 | if (IS_I965G(dev)) | |
327 | pfit_control |= PFIT_SCALING_AUTO; | |
328 | else | |
329 | pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
330 | VERT_INTERP_BILINEAR | | |
331 | HORIZ_INTERP_BILINEAR); | |
332 | break; | |
49be663f | 333 | |
3fbe18d6 ZY |
334 | default: |
335 | break; | |
336 | } | |
337 | ||
338 | out: | |
e9e331a8 CW |
339 | if (pfit_control != intel_lvds->pfit_control || |
340 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | |
341 | intel_lvds->pfit_control = pfit_control; | |
342 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
343 | intel_lvds->pfit_dirty = true; | |
344 | } | |
49be663f CW |
345 | dev_priv->lvds_border_bits = border; |
346 | ||
79e53945 JB |
347 | /* |
348 | * XXX: It would be nice to support lower refresh rates on the | |
349 | * panels to reduce power consumption, and perhaps match the | |
350 | * user's requested refresh rate. | |
351 | */ | |
352 | ||
353 | return true; | |
354 | } | |
355 | ||
356 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
357 | { | |
358 | struct drm_device *dev = encoder->dev; | |
359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 360 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 361 | |
a9573556 | 362 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
79e53945 | 363 | |
e9e331a8 CW |
364 | /* We try to do the minimum that is necessary in order to unlock |
365 | * the registers for mode setting. | |
366 | * | |
367 | * On Ironlake, this is quite simple as we just set the unlock key | |
368 | * and ignore all subtleties. (This may cause some issues...) | |
369 | * | |
370 | * Prior to Ironlake, we must disable the pipe if we want to adjust | |
371 | * the panel fitter. However at all other times we can just reset | |
372 | * the registers regardless. | |
373 | */ | |
374 | ||
375 | if (HAS_PCH_SPLIT(dev)) { | |
376 | I915_WRITE(PCH_PP_CONTROL, | |
377 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
378 | } else if (intel_lvds->pfit_dirty) { | |
379 | I915_WRITE(PP_CONTROL, | |
380 | I915_READ(PP_CONTROL) & ~POWER_TARGET_ON); | |
381 | I915_WRITE(LVDS, I915_READ(LVDS) & ~LVDS_PORT_EN); | |
382 | } else { | |
383 | I915_WRITE(PP_CONTROL, | |
384 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
385 | } | |
79e53945 JB |
386 | } |
387 | ||
e9e331a8 | 388 | static void intel_lvds_commit(struct drm_encoder *encoder) |
79e53945 JB |
389 | { |
390 | struct drm_device *dev = encoder->dev; | |
391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 392 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 393 | |
a9573556 CW |
394 | if (dev_priv->backlight_level == 0) |
395 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); | |
79e53945 | 396 | |
e9e331a8 CW |
397 | /* Undo any unlocking done in prepare to prevent accidental |
398 | * adjustment of the registers. | |
399 | */ | |
400 | if (HAS_PCH_SPLIT(dev)) { | |
401 | u32 val = I915_READ(PCH_PP_CONTROL); | |
402 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
403 | I915_WRITE(PCH_PP_CONTROL, val & 0x3); | |
404 | } else { | |
405 | u32 val = I915_READ(PP_CONTROL); | |
406 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
407 | I915_WRITE(PP_CONTROL, val & 0x3); | |
408 | } | |
409 | ||
410 | /* Always do a full power on as we do not know what state | |
411 | * we were left in. | |
412 | */ | |
413 | intel_lvds_set_power(intel_lvds, true); | |
79e53945 JB |
414 | } |
415 | ||
416 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
417 | struct drm_display_mode *mode, | |
418 | struct drm_display_mode *adjusted_mode) | |
419 | { | |
420 | struct drm_device *dev = encoder->dev; | |
421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 422 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
423 | |
424 | /* | |
425 | * The LVDS pin pair will already have been turned on in the | |
426 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
427 | * settings. | |
428 | */ | |
429 | ||
c619eed4 | 430 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
431 | return; |
432 | ||
e9e331a8 CW |
433 | if (!intel_lvds->pfit_dirty) |
434 | return; | |
435 | ||
79e53945 JB |
436 | /* |
437 | * Enable automatic panel scaling so that non-native modes fill the | |
438 | * screen. Should be enabled before the pipe is enabled, according to | |
439 | * register description and PRM. | |
440 | */ | |
e9e331a8 CW |
441 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) |
442 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
443 | ||
ea5b213a CW |
444 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); |
445 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
e9e331a8 | 446 | intel_lvds->pfit_dirty = false; |
79e53945 JB |
447 | } |
448 | ||
449 | /** | |
450 | * Detect the LVDS connection. | |
451 | * | |
b42d4c5c JB |
452 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
453 | * connected and closed means disconnected. We also send hotplug events as | |
454 | * needed, using lid status notification from the input layer. | |
79e53945 | 455 | */ |
7b334fcb | 456 | static enum drm_connector_status |
930a9e28 | 457 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 458 | { |
7b9c5abe | 459 | struct drm_device *dev = connector->dev; |
b42d4c5c JB |
460 | enum drm_connector_status status = connector_status_connected; |
461 | ||
7b9c5abe JB |
462 | /* ACPI lid methods were generally unreliable in this generation, so |
463 | * don't even bother. | |
464 | */ | |
6e6c8228 | 465 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
466 | return connector_status_connected; |
467 | ||
b42d4c5c | 468 | return status; |
79e53945 JB |
469 | } |
470 | ||
471 | /** | |
472 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
473 | */ | |
474 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
475 | { | |
788319d4 | 476 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
79e53945 | 477 | struct drm_device *dev = connector->dev; |
788319d4 | 478 | struct drm_display_mode *mode; |
79e53945 | 479 | |
219adae1 CW |
480 | if (intel_lvds->edid) { |
481 | drm_mode_connector_update_edid_property(connector, | |
482 | intel_lvds->edid); | |
483 | return drm_add_edid_modes(connector, intel_lvds->edid); | |
bfac4d67 | 484 | } |
79e53945 | 485 | |
788319d4 CW |
486 | mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); |
487 | if (mode == 0) | |
488 | return 0; | |
79e53945 | 489 | |
788319d4 CW |
490 | drm_mode_probed_add(connector, mode); |
491 | return 1; | |
79e53945 JB |
492 | } |
493 | ||
0544edfd TB |
494 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
495 | { | |
496 | DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); | |
497 | return 1; | |
498 | } | |
499 | ||
500 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
501 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
502 | { | |
503 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
504 | .ident = "Toshiba Tecra A11", | |
505 | .matches = { | |
506 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
507 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
508 | }, | |
509 | }, | |
510 | ||
511 | { } /* terminating entry */ | |
512 | }; | |
513 | ||
c9354c85 LT |
514 | /* |
515 | * Lid events. Note the use of 'modeset_on_lid': | |
516 | * - we set it on lid close, and reset it on open | |
517 | * - we use it as a "only once" bit (ie we ignore | |
518 | * duplicate events where it was already properly | |
519 | * set/reset) | |
520 | * - the suspend/resume paths will also set it to | |
521 | * zero, since they restore the mode ("lid open"). | |
522 | */ | |
c1c7af60 JB |
523 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
524 | void *unused) | |
525 | { | |
526 | struct drm_i915_private *dev_priv = | |
527 | container_of(nb, struct drm_i915_private, lid_notifier); | |
528 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 529 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 530 | |
a2565377 ZY |
531 | /* |
532 | * check and update the status of LVDS connector after receiving | |
533 | * the LID nofication event. | |
534 | */ | |
535 | if (connector) | |
7b334fcb | 536 | connector->status = connector->funcs->detect(connector, |
930a9e28 | 537 | false); |
7b334fcb | 538 | |
0544edfd TB |
539 | /* Don't force modeset on machines where it causes a GPU lockup */ |
540 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
541 | return NOTIFY_OK; | |
c9354c85 LT |
542 | if (!acpi_lid_open()) { |
543 | dev_priv->modeset_on_lid = 1; | |
544 | return NOTIFY_OK; | |
06891e27 | 545 | } |
c1c7af60 | 546 | |
c9354c85 LT |
547 | if (!dev_priv->modeset_on_lid) |
548 | return NOTIFY_OK; | |
549 | ||
550 | dev_priv->modeset_on_lid = 0; | |
551 | ||
552 | mutex_lock(&dev->mode_config.mutex); | |
553 | drm_helper_resume_force_mode(dev); | |
554 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 555 | |
c1c7af60 JB |
556 | return NOTIFY_OK; |
557 | } | |
558 | ||
79e53945 JB |
559 | /** |
560 | * intel_lvds_destroy - unregister and free LVDS structures | |
561 | * @connector: connector to free | |
562 | * | |
563 | * Unregister the DDC bus for this connector then free the driver private | |
564 | * structure. | |
565 | */ | |
566 | static void intel_lvds_destroy(struct drm_connector *connector) | |
567 | { | |
c1c7af60 | 568 | struct drm_device *dev = connector->dev; |
c1c7af60 | 569 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 570 | |
c1c7af60 JB |
571 | if (dev_priv->lid_notifier.notifier_call) |
572 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
573 | drm_sysfs_connector_remove(connector); |
574 | drm_connector_cleanup(connector); | |
575 | kfree(connector); | |
576 | } | |
577 | ||
335041ed JB |
578 | static int intel_lvds_set_property(struct drm_connector *connector, |
579 | struct drm_property *property, | |
580 | uint64_t value) | |
581 | { | |
788319d4 | 582 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
3fbe18d6 | 583 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 584 | |
788319d4 CW |
585 | if (property == dev->mode_config.scaling_mode_property) { |
586 | struct drm_crtc *crtc = intel_lvds->base.base.crtc; | |
bb8a3560 | 587 | |
53bd8389 JB |
588 | if (value == DRM_MODE_SCALE_NONE) { |
589 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 590 | return -EINVAL; |
3fbe18d6 | 591 | } |
788319d4 | 592 | |
ea5b213a | 593 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
594 | /* the LVDS scaling property is not changed */ |
595 | return 0; | |
596 | } | |
ea5b213a | 597 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
598 | if (crtc && crtc->enabled) { |
599 | /* | |
600 | * If the CRTC is enabled, the display will be changed | |
601 | * according to the new panel fitting mode. | |
602 | */ | |
603 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
604 | crtc->x, crtc->y, crtc->fb); | |
605 | } | |
606 | } | |
607 | ||
335041ed JB |
608 | return 0; |
609 | } | |
610 | ||
79e53945 JB |
611 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
612 | .dpms = intel_lvds_dpms, | |
613 | .mode_fixup = intel_lvds_mode_fixup, | |
614 | .prepare = intel_lvds_prepare, | |
615 | .mode_set = intel_lvds_mode_set, | |
616 | .commit = intel_lvds_commit, | |
617 | }; | |
618 | ||
619 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
620 | .get_modes = intel_lvds_get_modes, | |
621 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 622 | .best_encoder = intel_best_encoder, |
79e53945 JB |
623 | }; |
624 | ||
625 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 626 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
627 | .detect = intel_lvds_detect, |
628 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 629 | .set_property = intel_lvds_set_property, |
79e53945 JB |
630 | .destroy = intel_lvds_destroy, |
631 | }; | |
632 | ||
79e53945 | 633 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 634 | .destroy = intel_encoder_destroy, |
79e53945 JB |
635 | }; |
636 | ||
425d244c JW |
637 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
638 | { | |
8a4c47f3 | 639 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
640 | return 1; |
641 | } | |
79e53945 | 642 | |
425d244c | 643 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 644 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
645 | { |
646 | .callback = intel_no_lvds_dmi_callback, | |
647 | .ident = "Apple Mac Mini (Core series)", | |
648 | .matches = { | |
98acd46f | 649 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
650 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
651 | }, | |
652 | }, | |
653 | { | |
654 | .callback = intel_no_lvds_dmi_callback, | |
655 | .ident = "Apple Mac Mini (Core 2 series)", | |
656 | .matches = { | |
98acd46f | 657 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
658 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
659 | }, | |
660 | }, | |
661 | { | |
662 | .callback = intel_no_lvds_dmi_callback, | |
663 | .ident = "MSI IM-945GSE-A", | |
664 | .matches = { | |
665 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
666 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
667 | }, | |
668 | }, | |
669 | { | |
670 | .callback = intel_no_lvds_dmi_callback, | |
671 | .ident = "Dell Studio Hybrid", | |
672 | .matches = { | |
673 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
674 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
675 | }, | |
676 | }, | |
70aa96ca JW |
677 | { |
678 | .callback = intel_no_lvds_dmi_callback, | |
679 | .ident = "AOpen Mini PC", | |
680 | .matches = { | |
681 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
682 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
683 | }, | |
684 | }, | |
ed8c754b TV |
685 | { |
686 | .callback = intel_no_lvds_dmi_callback, | |
687 | .ident = "AOpen Mini PC MP915", | |
688 | .matches = { | |
689 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
690 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
691 | }, | |
692 | }, | |
fa0864b2 MC |
693 | { |
694 | .callback = intel_no_lvds_dmi_callback, | |
695 | .ident = "Aopen i945GTt-VFA", | |
696 | .matches = { | |
697 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
698 | }, | |
699 | }, | |
9875557e SB |
700 | { |
701 | .callback = intel_no_lvds_dmi_callback, | |
702 | .ident = "Clientron U800", | |
703 | .matches = { | |
704 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
705 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
706 | }, | |
707 | }, | |
425d244c JW |
708 | |
709 | { } /* terminating entry */ | |
710 | }; | |
79e53945 | 711 | |
18f9ed12 ZY |
712 | /** |
713 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
714 | * @dev: drm device | |
715 | * @connector: LVDS connector | |
716 | * | |
717 | * Find the reduced downclock for LVDS in EDID. | |
718 | */ | |
719 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
720 | struct drm_display_mode *fixed_mode, |
721 | struct drm_connector *connector) | |
18f9ed12 ZY |
722 | { |
723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 724 | struct drm_display_mode *scan; |
18f9ed12 ZY |
725 | int temp_downclock; |
726 | ||
788319d4 | 727 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
728 | list_for_each_entry(scan, &connector->probed_modes, head) { |
729 | /* | |
730 | * If one mode has the same resolution with the fixed_panel | |
731 | * mode while they have the different refresh rate, it means | |
732 | * that the reduced downclock is found for the LVDS. In such | |
733 | * case we can set the different FPx0/1 to dynamically select | |
734 | * between low and high frequency. | |
735 | */ | |
788319d4 CW |
736 | if (scan->hdisplay == fixed_mode->hdisplay && |
737 | scan->hsync_start == fixed_mode->hsync_start && | |
738 | scan->hsync_end == fixed_mode->hsync_end && | |
739 | scan->htotal == fixed_mode->htotal && | |
740 | scan->vdisplay == fixed_mode->vdisplay && | |
741 | scan->vsync_start == fixed_mode->vsync_start && | |
742 | scan->vsync_end == fixed_mode->vsync_end && | |
743 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
744 | if (scan->clock < temp_downclock) { |
745 | /* | |
746 | * The downclock is already found. But we | |
747 | * expect to find the lower downclock. | |
748 | */ | |
749 | temp_downclock = scan->clock; | |
750 | } | |
751 | } | |
752 | } | |
788319d4 | 753 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
754 | /* We found the downclock for LVDS. */ |
755 | dev_priv->lvds_downclock_avail = 1; | |
756 | dev_priv->lvds_downclock = temp_downclock; | |
757 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
758 | "Normal clock %dKhz, downclock %dKhz\n", |
759 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 760 | } |
18f9ed12 ZY |
761 | } |
762 | ||
7cf4f69d ZY |
763 | /* |
764 | * Enumerate the child dev array parsed from VBT to check whether | |
765 | * the LVDS is present. | |
766 | * If it is present, return 1. | |
767 | * If it is not present, return false. | |
768 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 769 | */ |
425904dd | 770 | static bool lvds_is_present_in_vbt(struct drm_device *dev) |
7cf4f69d ZY |
771 | { |
772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 773 | int i; |
7cf4f69d ZY |
774 | |
775 | if (!dev_priv->child_dev_num) | |
425904dd | 776 | return true; |
7cf4f69d | 777 | |
7cf4f69d | 778 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
779 | struct child_device_config *child = dev_priv->child_dev + i; |
780 | ||
781 | /* If the device type is not LFP, continue. | |
782 | * We have to check both the new identifiers as well as the | |
783 | * old for compatibility with some BIOSes. | |
7cf4f69d | 784 | */ |
425904dd CW |
785 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
786 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
787 | continue; |
788 | ||
425904dd CW |
789 | /* However, we cannot trust the BIOS writers to populate |
790 | * the VBT correctly. Since LVDS requires additional | |
791 | * information from AIM blocks, a non-zero addin offset is | |
792 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 793 | */ |
425904dd CW |
794 | if (child->addin_offset) |
795 | return true; | |
796 | ||
797 | /* But even then some BIOS writers perform some black magic | |
798 | * and instantiate the device without reference to any | |
799 | * additional data. Trust that if the VBT was written into | |
800 | * the OpRegion then they have validated the LVDS's existence. | |
801 | */ | |
802 | if (dev_priv->opregion.vbt) | |
803 | return true; | |
7cf4f69d | 804 | } |
425904dd CW |
805 | |
806 | return false; | |
7cf4f69d ZY |
807 | } |
808 | ||
79e53945 JB |
809 | /** |
810 | * intel_lvds_init - setup LVDS connectors on this device | |
811 | * @dev: drm device | |
812 | * | |
813 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
814 | * modes we can display on the LVDS panel (if present). | |
815 | */ | |
816 | void intel_lvds_init(struct drm_device *dev) | |
817 | { | |
818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 819 | struct intel_lvds *intel_lvds; |
21d40d37 | 820 | struct intel_encoder *intel_encoder; |
bb8a3560 | 821 | struct intel_connector *intel_connector; |
79e53945 JB |
822 | struct drm_connector *connector; |
823 | struct drm_encoder *encoder; | |
824 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
825 | struct drm_crtc *crtc; | |
826 | u32 lvds; | |
541998a1 | 827 | int pipe, gpio = GPIOC; |
79e53945 | 828 | |
425d244c JW |
829 | /* Skip init on machines we know falsely report LVDS */ |
830 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 831 | return; |
565dcd46 | 832 | |
11ba1592 MG |
833 | if (!lvds_is_present_in_vbt(dev)) { |
834 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); | |
e99da35f | 835 | return; |
38b3037e | 836 | } |
e99da35f | 837 | |
c619eed4 | 838 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
839 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
840 | return; | |
32f9d658 | 841 | if (dev_priv->edp_support) { |
28c97730 | 842 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
32f9d658 ZW |
843 | return; |
844 | } | |
541998a1 ZW |
845 | gpio = PCH_GPIOC; |
846 | } | |
847 | ||
ea5b213a CW |
848 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
849 | if (!intel_lvds) { | |
79e53945 JB |
850 | return; |
851 | } | |
852 | ||
bb8a3560 ZW |
853 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
854 | if (!intel_connector) { | |
ea5b213a | 855 | kfree(intel_lvds); |
bb8a3560 ZW |
856 | return; |
857 | } | |
858 | ||
e9e331a8 CW |
859 | if (!HAS_PCH_SPLIT(dev)) { |
860 | intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); | |
861 | } | |
862 | ||
ea5b213a | 863 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 864 | encoder = &intel_encoder->base; |
ea5b213a | 865 | connector = &intel_connector->base; |
bb8a3560 | 866 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
867 | DRM_MODE_CONNECTOR_LVDS); |
868 | ||
4ef69c7a | 869 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
870 | DRM_MODE_ENCODER_LVDS); |
871 | ||
df0e9248 | 872 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 873 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 874 | |
21d40d37 EA |
875 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
876 | intel_encoder->crtc_mask = (1 << 1); | |
79e53945 JB |
877 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
878 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
879 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
880 | connector->interlace_allowed = false; | |
881 | connector->doublescan_allowed = false; | |
882 | ||
3fbe18d6 ZY |
883 | /* create the scaling mode property */ |
884 | drm_mode_create_scaling_mode_property(dev); | |
885 | /* | |
886 | * the initial panel fitting mode will be FULL_SCREEN. | |
887 | */ | |
79e53945 | 888 | |
bb8a3560 | 889 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 890 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 891 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 892 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
893 | /* |
894 | * LVDS discovery: | |
895 | * 1) check for EDID on DDC | |
896 | * 2) check for VBT data | |
897 | * 3) check to see if LVDS is already on | |
898 | * if none of the above, no panel | |
899 | * 4) make sure lid is open | |
900 | * if closed, act like it's not there for now | |
901 | */ | |
902 | ||
79e53945 JB |
903 | /* |
904 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
905 | * preferred mode is the right one. | |
906 | */ | |
219adae1 CW |
907 | intel_lvds->edid = drm_get_edid(connector, |
908 | &dev_priv->gmbus[GMBUS_PORT_PANEL].adapter); | |
788319d4 | 909 | |
219adae1 | 910 | if (!intel_lvds->edid) { |
788319d4 CW |
911 | /* Didn't get an EDID, so |
912 | * Set wide sync ranges so we get all modes | |
913 | * handed to valid_mode for checking | |
914 | */ | |
915 | connector->display_info.min_vfreq = 0; | |
916 | connector->display_info.max_vfreq = 200; | |
917 | connector->display_info.min_hfreq = 0; | |
918 | connector->display_info.max_hfreq = 200; | |
919 | } | |
79e53945 JB |
920 | |
921 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 922 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
788319d4 | 923 | intel_lvds->fixed_mode = |
79e53945 | 924 | drm_mode_duplicate(dev, scan); |
788319d4 CW |
925 | intel_find_lvds_downclock(dev, |
926 | intel_lvds->fixed_mode, | |
927 | connector); | |
565dcd46 | 928 | goto out; |
79e53945 | 929 | } |
79e53945 JB |
930 | } |
931 | ||
932 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 933 | if (dev_priv->lfp_lvds_vbt_mode) { |
788319d4 | 934 | intel_lvds->fixed_mode = |
88631706 | 935 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
788319d4 CW |
936 | if (intel_lvds->fixed_mode) { |
937 | intel_lvds->fixed_mode->type |= | |
e285f3cd | 938 | DRM_MODE_TYPE_PREFERRED; |
e285f3cd JB |
939 | goto out; |
940 | } | |
79e53945 JB |
941 | } |
942 | ||
943 | /* | |
944 | * If we didn't get EDID, try checking if the panel is already turned | |
945 | * on. If so, assume that whatever is currently programmed is the | |
946 | * correct mode. | |
947 | */ | |
541998a1 | 948 | |
f2b115e6 | 949 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 950 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
951 | goto failed; |
952 | ||
79e53945 JB |
953 | lvds = I915_READ(LVDS); |
954 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 955 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
956 | |
957 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
788319d4 CW |
958 | intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); |
959 | if (intel_lvds->fixed_mode) { | |
960 | intel_lvds->fixed_mode->type |= | |
79e53945 | 961 | DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 962 | goto out; |
79e53945 JB |
963 | } |
964 | } | |
965 | ||
966 | /* If we still don't have a mode after all that, give up. */ | |
788319d4 | 967 | if (!intel_lvds->fixed_mode) |
79e53945 JB |
968 | goto failed; |
969 | ||
79e53945 | 970 | out: |
c619eed4 | 971 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
972 | u32 pwm; |
973 | /* make sure PWM is enabled */ | |
974 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
975 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
976 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
977 | ||
978 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
979 | pwm |= PWM_PCH_ENABLE; | |
980 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
981 | } | |
c1c7af60 JB |
982 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
983 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 984 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
985 | dev_priv->lid_notifier.notifier_call = NULL; |
986 | } | |
a2565377 ZY |
987 | /* keep the LVDS connector */ |
988 | dev_priv->int_lvds_connector = connector; | |
79e53945 JB |
989 | drm_sysfs_connector_add(connector); |
990 | return; | |
991 | ||
992 | failed: | |
8a4c47f3 | 993 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 994 | drm_connector_cleanup(connector); |
1991bdfa | 995 | drm_encoder_cleanup(encoder); |
ea5b213a | 996 | kfree(intel_lvds); |
bb8a3560 | 997 | kfree(intel_connector); |
79e53945 | 998 | } |