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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 JB |
32 | #include <linux/i2c.h> |
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "drm_crtc.h" | |
36 | #include "drm_edid.h" | |
37 | #include "intel_drv.h" | |
38 | #include "i915_drm.h" | |
39 | #include "i915_drv.h" | |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 ZY |
42 | /* Private structure for the integrated LVDS support */ |
43 | struct intel_lvds_priv { | |
44 | int fitting_mode; | |
45 | u32 pfit_control; | |
46 | u32 pfit_pgm_ratios; | |
47 | }; | |
48 | ||
79e53945 JB |
49 | /** |
50 | * Sets the backlight level. | |
51 | * | |
52 | * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). | |
53 | */ | |
54 | static void intel_lvds_set_backlight(struct drm_device *dev, int level) | |
55 | { | |
56 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 57 | u32 blc_pwm_ctl, reg; |
79e53945 | 58 | |
c619eed4 | 59 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
60 | reg = BLC_PWM_CPU_CTL; |
61 | else | |
62 | reg = BLC_PWM_CTL; | |
79e53945 | 63 | |
541998a1 ZW |
64 | blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
65 | I915_WRITE(reg, (blc_pwm_ctl | | |
79e53945 JB |
66 | (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); |
67 | } | |
68 | ||
69 | /** | |
70 | * Returns the maximum level of the backlight duty cycle field. | |
71 | */ | |
72 | static u32 intel_lvds_get_max_backlight(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
75 | u32 reg; |
76 | ||
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
78 | reg = BLC_PWM_PCH_CTL2; |
79 | else | |
80 | reg = BLC_PWM_CTL; | |
79e53945 | 81 | |
541998a1 | 82 | return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >> |
79e53945 JB |
83 | BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; |
84 | } | |
85 | ||
86 | /** | |
87 | * Sets the power state for the panel. | |
88 | */ | |
89 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
90 | { | |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
469d1296 | 92 | u32 pp_status, ctl_reg, status_reg, lvds_reg; |
541998a1 | 93 | |
c619eed4 | 94 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
95 | ctl_reg = PCH_PP_CONTROL; |
96 | status_reg = PCH_PP_STATUS; | |
469d1296 | 97 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
98 | } else { |
99 | ctl_reg = PP_CONTROL; | |
100 | status_reg = PP_STATUS; | |
469d1296 | 101 | lvds_reg = LVDS; |
541998a1 | 102 | } |
79e53945 JB |
103 | |
104 | if (on) { | |
469d1296 JB |
105 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
106 | POSTING_READ(lvds_reg); | |
107 | ||
541998a1 | 108 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | |
79e53945 JB |
109 | POWER_TARGET_ON); |
110 | do { | |
541998a1 | 111 | pp_status = I915_READ(status_reg); |
79e53945 JB |
112 | } while ((pp_status & PP_ON) == 0); |
113 | ||
114 | intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); | |
115 | } else { | |
116 | intel_lvds_set_backlight(dev, 0); | |
117 | ||
541998a1 | 118 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & |
79e53945 JB |
119 | ~POWER_TARGET_ON); |
120 | do { | |
541998a1 | 121 | pp_status = I915_READ(status_reg); |
79e53945 | 122 | } while (pp_status & PP_ON); |
469d1296 JB |
123 | |
124 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
125 | POSTING_READ(lvds_reg); | |
79e53945 JB |
126 | } |
127 | } | |
128 | ||
129 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
130 | { | |
131 | struct drm_device *dev = encoder->dev; | |
132 | ||
133 | if (mode == DRM_MODE_DPMS_ON) | |
134 | intel_lvds_set_power(dev, true); | |
135 | else | |
136 | intel_lvds_set_power(dev, false); | |
137 | ||
138 | /* XXX: We never power down the LVDS pairs. */ | |
139 | } | |
140 | ||
141 | static void intel_lvds_save(struct drm_connector *connector) | |
142 | { | |
143 | struct drm_device *dev = connector->dev; | |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
145 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
146 | u32 pwm_ctl_reg; | |
147 | ||
c619eed4 | 148 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
149 | pp_on_reg = PCH_PP_ON_DELAYS; |
150 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
151 | pp_ctl_reg = PCH_PP_CONTROL; | |
152 | pp_div_reg = PCH_PP_DIVISOR; | |
153 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
154 | } else { | |
155 | pp_on_reg = PP_ON_DELAYS; | |
156 | pp_off_reg = PP_OFF_DELAYS; | |
157 | pp_ctl_reg = PP_CONTROL; | |
158 | pp_div_reg = PP_DIVISOR; | |
159 | pwm_ctl_reg = BLC_PWM_CTL; | |
160 | } | |
79e53945 | 161 | |
541998a1 ZW |
162 | dev_priv->savePP_ON = I915_READ(pp_on_reg); |
163 | dev_priv->savePP_OFF = I915_READ(pp_off_reg); | |
164 | dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg); | |
165 | dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg); | |
166 | dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg); | |
79e53945 JB |
167 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
168 | BACKLIGHT_DUTY_CYCLE_MASK); | |
169 | ||
170 | /* | |
171 | * If the light is off at server startup, just make it full brightness | |
172 | */ | |
173 | if (dev_priv->backlight_duty_cycle == 0) | |
174 | dev_priv->backlight_duty_cycle = | |
175 | intel_lvds_get_max_backlight(dev); | |
176 | } | |
177 | ||
178 | static void intel_lvds_restore(struct drm_connector *connector) | |
179 | { | |
180 | struct drm_device *dev = connector->dev; | |
181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
182 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
183 | u32 pwm_ctl_reg; | |
184 | ||
c619eed4 | 185 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
186 | pp_on_reg = PCH_PP_ON_DELAYS; |
187 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
188 | pp_ctl_reg = PCH_PP_CONTROL; | |
189 | pp_div_reg = PCH_PP_DIVISOR; | |
190 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
191 | } else { | |
192 | pp_on_reg = PP_ON_DELAYS; | |
193 | pp_off_reg = PP_OFF_DELAYS; | |
194 | pp_ctl_reg = PP_CONTROL; | |
195 | pp_div_reg = PP_DIVISOR; | |
196 | pwm_ctl_reg = BLC_PWM_CTL; | |
197 | } | |
79e53945 | 198 | |
541998a1 ZW |
199 | I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL); |
200 | I915_WRITE(pp_on_reg, dev_priv->savePP_ON); | |
201 | I915_WRITE(pp_off_reg, dev_priv->savePP_OFF); | |
202 | I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR); | |
203 | I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL); | |
79e53945 JB |
204 | if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) |
205 | intel_lvds_set_power(dev, true); | |
206 | else | |
207 | intel_lvds_set_power(dev, false); | |
208 | } | |
209 | ||
210 | static int intel_lvds_mode_valid(struct drm_connector *connector, | |
211 | struct drm_display_mode *mode) | |
212 | { | |
213 | struct drm_device *dev = connector->dev; | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
216 | ||
217 | if (fixed_mode) { | |
218 | if (mode->hdisplay > fixed_mode->hdisplay) | |
219 | return MODE_PANEL; | |
220 | if (mode->vdisplay > fixed_mode->vdisplay) | |
221 | return MODE_PANEL; | |
222 | } | |
223 | ||
224 | return MODE_OK; | |
225 | } | |
226 | ||
227 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |
228 | struct drm_display_mode *mode, | |
229 | struct drm_display_mode *adjusted_mode) | |
230 | { | |
3fbe18d6 ZY |
231 | /* |
232 | * float point operation is not supported . So the PANEL_RATIO_FACTOR | |
233 | * is defined, which can avoid the float point computation when | |
234 | * calculating the panel ratio. | |
235 | */ | |
236 | #define PANEL_RATIO_FACTOR 8192 | |
79e53945 JB |
237 | struct drm_device *dev = encoder->dev; |
238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
239 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
240 | struct drm_encoder *tmp_encoder; | |
21d40d37 EA |
241 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
242 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; | |
3fbe18d6 ZY |
243 | u32 pfit_control = 0, pfit_pgm_ratios = 0; |
244 | int left_border = 0, right_border = 0, top_border = 0; | |
245 | int bottom_border = 0; | |
246 | bool border = 0; | |
247 | int panel_ratio, desired_ratio, vert_scale, horiz_scale; | |
248 | int horiz_ratio, vert_ratio; | |
aa0261f2 ZY |
249 | u32 hsync_width, vsync_width; |
250 | u32 hblank_width, vblank_width; | |
251 | u32 hsync_pos, vsync_pos; | |
79e53945 JB |
252 | |
253 | /* Should never happen!! */ | |
254 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
1ae8c0a5 | 255 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
256 | return false; |
257 | } | |
258 | ||
259 | /* Should never happen!! */ | |
260 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
261 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 262 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
263 | "encoder on the same pipe\n"); |
264 | return false; | |
265 | } | |
266 | } | |
3fbe18d6 ZY |
267 | /* If we don't have a panel mode, there is nothing we can do */ |
268 | if (dev_priv->panel_fixed_mode == NULL) | |
269 | return true; | |
79e53945 JB |
270 | /* |
271 | * If we have timings from the BIOS for the panel, put them in | |
272 | * to the adjusted mode. The CRTC will be set up for this mode, | |
273 | * with the panel scaling set up to source from the H/VDisplay | |
274 | * of the original mode. | |
275 | */ | |
276 | if (dev_priv->panel_fixed_mode != NULL) { | |
277 | adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; | |
278 | adjusted_mode->hsync_start = | |
279 | dev_priv->panel_fixed_mode->hsync_start; | |
280 | adjusted_mode->hsync_end = | |
281 | dev_priv->panel_fixed_mode->hsync_end; | |
282 | adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; | |
283 | adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; | |
284 | adjusted_mode->vsync_start = | |
285 | dev_priv->panel_fixed_mode->vsync_start; | |
286 | adjusted_mode->vsync_end = | |
287 | dev_priv->panel_fixed_mode->vsync_end; | |
288 | adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; | |
289 | adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; | |
290 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
291 | } | |
292 | ||
3fbe18d6 ZY |
293 | /* Make sure pre-965s set dither correctly */ |
294 | if (!IS_I965G(dev)) { | |
295 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) | |
296 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
297 | } | |
298 | ||
299 | /* Native modes don't need fitting */ | |
300 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
301 | adjusted_mode->vdisplay == mode->vdisplay) { | |
302 | pfit_pgm_ratios = 0; | |
303 | border = 0; | |
304 | goto out; | |
305 | } | |
306 | ||
8dd81a38 | 307 | /* full screen scale for now */ |
c619eed4 | 308 | if (HAS_PCH_SPLIT(dev)) |
8dd81a38 ZW |
309 | goto out; |
310 | ||
3fbe18d6 ZY |
311 | /* 965+ wants fuzzy fitting */ |
312 | if (IS_I965G(dev)) | |
313 | pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
314 | PFIT_FILTER_FUZZY; | |
315 | ||
aa0261f2 ZY |
316 | hsync_width = adjusted_mode->crtc_hsync_end - |
317 | adjusted_mode->crtc_hsync_start; | |
318 | vsync_width = adjusted_mode->crtc_vsync_end - | |
319 | adjusted_mode->crtc_vsync_start; | |
320 | hblank_width = adjusted_mode->crtc_hblank_end - | |
321 | adjusted_mode->crtc_hblank_start; | |
322 | vblank_width = adjusted_mode->crtc_vblank_end - | |
323 | adjusted_mode->crtc_vblank_start; | |
3fbe18d6 ZY |
324 | /* |
325 | * Deal with panel fitting options. Figure out how to stretch the | |
326 | * image based on its aspect ratio & the current panel fitting mode. | |
327 | */ | |
328 | panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR / | |
329 | adjusted_mode->vdisplay; | |
330 | desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR / | |
331 | mode->vdisplay; | |
332 | /* | |
333 | * Enable automatic panel scaling for non-native modes so that they fill | |
334 | * the screen. Should be enabled before the pipe is enabled, according | |
335 | * to register description and PRM. | |
336 | * Change the value here to see the borders for debugging | |
337 | */ | |
c619eed4 | 338 | if (!HAS_PCH_SPLIT(dev)) { |
8dd81a38 ZW |
339 | I915_WRITE(BCLRPAT_A, 0); |
340 | I915_WRITE(BCLRPAT_B, 0); | |
341 | } | |
3fbe18d6 ZY |
342 | |
343 | switch (lvds_priv->fitting_mode) { | |
53bd8389 | 344 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
345 | /* |
346 | * For centered modes, we have to calculate border widths & | |
347 | * heights and modify the values programmed into the CRTC. | |
348 | */ | |
349 | left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2; | |
350 | right_border = left_border; | |
351 | if (mode->hdisplay & 1) | |
352 | right_border++; | |
353 | top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2; | |
354 | bottom_border = top_border; | |
355 | if (mode->vdisplay & 1) | |
356 | bottom_border++; | |
357 | /* Set active & border values */ | |
358 | adjusted_mode->crtc_hdisplay = mode->hdisplay; | |
aa0261f2 ZY |
359 | /* Keep the boder be even */ |
360 | if (right_border & 1) | |
361 | right_border++; | |
362 | /* use the border directly instead of border minuse one */ | |
3fbe18d6 | 363 | adjusted_mode->crtc_hblank_start = mode->hdisplay + |
aa0261f2 ZY |
364 | right_border; |
365 | /* keep the blank width constant */ | |
366 | adjusted_mode->crtc_hblank_end = | |
367 | adjusted_mode->crtc_hblank_start + hblank_width; | |
368 | /* get the hsync pos relative to hblank start */ | |
369 | hsync_pos = (hblank_width - hsync_width) / 2; | |
370 | /* keep the hsync pos be even */ | |
371 | if (hsync_pos & 1) | |
372 | hsync_pos++; | |
3fbe18d6 | 373 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
374 | adjusted_mode->crtc_hblank_start + hsync_pos; |
375 | /* keep the hsync width constant */ | |
3fbe18d6 | 376 | adjusted_mode->crtc_hsync_end = |
aa0261f2 | 377 | adjusted_mode->crtc_hsync_start + hsync_width; |
3fbe18d6 | 378 | adjusted_mode->crtc_vdisplay = mode->vdisplay; |
aa0261f2 | 379 | /* use the border instead of border minus one */ |
3fbe18d6 | 380 | adjusted_mode->crtc_vblank_start = mode->vdisplay + |
aa0261f2 ZY |
381 | bottom_border; |
382 | /* keep the vblank width constant */ | |
383 | adjusted_mode->crtc_vblank_end = | |
384 | adjusted_mode->crtc_vblank_start + vblank_width; | |
385 | /* get the vsync start postion relative to vblank start */ | |
386 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 387 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
388 | adjusted_mode->crtc_vblank_start + vsync_pos; |
389 | /* keep the vsync width constant */ | |
3fbe18d6 | 390 | adjusted_mode->crtc_vsync_end = |
a3e17eb8 | 391 | adjusted_mode->crtc_vsync_start + vsync_width; |
3fbe18d6 ZY |
392 | border = 1; |
393 | break; | |
394 | case DRM_MODE_SCALE_ASPECT: | |
395 | /* Scale but preserve the spect ratio */ | |
396 | pfit_control |= PFIT_ENABLE; | |
397 | if (IS_I965G(dev)) { | |
398 | /* 965+ is easy, it does everything in hw */ | |
399 | if (panel_ratio > desired_ratio) | |
400 | pfit_control |= PFIT_SCALING_PILLAR; | |
401 | else if (panel_ratio < desired_ratio) | |
402 | pfit_control |= PFIT_SCALING_LETTER; | |
403 | else | |
404 | pfit_control |= PFIT_SCALING_AUTO; | |
405 | } else { | |
406 | /* | |
407 | * For earlier chips we have to calculate the scaling | |
408 | * ratio by hand and program it into the | |
409 | * PFIT_PGM_RATIO register | |
410 | */ | |
411 | u32 horiz_bits, vert_bits, bits = 12; | |
412 | horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/ | |
413 | adjusted_mode->hdisplay; | |
414 | vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/ | |
415 | adjusted_mode->vdisplay; | |
416 | horiz_scale = adjusted_mode->hdisplay * | |
417 | PANEL_RATIO_FACTOR / mode->hdisplay; | |
418 | vert_scale = adjusted_mode->vdisplay * | |
419 | PANEL_RATIO_FACTOR / mode->vdisplay; | |
420 | ||
421 | /* retain aspect ratio */ | |
422 | if (panel_ratio > desired_ratio) { /* Pillar */ | |
423 | u32 scaled_width; | |
424 | scaled_width = mode->hdisplay * vert_scale / | |
425 | PANEL_RATIO_FACTOR; | |
426 | horiz_ratio = vert_ratio; | |
427 | pfit_control |= (VERT_AUTO_SCALE | | |
428 | VERT_INTERP_BILINEAR | | |
429 | HORIZ_INTERP_BILINEAR); | |
430 | /* Pillar will have left/right borders */ | |
431 | left_border = (adjusted_mode->hdisplay - | |
432 | scaled_width) / 2; | |
433 | right_border = left_border; | |
434 | if (mode->hdisplay & 1) /* odd resolutions */ | |
435 | right_border++; | |
aa0261f2 ZY |
436 | /* keep the border be even */ |
437 | if (right_border & 1) | |
438 | right_border++; | |
3fbe18d6 | 439 | adjusted_mode->crtc_hdisplay = scaled_width; |
aa0261f2 | 440 | /* use border instead of border minus one */ |
3fbe18d6 | 441 | adjusted_mode->crtc_hblank_start = |
aa0261f2 ZY |
442 | scaled_width + right_border; |
443 | /* keep the hblank width constant */ | |
3fbe18d6 | 444 | adjusted_mode->crtc_hblank_end = |
aa0261f2 ZY |
445 | adjusted_mode->crtc_hblank_start + |
446 | hblank_width; | |
447 | /* | |
448 | * get the hsync start pos relative to | |
449 | * hblank start | |
450 | */ | |
451 | hsync_pos = (hblank_width - hsync_width) / 2; | |
452 | /* keep the hsync_pos be even */ | |
453 | if (hsync_pos & 1) | |
454 | hsync_pos++; | |
3fbe18d6 | 455 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
456 | adjusted_mode->crtc_hblank_start + |
457 | hsync_pos; | |
458 | /* keept hsync width constant */ | |
3fbe18d6 | 459 | adjusted_mode->crtc_hsync_end = |
aa0261f2 ZY |
460 | adjusted_mode->crtc_hsync_start + |
461 | hsync_width; | |
3fbe18d6 ZY |
462 | border = 1; |
463 | } else if (panel_ratio < desired_ratio) { /* letter */ | |
464 | u32 scaled_height = mode->vdisplay * | |
465 | horiz_scale / PANEL_RATIO_FACTOR; | |
466 | vert_ratio = horiz_ratio; | |
467 | pfit_control |= (HORIZ_AUTO_SCALE | | |
468 | VERT_INTERP_BILINEAR | | |
469 | HORIZ_INTERP_BILINEAR); | |
470 | /* Letterbox will have top/bottom border */ | |
471 | top_border = (adjusted_mode->vdisplay - | |
472 | scaled_height) / 2; | |
473 | bottom_border = top_border; | |
474 | if (mode->vdisplay & 1) | |
475 | bottom_border++; | |
476 | adjusted_mode->crtc_vdisplay = scaled_height; | |
aa0261f2 | 477 | /* use border instead of border minus one */ |
3fbe18d6 | 478 | adjusted_mode->crtc_vblank_start = |
aa0261f2 ZY |
479 | scaled_height + bottom_border; |
480 | /* keep the vblank width constant */ | |
3fbe18d6 | 481 | adjusted_mode->crtc_vblank_end = |
aa0261f2 ZY |
482 | adjusted_mode->crtc_vblank_start + |
483 | vblank_width; | |
484 | /* | |
485 | * get the vsync start pos relative to | |
486 | * vblank start | |
487 | */ | |
488 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 489 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
490 | adjusted_mode->crtc_vblank_start + |
491 | vsync_pos; | |
492 | /* keep the vsync width constant */ | |
3fbe18d6 | 493 | adjusted_mode->crtc_vsync_end = |
aa0261f2 ZY |
494 | adjusted_mode->crtc_vsync_start + |
495 | vsync_width; | |
3fbe18d6 ZY |
496 | border = 1; |
497 | } else { | |
498 | /* Aspects match, Let hw scale both directions */ | |
499 | pfit_control |= (VERT_AUTO_SCALE | | |
500 | HORIZ_AUTO_SCALE | | |
501 | VERT_INTERP_BILINEAR | | |
502 | HORIZ_INTERP_BILINEAR); | |
503 | } | |
504 | horiz_bits = (1 << bits) * horiz_ratio / | |
505 | PANEL_RATIO_FACTOR; | |
506 | vert_bits = (1 << bits) * vert_ratio / | |
507 | PANEL_RATIO_FACTOR; | |
508 | pfit_pgm_ratios = | |
509 | ((vert_bits << PFIT_VERT_SCALE_SHIFT) & | |
510 | PFIT_VERT_SCALE_MASK) | | |
511 | ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) & | |
512 | PFIT_HORIZ_SCALE_MASK); | |
513 | } | |
514 | break; | |
515 | ||
516 | case DRM_MODE_SCALE_FULLSCREEN: | |
517 | /* | |
518 | * Full scaling, even if it changes the aspect ratio. | |
519 | * Fortunately this is all done for us in hw. | |
520 | */ | |
521 | pfit_control |= PFIT_ENABLE; | |
522 | if (IS_I965G(dev)) | |
523 | pfit_control |= PFIT_SCALING_AUTO; | |
524 | else | |
525 | pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
526 | VERT_INTERP_BILINEAR | | |
527 | HORIZ_INTERP_BILINEAR); | |
528 | break; | |
529 | default: | |
530 | break; | |
531 | } | |
532 | ||
533 | out: | |
534 | lvds_priv->pfit_control = pfit_control; | |
535 | lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; | |
a3e17eb8 ZY |
536 | /* |
537 | * When there exists the border, it means that the LVDS_BORDR | |
538 | * should be enabled. | |
539 | */ | |
540 | if (border) | |
541 | dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE; | |
542 | else | |
543 | dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE); | |
79e53945 JB |
544 | /* |
545 | * XXX: It would be nice to support lower refresh rates on the | |
546 | * panels to reduce power consumption, and perhaps match the | |
547 | * user's requested refresh rate. | |
548 | */ | |
549 | ||
550 | return true; | |
551 | } | |
552 | ||
553 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
554 | { | |
555 | struct drm_device *dev = encoder->dev; | |
556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 557 | u32 reg; |
79e53945 | 558 | |
c619eed4 | 559 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
560 | reg = BLC_PWM_CPU_CTL; |
561 | else | |
562 | reg = BLC_PWM_CTL; | |
79e53945 | 563 | |
541998a1 | 564 | dev_priv->saveBLC_PWM_CTL = I915_READ(reg); |
79e53945 JB |
565 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
566 | BACKLIGHT_DUTY_CYCLE_MASK); | |
567 | ||
568 | intel_lvds_set_power(dev, false); | |
569 | } | |
570 | ||
571 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
572 | { | |
573 | struct drm_device *dev = encoder->dev; | |
574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
575 | ||
576 | if (dev_priv->backlight_duty_cycle == 0) | |
577 | dev_priv->backlight_duty_cycle = | |
578 | intel_lvds_get_max_backlight(dev); | |
579 | ||
580 | intel_lvds_set_power(dev, true); | |
581 | } | |
582 | ||
583 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
584 | struct drm_display_mode *mode, | |
585 | struct drm_display_mode *adjusted_mode) | |
586 | { | |
587 | struct drm_device *dev = encoder->dev; | |
588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 EA |
589 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
590 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; | |
79e53945 JB |
591 | |
592 | /* | |
593 | * The LVDS pin pair will already have been turned on in the | |
594 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
595 | * settings. | |
596 | */ | |
597 | ||
c619eed4 | 598 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
599 | return; |
600 | ||
79e53945 JB |
601 | /* |
602 | * Enable automatic panel scaling so that non-native modes fill the | |
603 | * screen. Should be enabled before the pipe is enabled, according to | |
604 | * register description and PRM. | |
605 | */ | |
3fbe18d6 ZY |
606 | I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios); |
607 | I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); | |
79e53945 JB |
608 | } |
609 | ||
610 | /** | |
611 | * Detect the LVDS connection. | |
612 | * | |
b42d4c5c JB |
613 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
614 | * connected and closed means disconnected. We also send hotplug events as | |
615 | * needed, using lid status notification from the input layer. | |
79e53945 JB |
616 | */ |
617 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
618 | { | |
7b9c5abe | 619 | struct drm_device *dev = connector->dev; |
b42d4c5c JB |
620 | enum drm_connector_status status = connector_status_connected; |
621 | ||
7b9c5abe JB |
622 | /* ACPI lid methods were generally unreliable in this generation, so |
623 | * don't even bother. | |
624 | */ | |
6e6c8228 | 625 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
626 | return connector_status_connected; |
627 | ||
b42d4c5c | 628 | return status; |
79e53945 JB |
629 | } |
630 | ||
631 | /** | |
632 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
633 | */ | |
634 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
635 | { | |
636 | struct drm_device *dev = connector->dev; | |
21d40d37 | 637 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); |
79e53945 JB |
638 | struct drm_i915_private *dev_priv = dev->dev_private; |
639 | int ret = 0; | |
640 | ||
21d40d37 | 641 | ret = intel_ddc_get_modes(intel_encoder); |
79e53945 JB |
642 | |
643 | if (ret) | |
644 | return ret; | |
645 | ||
646 | /* Didn't get an EDID, so | |
647 | * Set wide sync ranges so we get all modes | |
648 | * handed to valid_mode for checking | |
649 | */ | |
650 | connector->display_info.min_vfreq = 0; | |
651 | connector->display_info.max_vfreq = 200; | |
652 | connector->display_info.min_hfreq = 0; | |
653 | connector->display_info.max_hfreq = 200; | |
654 | ||
655 | if (dev_priv->panel_fixed_mode != NULL) { | |
656 | struct drm_display_mode *mode; | |
657 | ||
79e53945 JB |
658 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
659 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
660 | |
661 | return 1; | |
662 | } | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
c9354c85 LT |
667 | /* |
668 | * Lid events. Note the use of 'modeset_on_lid': | |
669 | * - we set it on lid close, and reset it on open | |
670 | * - we use it as a "only once" bit (ie we ignore | |
671 | * duplicate events where it was already properly | |
672 | * set/reset) | |
673 | * - the suspend/resume paths will also set it to | |
674 | * zero, since they restore the mode ("lid open"). | |
675 | */ | |
c1c7af60 JB |
676 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
677 | void *unused) | |
678 | { | |
679 | struct drm_i915_private *dev_priv = | |
680 | container_of(nb, struct drm_i915_private, lid_notifier); | |
681 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 682 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 683 | |
a2565377 ZY |
684 | /* |
685 | * check and update the status of LVDS connector after receiving | |
686 | * the LID nofication event. | |
687 | */ | |
688 | if (connector) | |
689 | connector->status = connector->funcs->detect(connector); | |
c9354c85 LT |
690 | if (!acpi_lid_open()) { |
691 | dev_priv->modeset_on_lid = 1; | |
692 | return NOTIFY_OK; | |
06891e27 | 693 | } |
c1c7af60 | 694 | |
c9354c85 LT |
695 | if (!dev_priv->modeset_on_lid) |
696 | return NOTIFY_OK; | |
697 | ||
698 | dev_priv->modeset_on_lid = 0; | |
699 | ||
700 | mutex_lock(&dev->mode_config.mutex); | |
701 | drm_helper_resume_force_mode(dev); | |
702 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 703 | |
c1c7af60 JB |
704 | return NOTIFY_OK; |
705 | } | |
706 | ||
79e53945 JB |
707 | /** |
708 | * intel_lvds_destroy - unregister and free LVDS structures | |
709 | * @connector: connector to free | |
710 | * | |
711 | * Unregister the DDC bus for this connector then free the driver private | |
712 | * structure. | |
713 | */ | |
714 | static void intel_lvds_destroy(struct drm_connector *connector) | |
715 | { | |
c1c7af60 | 716 | struct drm_device *dev = connector->dev; |
21d40d37 | 717 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); |
c1c7af60 | 718 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 719 | |
21d40d37 EA |
720 | if (intel_encoder->ddc_bus) |
721 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
c1c7af60 JB |
722 | if (dev_priv->lid_notifier.notifier_call) |
723 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
724 | drm_sysfs_connector_remove(connector); |
725 | drm_connector_cleanup(connector); | |
726 | kfree(connector); | |
727 | } | |
728 | ||
335041ed JB |
729 | static int intel_lvds_set_property(struct drm_connector *connector, |
730 | struct drm_property *property, | |
731 | uint64_t value) | |
732 | { | |
3fbe18d6 | 733 | struct drm_device *dev = connector->dev; |
21d40d37 EA |
734 | struct intel_encoder *intel_encoder = |
735 | to_intel_encoder(connector); | |
3fbe18d6 ZY |
736 | |
737 | if (property == dev->mode_config.scaling_mode_property && | |
738 | connector->encoder) { | |
739 | struct drm_crtc *crtc = connector->encoder->crtc; | |
21d40d37 | 740 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; |
53bd8389 JB |
741 | if (value == DRM_MODE_SCALE_NONE) { |
742 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3fbe18d6 ZY |
743 | return 0; |
744 | } | |
745 | if (lvds_priv->fitting_mode == value) { | |
746 | /* the LVDS scaling property is not changed */ | |
747 | return 0; | |
748 | } | |
749 | lvds_priv->fitting_mode = value; | |
750 | if (crtc && crtc->enabled) { | |
751 | /* | |
752 | * If the CRTC is enabled, the display will be changed | |
753 | * according to the new panel fitting mode. | |
754 | */ | |
755 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
756 | crtc->x, crtc->y, crtc->fb); | |
757 | } | |
758 | } | |
759 | ||
335041ed JB |
760 | return 0; |
761 | } | |
762 | ||
79e53945 JB |
763 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
764 | .dpms = intel_lvds_dpms, | |
765 | .mode_fixup = intel_lvds_mode_fixup, | |
766 | .prepare = intel_lvds_prepare, | |
767 | .mode_set = intel_lvds_mode_set, | |
768 | .commit = intel_lvds_commit, | |
769 | }; | |
770 | ||
771 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
772 | .get_modes = intel_lvds_get_modes, | |
773 | .mode_valid = intel_lvds_mode_valid, | |
774 | .best_encoder = intel_best_encoder, | |
775 | }; | |
776 | ||
777 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 778 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
779 | .save = intel_lvds_save, |
780 | .restore = intel_lvds_restore, | |
781 | .detect = intel_lvds_detect, | |
782 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 783 | .set_property = intel_lvds_set_property, |
79e53945 JB |
784 | .destroy = intel_lvds_destroy, |
785 | }; | |
786 | ||
787 | ||
788 | static void intel_lvds_enc_destroy(struct drm_encoder *encoder) | |
789 | { | |
790 | drm_encoder_cleanup(encoder); | |
791 | } | |
792 | ||
793 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
794 | .destroy = intel_lvds_enc_destroy, | |
795 | }; | |
796 | ||
425d244c JW |
797 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
798 | { | |
8a4c47f3 | 799 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
800 | return 1; |
801 | } | |
79e53945 | 802 | |
425d244c | 803 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 804 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
805 | { |
806 | .callback = intel_no_lvds_dmi_callback, | |
807 | .ident = "Apple Mac Mini (Core series)", | |
808 | .matches = { | |
98acd46f | 809 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
810 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
811 | }, | |
812 | }, | |
813 | { | |
814 | .callback = intel_no_lvds_dmi_callback, | |
815 | .ident = "Apple Mac Mini (Core 2 series)", | |
816 | .matches = { | |
98acd46f | 817 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
818 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
819 | }, | |
820 | }, | |
821 | { | |
822 | .callback = intel_no_lvds_dmi_callback, | |
823 | .ident = "MSI IM-945GSE-A", | |
824 | .matches = { | |
825 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
826 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
827 | }, | |
828 | }, | |
829 | { | |
830 | .callback = intel_no_lvds_dmi_callback, | |
831 | .ident = "Dell Studio Hybrid", | |
832 | .matches = { | |
833 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
834 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
835 | }, | |
836 | }, | |
70aa96ca JW |
837 | { |
838 | .callback = intel_no_lvds_dmi_callback, | |
839 | .ident = "AOpen Mini PC", | |
840 | .matches = { | |
841 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
842 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
843 | }, | |
844 | }, | |
ed8c754b TV |
845 | { |
846 | .callback = intel_no_lvds_dmi_callback, | |
847 | .ident = "AOpen Mini PC MP915", | |
848 | .matches = { | |
849 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
850 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
851 | }, | |
852 | }, | |
fa0864b2 MC |
853 | { |
854 | .callback = intel_no_lvds_dmi_callback, | |
855 | .ident = "Aopen i945GTt-VFA", | |
856 | .matches = { | |
857 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
858 | }, | |
859 | }, | |
425d244c JW |
860 | |
861 | { } /* terminating entry */ | |
862 | }; | |
79e53945 | 863 | |
18f9ed12 ZY |
864 | /** |
865 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
866 | * @dev: drm device | |
867 | * @connector: LVDS connector | |
868 | * | |
869 | * Find the reduced downclock for LVDS in EDID. | |
870 | */ | |
871 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
872 | struct drm_connector *connector) | |
873 | { | |
874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
875 | struct drm_display_mode *scan, *panel_fixed_mode; | |
876 | int temp_downclock; | |
877 | ||
878 | panel_fixed_mode = dev_priv->panel_fixed_mode; | |
879 | temp_downclock = panel_fixed_mode->clock; | |
880 | ||
881 | mutex_lock(&dev->mode_config.mutex); | |
882 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
883 | /* | |
884 | * If one mode has the same resolution with the fixed_panel | |
885 | * mode while they have the different refresh rate, it means | |
886 | * that the reduced downclock is found for the LVDS. In such | |
887 | * case we can set the different FPx0/1 to dynamically select | |
888 | * between low and high frequency. | |
889 | */ | |
890 | if (scan->hdisplay == panel_fixed_mode->hdisplay && | |
891 | scan->hsync_start == panel_fixed_mode->hsync_start && | |
892 | scan->hsync_end == panel_fixed_mode->hsync_end && | |
893 | scan->htotal == panel_fixed_mode->htotal && | |
894 | scan->vdisplay == panel_fixed_mode->vdisplay && | |
895 | scan->vsync_start == panel_fixed_mode->vsync_start && | |
896 | scan->vsync_end == panel_fixed_mode->vsync_end && | |
897 | scan->vtotal == panel_fixed_mode->vtotal) { | |
898 | if (scan->clock < temp_downclock) { | |
899 | /* | |
900 | * The downclock is already found. But we | |
901 | * expect to find the lower downclock. | |
902 | */ | |
903 | temp_downclock = scan->clock; | |
904 | } | |
905 | } | |
906 | } | |
907 | mutex_unlock(&dev->mode_config.mutex); | |
33814341 JB |
908 | if (temp_downclock < panel_fixed_mode->clock && |
909 | i915_lvds_downclock) { | |
18f9ed12 ZY |
910 | /* We found the downclock for LVDS. */ |
911 | dev_priv->lvds_downclock_avail = 1; | |
912 | dev_priv->lvds_downclock = temp_downclock; | |
913 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
914 | "Normal clock %dKhz, downclock %dKhz\n", | |
915 | panel_fixed_mode->clock, temp_downclock); | |
916 | } | |
917 | return; | |
918 | } | |
919 | ||
7cf4f69d ZY |
920 | /* |
921 | * Enumerate the child dev array parsed from VBT to check whether | |
922 | * the LVDS is present. | |
923 | * If it is present, return 1. | |
924 | * If it is not present, return false. | |
925 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
926 | * Note: The addin_offset should also be checked for LVDS panel. | |
927 | * Only when it is non-zero, it is assumed that it is present. | |
928 | */ | |
6e36595a | 929 | static int lvds_is_present_in_vbt(struct drm_device *dev) |
7cf4f69d ZY |
930 | { |
931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
932 | struct child_device_config *p_child; | |
933 | int i, ret; | |
934 | ||
935 | if (!dev_priv->child_dev_num) | |
936 | return 1; | |
937 | ||
938 | ret = 0; | |
939 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
940 | p_child = dev_priv->child_dev + i; | |
941 | /* | |
942 | * If the device type is not LFP, continue. | |
943 | * If the device type is 0x22, it is also regarded as LFP. | |
944 | */ | |
945 | if (p_child->device_type != DEVICE_TYPE_INT_LFP && | |
946 | p_child->device_type != DEVICE_TYPE_LFP) | |
947 | continue; | |
948 | ||
949 | /* The addin_offset should be checked. Only when it is | |
950 | * non-zero, it is regarded as present. | |
951 | */ | |
952 | if (p_child->addin_offset) { | |
953 | ret = 1; | |
954 | break; | |
955 | } | |
956 | } | |
957 | return ret; | |
958 | } | |
959 | ||
79e53945 JB |
960 | /** |
961 | * intel_lvds_init - setup LVDS connectors on this device | |
962 | * @dev: drm device | |
963 | * | |
964 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
965 | * modes we can display on the LVDS panel (if present). | |
966 | */ | |
967 | void intel_lvds_init(struct drm_device *dev) | |
968 | { | |
969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 | 970 | struct intel_encoder *intel_encoder; |
79e53945 JB |
971 | struct drm_connector *connector; |
972 | struct drm_encoder *encoder; | |
973 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
974 | struct drm_crtc *crtc; | |
3fbe18d6 | 975 | struct intel_lvds_priv *lvds_priv; |
79e53945 | 976 | u32 lvds; |
541998a1 | 977 | int pipe, gpio = GPIOC; |
79e53945 | 978 | |
425d244c JW |
979 | /* Skip init on machines we know falsely report LVDS */ |
980 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 981 | return; |
565dcd46 | 982 | |
11ba1592 MG |
983 | if (!lvds_is_present_in_vbt(dev)) { |
984 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); | |
e99da35f | 985 | return; |
38b3037e | 986 | } |
e99da35f | 987 | |
c619eed4 | 988 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
989 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
990 | return; | |
32f9d658 | 991 | if (dev_priv->edp_support) { |
28c97730 | 992 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
32f9d658 ZW |
993 | return; |
994 | } | |
541998a1 ZW |
995 | gpio = PCH_GPIOC; |
996 | } | |
997 | ||
21d40d37 | 998 | intel_encoder = kzalloc(sizeof(struct intel_encoder) + |
3fbe18d6 | 999 | sizeof(struct intel_lvds_priv), GFP_KERNEL); |
21d40d37 | 1000 | if (!intel_encoder) { |
79e53945 JB |
1001 | return; |
1002 | } | |
1003 | ||
21d40d37 EA |
1004 | connector = &intel_encoder->base; |
1005 | encoder = &intel_encoder->enc; | |
1006 | drm_connector_init(dev, &intel_encoder->base, &intel_lvds_connector_funcs, | |
79e53945 JB |
1007 | DRM_MODE_CONNECTOR_LVDS); |
1008 | ||
21d40d37 | 1009 | drm_encoder_init(dev, &intel_encoder->enc, &intel_lvds_enc_funcs, |
79e53945 JB |
1010 | DRM_MODE_ENCODER_LVDS); |
1011 | ||
21d40d37 EA |
1012 | drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc); |
1013 | intel_encoder->type = INTEL_OUTPUT_LVDS; | |
79e53945 | 1014 | |
21d40d37 EA |
1015 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
1016 | intel_encoder->crtc_mask = (1 << 1); | |
79e53945 JB |
1017 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1018 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1019 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1020 | connector->interlace_allowed = false; | |
1021 | connector->doublescan_allowed = false; | |
1022 | ||
21d40d37 EA |
1023 | lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1); |
1024 | intel_encoder->dev_priv = lvds_priv; | |
3fbe18d6 ZY |
1025 | /* create the scaling mode property */ |
1026 | drm_mode_create_scaling_mode_property(dev); | |
1027 | /* | |
1028 | * the initial panel fitting mode will be FULL_SCREEN. | |
1029 | */ | |
79e53945 | 1030 | |
21d40d37 | 1031 | drm_connector_attach_property(&intel_encoder->base, |
3fbe18d6 ZY |
1032 | dev->mode_config.scaling_mode_property, |
1033 | DRM_MODE_SCALE_FULLSCREEN); | |
1034 | lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN; | |
79e53945 JB |
1035 | /* |
1036 | * LVDS discovery: | |
1037 | * 1) check for EDID on DDC | |
1038 | * 2) check for VBT data | |
1039 | * 3) check to see if LVDS is already on | |
1040 | * if none of the above, no panel | |
1041 | * 4) make sure lid is open | |
1042 | * if closed, act like it's not there for now | |
1043 | */ | |
1044 | ||
1045 | /* Set up the DDC bus. */ | |
21d40d37 EA |
1046 | intel_encoder->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
1047 | if (!intel_encoder->ddc_bus) { | |
79e53945 JB |
1048 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
1049 | "failed.\n"); | |
1050 | goto failed; | |
1051 | } | |
1052 | ||
1053 | /* | |
1054 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1055 | * preferred mode is the right one. | |
1056 | */ | |
21d40d37 | 1057 | intel_ddc_get_modes(intel_encoder); |
79e53945 JB |
1058 | |
1059 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1060 | mutex_lock(&dev->mode_config.mutex); | |
1061 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
1062 | dev_priv->panel_fixed_mode = | |
1063 | drm_mode_duplicate(dev, scan); | |
1064 | mutex_unlock(&dev->mode_config.mutex); | |
18f9ed12 | 1065 | intel_find_lvds_downclock(dev, connector); |
565dcd46 | 1066 | goto out; |
79e53945 JB |
1067 | } |
1068 | mutex_unlock(&dev->mode_config.mutex); | |
1069 | } | |
1070 | ||
1071 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1072 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
1073 | mutex_lock(&dev->mode_config.mutex); |
1074 | dev_priv->panel_fixed_mode = | |
88631706 | 1075 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 1076 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
1077 | if (dev_priv->panel_fixed_mode) { |
1078 | dev_priv->panel_fixed_mode->type |= | |
1079 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1080 | goto out; |
1081 | } | |
79e53945 JB |
1082 | } |
1083 | ||
1084 | /* | |
1085 | * If we didn't get EDID, try checking if the panel is already turned | |
1086 | * on. If so, assume that whatever is currently programmed is the | |
1087 | * correct mode. | |
1088 | */ | |
541998a1 | 1089 | |
f2b115e6 | 1090 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1091 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1092 | goto failed; |
1093 | ||
79e53945 JB |
1094 | lvds = I915_READ(LVDS); |
1095 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1096 | crtc = intel_get_crtc_from_pipe(dev, pipe); | |
1097 | ||
1098 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
1099 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
1100 | if (dev_priv->panel_fixed_mode) { | |
1101 | dev_priv->panel_fixed_mode->type |= | |
1102 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 1103 | goto out; |
79e53945 JB |
1104 | } |
1105 | } | |
1106 | ||
1107 | /* If we still don't have a mode after all that, give up. */ | |
1108 | if (!dev_priv->panel_fixed_mode) | |
1109 | goto failed; | |
1110 | ||
79e53945 | 1111 | out: |
c619eed4 | 1112 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
1113 | u32 pwm; |
1114 | /* make sure PWM is enabled */ | |
1115 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
1116 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
1117 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
1118 | ||
1119 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1120 | pwm |= PWM_PCH_ENABLE; | |
1121 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
1122 | } | |
c1c7af60 JB |
1123 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1124 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1125 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1126 | dev_priv->lid_notifier.notifier_call = NULL; |
1127 | } | |
a2565377 ZY |
1128 | /* keep the LVDS connector */ |
1129 | dev_priv->int_lvds_connector = connector; | |
79e53945 JB |
1130 | drm_sysfs_connector_add(connector); |
1131 | return; | |
1132 | ||
1133 | failed: | |
8a4c47f3 | 1134 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
21d40d37 EA |
1135 | if (intel_encoder->ddc_bus) |
1136 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
79e53945 | 1137 | drm_connector_cleanup(connector); |
1991bdfa | 1138 | drm_encoder_cleanup(encoder); |
21d40d37 | 1139 | kfree(intel_encoder); |
79e53945 | 1140 | } |