drm/i915: panel fitter hw state readout&check support
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
fc683091
DV
89/* The LVDS pin pair needs to be on before the DPLLs are enabled.
90 * This is an exception to the general rule that mode_set doesn't turn
91 * things on.
92 */
93static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
94{
95 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
96 struct drm_device *dev = encoder->base.dev;
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
99 struct drm_display_mode *fixed_mode =
100 lvds_encoder->attached_connector->base.panel.fixed_mode;
101 int pipe = intel_crtc->pipe;
102 u32 temp;
103
fc683091
DV
104 temp = I915_READ(lvds_encoder->reg);
105 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
106
107 if (HAS_PCH_CPT(dev)) {
108 temp &= ~PORT_TRANS_SEL_MASK;
109 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 110 } else {
62810e5a
DV
111 if (pipe == 1) {
112 temp |= LVDS_PIPEB_SELECT;
113 } else {
114 temp &= ~LVDS_PIPEB_SELECT;
115 }
fc683091 116 }
62810e5a 117
fc683091 118 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 119 temp &= ~LVDS_BORDER_ENABLE;
68fc8742 120 temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
121 /* Set the B0-B3 data pairs corresponding to whether we're going to
122 * set the DPLLs for dual-channel mode or not.
123 */
124 if (lvds_encoder->is_dual_link)
125 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
126 else
127 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
128
129 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
130 * appropriately here, but we need to look more thoroughly into how
131 * panels behave in the two modes.
132 */
62810e5a
DV
133
134 /* Set the dithering flag on LVDS as needed, note that there is no
135 * special lvds dither control bit on pch-split platforms, dithering is
136 * only controlled through the PIPECONF reg. */
137 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
138 /* Bspec wording suggests that LVDS port dithering only exists
139 * for 18bpp panels. */
140 if (intel_crtc->config.dither &&
141 intel_crtc->config.pipe_bpp == 18)
fc683091
DV
142 temp |= LVDS_ENABLE_DITHER;
143 else
144 temp &= ~LVDS_ENABLE_DITHER;
145 }
146 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
147 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
148 temp |= LVDS_HSYNC_POLARITY;
149 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
150 temp |= LVDS_VSYNC_POLARITY;
151
152 I915_WRITE(lvds_encoder->reg, temp);
153}
154
79e53945
JB
155/**
156 * Sets the power state for the panel.
157 */
c22834ec 158static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 159{
c22834ec 160 struct drm_device *dev = encoder->base.dev;
29b99b48 161 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 162 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 163 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 164 u32 ctl_reg, stat_reg;
541998a1 165
c619eed4 166 if (HAS_PCH_SPLIT(dev)) {
541998a1 167 ctl_reg = PCH_PP_CONTROL;
de842eff 168 stat_reg = PCH_PP_STATUS;
541998a1
ZW
169 } else {
170 ctl_reg = PP_CONTROL;
de842eff 171 stat_reg = PP_STATUS;
541998a1 172 }
79e53945 173
7dec0606 174 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 175
2a1292fd 176 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 177 POSTING_READ(lvds_encoder->reg);
de842eff
KP
178 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
179 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 180
24ded204 181 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
182}
183
c22834ec 184static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 185{
c22834ec 186 struct drm_device *dev = encoder->base.dev;
29b99b48 187 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 188 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 189 u32 ctl_reg, stat_reg;
2a1292fd
CW
190
191 if (HAS_PCH_SPLIT(dev)) {
192 ctl_reg = PCH_PP_CONTROL;
de842eff 193 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
194 } else {
195 ctl_reg = PP_CONTROL;
de842eff 196 stat_reg = PP_STATUS;
2a1292fd
CW
197 }
198
47356eb6 199 intel_panel_disable_backlight(dev);
2a1292fd
CW
200
201 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
202 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
203 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 204
7dec0606
DV
205 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
206 POSTING_READ(lvds_encoder->reg);
79e53945
JB
207}
208
79e53945
JB
209static int intel_lvds_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
dd06f90e
JN
212 struct intel_connector *intel_connector = to_intel_connector(connector);
213 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 214
788319d4
CW
215 if (mode->hdisplay > fixed_mode->hdisplay)
216 return MODE_PANEL;
217 if (mode->vdisplay > fixed_mode->vdisplay)
218 return MODE_PANEL;
79e53945
JB
219
220 return MODE_OK;
221}
222
7ae89233
DV
223static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
224 struct intel_crtc_config *pipe_config)
79e53945 225{
7ae89233 226 struct drm_device *dev = intel_encoder->base.dev;
79e53945 227 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
228 struct intel_lvds_encoder *lvds_encoder =
229 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
230 struct intel_connector *intel_connector =
231 &lvds_encoder->attached_connector->base;
7ae89233 232 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 233 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 234 unsigned int lvds_bpp;
79e53945
JB
235
236 /* Should never happen!! */
a6c45cf0 237 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 238 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
239 return false;
240 }
241
29b99b48 242 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 243 return false;
1d8e1c75 244
4e53c2e0
DV
245 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
246 LVDS_A3_POWER_UP)
247 lvds_bpp = 8*3;
248 else
249 lvds_bpp = 6*3;
250
e29c22c0 251 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
252 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
253 pipe_config->pipe_bpp, lvds_bpp);
254 pipe_config->pipe_bpp = lvds_bpp;
255 }
d8b32247 256
79e53945 257 /*
71677043 258 * We have timings from the BIOS for the panel, put them in
79e53945
JB
259 * to the adjusted mode. The CRTC will be set up for this mode,
260 * with the panel scaling set up to source from the H/VDisplay
261 * of the original mode.
262 */
4d891523 263 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 264 adjusted_mode);
1d8e1c75
CW
265
266 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
267 pipe_config->has_pch_encoder = true;
268
b074cec8
JB
269 intel_pch_panel_fitting(intel_crtc, pipe_config,
270 intel_connector->panel.fitting_mode);
1d8e1c75 271 return true;
2dd24552
JB
272 } else {
273 intel_gmch_panel_fitting(intel_crtc, pipe_config,
274 intel_connector->panel.fitting_mode);
1d8e1c75 275 }
79e53945 276
f9bef081 277 drm_mode_set_crtcinfo(adjusted_mode, 0);
7ae89233 278 pipe_config->timings_set = true;
f9bef081 279
79e53945
JB
280 /*
281 * XXX: It would be nice to support lower refresh rates on the
282 * panels to reduce power consumption, and perhaps match the
283 * user's requested refresh rate.
284 */
285
286 return true;
287}
288
79e53945
JB
289static void intel_lvds_mode_set(struct drm_encoder *encoder,
290 struct drm_display_mode *mode,
291 struct drm_display_mode *adjusted_mode)
292{
79e53945
JB
293 /*
294 * The LVDS pin pair will already have been turned on in the
295 * intel_crtc_mode_set since it has a large impact on the DPLL
296 * settings.
297 */
79e53945
JB
298}
299
300/**
301 * Detect the LVDS connection.
302 *
b42d4c5c
JB
303 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
304 * connected and closed means disconnected. We also send hotplug events as
305 * needed, using lid status notification from the input layer.
79e53945 306 */
7b334fcb 307static enum drm_connector_status
930a9e28 308intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 309{
7b9c5abe 310 struct drm_device *dev = connector->dev;
6ee3b5a1 311 enum drm_connector_status status;
b42d4c5c 312
fe16d949
CW
313 status = intel_panel_detect(dev);
314 if (status != connector_status_unknown)
315 return status;
01fe9dbd 316
6ee3b5a1 317 return connector_status_connected;
79e53945
JB
318}
319
320/**
321 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
322 */
323static int intel_lvds_get_modes(struct drm_connector *connector)
324{
62165e0d 325 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 326 struct drm_device *dev = connector->dev;
788319d4 327 struct drm_display_mode *mode;
79e53945 328
9cd300e0 329 /* use cached edid if we have one */
2aa4f099 330 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 331 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 332
dd06f90e 333 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 334 if (mode == NULL)
788319d4 335 return 0;
79e53945 336
788319d4
CW
337 drm_mode_probed_add(connector, mode);
338 return 1;
79e53945
JB
339}
340
0544edfd
TB
341static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
342{
bc0daf48 343 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
344 return 1;
345}
346
347/* The GPU hangs up on these systems if modeset is performed on LID open */
348static const struct dmi_system_id intel_no_modeset_on_lid[] = {
349 {
350 .callback = intel_no_modeset_on_lid_dmi_callback,
351 .ident = "Toshiba Tecra A11",
352 .matches = {
353 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
354 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
355 },
356 },
357
358 { } /* terminating entry */
359};
360
c9354c85 361/*
b8efb17b
ZR
362 * Lid events. Note the use of 'modeset':
363 * - we set it to MODESET_ON_LID_OPEN on lid close,
364 * and set it to MODESET_DONE on open
c9354c85 365 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
366 * duplicate events where it was already properly set)
367 * - the suspend/resume paths will set it to
368 * MODESET_SUSPENDED and ignore the lid open event,
369 * because they restore the mode ("lid open").
c9354c85 370 */
c1c7af60
JB
371static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
372 void *unused)
373{
db1740a0
JN
374 struct intel_lvds_connector *lvds_connector =
375 container_of(nb, struct intel_lvds_connector, lid_notifier);
376 struct drm_connector *connector = &lvds_connector->base.base;
377 struct drm_device *dev = connector->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 379
2fb4e61d
AW
380 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
381 return NOTIFY_OK;
382
b8efb17b
ZR
383 mutex_lock(&dev_priv->modeset_restore_lock);
384 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
385 goto exit;
a2565377
ZY
386 /*
387 * check and update the status of LVDS connector after receiving
388 * the LID nofication event.
389 */
db1740a0 390 connector->status = connector->funcs->detect(connector, false);
7b334fcb 391
0544edfd
TB
392 /* Don't force modeset on machines where it causes a GPU lockup */
393 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 394 goto exit;
c9354c85 395 if (!acpi_lid_open()) {
b8efb17b
ZR
396 /* do modeset on next lid open event */
397 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
398 goto exit;
06891e27 399 }
c1c7af60 400
b8efb17b
ZR
401 if (dev_priv->modeset_restore == MODESET_DONE)
402 goto exit;
c9354c85 403
a0e99e68 404 drm_modeset_lock_all(dev);
45e2b5f6 405 intel_modeset_setup_hw_state(dev, true);
a0e99e68 406 drm_modeset_unlock_all(dev);
06324194 407
b8efb17b
ZR
408 dev_priv->modeset_restore = MODESET_DONE;
409
410exit:
411 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
412 return NOTIFY_OK;
413}
414
79e53945
JB
415/**
416 * intel_lvds_destroy - unregister and free LVDS structures
417 * @connector: connector to free
418 *
419 * Unregister the DDC bus for this connector then free the driver private
420 * structure.
421 */
422static void intel_lvds_destroy(struct drm_connector *connector)
423{
db1740a0
JN
424 struct intel_lvds_connector *lvds_connector =
425 to_lvds_connector(connector);
79e53945 426
db1740a0
JN
427 if (lvds_connector->lid_notifier.notifier_call)
428 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 429
9cd300e0
JN
430 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
431 kfree(lvds_connector->base.edid);
432
1d508706 433 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 434
79e53945
JB
435 drm_sysfs_connector_remove(connector);
436 drm_connector_cleanup(connector);
437 kfree(connector);
438}
439
335041ed
JB
440static int intel_lvds_set_property(struct drm_connector *connector,
441 struct drm_property *property,
442 uint64_t value)
443{
4d891523 444 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 445 struct drm_device *dev = connector->dev;
3fbe18d6 446
788319d4 447 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 448 struct drm_crtc *crtc;
bb8a3560 449
53bd8389
JB
450 if (value == DRM_MODE_SCALE_NONE) {
451 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 452 return -EINVAL;
3fbe18d6 453 }
788319d4 454
4d891523 455 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
456 /* the LVDS scaling property is not changed */
457 return 0;
458 }
4d891523 459 intel_connector->panel.fitting_mode = value;
62165e0d
JN
460
461 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
462 if (crtc && crtc->enabled) {
463 /*
464 * If the CRTC is enabled, the display will be changed
465 * according to the new panel fitting mode.
466 */
c0c36b94 467 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
468 }
469 }
470
335041ed
JB
471 return 0;
472}
473
79e53945 474static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 475 .mode_set = intel_lvds_mode_set,
79e53945
JB
476};
477
478static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
479 .get_modes = intel_lvds_get_modes,
480 .mode_valid = intel_lvds_mode_valid,
df0e9248 481 .best_encoder = intel_best_encoder,
79e53945
JB
482};
483
484static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 485 .dpms = intel_connector_dpms,
79e53945
JB
486 .detect = intel_lvds_detect,
487 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 488 .set_property = intel_lvds_set_property,
79e53945
JB
489 .destroy = intel_lvds_destroy,
490};
491
79e53945 492static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 493 .destroy = intel_encoder_destroy,
79e53945
JB
494};
495
425d244c
JW
496static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
497{
bc0daf48 498 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
499 return 1;
500}
79e53945 501
425d244c 502/* These systems claim to have LVDS, but really don't */
93c05f22 503static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
504 {
505 .callback = intel_no_lvds_dmi_callback,
506 .ident = "Apple Mac Mini (Core series)",
507 .matches = {
98acd46f 508 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
509 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
510 },
511 },
512 {
513 .callback = intel_no_lvds_dmi_callback,
514 .ident = "Apple Mac Mini (Core 2 series)",
515 .matches = {
98acd46f 516 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
517 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
518 },
519 },
520 {
521 .callback = intel_no_lvds_dmi_callback,
522 .ident = "MSI IM-945GSE-A",
523 .matches = {
524 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
525 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
526 },
527 },
528 {
529 .callback = intel_no_lvds_dmi_callback,
530 .ident = "Dell Studio Hybrid",
531 .matches = {
532 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
533 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
534 },
535 },
70aa96ca
JW
536 {
537 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
538 .ident = "Dell OptiPlex FX170",
539 .matches = {
540 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
541 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
542 },
543 },
544 {
545 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
546 .ident = "AOpen Mini PC",
547 .matches = {
548 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
549 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
550 },
551 },
ed8c754b
TV
552 {
553 .callback = intel_no_lvds_dmi_callback,
554 .ident = "AOpen Mini PC MP915",
555 .matches = {
556 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
557 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
558 },
559 },
22ab70d3
KP
560 {
561 .callback = intel_no_lvds_dmi_callback,
562 .ident = "AOpen i915GMm-HFS",
563 .matches = {
564 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
565 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
566 },
567 },
e57b6886
DV
568 {
569 .callback = intel_no_lvds_dmi_callback,
570 .ident = "AOpen i45GMx-I",
571 .matches = {
572 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
573 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
574 },
575 },
fa0864b2
MC
576 {
577 .callback = intel_no_lvds_dmi_callback,
578 .ident = "Aopen i945GTt-VFA",
579 .matches = {
580 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
581 },
582 },
9875557e
SB
583 {
584 .callback = intel_no_lvds_dmi_callback,
585 .ident = "Clientron U800",
586 .matches = {
587 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
588 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
589 },
590 },
6a574b5b 591 {
44306ab3
JS
592 .callback = intel_no_lvds_dmi_callback,
593 .ident = "Clientron E830",
594 .matches = {
595 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
596 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
597 },
598 },
599 {
6a574b5b
HG
600 .callback = intel_no_lvds_dmi_callback,
601 .ident = "Asus EeeBox PC EB1007",
602 .matches = {
603 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
604 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
605 },
606 },
0999bbe0
AJ
607 {
608 .callback = intel_no_lvds_dmi_callback,
609 .ident = "Asus AT5NM10T-I",
610 .matches = {
611 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
612 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
613 },
614 },
33471119
JBG
615 {
616 .callback = intel_no_lvds_dmi_callback,
617 .ident = "Hewlett-Packard HP t5740e Thin Client",
618 .matches = {
619 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
620 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
621 },
622 },
f5b8a7ed
MG
623 {
624 .callback = intel_no_lvds_dmi_callback,
625 .ident = "Hewlett-Packard t5745",
626 .matches = {
627 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 628 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
629 },
630 },
631 {
632 .callback = intel_no_lvds_dmi_callback,
633 .ident = "Hewlett-Packard st5747",
634 .matches = {
635 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 636 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
637 },
638 },
97effadb
AA
639 {
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "MSI Wind Box DC500",
642 .matches = {
643 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
644 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
645 },
646 },
a51d4ed0
CW
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "Gigabyte GA-D525TUD",
650 .matches = {
651 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
652 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
653 },
654 },
c31407a3
CW
655 {
656 .callback = intel_no_lvds_dmi_callback,
657 .ident = "Supermicro X7SPA-H",
658 .matches = {
659 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
660 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
661 },
662 },
9e9dd0e8
CL
663 {
664 .callback = intel_no_lvds_dmi_callback,
665 .ident = "Fujitsu Esprimo Q900",
666 .matches = {
667 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
668 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
669 },
670 },
425d244c
JW
671
672 { } /* terminating entry */
673};
79e53945 674
18f9ed12
ZY
675/**
676 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
677 * @dev: drm device
678 * @connector: LVDS connector
679 *
680 * Find the reduced downclock for LVDS in EDID.
681 */
682static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
683 struct drm_display_mode *fixed_mode,
684 struct drm_connector *connector)
18f9ed12
ZY
685{
686 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 687 struct drm_display_mode *scan;
18f9ed12
ZY
688 int temp_downclock;
689
788319d4 690 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
691 list_for_each_entry(scan, &connector->probed_modes, head) {
692 /*
693 * If one mode has the same resolution with the fixed_panel
694 * mode while they have the different refresh rate, it means
695 * that the reduced downclock is found for the LVDS. In such
696 * case we can set the different FPx0/1 to dynamically select
697 * between low and high frequency.
698 */
788319d4
CW
699 if (scan->hdisplay == fixed_mode->hdisplay &&
700 scan->hsync_start == fixed_mode->hsync_start &&
701 scan->hsync_end == fixed_mode->hsync_end &&
702 scan->htotal == fixed_mode->htotal &&
703 scan->vdisplay == fixed_mode->vdisplay &&
704 scan->vsync_start == fixed_mode->vsync_start &&
705 scan->vsync_end == fixed_mode->vsync_end &&
706 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
707 if (scan->clock < temp_downclock) {
708 /*
709 * The downclock is already found. But we
710 * expect to find the lower downclock.
711 */
712 temp_downclock = scan->clock;
713 }
714 }
715 }
788319d4 716 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
717 /* We found the downclock for LVDS. */
718 dev_priv->lvds_downclock_avail = 1;
719 dev_priv->lvds_downclock = temp_downclock;
720 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
721 "Normal clock %dKhz, downclock %dKhz\n",
722 fixed_mode->clock, temp_downclock);
18f9ed12 723 }
18f9ed12
ZY
724}
725
7cf4f69d
ZY
726/*
727 * Enumerate the child dev array parsed from VBT to check whether
728 * the LVDS is present.
729 * If it is present, return 1.
730 * If it is not present, return false.
731 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 732 */
270eea0f
CW
733static bool lvds_is_present_in_vbt(struct drm_device *dev,
734 u8 *i2c_pin)
7cf4f69d
ZY
735{
736 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 737 int i;
7cf4f69d 738
41aa3448 739 if (!dev_priv->vbt.child_dev_num)
425904dd 740 return true;
7cf4f69d 741
41aa3448
RV
742 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
743 struct child_device_config *child = dev_priv->vbt.child_dev + i;
425904dd
CW
744
745 /* If the device type is not LFP, continue.
746 * We have to check both the new identifiers as well as the
747 * old for compatibility with some BIOSes.
7cf4f69d 748 */
425904dd
CW
749 if (child->device_type != DEVICE_TYPE_INT_LFP &&
750 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
751 continue;
752
3bd7d909
DK
753 if (intel_gmbus_is_port_valid(child->i2c_pin))
754 *i2c_pin = child->i2c_pin;
270eea0f 755
425904dd
CW
756 /* However, we cannot trust the BIOS writers to populate
757 * the VBT correctly. Since LVDS requires additional
758 * information from AIM blocks, a non-zero addin offset is
759 * a good indicator that the LVDS is actually present.
7cf4f69d 760 */
425904dd
CW
761 if (child->addin_offset)
762 return true;
763
764 /* But even then some BIOS writers perform some black magic
765 * and instantiate the device without reference to any
766 * additional data. Trust that if the VBT was written into
767 * the OpRegion then they have validated the LVDS's existence.
768 */
769 if (dev_priv->opregion.vbt)
770 return true;
7cf4f69d 771 }
425904dd
CW
772
773 return false;
7cf4f69d
ZY
774}
775
1974cad0
DV
776static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
777{
778 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
779 return 1;
780}
781
782static const struct dmi_system_id intel_dual_link_lvds[] = {
783 {
784 .callback = intel_dual_link_lvds_callback,
785 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
786 .matches = {
787 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
788 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
789 },
790 },
791 { } /* terminating entry */
792};
793
794bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
795{
796 struct intel_encoder *encoder;
797 struct intel_lvds_encoder *lvds_encoder;
798
799 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
800 base.head) {
801 if (encoder->type == INTEL_OUTPUT_LVDS) {
802 lvds_encoder = to_lvds_encoder(&encoder->base);
803
804 return lvds_encoder->is_dual_link;
805 }
806 }
807
808 return false;
809}
810
7dec0606 811static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 812{
7dec0606 813 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
814 unsigned int val;
815 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
816
817 /* use the module option value if specified */
818 if (i915_lvds_channel_mode > 0)
819 return i915_lvds_channel_mode == 2;
820
821 if (dmi_check_system(intel_dual_link_lvds))
822 return true;
823
13c7d870
DV
824 /* BIOS should set the proper LVDS register value at boot, but
825 * in reality, it doesn't set the value when the lid is closed;
826 * we need to check "the value to be set" in VBT when LVDS
827 * register is uninitialized.
828 */
7dec0606 829 val = I915_READ(lvds_encoder->reg);
13c7d870 830 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 831 val = dev_priv->vbt.bios_lvds_val;
13c7d870 832
1974cad0
DV
833 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
834}
835
f3cfcba6
CW
836static bool intel_lvds_supported(struct drm_device *dev)
837{
838 /* With the introduction of the PCH we gained a dedicated
839 * LVDS presence pin, use it. */
311e359c 840 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
841 return true;
842
843 /* Otherwise LVDS was only attached to mobile products,
844 * except for the inglorious 830gm */
311e359c
PZ
845 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
846 return true;
847
848 return false;
f3cfcba6
CW
849}
850
79e53945
JB
851/**
852 * intel_lvds_init - setup LVDS connectors on this device
853 * @dev: drm device
854 *
855 * Create the connector, register the LVDS DDC bus, and try to figure out what
856 * modes we can display on the LVDS panel (if present).
857 */
c5d1b51d 858bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 861 struct intel_lvds_encoder *lvds_encoder;
21d40d37 862 struct intel_encoder *intel_encoder;
c7362c4d 863 struct intel_lvds_connector *lvds_connector;
bb8a3560 864 struct intel_connector *intel_connector;
79e53945
JB
865 struct drm_connector *connector;
866 struct drm_encoder *encoder;
867 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 868 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 869 struct edid *edid;
79e53945
JB
870 struct drm_crtc *crtc;
871 u32 lvds;
270eea0f
CW
872 int pipe;
873 u8 pin;
79e53945 874
f3cfcba6
CW
875 if (!intel_lvds_supported(dev))
876 return false;
877
425d244c
JW
878 /* Skip init on machines we know falsely report LVDS */
879 if (dmi_check_system(intel_no_lvds))
c5d1b51d 880 return false;
565dcd46 881
270eea0f
CW
882 pin = GMBUS_PORT_PANEL;
883 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 884 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 885 return false;
38b3037e 886 }
e99da35f 887
c619eed4 888 if (HAS_PCH_SPLIT(dev)) {
541998a1 889 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 890 return false;
41aa3448 891 if (dev_priv->vbt.edp_support) {
28c97730 892 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 893 return false;
32f9d658 894 }
541998a1
ZW
895 }
896
29b99b48
JN
897 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
898 if (!lvds_encoder)
c5d1b51d 899 return false;
79e53945 900
c7362c4d
JN
901 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
902 if (!lvds_connector) {
29b99b48 903 kfree(lvds_encoder);
c5d1b51d 904 return false;
bb8a3560
ZW
905 }
906
62165e0d
JN
907 lvds_encoder->attached_connector = lvds_connector;
908
29b99b48 909 intel_encoder = &lvds_encoder->base;
4ef69c7a 910 encoder = &intel_encoder->base;
c7362c4d 911 intel_connector = &lvds_connector->base;
ea5b213a 912 connector = &intel_connector->base;
bb8a3560 913 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
914 DRM_MODE_CONNECTOR_LVDS);
915
4ef69c7a 916 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
917 DRM_MODE_ENCODER_LVDS);
918
c22834ec 919 intel_encoder->enable = intel_enable_lvds;
fc683091 920 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
7ae89233 921 intel_encoder->compute_config = intel_lvds_compute_config;
c22834ec 922 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
923 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
924 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 925
df0e9248 926 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 927 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 928
66a9278e 929 intel_encoder->cloneable = false;
27f8227b
JB
930 if (HAS_PCH_SPLIT(dev))
931 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
932 else if (IS_GEN4(dev))
933 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
934 else
935 intel_encoder->crtc_mask = (1 << 1);
936
79e53945
JB
937 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
938 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
939 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
940 connector->interlace_allowed = false;
941 connector->doublescan_allowed = false;
942
7dec0606
DV
943 if (HAS_PCH_SPLIT(dev)) {
944 lvds_encoder->reg = PCH_LVDS;
945 } else {
946 lvds_encoder->reg = LVDS;
947 }
948
3fbe18d6
ZY
949 /* create the scaling mode property */
950 drm_mode_create_scaling_mode_property(dev);
662595df 951 drm_object_attach_property(&connector->base,
3fbe18d6 952 dev->mode_config.scaling_mode_property,
dd1ea37d 953 DRM_MODE_SCALE_ASPECT);
4d891523 954 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
955 /*
956 * LVDS discovery:
957 * 1) check for EDID on DDC
958 * 2) check for VBT data
959 * 3) check to see if LVDS is already on
960 * if none of the above, no panel
961 * 4) make sure lid is open
962 * if closed, act like it's not there for now
963 */
964
79e53945
JB
965 /*
966 * Attempt to get the fixed panel mode from DDC. Assume that the
967 * preferred mode is the right one.
968 */
9cd300e0
JN
969 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
970 if (edid) {
971 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 972 drm_mode_connector_update_edid_property(connector,
9cd300e0 973 edid);
3f8ff0e7 974 } else {
9cd300e0
JN
975 kfree(edid);
976 edid = ERR_PTR(-EINVAL);
3f8ff0e7 977 }
9cd300e0
JN
978 } else {
979 edid = ERR_PTR(-ENOENT);
3f8ff0e7 980 }
9cd300e0
JN
981 lvds_connector->base.edid = edid;
982
983 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
984 /* Didn't get an EDID, so
985 * Set wide sync ranges so we get all modes
986 * handed to valid_mode for checking
987 */
988 connector->display_info.min_vfreq = 0;
989 connector->display_info.max_vfreq = 200;
990 connector->display_info.min_hfreq = 0;
991 connector->display_info.max_hfreq = 200;
992 }
79e53945
JB
993
994 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 995 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
996 DRM_DEBUG_KMS("using preferred mode from EDID: ");
997 drm_mode_debug_printmodeline(scan);
998
dd06f90e 999 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1000 if (fixed_mode) {
1001 intel_find_lvds_downclock(dev, fixed_mode,
1002 connector);
1003 goto out;
1004 }
79e53945 1005 }
79e53945
JB
1006 }
1007
1008 /* Failed to get EDID, what about VBT? */
41aa3448 1009 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1010 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1011 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1012
41aa3448 1013 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1014 if (fixed_mode) {
1015 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1016 goto out;
1017 }
79e53945
JB
1018 }
1019
1020 /*
1021 * If we didn't get EDID, try checking if the panel is already turned
1022 * on. If so, assume that whatever is currently programmed is the
1023 * correct mode.
1024 */
541998a1 1025
f2b115e6 1026 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1027 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1028 goto failed;
1029
79e53945
JB
1030 lvds = I915_READ(LVDS);
1031 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1032 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1033
1034 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1035 fixed_mode = intel_crtc_mode_get(dev, crtc);
1036 if (fixed_mode) {
6a9d51b7
CW
1037 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1038 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1039 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1040 goto out;
79e53945
JB
1041 }
1042 }
1043
1044 /* If we still don't have a mode after all that, give up. */
dd06f90e 1045 if (!fixed_mode)
79e53945
JB
1046 goto failed;
1047
79e53945 1048out:
7dec0606 1049 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1050 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1051 lvds_encoder->is_dual_link ? "dual" : "single");
1052
24ded204
DV
1053 /*
1054 * Unlock registers and just
1055 * leave them unlocked
1056 */
c619eed4 1057 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1058 I915_WRITE(PCH_PP_CONTROL,
1059 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1060 } else {
ed10fca9
KP
1061 I915_WRITE(PP_CONTROL,
1062 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1063 }
db1740a0
JN
1064 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1065 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1066 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1067 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1068 }
79e53945 1069 drm_sysfs_connector_add(connector);
aaa6fd2a 1070
dd06f90e 1071 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1072 intel_panel_setup_backlight(connector);
aaa6fd2a 1073
c5d1b51d 1074 return true;
79e53945
JB
1075
1076failed:
8a4c47f3 1077 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1078 drm_connector_cleanup(connector);
1991bdfa 1079 drm_encoder_cleanup(encoder);
dd06f90e
JN
1080 if (fixed_mode)
1081 drm_mode_destroy(dev, fixed_mode);
29b99b48 1082 kfree(lvds_encoder);
c7362c4d 1083 kfree(lvds_connector);
c5d1b51d 1084 return false;
79e53945 1085}
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