Merge tag 'drm-intel-next-2013-09-21-merged' of git://people.freedesktop.org/~danvet...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
045ac3b5
JB
89static void intel_lvds_get_config(struct intel_encoder *encoder,
90 struct intel_crtc_config *pipe_config)
91{
92 struct drm_device *dev = encoder->base.dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 u32 lvds_reg, tmp, flags = 0;
18442d08 95 int dotclock;
045ac3b5
JB
96
97 if (HAS_PCH_SPLIT(dev))
98 lvds_reg = PCH_LVDS;
99 else
100 lvds_reg = LVDS;
101
102 tmp = I915_READ(lvds_reg);
103 if (tmp & LVDS_HSYNC_POLARITY)
104 flags |= DRM_MODE_FLAG_NHSYNC;
105 else
106 flags |= DRM_MODE_FLAG_PHSYNC;
107 if (tmp & LVDS_VSYNC_POLARITY)
108 flags |= DRM_MODE_FLAG_NVSYNC;
109 else
110 flags |= DRM_MODE_FLAG_PVSYNC;
111
112 pipe_config->adjusted_mode.flags |= flags;
06922821
DV
113
114 /* gen2/3 store dither state in pfit control, needs to match */
115 if (INTEL_INFO(dev)->gen < 4) {
116 tmp = I915_READ(PFIT_CONTROL);
117
118 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
119 }
18442d08
VS
120
121 dotclock = pipe_config->port_clock;
122
123 if (HAS_PCH_SPLIT(dev_priv->dev))
124 ironlake_check_encoder_dotclock(pipe_config, dotclock);
125
126 pipe_config->adjusted_mode.clock = dotclock;
045ac3b5
JB
127}
128
fc683091
DV
129/* The LVDS pin pair needs to be on before the DPLLs are enabled.
130 * This is an exception to the general rule that mode_set doesn't turn
131 * things on.
132 */
f6736a1a 133static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
134{
135 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
136 struct drm_device *dev = encoder->base.dev;
137 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 138 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4c6df4b4
VS
139 const struct drm_display_mode *adjusted_mode =
140 &crtc->config.adjusted_mode;
55607e8a 141 int pipe = crtc->pipe;
fc683091
DV
142 u32 temp;
143
55607e8a
DV
144 if (HAS_PCH_SPLIT(dev)) {
145 assert_fdi_rx_pll_disabled(dev_priv, pipe);
146 assert_shared_dpll_disabled(dev_priv,
147 intel_crtc_to_shared_dpll(crtc));
148 } else {
149 assert_pll_disabled(dev_priv, pipe);
150 }
151
fc683091
DV
152 temp = I915_READ(lvds_encoder->reg);
153 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
154
155 if (HAS_PCH_CPT(dev)) {
156 temp &= ~PORT_TRANS_SEL_MASK;
157 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 158 } else {
62810e5a
DV
159 if (pipe == 1) {
160 temp |= LVDS_PIPEB_SELECT;
161 } else {
162 temp &= ~LVDS_PIPEB_SELECT;
163 }
fc683091 164 }
62810e5a 165
fc683091 166 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 167 temp &= ~LVDS_BORDER_ENABLE;
55607e8a 168 temp |= crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
169 /* Set the B0-B3 data pairs corresponding to whether we're going to
170 * set the DPLLs for dual-channel mode or not.
171 */
172 if (lvds_encoder->is_dual_link)
173 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
174 else
175 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
176
177 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
178 * appropriately here, but we need to look more thoroughly into how
179 * panels behave in the two modes.
180 */
62810e5a
DV
181
182 /* Set the dithering flag on LVDS as needed, note that there is no
183 * special lvds dither control bit on pch-split platforms, dithering is
184 * only controlled through the PIPECONF reg. */
185 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
186 /* Bspec wording suggests that LVDS port dithering only exists
187 * for 18bpp panels. */
55607e8a 188 if (crtc->config.dither && crtc->config.pipe_bpp == 18)
fc683091
DV
189 temp |= LVDS_ENABLE_DITHER;
190 else
191 temp &= ~LVDS_ENABLE_DITHER;
192 }
193 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 194 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 195 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 196 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
197 temp |= LVDS_VSYNC_POLARITY;
198
199 I915_WRITE(lvds_encoder->reg, temp);
200}
201
79e53945
JB
202/**
203 * Sets the power state for the panel.
204 */
c22834ec 205static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 206{
c22834ec 207 struct drm_device *dev = encoder->base.dev;
29b99b48 208 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 209 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 210 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 211 u32 ctl_reg, stat_reg;
541998a1 212
c619eed4 213 if (HAS_PCH_SPLIT(dev)) {
541998a1 214 ctl_reg = PCH_PP_CONTROL;
de842eff 215 stat_reg = PCH_PP_STATUS;
541998a1
ZW
216 } else {
217 ctl_reg = PP_CONTROL;
de842eff 218 stat_reg = PP_STATUS;
541998a1 219 }
79e53945 220
7dec0606 221 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 222
2a1292fd 223 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 224 POSTING_READ(lvds_encoder->reg);
de842eff
KP
225 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
226 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 227
24ded204 228 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
229}
230
c22834ec 231static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 232{
c22834ec 233 struct drm_device *dev = encoder->base.dev;
29b99b48 234 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 235 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 236 u32 ctl_reg, stat_reg;
2a1292fd
CW
237
238 if (HAS_PCH_SPLIT(dev)) {
239 ctl_reg = PCH_PP_CONTROL;
de842eff 240 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
241 } else {
242 ctl_reg = PP_CONTROL;
de842eff 243 stat_reg = PP_STATUS;
2a1292fd
CW
244 }
245
47356eb6 246 intel_panel_disable_backlight(dev);
2a1292fd
CW
247
248 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
249 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
250 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 251
7dec0606
DV
252 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
253 POSTING_READ(lvds_encoder->reg);
79e53945
JB
254}
255
79e53945
JB
256static int intel_lvds_mode_valid(struct drm_connector *connector,
257 struct drm_display_mode *mode)
258{
dd06f90e
JN
259 struct intel_connector *intel_connector = to_intel_connector(connector);
260 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 261
788319d4
CW
262 if (mode->hdisplay > fixed_mode->hdisplay)
263 return MODE_PANEL;
264 if (mode->vdisplay > fixed_mode->vdisplay)
265 return MODE_PANEL;
79e53945
JB
266
267 return MODE_OK;
268}
269
7ae89233
DV
270static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
271 struct intel_crtc_config *pipe_config)
79e53945 272{
7ae89233 273 struct drm_device *dev = intel_encoder->base.dev;
79e53945 274 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
275 struct intel_lvds_encoder *lvds_encoder =
276 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
277 struct intel_connector *intel_connector =
278 &lvds_encoder->attached_connector->base;
7ae89233 279 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 280 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 281 unsigned int lvds_bpp;
79e53945
JB
282
283 /* Should never happen!! */
a6c45cf0 284 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 285 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
286 return false;
287 }
288
4e53c2e0
DV
289 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
290 LVDS_A3_POWER_UP)
291 lvds_bpp = 8*3;
292 else
293 lvds_bpp = 6*3;
294
e29c22c0 295 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
296 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
297 pipe_config->pipe_bpp, lvds_bpp);
298 pipe_config->pipe_bpp = lvds_bpp;
299 }
d8b32247 300
79e53945 301 /*
71677043 302 * We have timings from the BIOS for the panel, put them in
79e53945
JB
303 * to the adjusted mode. The CRTC will be set up for this mode,
304 * with the panel scaling set up to source from the H/VDisplay
305 * of the original mode.
306 */
4d891523 307 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 308 adjusted_mode);
1d8e1c75
CW
309
310 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
311 pipe_config->has_pch_encoder = true;
312
b074cec8
JB
313 intel_pch_panel_fitting(intel_crtc, pipe_config,
314 intel_connector->panel.fitting_mode);
2dd24552
JB
315 } else {
316 intel_gmch_panel_fitting(intel_crtc, pipe_config,
317 intel_connector->panel.fitting_mode);
79e53945 318
21d8a475 319 }
f9bef081 320
79e53945
JB
321 /*
322 * XXX: It would be nice to support lower refresh rates on the
323 * panels to reduce power consumption, and perhaps match the
324 * user's requested refresh rate.
325 */
326
327 return true;
328}
329
66df24d9 330static void intel_lvds_mode_set(struct intel_encoder *encoder)
79e53945 331{
79e53945 332 /*
66df24d9
DV
333 * We don't do anything here, the LVDS port is fully set up in the pre
334 * enable hook - the ordering constraints for enabling the lvds port vs.
335 * enabling the display pll are too strict.
79e53945 336 */
79e53945
JB
337}
338
339/**
340 * Detect the LVDS connection.
341 *
b42d4c5c
JB
342 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
343 * connected and closed means disconnected. We also send hotplug events as
344 * needed, using lid status notification from the input layer.
79e53945 345 */
7b334fcb 346static enum drm_connector_status
930a9e28 347intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 348{
7b9c5abe 349 struct drm_device *dev = connector->dev;
6ee3b5a1 350 enum drm_connector_status status;
b42d4c5c 351
164c8598
CW
352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
353 connector->base.id, drm_get_connector_name(connector));
354
fe16d949
CW
355 status = intel_panel_detect(dev);
356 if (status != connector_status_unknown)
357 return status;
01fe9dbd 358
6ee3b5a1 359 return connector_status_connected;
79e53945
JB
360}
361
362/**
363 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
364 */
365static int intel_lvds_get_modes(struct drm_connector *connector)
366{
62165e0d 367 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 368 struct drm_device *dev = connector->dev;
788319d4 369 struct drm_display_mode *mode;
79e53945 370
9cd300e0 371 /* use cached edid if we have one */
2aa4f099 372 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 373 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 374
dd06f90e 375 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 376 if (mode == NULL)
788319d4 377 return 0;
79e53945 378
788319d4
CW
379 drm_mode_probed_add(connector, mode);
380 return 1;
79e53945
JB
381}
382
0544edfd
TB
383static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
384{
bc0daf48 385 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
386 return 1;
387}
388
389/* The GPU hangs up on these systems if modeset is performed on LID open */
390static const struct dmi_system_id intel_no_modeset_on_lid[] = {
391 {
392 .callback = intel_no_modeset_on_lid_dmi_callback,
393 .ident = "Toshiba Tecra A11",
394 .matches = {
395 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
396 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
397 },
398 },
399
400 { } /* terminating entry */
401};
402
c9354c85 403/*
b8efb17b
ZR
404 * Lid events. Note the use of 'modeset':
405 * - we set it to MODESET_ON_LID_OPEN on lid close,
406 * and set it to MODESET_DONE on open
c9354c85 407 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
408 * duplicate events where it was already properly set)
409 * - the suspend/resume paths will set it to
410 * MODESET_SUSPENDED and ignore the lid open event,
411 * because they restore the mode ("lid open").
c9354c85 412 */
c1c7af60
JB
413static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
414 void *unused)
415{
db1740a0
JN
416 struct intel_lvds_connector *lvds_connector =
417 container_of(nb, struct intel_lvds_connector, lid_notifier);
418 struct drm_connector *connector = &lvds_connector->base.base;
419 struct drm_device *dev = connector->dev;
420 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 421
2fb4e61d
AW
422 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
423 return NOTIFY_OK;
424
b8efb17b
ZR
425 mutex_lock(&dev_priv->modeset_restore_lock);
426 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
427 goto exit;
a2565377
ZY
428 /*
429 * check and update the status of LVDS connector after receiving
430 * the LID nofication event.
431 */
db1740a0 432 connector->status = connector->funcs->detect(connector, false);
7b334fcb 433
0544edfd
TB
434 /* Don't force modeset on machines where it causes a GPU lockup */
435 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 436 goto exit;
c9354c85 437 if (!acpi_lid_open()) {
b8efb17b
ZR
438 /* do modeset on next lid open event */
439 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
440 goto exit;
06891e27 441 }
c1c7af60 442
b8efb17b
ZR
443 if (dev_priv->modeset_restore == MODESET_DONE)
444 goto exit;
c9354c85 445
a0e99e68 446 drm_modeset_lock_all(dev);
45e2b5f6 447 intel_modeset_setup_hw_state(dev, true);
a0e99e68 448 drm_modeset_unlock_all(dev);
06324194 449
b8efb17b
ZR
450 dev_priv->modeset_restore = MODESET_DONE;
451
452exit:
453 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
454 return NOTIFY_OK;
455}
456
79e53945
JB
457/**
458 * intel_lvds_destroy - unregister and free LVDS structures
459 * @connector: connector to free
460 *
461 * Unregister the DDC bus for this connector then free the driver private
462 * structure.
463 */
464static void intel_lvds_destroy(struct drm_connector *connector)
465{
db1740a0
JN
466 struct intel_lvds_connector *lvds_connector =
467 to_lvds_connector(connector);
79e53945 468
db1740a0
JN
469 if (lvds_connector->lid_notifier.notifier_call)
470 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 471
9cd300e0
JN
472 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
473 kfree(lvds_connector->base.edid);
474
1d508706 475 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 476
79e53945
JB
477 drm_sysfs_connector_remove(connector);
478 drm_connector_cleanup(connector);
479 kfree(connector);
480}
481
335041ed
JB
482static int intel_lvds_set_property(struct drm_connector *connector,
483 struct drm_property *property,
484 uint64_t value)
485{
4d891523 486 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 487 struct drm_device *dev = connector->dev;
3fbe18d6 488
788319d4 489 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 490 struct drm_crtc *crtc;
bb8a3560 491
53bd8389
JB
492 if (value == DRM_MODE_SCALE_NONE) {
493 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 494 return -EINVAL;
3fbe18d6 495 }
788319d4 496
4d891523 497 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
498 /* the LVDS scaling property is not changed */
499 return 0;
500 }
4d891523 501 intel_connector->panel.fitting_mode = value;
62165e0d
JN
502
503 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
504 if (crtc && crtc->enabled) {
505 /*
506 * If the CRTC is enabled, the display will be changed
507 * according to the new panel fitting mode.
508 */
c0c36b94 509 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
510 }
511 }
512
335041ed
JB
513 return 0;
514}
515
79e53945
JB
516static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
517 .get_modes = intel_lvds_get_modes,
518 .mode_valid = intel_lvds_mode_valid,
df0e9248 519 .best_encoder = intel_best_encoder,
79e53945
JB
520};
521
522static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 523 .dpms = intel_connector_dpms,
79e53945
JB
524 .detect = intel_lvds_detect,
525 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 526 .set_property = intel_lvds_set_property,
79e53945
JB
527 .destroy = intel_lvds_destroy,
528};
529
79e53945 530static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 531 .destroy = intel_encoder_destroy,
79e53945
JB
532};
533
425d244c
JW
534static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
535{
bc0daf48 536 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
537 return 1;
538}
79e53945 539
425d244c 540/* These systems claim to have LVDS, but really don't */
93c05f22 541static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
542 {
543 .callback = intel_no_lvds_dmi_callback,
544 .ident = "Apple Mac Mini (Core series)",
545 .matches = {
98acd46f 546 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
547 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
548 },
549 },
550 {
551 .callback = intel_no_lvds_dmi_callback,
552 .ident = "Apple Mac Mini (Core 2 series)",
553 .matches = {
98acd46f 554 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
555 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
556 },
557 },
558 {
559 .callback = intel_no_lvds_dmi_callback,
560 .ident = "MSI IM-945GSE-A",
561 .matches = {
562 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
563 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
564 },
565 },
566 {
567 .callback = intel_no_lvds_dmi_callback,
568 .ident = "Dell Studio Hybrid",
569 .matches = {
570 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
571 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
572 },
573 },
70aa96ca
JW
574 {
575 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
576 .ident = "Dell OptiPlex FX170",
577 .matches = {
578 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
579 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
580 },
581 },
582 {
583 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
584 .ident = "AOpen Mini PC",
585 .matches = {
586 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
587 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
588 },
589 },
ed8c754b
TV
590 {
591 .callback = intel_no_lvds_dmi_callback,
592 .ident = "AOpen Mini PC MP915",
593 .matches = {
594 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
595 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
596 },
597 },
22ab70d3
KP
598 {
599 .callback = intel_no_lvds_dmi_callback,
600 .ident = "AOpen i915GMm-HFS",
601 .matches = {
602 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
603 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
604 },
605 },
e57b6886
DV
606 {
607 .callback = intel_no_lvds_dmi_callback,
608 .ident = "AOpen i45GMx-I",
609 .matches = {
610 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
611 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
612 },
613 },
fa0864b2
MC
614 {
615 .callback = intel_no_lvds_dmi_callback,
616 .ident = "Aopen i945GTt-VFA",
617 .matches = {
618 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
619 },
620 },
9875557e
SB
621 {
622 .callback = intel_no_lvds_dmi_callback,
623 .ident = "Clientron U800",
624 .matches = {
625 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
626 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
627 },
628 },
6a574b5b 629 {
44306ab3
JS
630 .callback = intel_no_lvds_dmi_callback,
631 .ident = "Clientron E830",
632 .matches = {
633 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
634 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
635 },
636 },
637 {
6a574b5b
HG
638 .callback = intel_no_lvds_dmi_callback,
639 .ident = "Asus EeeBox PC EB1007",
640 .matches = {
641 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
642 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
643 },
644 },
0999bbe0
AJ
645 {
646 .callback = intel_no_lvds_dmi_callback,
647 .ident = "Asus AT5NM10T-I",
648 .matches = {
649 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
650 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
651 },
652 },
33471119
JBG
653 {
654 .callback = intel_no_lvds_dmi_callback,
45a211d7 655 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
656 .matches = {
657 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 658 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
659 },
660 },
f5b8a7ed
MG
661 {
662 .callback = intel_no_lvds_dmi_callback,
663 .ident = "Hewlett-Packard t5745",
664 .matches = {
665 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 666 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
667 },
668 },
669 {
670 .callback = intel_no_lvds_dmi_callback,
671 .ident = "Hewlett-Packard st5747",
672 .matches = {
673 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 674 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
675 },
676 },
97effadb
AA
677 {
678 .callback = intel_no_lvds_dmi_callback,
679 .ident = "MSI Wind Box DC500",
680 .matches = {
681 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
682 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
683 },
684 },
a51d4ed0
CW
685 {
686 .callback = intel_no_lvds_dmi_callback,
687 .ident = "Gigabyte GA-D525TUD",
688 .matches = {
689 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
690 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
691 },
692 },
c31407a3
CW
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "Supermicro X7SPA-H",
696 .matches = {
697 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
698 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
699 },
700 },
9e9dd0e8
CL
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Fujitsu Esprimo Q900",
704 .matches = {
705 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
706 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
707 },
708 },
e5614f0c
CW
709 {
710 .callback = intel_no_lvds_dmi_callback,
711 .ident = "Intel D510MO",
712 .matches = {
713 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
714 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
715 },
716 },
dcf6d294
JN
717 {
718 .callback = intel_no_lvds_dmi_callback,
719 .ident = "Intel D525MW",
720 .matches = {
721 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
722 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
723 },
724 },
425d244c
JW
725
726 { } /* terminating entry */
727};
79e53945 728
18f9ed12
ZY
729/**
730 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
731 * @dev: drm device
732 * @connector: LVDS connector
733 *
734 * Find the reduced downclock for LVDS in EDID.
735 */
736static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
737 struct drm_display_mode *fixed_mode,
738 struct drm_connector *connector)
18f9ed12
ZY
739{
740 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 741 struct drm_display_mode *scan;
18f9ed12
ZY
742 int temp_downclock;
743
788319d4 744 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
745 list_for_each_entry(scan, &connector->probed_modes, head) {
746 /*
747 * If one mode has the same resolution with the fixed_panel
748 * mode while they have the different refresh rate, it means
749 * that the reduced downclock is found for the LVDS. In such
750 * case we can set the different FPx0/1 to dynamically select
751 * between low and high frequency.
752 */
788319d4
CW
753 if (scan->hdisplay == fixed_mode->hdisplay &&
754 scan->hsync_start == fixed_mode->hsync_start &&
755 scan->hsync_end == fixed_mode->hsync_end &&
756 scan->htotal == fixed_mode->htotal &&
757 scan->vdisplay == fixed_mode->vdisplay &&
758 scan->vsync_start == fixed_mode->vsync_start &&
759 scan->vsync_end == fixed_mode->vsync_end &&
760 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
761 if (scan->clock < temp_downclock) {
762 /*
763 * The downclock is already found. But we
764 * expect to find the lower downclock.
765 */
766 temp_downclock = scan->clock;
767 }
768 }
769 }
788319d4 770 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
771 /* We found the downclock for LVDS. */
772 dev_priv->lvds_downclock_avail = 1;
773 dev_priv->lvds_downclock = temp_downclock;
774 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
775 "Normal clock %dKhz, downclock %dKhz\n",
776 fixed_mode->clock, temp_downclock);
18f9ed12 777 }
18f9ed12
ZY
778}
779
7cf4f69d
ZY
780/*
781 * Enumerate the child dev array parsed from VBT to check whether
782 * the LVDS is present.
783 * If it is present, return 1.
784 * If it is not present, return false.
785 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 786 */
270eea0f
CW
787static bool lvds_is_present_in_vbt(struct drm_device *dev,
788 u8 *i2c_pin)
7cf4f69d
ZY
789{
790 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 791 int i;
7cf4f69d 792
41aa3448 793 if (!dev_priv->vbt.child_dev_num)
425904dd 794 return true;
7cf4f69d 795
41aa3448
RV
796 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
797 struct child_device_config *child = dev_priv->vbt.child_dev + i;
425904dd
CW
798
799 /* If the device type is not LFP, continue.
800 * We have to check both the new identifiers as well as the
801 * old for compatibility with some BIOSes.
7cf4f69d 802 */
425904dd
CW
803 if (child->device_type != DEVICE_TYPE_INT_LFP &&
804 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
805 continue;
806
3bd7d909
DK
807 if (intel_gmbus_is_port_valid(child->i2c_pin))
808 *i2c_pin = child->i2c_pin;
270eea0f 809
425904dd
CW
810 /* However, we cannot trust the BIOS writers to populate
811 * the VBT correctly. Since LVDS requires additional
812 * information from AIM blocks, a non-zero addin offset is
813 * a good indicator that the LVDS is actually present.
7cf4f69d 814 */
425904dd
CW
815 if (child->addin_offset)
816 return true;
817
818 /* But even then some BIOS writers perform some black magic
819 * and instantiate the device without reference to any
820 * additional data. Trust that if the VBT was written into
821 * the OpRegion then they have validated the LVDS's existence.
822 */
823 if (dev_priv->opregion.vbt)
824 return true;
7cf4f69d 825 }
425904dd
CW
826
827 return false;
7cf4f69d
ZY
828}
829
1974cad0
DV
830static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
831{
832 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
833 return 1;
834}
835
836static const struct dmi_system_id intel_dual_link_lvds[] = {
837 {
838 .callback = intel_dual_link_lvds_callback,
839 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
840 .matches = {
841 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
842 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
843 },
844 },
845 { } /* terminating entry */
846};
847
848bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
849{
850 struct intel_encoder *encoder;
851 struct intel_lvds_encoder *lvds_encoder;
852
853 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
854 base.head) {
855 if (encoder->type == INTEL_OUTPUT_LVDS) {
856 lvds_encoder = to_lvds_encoder(&encoder->base);
857
858 return lvds_encoder->is_dual_link;
859 }
860 }
861
862 return false;
863}
864
7dec0606 865static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 866{
7dec0606 867 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
868 unsigned int val;
869 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
870
871 /* use the module option value if specified */
872 if (i915_lvds_channel_mode > 0)
873 return i915_lvds_channel_mode == 2;
874
875 if (dmi_check_system(intel_dual_link_lvds))
876 return true;
877
13c7d870
DV
878 /* BIOS should set the proper LVDS register value at boot, but
879 * in reality, it doesn't set the value when the lid is closed;
880 * we need to check "the value to be set" in VBT when LVDS
881 * register is uninitialized.
882 */
7dec0606 883 val = I915_READ(lvds_encoder->reg);
13c7d870 884 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 885 val = dev_priv->vbt.bios_lvds_val;
13c7d870 886
1974cad0
DV
887 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
888}
889
f3cfcba6
CW
890static bool intel_lvds_supported(struct drm_device *dev)
891{
892 /* With the introduction of the PCH we gained a dedicated
893 * LVDS presence pin, use it. */
311e359c 894 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
895 return true;
896
897 /* Otherwise LVDS was only attached to mobile products,
898 * except for the inglorious 830gm */
311e359c
PZ
899 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
900 return true;
901
902 return false;
f3cfcba6
CW
903}
904
79e53945
JB
905/**
906 * intel_lvds_init - setup LVDS connectors on this device
907 * @dev: drm device
908 *
909 * Create the connector, register the LVDS DDC bus, and try to figure out what
910 * modes we can display on the LVDS panel (if present).
911 */
c9093354 912void intel_lvds_init(struct drm_device *dev)
79e53945
JB
913{
914 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 915 struct intel_lvds_encoder *lvds_encoder;
21d40d37 916 struct intel_encoder *intel_encoder;
c7362c4d 917 struct intel_lvds_connector *lvds_connector;
bb8a3560 918 struct intel_connector *intel_connector;
79e53945
JB
919 struct drm_connector *connector;
920 struct drm_encoder *encoder;
921 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 922 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 923 struct edid *edid;
79e53945
JB
924 struct drm_crtc *crtc;
925 u32 lvds;
270eea0f
CW
926 int pipe;
927 u8 pin;
79e53945 928
f3cfcba6 929 if (!intel_lvds_supported(dev))
c9093354 930 return;
f3cfcba6 931
425d244c
JW
932 /* Skip init on machines we know falsely report LVDS */
933 if (dmi_check_system(intel_no_lvds))
c9093354 934 return;
565dcd46 935
270eea0f
CW
936 pin = GMBUS_PORT_PANEL;
937 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 938 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c9093354 939 return;
38b3037e 940 }
e99da35f 941
c619eed4 942 if (HAS_PCH_SPLIT(dev)) {
541998a1 943 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 944 return;
41aa3448 945 if (dev_priv->vbt.edp_support) {
28c97730 946 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 947 return;
32f9d658 948 }
541998a1
ZW
949 }
950
29b99b48
JN
951 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
952 if (!lvds_encoder)
c9093354 953 return;
79e53945 954
c7362c4d
JN
955 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
956 if (!lvds_connector) {
29b99b48 957 kfree(lvds_encoder);
c9093354 958 return;
bb8a3560
ZW
959 }
960
62165e0d
JN
961 lvds_encoder->attached_connector = lvds_connector;
962
29b99b48 963 intel_encoder = &lvds_encoder->base;
4ef69c7a 964 encoder = &intel_encoder->base;
c7362c4d 965 intel_connector = &lvds_connector->base;
ea5b213a 966 connector = &intel_connector->base;
bb8a3560 967 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
968 DRM_MODE_CONNECTOR_LVDS);
969
4ef69c7a 970 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
971 DRM_MODE_ENCODER_LVDS);
972
c22834ec 973 intel_encoder->enable = intel_enable_lvds;
f6736a1a 974 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 975 intel_encoder->compute_config = intel_lvds_compute_config;
66df24d9 976 intel_encoder->mode_set = intel_lvds_mode_set;
c22834ec 977 intel_encoder->disable = intel_disable_lvds;
b1dc332c 978 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 979 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 980 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 981
df0e9248 982 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 983 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 984
66a9278e 985 intel_encoder->cloneable = false;
27f8227b
JB
986 if (HAS_PCH_SPLIT(dev))
987 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
988 else if (IS_GEN4(dev))
989 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
990 else
991 intel_encoder->crtc_mask = (1 << 1);
992
79e53945
JB
993 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
994 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
995 connector->interlace_allowed = false;
996 connector->doublescan_allowed = false;
997
7dec0606
DV
998 if (HAS_PCH_SPLIT(dev)) {
999 lvds_encoder->reg = PCH_LVDS;
1000 } else {
1001 lvds_encoder->reg = LVDS;
1002 }
1003
3fbe18d6
ZY
1004 /* create the scaling mode property */
1005 drm_mode_create_scaling_mode_property(dev);
662595df 1006 drm_object_attach_property(&connector->base,
3fbe18d6 1007 dev->mode_config.scaling_mode_property,
dd1ea37d 1008 DRM_MODE_SCALE_ASPECT);
4d891523 1009 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1010 /*
1011 * LVDS discovery:
1012 * 1) check for EDID on DDC
1013 * 2) check for VBT data
1014 * 3) check to see if LVDS is already on
1015 * if none of the above, no panel
1016 * 4) make sure lid is open
1017 * if closed, act like it's not there for now
1018 */
1019
79e53945
JB
1020 /*
1021 * Attempt to get the fixed panel mode from DDC. Assume that the
1022 * preferred mode is the right one.
1023 */
9cd300e0
JN
1024 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1025 if (edid) {
1026 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1027 drm_mode_connector_update_edid_property(connector,
9cd300e0 1028 edid);
3f8ff0e7 1029 } else {
9cd300e0
JN
1030 kfree(edid);
1031 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1032 }
9cd300e0
JN
1033 } else {
1034 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1035 }
9cd300e0
JN
1036 lvds_connector->base.edid = edid;
1037
1038 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1039 /* Didn't get an EDID, so
1040 * Set wide sync ranges so we get all modes
1041 * handed to valid_mode for checking
1042 */
1043 connector->display_info.min_vfreq = 0;
1044 connector->display_info.max_vfreq = 200;
1045 connector->display_info.min_hfreq = 0;
1046 connector->display_info.max_hfreq = 200;
1047 }
79e53945
JB
1048
1049 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1050 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1051 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1052 drm_mode_debug_printmodeline(scan);
1053
dd06f90e 1054 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1055 if (fixed_mode) {
1056 intel_find_lvds_downclock(dev, fixed_mode,
1057 connector);
1058 goto out;
1059 }
79e53945 1060 }
79e53945
JB
1061 }
1062
1063 /* Failed to get EDID, what about VBT? */
41aa3448 1064 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1065 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1066 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1067
41aa3448 1068 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1069 if (fixed_mode) {
1070 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1071 goto out;
1072 }
79e53945
JB
1073 }
1074
1075 /*
1076 * If we didn't get EDID, try checking if the panel is already turned
1077 * on. If so, assume that whatever is currently programmed is the
1078 * correct mode.
1079 */
541998a1 1080
f2b115e6 1081 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1082 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1083 goto failed;
1084
79e53945
JB
1085 lvds = I915_READ(LVDS);
1086 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1087 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1088
1089 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1090 fixed_mode = intel_crtc_mode_get(dev, crtc);
1091 if (fixed_mode) {
6a9d51b7
CW
1092 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1093 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1094 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1095 goto out;
79e53945
JB
1096 }
1097 }
1098
1099 /* If we still don't have a mode after all that, give up. */
dd06f90e 1100 if (!fixed_mode)
79e53945
JB
1101 goto failed;
1102
79e53945 1103out:
7dec0606 1104 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1105 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1106 lvds_encoder->is_dual_link ? "dual" : "single");
1107
24ded204
DV
1108 /*
1109 * Unlock registers and just
1110 * leave them unlocked
1111 */
c619eed4 1112 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1113 I915_WRITE(PCH_PP_CONTROL,
1114 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1115 } else {
ed10fca9
KP
1116 I915_WRITE(PP_CONTROL,
1117 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1118 }
db1740a0
JN
1119 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1120 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1121 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1122 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1123 }
79e53945 1124 drm_sysfs_connector_add(connector);
aaa6fd2a 1125
dd06f90e 1126 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1127 intel_panel_setup_backlight(connector);
aaa6fd2a 1128
c9093354 1129 return;
79e53945
JB
1130
1131failed:
8a4c47f3 1132 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1133 drm_connector_cleanup(connector);
1991bdfa 1134 drm_encoder_cleanup(encoder);
dd06f90e
JN
1135 if (fixed_mode)
1136 drm_mode_destroy(dev, fixed_mode);
29b99b48 1137 kfree(lvds_encoder);
c7362c4d 1138 kfree(lvds_connector);
c9093354 1139 return;
79e53945 1140}
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