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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
788319d4 | 46 | |
219adae1 | 47 | struct edid *edid; |
788319d4 | 48 | |
3fbe18d6 ZY |
49 | int fitting_mode; |
50 | u32 pfit_control; | |
51 | u32 pfit_pgm_ratios; | |
e9e331a8 | 52 | bool pfit_dirty; |
788319d4 CW |
53 | |
54 | struct drm_display_mode *fixed_mode; | |
3fbe18d6 ZY |
55 | }; |
56 | ||
788319d4 | 57 | static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
60 | } |
61 | ||
788319d4 CW |
62 | static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_lvds, base); | |
66 | } | |
67 | ||
79e53945 JB |
68 | /** |
69 | * Sets the power state for the panel. | |
70 | */ | |
2a1292fd | 71 | static void intel_lvds_enable(struct intel_lvds *intel_lvds) |
79e53945 | 72 | { |
e9e331a8 | 73 | struct drm_device *dev = intel_lvds->base.base.dev; |
79e53945 | 74 | struct drm_i915_private *dev_priv = dev->dev_private; |
de842eff | 75 | u32 ctl_reg, lvds_reg, stat_reg; |
541998a1 | 76 | |
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 78 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 79 | lvds_reg = PCH_LVDS; |
de842eff | 80 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
81 | } else { |
82 | ctl_reg = PP_CONTROL; | |
469d1296 | 83 | lvds_reg = LVDS; |
de842eff | 84 | stat_reg = PP_STATUS; |
541998a1 | 85 | } |
79e53945 | 86 | |
2a1292fd | 87 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
e9e331a8 | 88 | |
2a1292fd CW |
89 | if (intel_lvds->pfit_dirty) { |
90 | /* | |
91 | * Enable automatic panel scaling so that non-native modes | |
92 | * fill the screen. The panel fitter should only be | |
93 | * adjusted whilst the pipe is disabled, according to | |
94 | * register description and PRM. | |
95 | */ | |
96 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
97 | intel_lvds->pfit_control, | |
98 | intel_lvds->pfit_pgm_ratios); | |
de842eff KP |
99 | |
100 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); | |
101 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
102 | intel_lvds->pfit_dirty = false; | |
2a1292fd CW |
103 | } |
104 | ||
105 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); | |
106 | POSTING_READ(lvds_reg); | |
de842eff KP |
107 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
108 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 109 | |
47356eb6 | 110 | intel_panel_enable_backlight(dev); |
2a1292fd CW |
111 | } |
112 | ||
113 | static void intel_lvds_disable(struct intel_lvds *intel_lvds) | |
114 | { | |
115 | struct drm_device *dev = intel_lvds->base.base.dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de842eff | 117 | u32 ctl_reg, lvds_reg, stat_reg; |
2a1292fd CW |
118 | |
119 | if (HAS_PCH_SPLIT(dev)) { | |
120 | ctl_reg = PCH_PP_CONTROL; | |
121 | lvds_reg = PCH_LVDS; | |
de842eff | 122 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
123 | } else { |
124 | ctl_reg = PP_CONTROL; | |
125 | lvds_reg = LVDS; | |
de842eff | 126 | stat_reg = PP_STATUS; |
2a1292fd CW |
127 | } |
128 | ||
47356eb6 | 129 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
130 | |
131 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
132 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
133 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd CW |
134 | |
135 | if (intel_lvds->pfit_control) { | |
2a1292fd CW |
136 | I915_WRITE(PFIT_CONTROL, 0); |
137 | intel_lvds->pfit_dirty = true; | |
79e53945 | 138 | } |
2a1292fd CW |
139 | |
140 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
c9f9ccc1 | 141 | POSTING_READ(lvds_reg); |
79e53945 JB |
142 | } |
143 | ||
144 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
145 | { | |
788319d4 | 146 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
147 | |
148 | if (mode == DRM_MODE_DPMS_ON) | |
2a1292fd | 149 | intel_lvds_enable(intel_lvds); |
79e53945 | 150 | else |
2a1292fd | 151 | intel_lvds_disable(intel_lvds); |
79e53945 JB |
152 | |
153 | /* XXX: We never power down the LVDS pairs. */ | |
154 | } | |
155 | ||
79e53945 JB |
156 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
157 | struct drm_display_mode *mode) | |
158 | { | |
788319d4 CW |
159 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
160 | struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; | |
79e53945 | 161 | |
788319d4 CW |
162 | if (mode->hdisplay > fixed_mode->hdisplay) |
163 | return MODE_PANEL; | |
164 | if (mode->vdisplay > fixed_mode->vdisplay) | |
165 | return MODE_PANEL; | |
79e53945 JB |
166 | |
167 | return MODE_OK; | |
168 | } | |
169 | ||
49be663f CW |
170 | static void |
171 | centre_horizontally(struct drm_display_mode *mode, | |
172 | int width) | |
173 | { | |
174 | u32 border, sync_pos, blank_width, sync_width; | |
175 | ||
176 | /* keep the hsync and hblank widths constant */ | |
177 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
178 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
179 | sync_pos = (blank_width - sync_width + 1) / 2; | |
180 | ||
181 | border = (mode->hdisplay - width + 1) / 2; | |
182 | border += border & 1; /* make the border even */ | |
183 | ||
184 | mode->crtc_hdisplay = width; | |
185 | mode->crtc_hblank_start = width + border; | |
186 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
187 | ||
188 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
189 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
190 | } | |
191 | ||
192 | static void | |
193 | centre_vertically(struct drm_display_mode *mode, | |
194 | int height) | |
195 | { | |
196 | u32 border, sync_pos, blank_width, sync_width; | |
197 | ||
198 | /* keep the vsync and vblank widths constant */ | |
199 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
200 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
201 | sync_pos = (blank_width - sync_width + 1) / 2; | |
202 | ||
203 | border = (mode->vdisplay - height + 1) / 2; | |
204 | ||
205 | mode->crtc_vdisplay = height; | |
206 | mode->crtc_vblank_start = height + border; | |
207 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
208 | ||
209 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
210 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
211 | } | |
212 | ||
213 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
214 | { | |
215 | /* | |
216 | * Floating point operation is not supported. So the FACTOR | |
217 | * is defined, which can avoid the floating point computation | |
218 | * when calculating the panel ratio. | |
219 | */ | |
220 | #define ACCURACY 12 | |
221 | #define FACTOR (1 << ACCURACY) | |
222 | u32 ratio = source * FACTOR / target; | |
223 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
224 | } | |
225 | ||
79e53945 JB |
226 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
227 | struct drm_display_mode *mode, | |
228 | struct drm_display_mode *adjusted_mode) | |
229 | { | |
230 | struct drm_device *dev = encoder->dev; | |
231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
232 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
788319d4 | 233 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 234 | struct drm_encoder *tmp_encoder; |
49be663f | 235 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
9db4a9c7 | 236 | int pipe; |
79e53945 JB |
237 | |
238 | /* Should never happen!! */ | |
a6c45cf0 | 239 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 240 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
241 | return false; |
242 | } | |
243 | ||
244 | /* Should never happen!! */ | |
245 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
246 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 247 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
248 | "encoder on the same pipe\n"); |
249 | return false; | |
250 | } | |
251 | } | |
1d8e1c75 | 252 | |
79e53945 | 253 | /* |
71677043 | 254 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
255 | * to the adjusted mode. The CRTC will be set up for this mode, |
256 | * with the panel scaling set up to source from the H/VDisplay | |
257 | * of the original mode. | |
258 | */ | |
788319d4 | 259 | intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); |
1d8e1c75 CW |
260 | |
261 | if (HAS_PCH_SPLIT(dev)) { | |
262 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
263 | mode, adjusted_mode); | |
264 | return true; | |
265 | } | |
79e53945 | 266 | |
3fbe18d6 ZY |
267 | /* Native modes don't need fitting */ |
268 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 269 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 270 | goto out; |
3fbe18d6 ZY |
271 | |
272 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 273 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
274 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
275 | PFIT_FILTER_FUZZY); | |
276 | ||
3fbe18d6 ZY |
277 | /* |
278 | * Enable automatic panel scaling for non-native modes so that they fill | |
279 | * the screen. Should be enabled before the pipe is enabled, according | |
280 | * to register description and PRM. | |
281 | * Change the value here to see the borders for debugging | |
282 | */ | |
9db4a9c7 JB |
283 | for_each_pipe(pipe) |
284 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 285 | |
ea5b213a | 286 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 287 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
288 | /* |
289 | * For centered modes, we have to calculate border widths & | |
290 | * heights and modify the values programmed into the CRTC. | |
291 | */ | |
49be663f CW |
292 | centre_horizontally(adjusted_mode, mode->hdisplay); |
293 | centre_vertically(adjusted_mode, mode->vdisplay); | |
294 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 295 | break; |
49be663f | 296 | |
3fbe18d6 | 297 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 298 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 299 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
300 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
301 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
302 | ||
3fbe18d6 | 303 | /* 965+ is easy, it does everything in hw */ |
49be663f | 304 | if (scaled_width > scaled_height) |
257e48f1 | 305 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 306 | else if (scaled_width < scaled_height) |
257e48f1 CW |
307 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
308 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
309 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 310 | } else { |
49be663f CW |
311 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
312 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
313 | /* |
314 | * For earlier chips we have to calculate the scaling | |
315 | * ratio by hand and program it into the | |
316 | * PFIT_PGM_RATIO register | |
317 | */ | |
49be663f CW |
318 | if (scaled_width > scaled_height) { /* pillar */ |
319 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
320 | ||
321 | border = LVDS_BORDER_ENABLE; | |
322 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
323 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
324 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
325 | bits << PFIT_VERT_SCALE_SHIFT); | |
326 | pfit_control |= (PFIT_ENABLE | | |
327 | VERT_INTERP_BILINEAR | | |
328 | HORIZ_INTERP_BILINEAR); | |
329 | } | |
330 | } else if (scaled_width < scaled_height) { /* letter */ | |
331 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
332 | ||
333 | border = LVDS_BORDER_ENABLE; | |
334 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
335 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
336 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
337 | bits << PFIT_VERT_SCALE_SHIFT); | |
338 | pfit_control |= (PFIT_ENABLE | | |
339 | VERT_INTERP_BILINEAR | | |
340 | HORIZ_INTERP_BILINEAR); | |
341 | } | |
342 | } else | |
343 | /* Aspects match, Let hw scale both directions */ | |
344 | pfit_control |= (PFIT_ENABLE | | |
345 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
346 | VERT_INTERP_BILINEAR | |
347 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
348 | } |
349 | break; | |
350 | ||
351 | case DRM_MODE_SCALE_FULLSCREEN: | |
352 | /* | |
353 | * Full scaling, even if it changes the aspect ratio. | |
354 | * Fortunately this is all done for us in hw. | |
355 | */ | |
257e48f1 CW |
356 | if (mode->vdisplay != adjusted_mode->vdisplay || |
357 | mode->hdisplay != adjusted_mode->hdisplay) { | |
358 | pfit_control |= PFIT_ENABLE; | |
359 | if (INTEL_INFO(dev)->gen >= 4) | |
360 | pfit_control |= PFIT_SCALING_AUTO; | |
361 | else | |
362 | pfit_control |= (VERT_AUTO_SCALE | | |
363 | VERT_INTERP_BILINEAR | | |
364 | HORIZ_AUTO_SCALE | | |
365 | HORIZ_INTERP_BILINEAR); | |
366 | } | |
3fbe18d6 | 367 | break; |
49be663f | 368 | |
3fbe18d6 ZY |
369 | default: |
370 | break; | |
371 | } | |
372 | ||
373 | out: | |
72389a33 | 374 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
375 | if ((pfit_control & PFIT_ENABLE) == 0) { |
376 | pfit_control = 0; | |
377 | pfit_pgm_ratios = 0; | |
378 | } | |
72389a33 CW |
379 | |
380 | /* Make sure pre-965 set dither correctly */ | |
381 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
382 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
383 | ||
e9e331a8 CW |
384 | if (pfit_control != intel_lvds->pfit_control || |
385 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | |
386 | intel_lvds->pfit_control = pfit_control; | |
387 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
388 | intel_lvds->pfit_dirty = true; | |
389 | } | |
49be663f CW |
390 | dev_priv->lvds_border_bits = border; |
391 | ||
79e53945 JB |
392 | /* |
393 | * XXX: It would be nice to support lower refresh rates on the | |
394 | * panels to reduce power consumption, and perhaps match the | |
395 | * user's requested refresh rate. | |
396 | */ | |
397 | ||
398 | return true; | |
399 | } | |
400 | ||
401 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
402 | { | |
788319d4 | 403 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 404 | |
ed10fca9 | 405 | /* |
e9e331a8 CW |
406 | * Prior to Ironlake, we must disable the pipe if we want to adjust |
407 | * the panel fitter. However at all other times we can just reset | |
408 | * the registers regardless. | |
409 | */ | |
ed10fca9 KP |
410 | if (!HAS_PCH_SPLIT(encoder->dev) && intel_lvds->pfit_dirty) |
411 | intel_lvds_disable(intel_lvds); | |
79e53945 JB |
412 | } |
413 | ||
e9e331a8 | 414 | static void intel_lvds_commit(struct drm_encoder *encoder) |
79e53945 | 415 | { |
788319d4 | 416 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 417 | |
e9e331a8 CW |
418 | /* Always do a full power on as we do not know what state |
419 | * we were left in. | |
420 | */ | |
2a1292fd | 421 | intel_lvds_enable(intel_lvds); |
79e53945 JB |
422 | } |
423 | ||
424 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
425 | struct drm_display_mode *mode, | |
426 | struct drm_display_mode *adjusted_mode) | |
427 | { | |
79e53945 JB |
428 | /* |
429 | * The LVDS pin pair will already have been turned on in the | |
430 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
431 | * settings. | |
432 | */ | |
79e53945 JB |
433 | } |
434 | ||
435 | /** | |
436 | * Detect the LVDS connection. | |
437 | * | |
b42d4c5c JB |
438 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
439 | * connected and closed means disconnected. We also send hotplug events as | |
440 | * needed, using lid status notification from the input layer. | |
79e53945 | 441 | */ |
7b334fcb | 442 | static enum drm_connector_status |
930a9e28 | 443 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 444 | { |
7b9c5abe | 445 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 446 | enum drm_connector_status status; |
b42d4c5c | 447 | |
fe16d949 CW |
448 | status = intel_panel_detect(dev); |
449 | if (status != connector_status_unknown) | |
450 | return status; | |
01fe9dbd | 451 | |
6ee3b5a1 | 452 | return connector_status_connected; |
79e53945 JB |
453 | } |
454 | ||
455 | /** | |
456 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
457 | */ | |
458 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
459 | { | |
788319d4 | 460 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
79e53945 | 461 | struct drm_device *dev = connector->dev; |
788319d4 | 462 | struct drm_display_mode *mode; |
79e53945 | 463 | |
3f8ff0e7 | 464 | if (intel_lvds->edid) |
219adae1 | 465 | return drm_add_edid_modes(connector, intel_lvds->edid); |
79e53945 | 466 | |
788319d4 | 467 | mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); |
311bd68e | 468 | if (mode == NULL) |
788319d4 | 469 | return 0; |
79e53945 | 470 | |
788319d4 CW |
471 | drm_mode_probed_add(connector, mode); |
472 | return 1; | |
79e53945 JB |
473 | } |
474 | ||
0544edfd TB |
475 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
476 | { | |
477 | DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); | |
478 | return 1; | |
479 | } | |
480 | ||
481 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
482 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
483 | { | |
484 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
485 | .ident = "Toshiba Tecra A11", | |
486 | .matches = { | |
487 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
488 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
489 | }, | |
490 | }, | |
491 | ||
492 | { } /* terminating entry */ | |
493 | }; | |
494 | ||
c9354c85 LT |
495 | /* |
496 | * Lid events. Note the use of 'modeset_on_lid': | |
497 | * - we set it on lid close, and reset it on open | |
498 | * - we use it as a "only once" bit (ie we ignore | |
499 | * duplicate events where it was already properly | |
500 | * set/reset) | |
501 | * - the suspend/resume paths will also set it to | |
502 | * zero, since they restore the mode ("lid open"). | |
503 | */ | |
c1c7af60 JB |
504 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
505 | void *unused) | |
506 | { | |
507 | struct drm_i915_private *dev_priv = | |
508 | container_of(nb, struct drm_i915_private, lid_notifier); | |
509 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 510 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 511 | |
2fb4e61d AW |
512 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
513 | return NOTIFY_OK; | |
514 | ||
a2565377 ZY |
515 | /* |
516 | * check and update the status of LVDS connector after receiving | |
517 | * the LID nofication event. | |
518 | */ | |
519 | if (connector) | |
7b334fcb | 520 | connector->status = connector->funcs->detect(connector, |
930a9e28 | 521 | false); |
7b334fcb | 522 | |
0544edfd TB |
523 | /* Don't force modeset on machines where it causes a GPU lockup */ |
524 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
525 | return NOTIFY_OK; | |
c9354c85 LT |
526 | if (!acpi_lid_open()) { |
527 | dev_priv->modeset_on_lid = 1; | |
528 | return NOTIFY_OK; | |
06891e27 | 529 | } |
c1c7af60 | 530 | |
c9354c85 LT |
531 | if (!dev_priv->modeset_on_lid) |
532 | return NOTIFY_OK; | |
533 | ||
534 | dev_priv->modeset_on_lid = 0; | |
535 | ||
536 | mutex_lock(&dev->mode_config.mutex); | |
537 | drm_helper_resume_force_mode(dev); | |
538 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 539 | |
c1c7af60 JB |
540 | return NOTIFY_OK; |
541 | } | |
542 | ||
79e53945 JB |
543 | /** |
544 | * intel_lvds_destroy - unregister and free LVDS structures | |
545 | * @connector: connector to free | |
546 | * | |
547 | * Unregister the DDC bus for this connector then free the driver private | |
548 | * structure. | |
549 | */ | |
550 | static void intel_lvds_destroy(struct drm_connector *connector) | |
551 | { | |
c1c7af60 | 552 | struct drm_device *dev = connector->dev; |
c1c7af60 | 553 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 554 | |
aaa6fd2a MG |
555 | intel_panel_destroy_backlight(dev); |
556 | ||
c1c7af60 JB |
557 | if (dev_priv->lid_notifier.notifier_call) |
558 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
559 | drm_sysfs_connector_remove(connector); |
560 | drm_connector_cleanup(connector); | |
561 | kfree(connector); | |
562 | } | |
563 | ||
335041ed JB |
564 | static int intel_lvds_set_property(struct drm_connector *connector, |
565 | struct drm_property *property, | |
566 | uint64_t value) | |
567 | { | |
788319d4 | 568 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
3fbe18d6 | 569 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 570 | |
788319d4 CW |
571 | if (property == dev->mode_config.scaling_mode_property) { |
572 | struct drm_crtc *crtc = intel_lvds->base.base.crtc; | |
bb8a3560 | 573 | |
53bd8389 JB |
574 | if (value == DRM_MODE_SCALE_NONE) { |
575 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 576 | return -EINVAL; |
3fbe18d6 | 577 | } |
788319d4 | 578 | |
ea5b213a | 579 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
580 | /* the LVDS scaling property is not changed */ |
581 | return 0; | |
582 | } | |
ea5b213a | 583 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
584 | if (crtc && crtc->enabled) { |
585 | /* | |
586 | * If the CRTC is enabled, the display will be changed | |
587 | * according to the new panel fitting mode. | |
588 | */ | |
589 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
590 | crtc->x, crtc->y, crtc->fb); | |
591 | } | |
592 | } | |
593 | ||
335041ed JB |
594 | return 0; |
595 | } | |
596 | ||
79e53945 JB |
597 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
598 | .dpms = intel_lvds_dpms, | |
599 | .mode_fixup = intel_lvds_mode_fixup, | |
600 | .prepare = intel_lvds_prepare, | |
601 | .mode_set = intel_lvds_mode_set, | |
602 | .commit = intel_lvds_commit, | |
603 | }; | |
604 | ||
605 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
606 | .get_modes = intel_lvds_get_modes, | |
607 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 608 | .best_encoder = intel_best_encoder, |
79e53945 JB |
609 | }; |
610 | ||
611 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 612 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
613 | .detect = intel_lvds_detect, |
614 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 615 | .set_property = intel_lvds_set_property, |
79e53945 JB |
616 | .destroy = intel_lvds_destroy, |
617 | }; | |
618 | ||
79e53945 | 619 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 620 | .destroy = intel_encoder_destroy, |
79e53945 JB |
621 | }; |
622 | ||
425d244c JW |
623 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
624 | { | |
8a4c47f3 | 625 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
626 | return 1; |
627 | } | |
79e53945 | 628 | |
425d244c | 629 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 630 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
631 | { |
632 | .callback = intel_no_lvds_dmi_callback, | |
633 | .ident = "Apple Mac Mini (Core series)", | |
634 | .matches = { | |
98acd46f | 635 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
636 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
637 | }, | |
638 | }, | |
639 | { | |
640 | .callback = intel_no_lvds_dmi_callback, | |
641 | .ident = "Apple Mac Mini (Core 2 series)", | |
642 | .matches = { | |
98acd46f | 643 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
644 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
645 | }, | |
646 | }, | |
647 | { | |
648 | .callback = intel_no_lvds_dmi_callback, | |
649 | .ident = "MSI IM-945GSE-A", | |
650 | .matches = { | |
651 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
652 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
653 | }, | |
654 | }, | |
655 | { | |
656 | .callback = intel_no_lvds_dmi_callback, | |
657 | .ident = "Dell Studio Hybrid", | |
658 | .matches = { | |
659 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
660 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
661 | }, | |
662 | }, | |
70aa96ca JW |
663 | { |
664 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
665 | .ident = "Dell OptiPlex FX170", |
666 | .matches = { | |
667 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
668 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
669 | }, | |
670 | }, | |
671 | { | |
672 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
673 | .ident = "AOpen Mini PC", |
674 | .matches = { | |
675 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
676 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
677 | }, | |
678 | }, | |
ed8c754b TV |
679 | { |
680 | .callback = intel_no_lvds_dmi_callback, | |
681 | .ident = "AOpen Mini PC MP915", | |
682 | .matches = { | |
683 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
684 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
685 | }, | |
686 | }, | |
22ab70d3 KP |
687 | { |
688 | .callback = intel_no_lvds_dmi_callback, | |
689 | .ident = "AOpen i915GMm-HFS", | |
690 | .matches = { | |
691 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
692 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
693 | }, | |
694 | }, | |
e57b6886 DV |
695 | { |
696 | .callback = intel_no_lvds_dmi_callback, | |
697 | .ident = "AOpen i45GMx-I", | |
698 | .matches = { | |
699 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
700 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
701 | }, | |
702 | }, | |
fa0864b2 MC |
703 | { |
704 | .callback = intel_no_lvds_dmi_callback, | |
705 | .ident = "Aopen i945GTt-VFA", | |
706 | .matches = { | |
707 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
708 | }, | |
709 | }, | |
9875557e SB |
710 | { |
711 | .callback = intel_no_lvds_dmi_callback, | |
712 | .ident = "Clientron U800", | |
713 | .matches = { | |
714 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
715 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
716 | }, | |
717 | }, | |
6a574b5b | 718 | { |
44306ab3 JS |
719 | .callback = intel_no_lvds_dmi_callback, |
720 | .ident = "Clientron E830", | |
721 | .matches = { | |
722 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
723 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
724 | }, | |
725 | }, | |
726 | { | |
6a574b5b HG |
727 | .callback = intel_no_lvds_dmi_callback, |
728 | .ident = "Asus EeeBox PC EB1007", | |
729 | .matches = { | |
730 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
731 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
732 | }, | |
733 | }, | |
0999bbe0 AJ |
734 | { |
735 | .callback = intel_no_lvds_dmi_callback, | |
736 | .ident = "Asus AT5NM10T-I", | |
737 | .matches = { | |
738 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
739 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
740 | }, | |
741 | }, | |
f5b8a7ed MG |
742 | { |
743 | .callback = intel_no_lvds_dmi_callback, | |
744 | .ident = "Hewlett-Packard t5745", | |
745 | .matches = { | |
746 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
747 | DMI_MATCH(DMI_BOARD_NAME, "hp t5745"), | |
748 | }, | |
749 | }, | |
750 | { | |
751 | .callback = intel_no_lvds_dmi_callback, | |
752 | .ident = "Hewlett-Packard st5747", | |
753 | .matches = { | |
754 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
755 | DMI_MATCH(DMI_BOARD_NAME, "hp st5747"), | |
756 | }, | |
757 | }, | |
425d244c JW |
758 | |
759 | { } /* terminating entry */ | |
760 | }; | |
79e53945 | 761 | |
18f9ed12 ZY |
762 | /** |
763 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
764 | * @dev: drm device | |
765 | * @connector: LVDS connector | |
766 | * | |
767 | * Find the reduced downclock for LVDS in EDID. | |
768 | */ | |
769 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
770 | struct drm_display_mode *fixed_mode, |
771 | struct drm_connector *connector) | |
18f9ed12 ZY |
772 | { |
773 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 774 | struct drm_display_mode *scan; |
18f9ed12 ZY |
775 | int temp_downclock; |
776 | ||
788319d4 | 777 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
778 | list_for_each_entry(scan, &connector->probed_modes, head) { |
779 | /* | |
780 | * If one mode has the same resolution with the fixed_panel | |
781 | * mode while they have the different refresh rate, it means | |
782 | * that the reduced downclock is found for the LVDS. In such | |
783 | * case we can set the different FPx0/1 to dynamically select | |
784 | * between low and high frequency. | |
785 | */ | |
788319d4 CW |
786 | if (scan->hdisplay == fixed_mode->hdisplay && |
787 | scan->hsync_start == fixed_mode->hsync_start && | |
788 | scan->hsync_end == fixed_mode->hsync_end && | |
789 | scan->htotal == fixed_mode->htotal && | |
790 | scan->vdisplay == fixed_mode->vdisplay && | |
791 | scan->vsync_start == fixed_mode->vsync_start && | |
792 | scan->vsync_end == fixed_mode->vsync_end && | |
793 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
794 | if (scan->clock < temp_downclock) { |
795 | /* | |
796 | * The downclock is already found. But we | |
797 | * expect to find the lower downclock. | |
798 | */ | |
799 | temp_downclock = scan->clock; | |
800 | } | |
801 | } | |
802 | } | |
788319d4 | 803 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
804 | /* We found the downclock for LVDS. */ |
805 | dev_priv->lvds_downclock_avail = 1; | |
806 | dev_priv->lvds_downclock = temp_downclock; | |
807 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
808 | "Normal clock %dKhz, downclock %dKhz\n", |
809 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 810 | } |
18f9ed12 ZY |
811 | } |
812 | ||
7cf4f69d ZY |
813 | /* |
814 | * Enumerate the child dev array parsed from VBT to check whether | |
815 | * the LVDS is present. | |
816 | * If it is present, return 1. | |
817 | * If it is not present, return false. | |
818 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 819 | */ |
270eea0f CW |
820 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
821 | u8 *i2c_pin) | |
7cf4f69d ZY |
822 | { |
823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 824 | int i; |
7cf4f69d ZY |
825 | |
826 | if (!dev_priv->child_dev_num) | |
425904dd | 827 | return true; |
7cf4f69d | 828 | |
7cf4f69d | 829 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
830 | struct child_device_config *child = dev_priv->child_dev + i; |
831 | ||
832 | /* If the device type is not LFP, continue. | |
833 | * We have to check both the new identifiers as well as the | |
834 | * old for compatibility with some BIOSes. | |
7cf4f69d | 835 | */ |
425904dd CW |
836 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
837 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
838 | continue; |
839 | ||
270eea0f CW |
840 | if (child->i2c_pin) |
841 | *i2c_pin = child->i2c_pin; | |
842 | ||
425904dd CW |
843 | /* However, we cannot trust the BIOS writers to populate |
844 | * the VBT correctly. Since LVDS requires additional | |
845 | * information from AIM blocks, a non-zero addin offset is | |
846 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 847 | */ |
425904dd CW |
848 | if (child->addin_offset) |
849 | return true; | |
850 | ||
851 | /* But even then some BIOS writers perform some black magic | |
852 | * and instantiate the device without reference to any | |
853 | * additional data. Trust that if the VBT was written into | |
854 | * the OpRegion then they have validated the LVDS's existence. | |
855 | */ | |
856 | if (dev_priv->opregion.vbt) | |
857 | return true; | |
7cf4f69d | 858 | } |
425904dd CW |
859 | |
860 | return false; | |
7cf4f69d ZY |
861 | } |
862 | ||
f3cfcba6 CW |
863 | static bool intel_lvds_supported(struct drm_device *dev) |
864 | { | |
865 | /* With the introduction of the PCH we gained a dedicated | |
866 | * LVDS presence pin, use it. */ | |
867 | if (HAS_PCH_SPLIT(dev)) | |
868 | return true; | |
869 | ||
870 | /* Otherwise LVDS was only attached to mobile products, | |
871 | * except for the inglorious 830gm */ | |
872 | return IS_MOBILE(dev) && !IS_I830(dev); | |
873 | } | |
874 | ||
79e53945 JB |
875 | /** |
876 | * intel_lvds_init - setup LVDS connectors on this device | |
877 | * @dev: drm device | |
878 | * | |
879 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
880 | * modes we can display on the LVDS panel (if present). | |
881 | */ | |
c5d1b51d | 882 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
883 | { |
884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 885 | struct intel_lvds *intel_lvds; |
21d40d37 | 886 | struct intel_encoder *intel_encoder; |
bb8a3560 | 887 | struct intel_connector *intel_connector; |
79e53945 JB |
888 | struct drm_connector *connector; |
889 | struct drm_encoder *encoder; | |
890 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
891 | struct drm_crtc *crtc; | |
892 | u32 lvds; | |
270eea0f CW |
893 | int pipe; |
894 | u8 pin; | |
79e53945 | 895 | |
f3cfcba6 CW |
896 | if (!intel_lvds_supported(dev)) |
897 | return false; | |
898 | ||
425d244c JW |
899 | /* Skip init on machines we know falsely report LVDS */ |
900 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 901 | return false; |
565dcd46 | 902 | |
270eea0f CW |
903 | pin = GMBUS_PORT_PANEL; |
904 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 905 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 906 | return false; |
38b3037e | 907 | } |
e99da35f | 908 | |
c619eed4 | 909 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 910 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 911 | return false; |
5ceb0f9b | 912 | if (dev_priv->edp.support) { |
28c97730 | 913 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 914 | return false; |
32f9d658 | 915 | } |
541998a1 ZW |
916 | } |
917 | ||
ea5b213a CW |
918 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
919 | if (!intel_lvds) { | |
c5d1b51d | 920 | return false; |
79e53945 JB |
921 | } |
922 | ||
bb8a3560 ZW |
923 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
924 | if (!intel_connector) { | |
ea5b213a | 925 | kfree(intel_lvds); |
c5d1b51d | 926 | return false; |
bb8a3560 ZW |
927 | } |
928 | ||
e9e331a8 CW |
929 | if (!HAS_PCH_SPLIT(dev)) { |
930 | intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); | |
931 | } | |
932 | ||
ea5b213a | 933 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 934 | encoder = &intel_encoder->base; |
ea5b213a | 935 | connector = &intel_connector->base; |
bb8a3560 | 936 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
937 | DRM_MODE_CONNECTOR_LVDS); |
938 | ||
4ef69c7a | 939 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
940 | DRM_MODE_ENCODER_LVDS); |
941 | ||
df0e9248 | 942 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 943 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 944 | |
21d40d37 | 945 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
27f8227b JB |
946 | if (HAS_PCH_SPLIT(dev)) |
947 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
948 | else | |
949 | intel_encoder->crtc_mask = (1 << 1); | |
950 | ||
79e53945 JB |
951 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
952 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
953 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
954 | connector->interlace_allowed = false; | |
955 | connector->doublescan_allowed = false; | |
956 | ||
3fbe18d6 ZY |
957 | /* create the scaling mode property */ |
958 | drm_mode_create_scaling_mode_property(dev); | |
959 | /* | |
960 | * the initial panel fitting mode will be FULL_SCREEN. | |
961 | */ | |
79e53945 | 962 | |
bb8a3560 | 963 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 964 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 965 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 966 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
967 | /* |
968 | * LVDS discovery: | |
969 | * 1) check for EDID on DDC | |
970 | * 2) check for VBT data | |
971 | * 3) check to see if LVDS is already on | |
972 | * if none of the above, no panel | |
973 | * 4) make sure lid is open | |
974 | * if closed, act like it's not there for now | |
975 | */ | |
976 | ||
79e53945 JB |
977 | /* |
978 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
979 | * preferred mode is the right one. | |
980 | */ | |
219adae1 | 981 | intel_lvds->edid = drm_get_edid(connector, |
270eea0f | 982 | &dev_priv->gmbus[pin].adapter); |
3f8ff0e7 CW |
983 | if (intel_lvds->edid) { |
984 | if (drm_add_edid_modes(connector, | |
985 | intel_lvds->edid)) { | |
986 | drm_mode_connector_update_edid_property(connector, | |
987 | intel_lvds->edid); | |
988 | } else { | |
989 | kfree(intel_lvds->edid); | |
990 | intel_lvds->edid = NULL; | |
991 | } | |
992 | } | |
219adae1 | 993 | if (!intel_lvds->edid) { |
788319d4 CW |
994 | /* Didn't get an EDID, so |
995 | * Set wide sync ranges so we get all modes | |
996 | * handed to valid_mode for checking | |
997 | */ | |
998 | connector->display_info.min_vfreq = 0; | |
999 | connector->display_info.max_vfreq = 200; | |
1000 | connector->display_info.min_hfreq = 0; | |
1001 | connector->display_info.max_hfreq = 200; | |
1002 | } | |
79e53945 JB |
1003 | |
1004 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1005 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
788319d4 | 1006 | intel_lvds->fixed_mode = |
79e53945 | 1007 | drm_mode_duplicate(dev, scan); |
788319d4 CW |
1008 | intel_find_lvds_downclock(dev, |
1009 | intel_lvds->fixed_mode, | |
1010 | connector); | |
565dcd46 | 1011 | goto out; |
79e53945 | 1012 | } |
79e53945 JB |
1013 | } |
1014 | ||
1015 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1016 | if (dev_priv->lfp_lvds_vbt_mode) { |
788319d4 | 1017 | intel_lvds->fixed_mode = |
88631706 | 1018 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
788319d4 CW |
1019 | if (intel_lvds->fixed_mode) { |
1020 | intel_lvds->fixed_mode->type |= | |
e285f3cd | 1021 | DRM_MODE_TYPE_PREFERRED; |
e285f3cd JB |
1022 | goto out; |
1023 | } | |
79e53945 JB |
1024 | } |
1025 | ||
1026 | /* | |
1027 | * If we didn't get EDID, try checking if the panel is already turned | |
1028 | * on. If so, assume that whatever is currently programmed is the | |
1029 | * correct mode. | |
1030 | */ | |
541998a1 | 1031 | |
f2b115e6 | 1032 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1033 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1034 | goto failed; |
1035 | ||
79e53945 JB |
1036 | lvds = I915_READ(LVDS); |
1037 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1038 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1039 | |
1040 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
788319d4 CW |
1041 | intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); |
1042 | if (intel_lvds->fixed_mode) { | |
1043 | intel_lvds->fixed_mode->type |= | |
79e53945 | 1044 | DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1045 | goto out; |
79e53945 JB |
1046 | } |
1047 | } | |
1048 | ||
1049 | /* If we still don't have a mode after all that, give up. */ | |
788319d4 | 1050 | if (!intel_lvds->fixed_mode) |
79e53945 JB |
1051 | goto failed; |
1052 | ||
79e53945 | 1053 | out: |
c619eed4 | 1054 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1055 | u32 pwm; |
17fe6981 CW |
1056 | |
1057 | pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1058 | ||
1059 | /* make sure PWM is enabled and locked to the LVDS pipe */ | |
541998a1 | 1060 | pwm = I915_READ(BLC_PWM_CPU_CTL2); |
17fe6981 CW |
1061 | if (pipe == 0 && (pwm & PWM_PIPE_B)) |
1062 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); | |
1063 | if (pipe) | |
1064 | pwm |= PWM_PIPE_B; | |
1065 | else | |
1066 | pwm &= ~PWM_PIPE_B; | |
1067 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); | |
541998a1 ZW |
1068 | |
1069 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1070 | pwm |= PWM_PCH_ENABLE; | |
1071 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
ed10fca9 KP |
1072 | /* |
1073 | * Unlock registers and just | |
1074 | * leave them unlocked | |
1075 | */ | |
1076 | I915_WRITE(PCH_PP_CONTROL, | |
1077 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1078 | } else { | |
1079 | /* | |
1080 | * Unlock registers and just | |
1081 | * leave them unlocked | |
1082 | */ | |
1083 | I915_WRITE(PP_CONTROL, | |
1084 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1085 | } |
c1c7af60 JB |
1086 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1087 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1088 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1089 | dev_priv->lid_notifier.notifier_call = NULL; |
1090 | } | |
a2565377 ZY |
1091 | /* keep the LVDS connector */ |
1092 | dev_priv->int_lvds_connector = connector; | |
79e53945 | 1093 | drm_sysfs_connector_add(connector); |
aaa6fd2a MG |
1094 | |
1095 | intel_panel_setup_backlight(dev); | |
1096 | ||
c5d1b51d | 1097 | return true; |
79e53945 JB |
1098 | |
1099 | failed: | |
8a4c47f3 | 1100 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1101 | drm_connector_cleanup(connector); |
1991bdfa | 1102 | drm_encoder_cleanup(encoder); |
ea5b213a | 1103 | kfree(intel_lvds); |
bb8a3560 | 1104 | kfree(intel_connector); |
c5d1b51d | 1105 | return false; |
79e53945 | 1106 | } |