Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
3fbe18d6 ZY |
52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | |
13c7d870 | 54 | bool is_dual_link; |
7dec0606 | 55 | u32 reg; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
76 | u32 tmp; | |
b1dc332c | 77 | |
7dec0606 | 78 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
79 | |
80 | if (!(tmp & LVDS_PORT_EN)) | |
81 | return false; | |
82 | ||
83 | if (HAS_PCH_CPT(dev)) | |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
85 | else | |
86 | *pipe = PORT_TO_PIPE(tmp); | |
87 | ||
88 | return true; | |
89 | } | |
90 | ||
fc683091 DV |
91 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
92 | * This is an exception to the general rule that mode_set doesn't turn | |
93 | * things on. | |
94 | */ | |
95 | static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |
96 | { | |
97 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
98 | struct drm_device *dev = encoder->base.dev; | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
101 | struct drm_display_mode *fixed_mode = | |
102 | lvds_encoder->attached_connector->base.panel.fixed_mode; | |
103 | int pipe = intel_crtc->pipe; | |
104 | u32 temp; | |
105 | ||
fc683091 DV |
106 | temp = I915_READ(lvds_encoder->reg); |
107 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
108 | |
109 | if (HAS_PCH_CPT(dev)) { | |
110 | temp &= ~PORT_TRANS_SEL_MASK; | |
111 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 112 | } else { |
62810e5a DV |
113 | if (pipe == 1) { |
114 | temp |= LVDS_PIPEB_SELECT; | |
115 | } else { | |
116 | temp &= ~LVDS_PIPEB_SELECT; | |
117 | } | |
fc683091 | 118 | } |
62810e5a | 119 | |
fc683091 DV |
120 | /* set the corresponsding LVDS_BORDER bit */ |
121 | temp |= dev_priv->lvds_border_bits; | |
122 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
123 | * set the DPLLs for dual-channel mode or not. | |
124 | */ | |
125 | if (lvds_encoder->is_dual_link) | |
126 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
127 | else | |
128 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
129 | ||
130 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
131 | * appropriately here, but we need to look more thoroughly into how | |
132 | * panels behave in the two modes. | |
133 | */ | |
62810e5a DV |
134 | |
135 | /* Set the dithering flag on LVDS as needed, note that there is no | |
136 | * special lvds dither control bit on pch-split platforms, dithering is | |
137 | * only controlled through the PIPECONF reg. */ | |
138 | if (INTEL_INFO(dev)->gen == 4) { | |
fc683091 DV |
139 | if (dev_priv->lvds_dither) |
140 | temp |= LVDS_ENABLE_DITHER; | |
141 | else | |
142 | temp &= ~LVDS_ENABLE_DITHER; | |
143 | } | |
144 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
145 | if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
146 | temp |= LVDS_HSYNC_POLARITY; | |
147 | if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
148 | temp |= LVDS_VSYNC_POLARITY; | |
149 | ||
150 | I915_WRITE(lvds_encoder->reg, temp); | |
151 | } | |
152 | ||
9d6d9f19 MK |
153 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
154 | { | |
155 | struct drm_device *dev = encoder->base.dev; | |
156 | struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | ||
159 | if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) | |
160 | return; | |
161 | ||
162 | /* | |
163 | * Enable automatic panel scaling so that non-native modes | |
164 | * fill the screen. The panel fitter should only be | |
165 | * adjusted whilst the pipe is disabled, according to | |
166 | * register description and PRM. | |
167 | */ | |
168 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
169 | enc->pfit_control, | |
170 | enc->pfit_pgm_ratios); | |
171 | ||
172 | I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); | |
173 | I915_WRITE(PFIT_CONTROL, enc->pfit_control); | |
174 | } | |
175 | ||
79e53945 JB |
176 | /** |
177 | * Sets the power state for the panel. | |
178 | */ | |
c22834ec | 179 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 180 | { |
c22834ec | 181 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 182 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 183 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 184 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 185 | u32 ctl_reg, stat_reg; |
541998a1 | 186 | |
c619eed4 | 187 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 188 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 189 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
190 | } else { |
191 | ctl_reg = PP_CONTROL; | |
de842eff | 192 | stat_reg = PP_STATUS; |
541998a1 | 193 | } |
79e53945 | 194 | |
7dec0606 | 195 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 196 | |
2a1292fd | 197 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 198 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
199 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
200 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 201 | |
24ded204 | 202 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
203 | } |
204 | ||
c22834ec | 205 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 206 | { |
c22834ec | 207 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 208 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 210 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
211 | |
212 | if (HAS_PCH_SPLIT(dev)) { | |
213 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 214 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
215 | } else { |
216 | ctl_reg = PP_CONTROL; | |
de842eff | 217 | stat_reg = PP_STATUS; |
2a1292fd CW |
218 | } |
219 | ||
47356eb6 | 220 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
221 | |
222 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
223 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
224 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 225 | |
7dec0606 DV |
226 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
227 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
228 | } |
229 | ||
79e53945 JB |
230 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
231 | struct drm_display_mode *mode) | |
232 | { | |
dd06f90e JN |
233 | struct intel_connector *intel_connector = to_intel_connector(connector); |
234 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 235 | |
788319d4 CW |
236 | if (mode->hdisplay > fixed_mode->hdisplay) |
237 | return MODE_PANEL; | |
238 | if (mode->vdisplay > fixed_mode->vdisplay) | |
239 | return MODE_PANEL; | |
79e53945 JB |
240 | |
241 | return MODE_OK; | |
242 | } | |
243 | ||
49be663f CW |
244 | static void |
245 | centre_horizontally(struct drm_display_mode *mode, | |
246 | int width) | |
247 | { | |
248 | u32 border, sync_pos, blank_width, sync_width; | |
249 | ||
250 | /* keep the hsync and hblank widths constant */ | |
251 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
252 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
253 | sync_pos = (blank_width - sync_width + 1) / 2; | |
254 | ||
255 | border = (mode->hdisplay - width + 1) / 2; | |
256 | border += border & 1; /* make the border even */ | |
257 | ||
258 | mode->crtc_hdisplay = width; | |
259 | mode->crtc_hblank_start = width + border; | |
260 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
261 | ||
262 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
263 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
264 | } | |
265 | ||
266 | static void | |
267 | centre_vertically(struct drm_display_mode *mode, | |
268 | int height) | |
269 | { | |
270 | u32 border, sync_pos, blank_width, sync_width; | |
271 | ||
272 | /* keep the vsync and vblank widths constant */ | |
273 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
274 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
275 | sync_pos = (blank_width - sync_width + 1) / 2; | |
276 | ||
277 | border = (mode->vdisplay - height + 1) / 2; | |
278 | ||
279 | mode->crtc_vdisplay = height; | |
280 | mode->crtc_vblank_start = height + border; | |
281 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
282 | ||
283 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
284 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
285 | } | |
286 | ||
287 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
288 | { | |
289 | /* | |
290 | * Floating point operation is not supported. So the FACTOR | |
291 | * is defined, which can avoid the floating point computation | |
292 | * when calculating the panel ratio. | |
293 | */ | |
294 | #define ACCURACY 12 | |
295 | #define FACTOR (1 << ACCURACY) | |
296 | u32 ratio = source * FACTOR / target; | |
297 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
298 | } | |
299 | ||
7ae89233 DV |
300 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
301 | struct intel_crtc_config *pipe_config) | |
79e53945 | 302 | { |
7ae89233 | 303 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
305 | struct intel_lvds_encoder *lvds_encoder = |
306 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
307 | struct intel_connector *intel_connector = |
308 | &lvds_encoder->attached_connector->base; | |
7ae89233 DV |
309 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
310 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
29b99b48 | 311 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
49be663f | 312 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
4e53c2e0 | 313 | unsigned int lvds_bpp; |
9db4a9c7 | 314 | int pipe; |
79e53945 JB |
315 | |
316 | /* Should never happen!! */ | |
a6c45cf0 | 317 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 318 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
319 | return false; |
320 | } | |
321 | ||
29b99b48 | 322 | if (intel_encoder_check_is_cloned(&lvds_encoder->base)) |
e24c5c29 | 323 | return false; |
1d8e1c75 | 324 | |
4e53c2e0 DV |
325 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
326 | LVDS_A3_POWER_UP) | |
327 | lvds_bpp = 8*3; | |
328 | else | |
329 | lvds_bpp = 6*3; | |
330 | ||
331 | if (lvds_bpp != pipe_config->pipe_bpp) { | |
332 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", | |
333 | pipe_config->pipe_bpp, lvds_bpp); | |
334 | pipe_config->pipe_bpp = lvds_bpp; | |
335 | } | |
79e53945 | 336 | /* |
71677043 | 337 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
338 | * to the adjusted mode. The CRTC will be set up for this mode, |
339 | * with the panel scaling set up to source from the H/VDisplay | |
340 | * of the original mode. | |
341 | */ | |
4d891523 | 342 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 343 | adjusted_mode); |
1d8e1c75 CW |
344 | |
345 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
346 | pipe_config->has_pch_encoder = true; |
347 | ||
4d891523 JN |
348 | intel_pch_panel_fitting(dev, |
349 | intel_connector->panel.fitting_mode, | |
1d8e1c75 CW |
350 | mode, adjusted_mode); |
351 | return true; | |
352 | } | |
79e53945 | 353 | |
3fbe18d6 ZY |
354 | /* Native modes don't need fitting */ |
355 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 356 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 357 | goto out; |
3fbe18d6 ZY |
358 | |
359 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 360 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
361 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
362 | PFIT_FILTER_FUZZY); | |
363 | ||
3fbe18d6 ZY |
364 | /* |
365 | * Enable automatic panel scaling for non-native modes so that they fill | |
366 | * the screen. Should be enabled before the pipe is enabled, according | |
367 | * to register description and PRM. | |
368 | * Change the value here to see the borders for debugging | |
369 | */ | |
9db4a9c7 JB |
370 | for_each_pipe(pipe) |
371 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 372 | |
f9bef081 | 373 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
7ae89233 | 374 | pipe_config->timings_set = true; |
f9bef081 | 375 | |
4d891523 | 376 | switch (intel_connector->panel.fitting_mode) { |
53bd8389 | 377 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
378 | /* |
379 | * For centered modes, we have to calculate border widths & | |
380 | * heights and modify the values programmed into the CRTC. | |
381 | */ | |
49be663f CW |
382 | centre_horizontally(adjusted_mode, mode->hdisplay); |
383 | centre_vertically(adjusted_mode, mode->vdisplay); | |
384 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 385 | break; |
49be663f | 386 | |
3fbe18d6 | 387 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 388 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 389 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
390 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
391 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
392 | ||
3fbe18d6 | 393 | /* 965+ is easy, it does everything in hw */ |
49be663f | 394 | if (scaled_width > scaled_height) |
257e48f1 | 395 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 396 | else if (scaled_width < scaled_height) |
257e48f1 CW |
397 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
398 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
399 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 400 | } else { |
49be663f CW |
401 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
402 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
403 | /* |
404 | * For earlier chips we have to calculate the scaling | |
405 | * ratio by hand and program it into the | |
406 | * PFIT_PGM_RATIO register | |
407 | */ | |
49be663f CW |
408 | if (scaled_width > scaled_height) { /* pillar */ |
409 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
410 | ||
411 | border = LVDS_BORDER_ENABLE; | |
412 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
413 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
414 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
415 | bits << PFIT_VERT_SCALE_SHIFT); | |
416 | pfit_control |= (PFIT_ENABLE | | |
417 | VERT_INTERP_BILINEAR | | |
418 | HORIZ_INTERP_BILINEAR); | |
419 | } | |
420 | } else if (scaled_width < scaled_height) { /* letter */ | |
421 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
422 | ||
423 | border = LVDS_BORDER_ENABLE; | |
424 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
425 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
426 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
427 | bits << PFIT_VERT_SCALE_SHIFT); | |
428 | pfit_control |= (PFIT_ENABLE | | |
429 | VERT_INTERP_BILINEAR | | |
430 | HORIZ_INTERP_BILINEAR); | |
431 | } | |
432 | } else | |
433 | /* Aspects match, Let hw scale both directions */ | |
434 | pfit_control |= (PFIT_ENABLE | | |
435 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
436 | VERT_INTERP_BILINEAR | |
437 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
438 | } |
439 | break; | |
440 | ||
441 | case DRM_MODE_SCALE_FULLSCREEN: | |
442 | /* | |
443 | * Full scaling, even if it changes the aspect ratio. | |
444 | * Fortunately this is all done for us in hw. | |
445 | */ | |
257e48f1 CW |
446 | if (mode->vdisplay != adjusted_mode->vdisplay || |
447 | mode->hdisplay != adjusted_mode->hdisplay) { | |
448 | pfit_control |= PFIT_ENABLE; | |
449 | if (INTEL_INFO(dev)->gen >= 4) | |
450 | pfit_control |= PFIT_SCALING_AUTO; | |
451 | else | |
452 | pfit_control |= (VERT_AUTO_SCALE | | |
453 | VERT_INTERP_BILINEAR | | |
454 | HORIZ_AUTO_SCALE | | |
455 | HORIZ_INTERP_BILINEAR); | |
456 | } | |
3fbe18d6 | 457 | break; |
49be663f | 458 | |
3fbe18d6 ZY |
459 | default: |
460 | break; | |
461 | } | |
462 | ||
463 | out: | |
72389a33 | 464 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
465 | if ((pfit_control & PFIT_ENABLE) == 0) { |
466 | pfit_control = 0; | |
467 | pfit_pgm_ratios = 0; | |
468 | } | |
72389a33 CW |
469 | |
470 | /* Make sure pre-965 set dither correctly */ | |
471 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
472 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
473 | ||
29b99b48 JN |
474 | if (pfit_control != lvds_encoder->pfit_control || |
475 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | |
476 | lvds_encoder->pfit_control = pfit_control; | |
477 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | |
e9e331a8 | 478 | } |
49be663f CW |
479 | dev_priv->lvds_border_bits = border; |
480 | ||
79e53945 JB |
481 | /* |
482 | * XXX: It would be nice to support lower refresh rates on the | |
483 | * panels to reduce power consumption, and perhaps match the | |
484 | * user's requested refresh rate. | |
485 | */ | |
486 | ||
487 | return true; | |
488 | } | |
489 | ||
79e53945 JB |
490 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
491 | struct drm_display_mode *mode, | |
492 | struct drm_display_mode *adjusted_mode) | |
493 | { | |
79e53945 JB |
494 | /* |
495 | * The LVDS pin pair will already have been turned on in the | |
496 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
497 | * settings. | |
498 | */ | |
79e53945 JB |
499 | } |
500 | ||
501 | /** | |
502 | * Detect the LVDS connection. | |
503 | * | |
b42d4c5c JB |
504 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
505 | * connected and closed means disconnected. We also send hotplug events as | |
506 | * needed, using lid status notification from the input layer. | |
79e53945 | 507 | */ |
7b334fcb | 508 | static enum drm_connector_status |
930a9e28 | 509 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 510 | { |
7b9c5abe | 511 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 512 | enum drm_connector_status status; |
b42d4c5c | 513 | |
fe16d949 CW |
514 | status = intel_panel_detect(dev); |
515 | if (status != connector_status_unknown) | |
516 | return status; | |
01fe9dbd | 517 | |
6ee3b5a1 | 518 | return connector_status_connected; |
79e53945 JB |
519 | } |
520 | ||
521 | /** | |
522 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
523 | */ | |
524 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
525 | { | |
62165e0d | 526 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 527 | struct drm_device *dev = connector->dev; |
788319d4 | 528 | struct drm_display_mode *mode; |
79e53945 | 529 | |
9cd300e0 | 530 | /* use cached edid if we have one */ |
2aa4f099 | 531 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 532 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 533 | |
dd06f90e | 534 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 535 | if (mode == NULL) |
788319d4 | 536 | return 0; |
79e53945 | 537 | |
788319d4 CW |
538 | drm_mode_probed_add(connector, mode); |
539 | return 1; | |
79e53945 JB |
540 | } |
541 | ||
0544edfd TB |
542 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
543 | { | |
bc0daf48 | 544 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
545 | return 1; |
546 | } | |
547 | ||
548 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
549 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
550 | { | |
551 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
552 | .ident = "Toshiba Tecra A11", | |
553 | .matches = { | |
554 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
555 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
556 | }, | |
557 | }, | |
558 | ||
559 | { } /* terminating entry */ | |
560 | }; | |
561 | ||
c9354c85 | 562 | /* |
b8efb17b ZR |
563 | * Lid events. Note the use of 'modeset': |
564 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
565 | * and set it to MODESET_DONE on open | |
c9354c85 | 566 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
567 | * duplicate events where it was already properly set) |
568 | * - the suspend/resume paths will set it to | |
569 | * MODESET_SUSPENDED and ignore the lid open event, | |
570 | * because they restore the mode ("lid open"). | |
c9354c85 | 571 | */ |
c1c7af60 JB |
572 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
573 | void *unused) | |
574 | { | |
db1740a0 JN |
575 | struct intel_lvds_connector *lvds_connector = |
576 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
577 | struct drm_connector *connector = &lvds_connector->base.base; | |
578 | struct drm_device *dev = connector->dev; | |
579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 580 | |
2fb4e61d AW |
581 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
582 | return NOTIFY_OK; | |
583 | ||
b8efb17b ZR |
584 | mutex_lock(&dev_priv->modeset_restore_lock); |
585 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
586 | goto exit; | |
a2565377 ZY |
587 | /* |
588 | * check and update the status of LVDS connector after receiving | |
589 | * the LID nofication event. | |
590 | */ | |
db1740a0 | 591 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 592 | |
0544edfd TB |
593 | /* Don't force modeset on machines where it causes a GPU lockup */ |
594 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 595 | goto exit; |
c9354c85 | 596 | if (!acpi_lid_open()) { |
b8efb17b ZR |
597 | /* do modeset on next lid open event */ |
598 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
599 | goto exit; | |
06891e27 | 600 | } |
c1c7af60 | 601 | |
b8efb17b ZR |
602 | if (dev_priv->modeset_restore == MODESET_DONE) |
603 | goto exit; | |
c9354c85 | 604 | |
a0e99e68 | 605 | drm_modeset_lock_all(dev); |
45e2b5f6 | 606 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 607 | drm_modeset_unlock_all(dev); |
06324194 | 608 | |
b8efb17b ZR |
609 | dev_priv->modeset_restore = MODESET_DONE; |
610 | ||
611 | exit: | |
612 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
613 | return NOTIFY_OK; |
614 | } | |
615 | ||
79e53945 JB |
616 | /** |
617 | * intel_lvds_destroy - unregister and free LVDS structures | |
618 | * @connector: connector to free | |
619 | * | |
620 | * Unregister the DDC bus for this connector then free the driver private | |
621 | * structure. | |
622 | */ | |
623 | static void intel_lvds_destroy(struct drm_connector *connector) | |
624 | { | |
db1740a0 JN |
625 | struct intel_lvds_connector *lvds_connector = |
626 | to_lvds_connector(connector); | |
79e53945 | 627 | |
db1740a0 JN |
628 | if (lvds_connector->lid_notifier.notifier_call) |
629 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 630 | |
9cd300e0 JN |
631 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
632 | kfree(lvds_connector->base.edid); | |
633 | ||
db1740a0 | 634 | intel_panel_destroy_backlight(connector->dev); |
1d508706 | 635 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 636 | |
79e53945 JB |
637 | drm_sysfs_connector_remove(connector); |
638 | drm_connector_cleanup(connector); | |
639 | kfree(connector); | |
640 | } | |
641 | ||
335041ed JB |
642 | static int intel_lvds_set_property(struct drm_connector *connector, |
643 | struct drm_property *property, | |
644 | uint64_t value) | |
645 | { | |
4d891523 | 646 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 647 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 648 | |
788319d4 | 649 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 650 | struct drm_crtc *crtc; |
bb8a3560 | 651 | |
53bd8389 JB |
652 | if (value == DRM_MODE_SCALE_NONE) { |
653 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 654 | return -EINVAL; |
3fbe18d6 | 655 | } |
788319d4 | 656 | |
4d891523 | 657 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
658 | /* the LVDS scaling property is not changed */ |
659 | return 0; | |
660 | } | |
4d891523 | 661 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
662 | |
663 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
664 | if (crtc && crtc->enabled) { |
665 | /* | |
666 | * If the CRTC is enabled, the display will be changed | |
667 | * according to the new panel fitting mode. | |
668 | */ | |
c0c36b94 | 669 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
670 | } |
671 | } | |
672 | ||
335041ed JB |
673 | return 0; |
674 | } | |
675 | ||
79e53945 | 676 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 677 | .mode_set = intel_lvds_mode_set, |
79e53945 JB |
678 | }; |
679 | ||
680 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
681 | .get_modes = intel_lvds_get_modes, | |
682 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 683 | .best_encoder = intel_best_encoder, |
79e53945 JB |
684 | }; |
685 | ||
686 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 687 | .dpms = intel_connector_dpms, |
79e53945 JB |
688 | .detect = intel_lvds_detect, |
689 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 690 | .set_property = intel_lvds_set_property, |
79e53945 JB |
691 | .destroy = intel_lvds_destroy, |
692 | }; | |
693 | ||
79e53945 | 694 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 695 | .destroy = intel_encoder_destroy, |
79e53945 JB |
696 | }; |
697 | ||
425d244c JW |
698 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
699 | { | |
bc0daf48 | 700 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
701 | return 1; |
702 | } | |
79e53945 | 703 | |
425d244c | 704 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 705 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
706 | { |
707 | .callback = intel_no_lvds_dmi_callback, | |
708 | .ident = "Apple Mac Mini (Core series)", | |
709 | .matches = { | |
98acd46f | 710 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
711 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
712 | }, | |
713 | }, | |
714 | { | |
715 | .callback = intel_no_lvds_dmi_callback, | |
716 | .ident = "Apple Mac Mini (Core 2 series)", | |
717 | .matches = { | |
98acd46f | 718 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
719 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
720 | }, | |
721 | }, | |
722 | { | |
723 | .callback = intel_no_lvds_dmi_callback, | |
724 | .ident = "MSI IM-945GSE-A", | |
725 | .matches = { | |
726 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
727 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
728 | }, | |
729 | }, | |
730 | { | |
731 | .callback = intel_no_lvds_dmi_callback, | |
732 | .ident = "Dell Studio Hybrid", | |
733 | .matches = { | |
734 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
735 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
736 | }, | |
737 | }, | |
70aa96ca JW |
738 | { |
739 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
740 | .ident = "Dell OptiPlex FX170", |
741 | .matches = { | |
742 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
743 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
744 | }, | |
745 | }, | |
746 | { | |
747 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
748 | .ident = "AOpen Mini PC", |
749 | .matches = { | |
750 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
751 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
752 | }, | |
753 | }, | |
ed8c754b TV |
754 | { |
755 | .callback = intel_no_lvds_dmi_callback, | |
756 | .ident = "AOpen Mini PC MP915", | |
757 | .matches = { | |
758 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
759 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
760 | }, | |
761 | }, | |
22ab70d3 KP |
762 | { |
763 | .callback = intel_no_lvds_dmi_callback, | |
764 | .ident = "AOpen i915GMm-HFS", | |
765 | .matches = { | |
766 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
767 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
768 | }, | |
769 | }, | |
e57b6886 DV |
770 | { |
771 | .callback = intel_no_lvds_dmi_callback, | |
772 | .ident = "AOpen i45GMx-I", | |
773 | .matches = { | |
774 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
775 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
776 | }, | |
777 | }, | |
fa0864b2 MC |
778 | { |
779 | .callback = intel_no_lvds_dmi_callback, | |
780 | .ident = "Aopen i945GTt-VFA", | |
781 | .matches = { | |
782 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
783 | }, | |
784 | }, | |
9875557e SB |
785 | { |
786 | .callback = intel_no_lvds_dmi_callback, | |
787 | .ident = "Clientron U800", | |
788 | .matches = { | |
789 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
790 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
791 | }, | |
792 | }, | |
6a574b5b | 793 | { |
44306ab3 JS |
794 | .callback = intel_no_lvds_dmi_callback, |
795 | .ident = "Clientron E830", | |
796 | .matches = { | |
797 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
798 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
799 | }, | |
800 | }, | |
801 | { | |
6a574b5b HG |
802 | .callback = intel_no_lvds_dmi_callback, |
803 | .ident = "Asus EeeBox PC EB1007", | |
804 | .matches = { | |
805 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
806 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
807 | }, | |
808 | }, | |
0999bbe0 AJ |
809 | { |
810 | .callback = intel_no_lvds_dmi_callback, | |
811 | .ident = "Asus AT5NM10T-I", | |
812 | .matches = { | |
813 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
814 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
815 | }, | |
816 | }, | |
33471119 JBG |
817 | { |
818 | .callback = intel_no_lvds_dmi_callback, | |
819 | .ident = "Hewlett-Packard HP t5740e Thin Client", | |
820 | .matches = { | |
821 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
822 | DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"), | |
823 | }, | |
824 | }, | |
f5b8a7ed MG |
825 | { |
826 | .callback = intel_no_lvds_dmi_callback, | |
827 | .ident = "Hewlett-Packard t5745", | |
828 | .matches = { | |
829 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 830 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
831 | }, |
832 | }, | |
833 | { | |
834 | .callback = intel_no_lvds_dmi_callback, | |
835 | .ident = "Hewlett-Packard st5747", | |
836 | .matches = { | |
837 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 838 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
839 | }, |
840 | }, | |
97effadb AA |
841 | { |
842 | .callback = intel_no_lvds_dmi_callback, | |
843 | .ident = "MSI Wind Box DC500", | |
844 | .matches = { | |
845 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
846 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
847 | }, | |
848 | }, | |
a51d4ed0 CW |
849 | { |
850 | .callback = intel_no_lvds_dmi_callback, | |
851 | .ident = "Gigabyte GA-D525TUD", | |
852 | .matches = { | |
853 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
854 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
855 | }, | |
856 | }, | |
c31407a3 CW |
857 | { |
858 | .callback = intel_no_lvds_dmi_callback, | |
859 | .ident = "Supermicro X7SPA-H", | |
860 | .matches = { | |
861 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
862 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
863 | }, | |
864 | }, | |
425d244c JW |
865 | |
866 | { } /* terminating entry */ | |
867 | }; | |
79e53945 | 868 | |
18f9ed12 ZY |
869 | /** |
870 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
871 | * @dev: drm device | |
872 | * @connector: LVDS connector | |
873 | * | |
874 | * Find the reduced downclock for LVDS in EDID. | |
875 | */ | |
876 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
877 | struct drm_display_mode *fixed_mode, |
878 | struct drm_connector *connector) | |
18f9ed12 ZY |
879 | { |
880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 881 | struct drm_display_mode *scan; |
18f9ed12 ZY |
882 | int temp_downclock; |
883 | ||
788319d4 | 884 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
885 | list_for_each_entry(scan, &connector->probed_modes, head) { |
886 | /* | |
887 | * If one mode has the same resolution with the fixed_panel | |
888 | * mode while they have the different refresh rate, it means | |
889 | * that the reduced downclock is found for the LVDS. In such | |
890 | * case we can set the different FPx0/1 to dynamically select | |
891 | * between low and high frequency. | |
892 | */ | |
788319d4 CW |
893 | if (scan->hdisplay == fixed_mode->hdisplay && |
894 | scan->hsync_start == fixed_mode->hsync_start && | |
895 | scan->hsync_end == fixed_mode->hsync_end && | |
896 | scan->htotal == fixed_mode->htotal && | |
897 | scan->vdisplay == fixed_mode->vdisplay && | |
898 | scan->vsync_start == fixed_mode->vsync_start && | |
899 | scan->vsync_end == fixed_mode->vsync_end && | |
900 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
901 | if (scan->clock < temp_downclock) { |
902 | /* | |
903 | * The downclock is already found. But we | |
904 | * expect to find the lower downclock. | |
905 | */ | |
906 | temp_downclock = scan->clock; | |
907 | } | |
908 | } | |
909 | } | |
788319d4 | 910 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
911 | /* We found the downclock for LVDS. */ |
912 | dev_priv->lvds_downclock_avail = 1; | |
913 | dev_priv->lvds_downclock = temp_downclock; | |
914 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
915 | "Normal clock %dKhz, downclock %dKhz\n", |
916 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 917 | } |
18f9ed12 ZY |
918 | } |
919 | ||
7cf4f69d ZY |
920 | /* |
921 | * Enumerate the child dev array parsed from VBT to check whether | |
922 | * the LVDS is present. | |
923 | * If it is present, return 1. | |
924 | * If it is not present, return false. | |
925 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 926 | */ |
270eea0f CW |
927 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
928 | u8 *i2c_pin) | |
7cf4f69d ZY |
929 | { |
930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 931 | int i; |
7cf4f69d ZY |
932 | |
933 | if (!dev_priv->child_dev_num) | |
425904dd | 934 | return true; |
7cf4f69d | 935 | |
7cf4f69d | 936 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
937 | struct child_device_config *child = dev_priv->child_dev + i; |
938 | ||
939 | /* If the device type is not LFP, continue. | |
940 | * We have to check both the new identifiers as well as the | |
941 | * old for compatibility with some BIOSes. | |
7cf4f69d | 942 | */ |
425904dd CW |
943 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
944 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
945 | continue; |
946 | ||
3bd7d909 DK |
947 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
948 | *i2c_pin = child->i2c_pin; | |
270eea0f | 949 | |
425904dd CW |
950 | /* However, we cannot trust the BIOS writers to populate |
951 | * the VBT correctly. Since LVDS requires additional | |
952 | * information from AIM blocks, a non-zero addin offset is | |
953 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 954 | */ |
425904dd CW |
955 | if (child->addin_offset) |
956 | return true; | |
957 | ||
958 | /* But even then some BIOS writers perform some black magic | |
959 | * and instantiate the device without reference to any | |
960 | * additional data. Trust that if the VBT was written into | |
961 | * the OpRegion then they have validated the LVDS's existence. | |
962 | */ | |
963 | if (dev_priv->opregion.vbt) | |
964 | return true; | |
7cf4f69d | 965 | } |
425904dd CW |
966 | |
967 | return false; | |
7cf4f69d ZY |
968 | } |
969 | ||
1974cad0 DV |
970 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
971 | { | |
972 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
973 | return 1; | |
974 | } | |
975 | ||
976 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
977 | { | |
978 | .callback = intel_dual_link_lvds_callback, | |
979 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
980 | .matches = { | |
981 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
982 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
983 | }, | |
984 | }, | |
985 | { } /* terminating entry */ | |
986 | }; | |
987 | ||
988 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
989 | { |
990 | struct intel_encoder *encoder; | |
991 | struct intel_lvds_encoder *lvds_encoder; | |
992 | ||
993 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
994 | base.head) { | |
995 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
996 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
997 | ||
998 | return lvds_encoder->is_dual_link; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | return false; | |
1003 | } | |
1004 | ||
7dec0606 | 1005 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 1006 | { |
7dec0606 | 1007 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
1008 | unsigned int val; |
1009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
1010 | |
1011 | /* use the module option value if specified */ | |
1012 | if (i915_lvds_channel_mode > 0) | |
1013 | return i915_lvds_channel_mode == 2; | |
1014 | ||
1015 | if (dmi_check_system(intel_dual_link_lvds)) | |
1016 | return true; | |
1017 | ||
13c7d870 DV |
1018 | /* BIOS should set the proper LVDS register value at boot, but |
1019 | * in reality, it doesn't set the value when the lid is closed; | |
1020 | * we need to check "the value to be set" in VBT when LVDS | |
1021 | * register is uninitialized. | |
1022 | */ | |
7dec0606 | 1023 | val = I915_READ(lvds_encoder->reg); |
13c7d870 DV |
1024 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
1025 | val = dev_priv->bios_lvds_val; | |
1026 | ||
1974cad0 DV |
1027 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
1028 | } | |
1029 | ||
f3cfcba6 CW |
1030 | static bool intel_lvds_supported(struct drm_device *dev) |
1031 | { | |
1032 | /* With the introduction of the PCH we gained a dedicated | |
1033 | * LVDS presence pin, use it. */ | |
311e359c | 1034 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
1035 | return true; |
1036 | ||
1037 | /* Otherwise LVDS was only attached to mobile products, | |
1038 | * except for the inglorious 830gm */ | |
311e359c PZ |
1039 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
1040 | return true; | |
1041 | ||
1042 | return false; | |
f3cfcba6 CW |
1043 | } |
1044 | ||
79e53945 JB |
1045 | /** |
1046 | * intel_lvds_init - setup LVDS connectors on this device | |
1047 | * @dev: drm device | |
1048 | * | |
1049 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
1050 | * modes we can display on the LVDS panel (if present). | |
1051 | */ | |
c5d1b51d | 1052 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
1053 | { |
1054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 1055 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 1056 | struct intel_encoder *intel_encoder; |
c7362c4d | 1057 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 1058 | struct intel_connector *intel_connector; |
79e53945 JB |
1059 | struct drm_connector *connector; |
1060 | struct drm_encoder *encoder; | |
1061 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 1062 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 1063 | struct edid *edid; |
79e53945 JB |
1064 | struct drm_crtc *crtc; |
1065 | u32 lvds; | |
270eea0f CW |
1066 | int pipe; |
1067 | u8 pin; | |
79e53945 | 1068 | |
f3cfcba6 CW |
1069 | if (!intel_lvds_supported(dev)) |
1070 | return false; | |
1071 | ||
425d244c JW |
1072 | /* Skip init on machines we know falsely report LVDS */ |
1073 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 1074 | return false; |
565dcd46 | 1075 | |
270eea0f CW |
1076 | pin = GMBUS_PORT_PANEL; |
1077 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 1078 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 1079 | return false; |
38b3037e | 1080 | } |
e99da35f | 1081 | |
c619eed4 | 1082 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1083 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 1084 | return false; |
5ceb0f9b | 1085 | if (dev_priv->edp.support) { |
28c97730 | 1086 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 1087 | return false; |
32f9d658 | 1088 | } |
541998a1 ZW |
1089 | } |
1090 | ||
29b99b48 JN |
1091 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
1092 | if (!lvds_encoder) | |
c5d1b51d | 1093 | return false; |
79e53945 | 1094 | |
c7362c4d JN |
1095 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
1096 | if (!lvds_connector) { | |
29b99b48 | 1097 | kfree(lvds_encoder); |
c5d1b51d | 1098 | return false; |
bb8a3560 ZW |
1099 | } |
1100 | ||
62165e0d JN |
1101 | lvds_encoder->attached_connector = lvds_connector; |
1102 | ||
e9e331a8 | 1103 | if (!HAS_PCH_SPLIT(dev)) { |
29b99b48 | 1104 | lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); |
e9e331a8 CW |
1105 | } |
1106 | ||
29b99b48 | 1107 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1108 | encoder = &intel_encoder->base; |
c7362c4d | 1109 | intel_connector = &lvds_connector->base; |
ea5b213a | 1110 | connector = &intel_connector->base; |
bb8a3560 | 1111 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1112 | DRM_MODE_CONNECTOR_LVDS); |
1113 | ||
4ef69c7a | 1114 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
1115 | DRM_MODE_ENCODER_LVDS); |
1116 | ||
c22834ec | 1117 | intel_encoder->enable = intel_enable_lvds; |
9d6d9f19 | 1118 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
fc683091 | 1119 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
7ae89233 | 1120 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 1121 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c DV |
1122 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
1123 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
c22834ec | 1124 | |
df0e9248 | 1125 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1126 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1127 | |
66a9278e | 1128 | intel_encoder->cloneable = false; |
27f8227b JB |
1129 | if (HAS_PCH_SPLIT(dev)) |
1130 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1131 | else if (IS_GEN4(dev)) |
1132 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1133 | else |
1134 | intel_encoder->crtc_mask = (1 << 1); | |
1135 | ||
79e53945 JB |
1136 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1137 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1138 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1139 | connector->interlace_allowed = false; | |
1140 | connector->doublescan_allowed = false; | |
1141 | ||
7dec0606 DV |
1142 | if (HAS_PCH_SPLIT(dev)) { |
1143 | lvds_encoder->reg = PCH_LVDS; | |
1144 | } else { | |
1145 | lvds_encoder->reg = LVDS; | |
1146 | } | |
1147 | ||
3fbe18d6 ZY |
1148 | /* create the scaling mode property */ |
1149 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1150 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1151 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1152 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1153 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1154 | /* |
1155 | * LVDS discovery: | |
1156 | * 1) check for EDID on DDC | |
1157 | * 2) check for VBT data | |
1158 | * 3) check to see if LVDS is already on | |
1159 | * if none of the above, no panel | |
1160 | * 4) make sure lid is open | |
1161 | * if closed, act like it's not there for now | |
1162 | */ | |
1163 | ||
79e53945 JB |
1164 | /* |
1165 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1166 | * preferred mode is the right one. | |
1167 | */ | |
9cd300e0 JN |
1168 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1169 | if (edid) { | |
1170 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1171 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1172 | edid); |
3f8ff0e7 | 1173 | } else { |
9cd300e0 JN |
1174 | kfree(edid); |
1175 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1176 | } |
9cd300e0 JN |
1177 | } else { |
1178 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1179 | } |
9cd300e0 JN |
1180 | lvds_connector->base.edid = edid; |
1181 | ||
1182 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1183 | /* Didn't get an EDID, so |
1184 | * Set wide sync ranges so we get all modes | |
1185 | * handed to valid_mode for checking | |
1186 | */ | |
1187 | connector->display_info.min_vfreq = 0; | |
1188 | connector->display_info.max_vfreq = 200; | |
1189 | connector->display_info.min_hfreq = 0; | |
1190 | connector->display_info.max_hfreq = 200; | |
1191 | } | |
79e53945 JB |
1192 | |
1193 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1194 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1195 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1196 | drm_mode_debug_printmodeline(scan); | |
1197 | ||
dd06f90e | 1198 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1199 | if (fixed_mode) { |
1200 | intel_find_lvds_downclock(dev, fixed_mode, | |
1201 | connector); | |
1202 | goto out; | |
1203 | } | |
79e53945 | 1204 | } |
79e53945 JB |
1205 | } |
1206 | ||
1207 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1208 | if (dev_priv->lfp_lvds_vbt_mode) { |
6a9d51b7 CW |
1209 | DRM_DEBUG_KMS("using mode from VBT: "); |
1210 | drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); | |
1211 | ||
dd06f90e JN |
1212 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
1213 | if (fixed_mode) { | |
1214 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1215 | goto out; |
1216 | } | |
79e53945 JB |
1217 | } |
1218 | ||
1219 | /* | |
1220 | * If we didn't get EDID, try checking if the panel is already turned | |
1221 | * on. If so, assume that whatever is currently programmed is the | |
1222 | * correct mode. | |
1223 | */ | |
541998a1 | 1224 | |
f2b115e6 | 1225 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1226 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1227 | goto failed; |
1228 | ||
79e53945 JB |
1229 | lvds = I915_READ(LVDS); |
1230 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1231 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1232 | |
1233 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1234 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1235 | if (fixed_mode) { | |
6a9d51b7 CW |
1236 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1237 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1238 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1239 | goto out; |
79e53945 JB |
1240 | } |
1241 | } | |
1242 | ||
1243 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1244 | if (!fixed_mode) |
79e53945 JB |
1245 | goto failed; |
1246 | ||
79e53945 | 1247 | out: |
7dec0606 | 1248 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1249 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1250 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1251 | ||
24ded204 DV |
1252 | /* |
1253 | * Unlock registers and just | |
1254 | * leave them unlocked | |
1255 | */ | |
c619eed4 | 1256 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1257 | I915_WRITE(PCH_PP_CONTROL, |
1258 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1259 | } else { | |
ed10fca9 KP |
1260 | I915_WRITE(PP_CONTROL, |
1261 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1262 | } |
db1740a0 JN |
1263 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1264 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1265 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1266 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1267 | } |
79e53945 | 1268 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1269 | |
dd06f90e | 1270 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1271 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1272 | |
c5d1b51d | 1273 | return true; |
79e53945 JB |
1274 | |
1275 | failed: | |
8a4c47f3 | 1276 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1277 | drm_connector_cleanup(connector); |
1991bdfa | 1278 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1279 | if (fixed_mode) |
1280 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1281 | kfree(lvds_encoder); |
c7362c4d | 1282 | kfree(lvds_connector); |
c5d1b51d | 1283 | return false; |
79e53945 | 1284 | } |