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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 JB |
32 | #include <linux/i2c.h> |
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "drm_crtc.h" | |
36 | #include "drm_edid.h" | |
37 | #include "intel_drv.h" | |
38 | #include "i915_drm.h" | |
39 | #include "i915_drv.h" | |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 ZY |
42 | /* Private structure for the integrated LVDS support */ |
43 | struct intel_lvds_priv { | |
44 | int fitting_mode; | |
45 | u32 pfit_control; | |
46 | u32 pfit_pgm_ratios; | |
47 | }; | |
48 | ||
79e53945 JB |
49 | /** |
50 | * Sets the backlight level. | |
51 | * | |
52 | * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). | |
53 | */ | |
54 | static void intel_lvds_set_backlight(struct drm_device *dev, int level) | |
55 | { | |
56 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 57 | u32 blc_pwm_ctl, reg; |
79e53945 | 58 | |
c619eed4 | 59 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
60 | reg = BLC_PWM_CPU_CTL; |
61 | else | |
62 | reg = BLC_PWM_CTL; | |
79e53945 | 63 | |
541998a1 ZW |
64 | blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
65 | I915_WRITE(reg, (blc_pwm_ctl | | |
79e53945 JB |
66 | (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); |
67 | } | |
68 | ||
69 | /** | |
70 | * Returns the maximum level of the backlight duty cycle field. | |
71 | */ | |
72 | static u32 intel_lvds_get_max_backlight(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
75 | u32 reg; |
76 | ||
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
78 | reg = BLC_PWM_PCH_CTL2; |
79 | else | |
80 | reg = BLC_PWM_CTL; | |
79e53945 | 81 | |
541998a1 | 82 | return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >> |
79e53945 JB |
83 | BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; |
84 | } | |
85 | ||
86 | /** | |
87 | * Sets the power state for the panel. | |
88 | */ | |
89 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
90 | { | |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
469d1296 | 92 | u32 pp_status, ctl_reg, status_reg, lvds_reg; |
541998a1 | 93 | |
c619eed4 | 94 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
95 | ctl_reg = PCH_PP_CONTROL; |
96 | status_reg = PCH_PP_STATUS; | |
469d1296 | 97 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
98 | } else { |
99 | ctl_reg = PP_CONTROL; | |
100 | status_reg = PP_STATUS; | |
469d1296 | 101 | lvds_reg = LVDS; |
541998a1 | 102 | } |
79e53945 JB |
103 | |
104 | if (on) { | |
469d1296 JB |
105 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
106 | POSTING_READ(lvds_reg); | |
107 | ||
541998a1 | 108 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | |
79e53945 JB |
109 | POWER_TARGET_ON); |
110 | do { | |
541998a1 | 111 | pp_status = I915_READ(status_reg); |
79e53945 JB |
112 | } while ((pp_status & PP_ON) == 0); |
113 | ||
114 | intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); | |
115 | } else { | |
116 | intel_lvds_set_backlight(dev, 0); | |
117 | ||
541998a1 | 118 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & |
79e53945 JB |
119 | ~POWER_TARGET_ON); |
120 | do { | |
541998a1 | 121 | pp_status = I915_READ(status_reg); |
79e53945 | 122 | } while (pp_status & PP_ON); |
469d1296 JB |
123 | |
124 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
125 | POSTING_READ(lvds_reg); | |
79e53945 JB |
126 | } |
127 | } | |
128 | ||
129 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
130 | { | |
131 | struct drm_device *dev = encoder->dev; | |
132 | ||
133 | if (mode == DRM_MODE_DPMS_ON) | |
134 | intel_lvds_set_power(dev, true); | |
135 | else | |
136 | intel_lvds_set_power(dev, false); | |
137 | ||
138 | /* XXX: We never power down the LVDS pairs. */ | |
139 | } | |
140 | ||
79e53945 JB |
141 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
142 | struct drm_display_mode *mode) | |
143 | { | |
144 | struct drm_device *dev = connector->dev; | |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
146 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
147 | ||
148 | if (fixed_mode) { | |
149 | if (mode->hdisplay > fixed_mode->hdisplay) | |
150 | return MODE_PANEL; | |
151 | if (mode->vdisplay > fixed_mode->vdisplay) | |
152 | return MODE_PANEL; | |
153 | } | |
154 | ||
155 | return MODE_OK; | |
156 | } | |
157 | ||
158 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |
159 | struct drm_display_mode *mode, | |
160 | struct drm_display_mode *adjusted_mode) | |
161 | { | |
3fbe18d6 ZY |
162 | /* |
163 | * float point operation is not supported . So the PANEL_RATIO_FACTOR | |
164 | * is defined, which can avoid the float point computation when | |
165 | * calculating the panel ratio. | |
166 | */ | |
167 | #define PANEL_RATIO_FACTOR 8192 | |
79e53945 JB |
168 | struct drm_device *dev = encoder->dev; |
169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
170 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
171 | struct drm_encoder *tmp_encoder; | |
21d40d37 EA |
172 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
173 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; | |
3fbe18d6 ZY |
174 | u32 pfit_control = 0, pfit_pgm_ratios = 0; |
175 | int left_border = 0, right_border = 0, top_border = 0; | |
176 | int bottom_border = 0; | |
177 | bool border = 0; | |
178 | int panel_ratio, desired_ratio, vert_scale, horiz_scale; | |
179 | int horiz_ratio, vert_ratio; | |
aa0261f2 ZY |
180 | u32 hsync_width, vsync_width; |
181 | u32 hblank_width, vblank_width; | |
182 | u32 hsync_pos, vsync_pos; | |
79e53945 JB |
183 | |
184 | /* Should never happen!! */ | |
185 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
1ae8c0a5 | 186 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
187 | return false; |
188 | } | |
189 | ||
190 | /* Should never happen!! */ | |
191 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
192 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 193 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
194 | "encoder on the same pipe\n"); |
195 | return false; | |
196 | } | |
197 | } | |
3fbe18d6 ZY |
198 | /* If we don't have a panel mode, there is nothing we can do */ |
199 | if (dev_priv->panel_fixed_mode == NULL) | |
200 | return true; | |
79e53945 JB |
201 | /* |
202 | * If we have timings from the BIOS for the panel, put them in | |
203 | * to the adjusted mode. The CRTC will be set up for this mode, | |
204 | * with the panel scaling set up to source from the H/VDisplay | |
205 | * of the original mode. | |
206 | */ | |
207 | if (dev_priv->panel_fixed_mode != NULL) { | |
208 | adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; | |
209 | adjusted_mode->hsync_start = | |
210 | dev_priv->panel_fixed_mode->hsync_start; | |
211 | adjusted_mode->hsync_end = | |
212 | dev_priv->panel_fixed_mode->hsync_end; | |
213 | adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; | |
214 | adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; | |
215 | adjusted_mode->vsync_start = | |
216 | dev_priv->panel_fixed_mode->vsync_start; | |
217 | adjusted_mode->vsync_end = | |
218 | dev_priv->panel_fixed_mode->vsync_end; | |
219 | adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; | |
220 | adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; | |
221 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
222 | } | |
223 | ||
3fbe18d6 ZY |
224 | /* Make sure pre-965s set dither correctly */ |
225 | if (!IS_I965G(dev)) { | |
226 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) | |
227 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
228 | } | |
229 | ||
230 | /* Native modes don't need fitting */ | |
231 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
232 | adjusted_mode->vdisplay == mode->vdisplay) { | |
233 | pfit_pgm_ratios = 0; | |
234 | border = 0; | |
235 | goto out; | |
236 | } | |
237 | ||
8dd81a38 | 238 | /* full screen scale for now */ |
c619eed4 | 239 | if (HAS_PCH_SPLIT(dev)) |
8dd81a38 ZW |
240 | goto out; |
241 | ||
3fbe18d6 ZY |
242 | /* 965+ wants fuzzy fitting */ |
243 | if (IS_I965G(dev)) | |
244 | pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
245 | PFIT_FILTER_FUZZY; | |
246 | ||
aa0261f2 ZY |
247 | hsync_width = adjusted_mode->crtc_hsync_end - |
248 | adjusted_mode->crtc_hsync_start; | |
249 | vsync_width = adjusted_mode->crtc_vsync_end - | |
250 | adjusted_mode->crtc_vsync_start; | |
251 | hblank_width = adjusted_mode->crtc_hblank_end - | |
252 | adjusted_mode->crtc_hblank_start; | |
253 | vblank_width = adjusted_mode->crtc_vblank_end - | |
254 | adjusted_mode->crtc_vblank_start; | |
3fbe18d6 ZY |
255 | /* |
256 | * Deal with panel fitting options. Figure out how to stretch the | |
257 | * image based on its aspect ratio & the current panel fitting mode. | |
258 | */ | |
259 | panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR / | |
260 | adjusted_mode->vdisplay; | |
261 | desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR / | |
262 | mode->vdisplay; | |
263 | /* | |
264 | * Enable automatic panel scaling for non-native modes so that they fill | |
265 | * the screen. Should be enabled before the pipe is enabled, according | |
266 | * to register description and PRM. | |
267 | * Change the value here to see the borders for debugging | |
268 | */ | |
c619eed4 | 269 | if (!HAS_PCH_SPLIT(dev)) { |
8dd81a38 ZW |
270 | I915_WRITE(BCLRPAT_A, 0); |
271 | I915_WRITE(BCLRPAT_B, 0); | |
272 | } | |
3fbe18d6 ZY |
273 | |
274 | switch (lvds_priv->fitting_mode) { | |
53bd8389 | 275 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
276 | /* |
277 | * For centered modes, we have to calculate border widths & | |
278 | * heights and modify the values programmed into the CRTC. | |
279 | */ | |
280 | left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2; | |
281 | right_border = left_border; | |
282 | if (mode->hdisplay & 1) | |
283 | right_border++; | |
284 | top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2; | |
285 | bottom_border = top_border; | |
286 | if (mode->vdisplay & 1) | |
287 | bottom_border++; | |
288 | /* Set active & border values */ | |
289 | adjusted_mode->crtc_hdisplay = mode->hdisplay; | |
aa0261f2 ZY |
290 | /* Keep the boder be even */ |
291 | if (right_border & 1) | |
292 | right_border++; | |
293 | /* use the border directly instead of border minuse one */ | |
3fbe18d6 | 294 | adjusted_mode->crtc_hblank_start = mode->hdisplay + |
aa0261f2 ZY |
295 | right_border; |
296 | /* keep the blank width constant */ | |
297 | adjusted_mode->crtc_hblank_end = | |
298 | adjusted_mode->crtc_hblank_start + hblank_width; | |
299 | /* get the hsync pos relative to hblank start */ | |
300 | hsync_pos = (hblank_width - hsync_width) / 2; | |
301 | /* keep the hsync pos be even */ | |
302 | if (hsync_pos & 1) | |
303 | hsync_pos++; | |
3fbe18d6 | 304 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
305 | adjusted_mode->crtc_hblank_start + hsync_pos; |
306 | /* keep the hsync width constant */ | |
3fbe18d6 | 307 | adjusted_mode->crtc_hsync_end = |
aa0261f2 | 308 | adjusted_mode->crtc_hsync_start + hsync_width; |
3fbe18d6 | 309 | adjusted_mode->crtc_vdisplay = mode->vdisplay; |
aa0261f2 | 310 | /* use the border instead of border minus one */ |
3fbe18d6 | 311 | adjusted_mode->crtc_vblank_start = mode->vdisplay + |
aa0261f2 ZY |
312 | bottom_border; |
313 | /* keep the vblank width constant */ | |
314 | adjusted_mode->crtc_vblank_end = | |
315 | adjusted_mode->crtc_vblank_start + vblank_width; | |
316 | /* get the vsync start postion relative to vblank start */ | |
317 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 318 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
319 | adjusted_mode->crtc_vblank_start + vsync_pos; |
320 | /* keep the vsync width constant */ | |
3fbe18d6 | 321 | adjusted_mode->crtc_vsync_end = |
a3e17eb8 | 322 | adjusted_mode->crtc_vsync_start + vsync_width; |
3fbe18d6 ZY |
323 | border = 1; |
324 | break; | |
325 | case DRM_MODE_SCALE_ASPECT: | |
326 | /* Scale but preserve the spect ratio */ | |
327 | pfit_control |= PFIT_ENABLE; | |
328 | if (IS_I965G(dev)) { | |
329 | /* 965+ is easy, it does everything in hw */ | |
330 | if (panel_ratio > desired_ratio) | |
331 | pfit_control |= PFIT_SCALING_PILLAR; | |
332 | else if (panel_ratio < desired_ratio) | |
333 | pfit_control |= PFIT_SCALING_LETTER; | |
334 | else | |
335 | pfit_control |= PFIT_SCALING_AUTO; | |
336 | } else { | |
337 | /* | |
338 | * For earlier chips we have to calculate the scaling | |
339 | * ratio by hand and program it into the | |
340 | * PFIT_PGM_RATIO register | |
341 | */ | |
342 | u32 horiz_bits, vert_bits, bits = 12; | |
343 | horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/ | |
344 | adjusted_mode->hdisplay; | |
345 | vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/ | |
346 | adjusted_mode->vdisplay; | |
347 | horiz_scale = adjusted_mode->hdisplay * | |
348 | PANEL_RATIO_FACTOR / mode->hdisplay; | |
349 | vert_scale = adjusted_mode->vdisplay * | |
350 | PANEL_RATIO_FACTOR / mode->vdisplay; | |
351 | ||
352 | /* retain aspect ratio */ | |
353 | if (panel_ratio > desired_ratio) { /* Pillar */ | |
354 | u32 scaled_width; | |
355 | scaled_width = mode->hdisplay * vert_scale / | |
356 | PANEL_RATIO_FACTOR; | |
357 | horiz_ratio = vert_ratio; | |
358 | pfit_control |= (VERT_AUTO_SCALE | | |
359 | VERT_INTERP_BILINEAR | | |
360 | HORIZ_INTERP_BILINEAR); | |
361 | /* Pillar will have left/right borders */ | |
362 | left_border = (adjusted_mode->hdisplay - | |
363 | scaled_width) / 2; | |
364 | right_border = left_border; | |
365 | if (mode->hdisplay & 1) /* odd resolutions */ | |
366 | right_border++; | |
aa0261f2 ZY |
367 | /* keep the border be even */ |
368 | if (right_border & 1) | |
369 | right_border++; | |
3fbe18d6 | 370 | adjusted_mode->crtc_hdisplay = scaled_width; |
aa0261f2 | 371 | /* use border instead of border minus one */ |
3fbe18d6 | 372 | adjusted_mode->crtc_hblank_start = |
aa0261f2 ZY |
373 | scaled_width + right_border; |
374 | /* keep the hblank width constant */ | |
3fbe18d6 | 375 | adjusted_mode->crtc_hblank_end = |
aa0261f2 ZY |
376 | adjusted_mode->crtc_hblank_start + |
377 | hblank_width; | |
378 | /* | |
379 | * get the hsync start pos relative to | |
380 | * hblank start | |
381 | */ | |
382 | hsync_pos = (hblank_width - hsync_width) / 2; | |
383 | /* keep the hsync_pos be even */ | |
384 | if (hsync_pos & 1) | |
385 | hsync_pos++; | |
3fbe18d6 | 386 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
387 | adjusted_mode->crtc_hblank_start + |
388 | hsync_pos; | |
389 | /* keept hsync width constant */ | |
3fbe18d6 | 390 | adjusted_mode->crtc_hsync_end = |
aa0261f2 ZY |
391 | adjusted_mode->crtc_hsync_start + |
392 | hsync_width; | |
3fbe18d6 ZY |
393 | border = 1; |
394 | } else if (panel_ratio < desired_ratio) { /* letter */ | |
395 | u32 scaled_height = mode->vdisplay * | |
396 | horiz_scale / PANEL_RATIO_FACTOR; | |
397 | vert_ratio = horiz_ratio; | |
398 | pfit_control |= (HORIZ_AUTO_SCALE | | |
399 | VERT_INTERP_BILINEAR | | |
400 | HORIZ_INTERP_BILINEAR); | |
401 | /* Letterbox will have top/bottom border */ | |
402 | top_border = (adjusted_mode->vdisplay - | |
403 | scaled_height) / 2; | |
404 | bottom_border = top_border; | |
405 | if (mode->vdisplay & 1) | |
406 | bottom_border++; | |
407 | adjusted_mode->crtc_vdisplay = scaled_height; | |
aa0261f2 | 408 | /* use border instead of border minus one */ |
3fbe18d6 | 409 | adjusted_mode->crtc_vblank_start = |
aa0261f2 ZY |
410 | scaled_height + bottom_border; |
411 | /* keep the vblank width constant */ | |
3fbe18d6 | 412 | adjusted_mode->crtc_vblank_end = |
aa0261f2 ZY |
413 | adjusted_mode->crtc_vblank_start + |
414 | vblank_width; | |
415 | /* | |
416 | * get the vsync start pos relative to | |
417 | * vblank start | |
418 | */ | |
419 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 420 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
421 | adjusted_mode->crtc_vblank_start + |
422 | vsync_pos; | |
423 | /* keep the vsync width constant */ | |
3fbe18d6 | 424 | adjusted_mode->crtc_vsync_end = |
aa0261f2 ZY |
425 | adjusted_mode->crtc_vsync_start + |
426 | vsync_width; | |
3fbe18d6 ZY |
427 | border = 1; |
428 | } else { | |
429 | /* Aspects match, Let hw scale both directions */ | |
430 | pfit_control |= (VERT_AUTO_SCALE | | |
431 | HORIZ_AUTO_SCALE | | |
432 | VERT_INTERP_BILINEAR | | |
433 | HORIZ_INTERP_BILINEAR); | |
434 | } | |
435 | horiz_bits = (1 << bits) * horiz_ratio / | |
436 | PANEL_RATIO_FACTOR; | |
437 | vert_bits = (1 << bits) * vert_ratio / | |
438 | PANEL_RATIO_FACTOR; | |
439 | pfit_pgm_ratios = | |
440 | ((vert_bits << PFIT_VERT_SCALE_SHIFT) & | |
441 | PFIT_VERT_SCALE_MASK) | | |
442 | ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) & | |
443 | PFIT_HORIZ_SCALE_MASK); | |
444 | } | |
445 | break; | |
446 | ||
447 | case DRM_MODE_SCALE_FULLSCREEN: | |
448 | /* | |
449 | * Full scaling, even if it changes the aspect ratio. | |
450 | * Fortunately this is all done for us in hw. | |
451 | */ | |
452 | pfit_control |= PFIT_ENABLE; | |
453 | if (IS_I965G(dev)) | |
454 | pfit_control |= PFIT_SCALING_AUTO; | |
455 | else | |
456 | pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
457 | VERT_INTERP_BILINEAR | | |
458 | HORIZ_INTERP_BILINEAR); | |
459 | break; | |
460 | default: | |
461 | break; | |
462 | } | |
463 | ||
464 | out: | |
465 | lvds_priv->pfit_control = pfit_control; | |
466 | lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; | |
a3e17eb8 ZY |
467 | /* |
468 | * When there exists the border, it means that the LVDS_BORDR | |
469 | * should be enabled. | |
470 | */ | |
471 | if (border) | |
472 | dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE; | |
473 | else | |
474 | dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE); | |
79e53945 JB |
475 | /* |
476 | * XXX: It would be nice to support lower refresh rates on the | |
477 | * panels to reduce power consumption, and perhaps match the | |
478 | * user's requested refresh rate. | |
479 | */ | |
480 | ||
481 | return true; | |
482 | } | |
483 | ||
484 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
485 | { | |
486 | struct drm_device *dev = encoder->dev; | |
487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 488 | u32 reg; |
79e53945 | 489 | |
c619eed4 | 490 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
491 | reg = BLC_PWM_CPU_CTL; |
492 | else | |
493 | reg = BLC_PWM_CTL; | |
79e53945 | 494 | |
541998a1 | 495 | dev_priv->saveBLC_PWM_CTL = I915_READ(reg); |
79e53945 JB |
496 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
497 | BACKLIGHT_DUTY_CYCLE_MASK); | |
498 | ||
499 | intel_lvds_set_power(dev, false); | |
500 | } | |
501 | ||
502 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
503 | { | |
504 | struct drm_device *dev = encoder->dev; | |
505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
506 | ||
507 | if (dev_priv->backlight_duty_cycle == 0) | |
508 | dev_priv->backlight_duty_cycle = | |
509 | intel_lvds_get_max_backlight(dev); | |
510 | ||
511 | intel_lvds_set_power(dev, true); | |
512 | } | |
513 | ||
514 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
515 | struct drm_display_mode *mode, | |
516 | struct drm_display_mode *adjusted_mode) | |
517 | { | |
518 | struct drm_device *dev = encoder->dev; | |
519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 EA |
520 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
521 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; | |
79e53945 JB |
522 | |
523 | /* | |
524 | * The LVDS pin pair will already have been turned on in the | |
525 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
526 | * settings. | |
527 | */ | |
528 | ||
c619eed4 | 529 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
530 | return; |
531 | ||
79e53945 JB |
532 | /* |
533 | * Enable automatic panel scaling so that non-native modes fill the | |
534 | * screen. Should be enabled before the pipe is enabled, according to | |
535 | * register description and PRM. | |
536 | */ | |
3fbe18d6 ZY |
537 | I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios); |
538 | I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); | |
79e53945 JB |
539 | } |
540 | ||
541 | /** | |
542 | * Detect the LVDS connection. | |
543 | * | |
b42d4c5c JB |
544 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
545 | * connected and closed means disconnected. We also send hotplug events as | |
546 | * needed, using lid status notification from the input layer. | |
79e53945 JB |
547 | */ |
548 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
549 | { | |
7b9c5abe | 550 | struct drm_device *dev = connector->dev; |
b42d4c5c JB |
551 | enum drm_connector_status status = connector_status_connected; |
552 | ||
7b9c5abe JB |
553 | /* ACPI lid methods were generally unreliable in this generation, so |
554 | * don't even bother. | |
555 | */ | |
6e6c8228 | 556 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
557 | return connector_status_connected; |
558 | ||
b42d4c5c | 559 | return status; |
79e53945 JB |
560 | } |
561 | ||
562 | /** | |
563 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
564 | */ | |
565 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
566 | { | |
567 | struct drm_device *dev = connector->dev; | |
21d40d37 | 568 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); |
79e53945 JB |
569 | struct drm_i915_private *dev_priv = dev->dev_private; |
570 | int ret = 0; | |
571 | ||
bfac4d67 | 572 | if (dev_priv->lvds_edid_good) { |
335af9a2 | 573 | ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
79e53945 | 574 | |
bfac4d67 ZY |
575 | if (ret) |
576 | return ret; | |
577 | } | |
79e53945 JB |
578 | |
579 | /* Didn't get an EDID, so | |
580 | * Set wide sync ranges so we get all modes | |
581 | * handed to valid_mode for checking | |
582 | */ | |
583 | connector->display_info.min_vfreq = 0; | |
584 | connector->display_info.max_vfreq = 200; | |
585 | connector->display_info.min_hfreq = 0; | |
586 | connector->display_info.max_hfreq = 200; | |
587 | ||
588 | if (dev_priv->panel_fixed_mode != NULL) { | |
589 | struct drm_display_mode *mode; | |
590 | ||
79e53945 JB |
591 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
592 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
593 | |
594 | return 1; | |
595 | } | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
c9354c85 LT |
600 | /* |
601 | * Lid events. Note the use of 'modeset_on_lid': | |
602 | * - we set it on lid close, and reset it on open | |
603 | * - we use it as a "only once" bit (ie we ignore | |
604 | * duplicate events where it was already properly | |
605 | * set/reset) | |
606 | * - the suspend/resume paths will also set it to | |
607 | * zero, since they restore the mode ("lid open"). | |
608 | */ | |
c1c7af60 JB |
609 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
610 | void *unused) | |
611 | { | |
612 | struct drm_i915_private *dev_priv = | |
613 | container_of(nb, struct drm_i915_private, lid_notifier); | |
614 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 615 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 616 | |
a2565377 ZY |
617 | /* |
618 | * check and update the status of LVDS connector after receiving | |
619 | * the LID nofication event. | |
620 | */ | |
621 | if (connector) | |
622 | connector->status = connector->funcs->detect(connector); | |
c9354c85 LT |
623 | if (!acpi_lid_open()) { |
624 | dev_priv->modeset_on_lid = 1; | |
625 | return NOTIFY_OK; | |
06891e27 | 626 | } |
c1c7af60 | 627 | |
c9354c85 LT |
628 | if (!dev_priv->modeset_on_lid) |
629 | return NOTIFY_OK; | |
630 | ||
631 | dev_priv->modeset_on_lid = 0; | |
632 | ||
633 | mutex_lock(&dev->mode_config.mutex); | |
634 | drm_helper_resume_force_mode(dev); | |
635 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 636 | |
c1c7af60 JB |
637 | return NOTIFY_OK; |
638 | } | |
639 | ||
79e53945 JB |
640 | /** |
641 | * intel_lvds_destroy - unregister and free LVDS structures | |
642 | * @connector: connector to free | |
643 | * | |
644 | * Unregister the DDC bus for this connector then free the driver private | |
645 | * structure. | |
646 | */ | |
647 | static void intel_lvds_destroy(struct drm_connector *connector) | |
648 | { | |
c1c7af60 | 649 | struct drm_device *dev = connector->dev; |
21d40d37 | 650 | struct intel_encoder *intel_encoder = to_intel_encoder(connector); |
c1c7af60 | 651 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 652 | |
21d40d37 EA |
653 | if (intel_encoder->ddc_bus) |
654 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
c1c7af60 JB |
655 | if (dev_priv->lid_notifier.notifier_call) |
656 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
657 | drm_sysfs_connector_remove(connector); |
658 | drm_connector_cleanup(connector); | |
659 | kfree(connector); | |
660 | } | |
661 | ||
335041ed JB |
662 | static int intel_lvds_set_property(struct drm_connector *connector, |
663 | struct drm_property *property, | |
664 | uint64_t value) | |
665 | { | |
3fbe18d6 | 666 | struct drm_device *dev = connector->dev; |
21d40d37 EA |
667 | struct intel_encoder *intel_encoder = |
668 | to_intel_encoder(connector); | |
3fbe18d6 ZY |
669 | |
670 | if (property == dev->mode_config.scaling_mode_property && | |
671 | connector->encoder) { | |
672 | struct drm_crtc *crtc = connector->encoder->crtc; | |
21d40d37 | 673 | struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv; |
53bd8389 JB |
674 | if (value == DRM_MODE_SCALE_NONE) { |
675 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3fbe18d6 ZY |
676 | return 0; |
677 | } | |
678 | if (lvds_priv->fitting_mode == value) { | |
679 | /* the LVDS scaling property is not changed */ | |
680 | return 0; | |
681 | } | |
682 | lvds_priv->fitting_mode = value; | |
683 | if (crtc && crtc->enabled) { | |
684 | /* | |
685 | * If the CRTC is enabled, the display will be changed | |
686 | * according to the new panel fitting mode. | |
687 | */ | |
688 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
689 | crtc->x, crtc->y, crtc->fb); | |
690 | } | |
691 | } | |
692 | ||
335041ed JB |
693 | return 0; |
694 | } | |
695 | ||
79e53945 JB |
696 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
697 | .dpms = intel_lvds_dpms, | |
698 | .mode_fixup = intel_lvds_mode_fixup, | |
699 | .prepare = intel_lvds_prepare, | |
700 | .mode_set = intel_lvds_mode_set, | |
701 | .commit = intel_lvds_commit, | |
702 | }; | |
703 | ||
704 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
705 | .get_modes = intel_lvds_get_modes, | |
706 | .mode_valid = intel_lvds_mode_valid, | |
707 | .best_encoder = intel_best_encoder, | |
708 | }; | |
709 | ||
710 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 711 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
712 | .detect = intel_lvds_detect, |
713 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 714 | .set_property = intel_lvds_set_property, |
79e53945 JB |
715 | .destroy = intel_lvds_destroy, |
716 | }; | |
717 | ||
718 | ||
719 | static void intel_lvds_enc_destroy(struct drm_encoder *encoder) | |
720 | { | |
721 | drm_encoder_cleanup(encoder); | |
722 | } | |
723 | ||
724 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
725 | .destroy = intel_lvds_enc_destroy, | |
726 | }; | |
727 | ||
425d244c JW |
728 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
729 | { | |
8a4c47f3 | 730 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
731 | return 1; |
732 | } | |
79e53945 | 733 | |
425d244c | 734 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 735 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
736 | { |
737 | .callback = intel_no_lvds_dmi_callback, | |
738 | .ident = "Apple Mac Mini (Core series)", | |
739 | .matches = { | |
98acd46f | 740 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
741 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
742 | }, | |
743 | }, | |
744 | { | |
745 | .callback = intel_no_lvds_dmi_callback, | |
746 | .ident = "Apple Mac Mini (Core 2 series)", | |
747 | .matches = { | |
98acd46f | 748 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
749 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
750 | }, | |
751 | }, | |
752 | { | |
753 | .callback = intel_no_lvds_dmi_callback, | |
754 | .ident = "MSI IM-945GSE-A", | |
755 | .matches = { | |
756 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
757 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
758 | }, | |
759 | }, | |
760 | { | |
761 | .callback = intel_no_lvds_dmi_callback, | |
762 | .ident = "Dell Studio Hybrid", | |
763 | .matches = { | |
764 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
765 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
766 | }, | |
767 | }, | |
70aa96ca JW |
768 | { |
769 | .callback = intel_no_lvds_dmi_callback, | |
770 | .ident = "AOpen Mini PC", | |
771 | .matches = { | |
772 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
773 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
774 | }, | |
775 | }, | |
ed8c754b TV |
776 | { |
777 | .callback = intel_no_lvds_dmi_callback, | |
778 | .ident = "AOpen Mini PC MP915", | |
779 | .matches = { | |
780 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
781 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
782 | }, | |
783 | }, | |
fa0864b2 MC |
784 | { |
785 | .callback = intel_no_lvds_dmi_callback, | |
786 | .ident = "Aopen i945GTt-VFA", | |
787 | .matches = { | |
788 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
789 | }, | |
790 | }, | |
9875557e SB |
791 | { |
792 | .callback = intel_no_lvds_dmi_callback, | |
793 | .ident = "Clientron U800", | |
794 | .matches = { | |
795 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
796 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
797 | }, | |
798 | }, | |
425d244c JW |
799 | |
800 | { } /* terminating entry */ | |
801 | }; | |
79e53945 | 802 | |
18f9ed12 ZY |
803 | /** |
804 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
805 | * @dev: drm device | |
806 | * @connector: LVDS connector | |
807 | * | |
808 | * Find the reduced downclock for LVDS in EDID. | |
809 | */ | |
810 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
811 | struct drm_connector *connector) | |
812 | { | |
813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
814 | struct drm_display_mode *scan, *panel_fixed_mode; | |
815 | int temp_downclock; | |
816 | ||
817 | panel_fixed_mode = dev_priv->panel_fixed_mode; | |
818 | temp_downclock = panel_fixed_mode->clock; | |
819 | ||
820 | mutex_lock(&dev->mode_config.mutex); | |
821 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
822 | /* | |
823 | * If one mode has the same resolution with the fixed_panel | |
824 | * mode while they have the different refresh rate, it means | |
825 | * that the reduced downclock is found for the LVDS. In such | |
826 | * case we can set the different FPx0/1 to dynamically select | |
827 | * between low and high frequency. | |
828 | */ | |
829 | if (scan->hdisplay == panel_fixed_mode->hdisplay && | |
830 | scan->hsync_start == panel_fixed_mode->hsync_start && | |
831 | scan->hsync_end == panel_fixed_mode->hsync_end && | |
832 | scan->htotal == panel_fixed_mode->htotal && | |
833 | scan->vdisplay == panel_fixed_mode->vdisplay && | |
834 | scan->vsync_start == panel_fixed_mode->vsync_start && | |
835 | scan->vsync_end == panel_fixed_mode->vsync_end && | |
836 | scan->vtotal == panel_fixed_mode->vtotal) { | |
837 | if (scan->clock < temp_downclock) { | |
838 | /* | |
839 | * The downclock is already found. But we | |
840 | * expect to find the lower downclock. | |
841 | */ | |
842 | temp_downclock = scan->clock; | |
843 | } | |
844 | } | |
845 | } | |
846 | mutex_unlock(&dev->mode_config.mutex); | |
33814341 JB |
847 | if (temp_downclock < panel_fixed_mode->clock && |
848 | i915_lvds_downclock) { | |
18f9ed12 ZY |
849 | /* We found the downclock for LVDS. */ |
850 | dev_priv->lvds_downclock_avail = 1; | |
851 | dev_priv->lvds_downclock = temp_downclock; | |
852 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
853 | "Normal clock %dKhz, downclock %dKhz\n", | |
854 | panel_fixed_mode->clock, temp_downclock); | |
855 | } | |
856 | return; | |
857 | } | |
858 | ||
7cf4f69d ZY |
859 | /* |
860 | * Enumerate the child dev array parsed from VBT to check whether | |
861 | * the LVDS is present. | |
862 | * If it is present, return 1. | |
863 | * If it is not present, return false. | |
864 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
865 | * Note: The addin_offset should also be checked for LVDS panel. | |
866 | * Only when it is non-zero, it is assumed that it is present. | |
867 | */ | |
6e36595a | 868 | static int lvds_is_present_in_vbt(struct drm_device *dev) |
7cf4f69d ZY |
869 | { |
870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
871 | struct child_device_config *p_child; | |
872 | int i, ret; | |
873 | ||
874 | if (!dev_priv->child_dev_num) | |
875 | return 1; | |
876 | ||
877 | ret = 0; | |
878 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
879 | p_child = dev_priv->child_dev + i; | |
880 | /* | |
881 | * If the device type is not LFP, continue. | |
882 | * If the device type is 0x22, it is also regarded as LFP. | |
883 | */ | |
884 | if (p_child->device_type != DEVICE_TYPE_INT_LFP && | |
885 | p_child->device_type != DEVICE_TYPE_LFP) | |
886 | continue; | |
887 | ||
888 | /* The addin_offset should be checked. Only when it is | |
889 | * non-zero, it is regarded as present. | |
890 | */ | |
891 | if (p_child->addin_offset) { | |
892 | ret = 1; | |
893 | break; | |
894 | } | |
895 | } | |
896 | return ret; | |
897 | } | |
898 | ||
79e53945 JB |
899 | /** |
900 | * intel_lvds_init - setup LVDS connectors on this device | |
901 | * @dev: drm device | |
902 | * | |
903 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
904 | * modes we can display on the LVDS panel (if present). | |
905 | */ | |
906 | void intel_lvds_init(struct drm_device *dev) | |
907 | { | |
908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 | 909 | struct intel_encoder *intel_encoder; |
79e53945 JB |
910 | struct drm_connector *connector; |
911 | struct drm_encoder *encoder; | |
912 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
913 | struct drm_crtc *crtc; | |
3fbe18d6 | 914 | struct intel_lvds_priv *lvds_priv; |
79e53945 | 915 | u32 lvds; |
541998a1 | 916 | int pipe, gpio = GPIOC; |
79e53945 | 917 | |
425d244c JW |
918 | /* Skip init on machines we know falsely report LVDS */ |
919 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 920 | return; |
565dcd46 | 921 | |
11ba1592 MG |
922 | if (!lvds_is_present_in_vbt(dev)) { |
923 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); | |
e99da35f | 924 | return; |
38b3037e | 925 | } |
e99da35f | 926 | |
c619eed4 | 927 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
928 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
929 | return; | |
32f9d658 | 930 | if (dev_priv->edp_support) { |
28c97730 | 931 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
32f9d658 ZW |
932 | return; |
933 | } | |
541998a1 ZW |
934 | gpio = PCH_GPIOC; |
935 | } | |
936 | ||
21d40d37 | 937 | intel_encoder = kzalloc(sizeof(struct intel_encoder) + |
3fbe18d6 | 938 | sizeof(struct intel_lvds_priv), GFP_KERNEL); |
21d40d37 | 939 | if (!intel_encoder) { |
79e53945 JB |
940 | return; |
941 | } | |
942 | ||
21d40d37 EA |
943 | connector = &intel_encoder->base; |
944 | encoder = &intel_encoder->enc; | |
945 | drm_connector_init(dev, &intel_encoder->base, &intel_lvds_connector_funcs, | |
79e53945 JB |
946 | DRM_MODE_CONNECTOR_LVDS); |
947 | ||
21d40d37 | 948 | drm_encoder_init(dev, &intel_encoder->enc, &intel_lvds_enc_funcs, |
79e53945 JB |
949 | DRM_MODE_ENCODER_LVDS); |
950 | ||
21d40d37 EA |
951 | drm_mode_connector_attach_encoder(&intel_encoder->base, &intel_encoder->enc); |
952 | intel_encoder->type = INTEL_OUTPUT_LVDS; | |
79e53945 | 953 | |
21d40d37 EA |
954 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
955 | intel_encoder->crtc_mask = (1 << 1); | |
79e53945 JB |
956 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
957 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
958 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
959 | connector->interlace_allowed = false; | |
960 | connector->doublescan_allowed = false; | |
961 | ||
21d40d37 EA |
962 | lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1); |
963 | intel_encoder->dev_priv = lvds_priv; | |
3fbe18d6 ZY |
964 | /* create the scaling mode property */ |
965 | drm_mode_create_scaling_mode_property(dev); | |
966 | /* | |
967 | * the initial panel fitting mode will be FULL_SCREEN. | |
968 | */ | |
79e53945 | 969 | |
21d40d37 | 970 | drm_connector_attach_property(&intel_encoder->base, |
3fbe18d6 ZY |
971 | dev->mode_config.scaling_mode_property, |
972 | DRM_MODE_SCALE_FULLSCREEN); | |
973 | lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN; | |
79e53945 JB |
974 | /* |
975 | * LVDS discovery: | |
976 | * 1) check for EDID on DDC | |
977 | * 2) check for VBT data | |
978 | * 3) check to see if LVDS is already on | |
979 | * if none of the above, no panel | |
980 | * 4) make sure lid is open | |
981 | * if closed, act like it's not there for now | |
982 | */ | |
983 | ||
984 | /* Set up the DDC bus. */ | |
21d40d37 EA |
985 | intel_encoder->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
986 | if (!intel_encoder->ddc_bus) { | |
79e53945 JB |
987 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
988 | "failed.\n"); | |
989 | goto failed; | |
990 | } | |
991 | ||
992 | /* | |
993 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
994 | * preferred mode is the right one. | |
995 | */ | |
bfac4d67 ZY |
996 | dev_priv->lvds_edid_good = true; |
997 | ||
335af9a2 | 998 | if (!intel_ddc_get_modes(connector, intel_encoder->ddc_bus)) |
bfac4d67 | 999 | dev_priv->lvds_edid_good = false; |
79e53945 JB |
1000 | |
1001 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1002 | mutex_lock(&dev->mode_config.mutex); | |
1003 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
1004 | dev_priv->panel_fixed_mode = | |
1005 | drm_mode_duplicate(dev, scan); | |
1006 | mutex_unlock(&dev->mode_config.mutex); | |
18f9ed12 | 1007 | intel_find_lvds_downclock(dev, connector); |
565dcd46 | 1008 | goto out; |
79e53945 JB |
1009 | } |
1010 | mutex_unlock(&dev->mode_config.mutex); | |
1011 | } | |
1012 | ||
1013 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1014 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
1015 | mutex_lock(&dev->mode_config.mutex); |
1016 | dev_priv->panel_fixed_mode = | |
88631706 | 1017 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 1018 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
1019 | if (dev_priv->panel_fixed_mode) { |
1020 | dev_priv->panel_fixed_mode->type |= | |
1021 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1022 | goto out; |
1023 | } | |
79e53945 JB |
1024 | } |
1025 | ||
1026 | /* | |
1027 | * If we didn't get EDID, try checking if the panel is already turned | |
1028 | * on. If so, assume that whatever is currently programmed is the | |
1029 | * correct mode. | |
1030 | */ | |
541998a1 | 1031 | |
f2b115e6 | 1032 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1033 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1034 | goto failed; |
1035 | ||
79e53945 JB |
1036 | lvds = I915_READ(LVDS); |
1037 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1038 | crtc = intel_get_crtc_from_pipe(dev, pipe); | |
1039 | ||
1040 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
1041 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
1042 | if (dev_priv->panel_fixed_mode) { | |
1043 | dev_priv->panel_fixed_mode->type |= | |
1044 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 1045 | goto out; |
79e53945 JB |
1046 | } |
1047 | } | |
1048 | ||
1049 | /* If we still don't have a mode after all that, give up. */ | |
1050 | if (!dev_priv->panel_fixed_mode) | |
1051 | goto failed; | |
1052 | ||
79e53945 | 1053 | out: |
c619eed4 | 1054 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
1055 | u32 pwm; |
1056 | /* make sure PWM is enabled */ | |
1057 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
1058 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
1059 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
1060 | ||
1061 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1062 | pwm |= PWM_PCH_ENABLE; | |
1063 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
1064 | } | |
c1c7af60 JB |
1065 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1066 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1067 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1068 | dev_priv->lid_notifier.notifier_call = NULL; |
1069 | } | |
a2565377 ZY |
1070 | /* keep the LVDS connector */ |
1071 | dev_priv->int_lvds_connector = connector; | |
79e53945 JB |
1072 | drm_sysfs_connector_add(connector); |
1073 | return; | |
1074 | ||
1075 | failed: | |
8a4c47f3 | 1076 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
21d40d37 EA |
1077 | if (intel_encoder->ddc_bus) |
1078 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
79e53945 | 1079 | drm_connector_cleanup(connector); |
1991bdfa | 1080 | drm_encoder_cleanup(encoder); |
21d40d37 | 1081 | kfree(intel_encoder); |
79e53945 | 1082 | } |