drm/i915: simplify possible_clones computation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
79e53945
JB
34#include "drmP.h"
35#include "drm.h"
36#include "drm_crtc.h"
37#include "drm_edid.h"
38#include "intel_drv.h"
39#include "i915_drm.h"
40#include "i915_drv.h"
e99da35f 41#include <linux/acpi.h>
79e53945 42
3fbe18d6 43/* Private structure for the integrated LVDS support */
ea5b213a
CW
44struct intel_lvds {
45 struct intel_encoder base;
788319d4 46
219adae1 47 struct edid *edid;
788319d4 48
3fbe18d6
ZY
49 int fitting_mode;
50 u32 pfit_control;
51 u32 pfit_pgm_ratios;
e9e331a8 52 bool pfit_dirty;
788319d4
CW
53
54 struct drm_display_mode *fixed_mode;
3fbe18d6
ZY
55};
56
788319d4 57static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder)
ea5b213a 58{
4ef69c7a 59 return container_of(encoder, struct intel_lvds, base.base);
ea5b213a
CW
60}
61
788319d4
CW
62static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
63{
64 return container_of(intel_attached_encoder(connector),
65 struct intel_lvds, base);
66}
67
79e53945
JB
68/**
69 * Sets the power state for the panel.
70 */
2a1292fd 71static void intel_lvds_enable(struct intel_lvds *intel_lvds)
79e53945 72{
e9e331a8 73 struct drm_device *dev = intel_lvds->base.base.dev;
24ded204 74 struct intel_crtc *intel_crtc = to_intel_crtc(intel_lvds->base.base.crtc);
79e53945 75 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 76 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 77
c619eed4 78 if (HAS_PCH_SPLIT(dev)) {
541998a1 79 ctl_reg = PCH_PP_CONTROL;
469d1296 80 lvds_reg = PCH_LVDS;
de842eff 81 stat_reg = PCH_PP_STATUS;
541998a1
ZW
82 } else {
83 ctl_reg = PP_CONTROL;
469d1296 84 lvds_reg = LVDS;
de842eff 85 stat_reg = PP_STATUS;
541998a1 86 }
79e53945 87
2a1292fd 88 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 89
2a1292fd
CW
90 if (intel_lvds->pfit_dirty) {
91 /*
92 * Enable automatic panel scaling so that non-native modes
93 * fill the screen. The panel fitter should only be
94 * adjusted whilst the pipe is disabled, according to
95 * register description and PRM.
96 */
97 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
98 intel_lvds->pfit_control,
99 intel_lvds->pfit_pgm_ratios);
de842eff
KP
100
101 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
102 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
103 intel_lvds->pfit_dirty = false;
2a1292fd
CW
104 }
105
106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
107 POSTING_READ(lvds_reg);
de842eff
KP
108 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
109 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 110
24ded204 111 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
112}
113
114static void intel_lvds_disable(struct intel_lvds *intel_lvds)
115{
116 struct drm_device *dev = intel_lvds->base.base.dev;
117 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 118 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
119
120 if (HAS_PCH_SPLIT(dev)) {
121 ctl_reg = PCH_PP_CONTROL;
122 lvds_reg = PCH_LVDS;
de842eff 123 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
124 } else {
125 ctl_reg = PP_CONTROL;
126 lvds_reg = LVDS;
de842eff 127 stat_reg = PP_STATUS;
2a1292fd
CW
128 }
129
47356eb6 130 intel_panel_disable_backlight(dev);
2a1292fd
CW
131
132 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
133 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
134 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd
CW
135
136 if (intel_lvds->pfit_control) {
2a1292fd
CW
137 I915_WRITE(PFIT_CONTROL, 0);
138 intel_lvds->pfit_dirty = true;
79e53945 139 }
2a1292fd
CW
140
141 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 142 POSTING_READ(lvds_reg);
79e53945
JB
143}
144
145static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
146{
788319d4 147 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
79e53945
JB
148
149 if (mode == DRM_MODE_DPMS_ON)
2a1292fd 150 intel_lvds_enable(intel_lvds);
79e53945 151 else
2a1292fd 152 intel_lvds_disable(intel_lvds);
79e53945
JB
153
154 /* XXX: We never power down the LVDS pairs. */
155}
156
79e53945
JB
157static int intel_lvds_mode_valid(struct drm_connector *connector,
158 struct drm_display_mode *mode)
159{
788319d4
CW
160 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
161 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode;
79e53945 162
788319d4
CW
163 if (mode->hdisplay > fixed_mode->hdisplay)
164 return MODE_PANEL;
165 if (mode->vdisplay > fixed_mode->vdisplay)
166 return MODE_PANEL;
79e53945
JB
167
168 return MODE_OK;
169}
170
49be663f
CW
171static void
172centre_horizontally(struct drm_display_mode *mode,
173 int width)
174{
175 u32 border, sync_pos, blank_width, sync_width;
176
177 /* keep the hsync and hblank widths constant */
178 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
179 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
180 sync_pos = (blank_width - sync_width + 1) / 2;
181
182 border = (mode->hdisplay - width + 1) / 2;
183 border += border & 1; /* make the border even */
184
185 mode->crtc_hdisplay = width;
186 mode->crtc_hblank_start = width + border;
187 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
188
189 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
190 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
191
192 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
193}
194
195static void
196centre_vertically(struct drm_display_mode *mode,
197 int height)
198{
199 u32 border, sync_pos, blank_width, sync_width;
200
201 /* keep the vsync and vblank widths constant */
202 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
203 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
204 sync_pos = (blank_width - sync_width + 1) / 2;
205
206 border = (mode->vdisplay - height + 1) / 2;
207
208 mode->crtc_vdisplay = height;
209 mode->crtc_vblank_start = height + border;
210 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
211
212 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
213 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
214
215 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
216}
217
218static inline u32 panel_fitter_scaling(u32 source, u32 target)
219{
220 /*
221 * Floating point operation is not supported. So the FACTOR
222 * is defined, which can avoid the floating point computation
223 * when calculating the panel ratio.
224 */
225#define ACCURACY 12
226#define FACTOR (1 << ACCURACY)
227 u32 ratio = source * FACTOR / target;
228 return (FACTOR * ratio + FACTOR/2) / FACTOR;
229}
230
79e53945 231static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 232 const struct drm_display_mode *mode,
79e53945
JB
233 struct drm_display_mode *adjusted_mode)
234{
235 struct drm_device *dev = encoder->dev;
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
788319d4 238 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
6c2b7c12 239 struct intel_encoder *tmp_encoder;
49be663f 240 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 241 int pipe;
79e53945
JB
242
243 /* Should never happen!! */
a6c45cf0 244 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 245 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
246 return false;
247 }
248
249 /* Should never happen!! */
6c2b7c12
DV
250 for_each_encoder_on_crtc(dev, encoder->crtc, tmp_encoder) {
251 if (&tmp_encoder->base != encoder) {
1ae8c0a5 252 DRM_ERROR("Can't enable LVDS and another "
79e53945
JB
253 "encoder on the same pipe\n");
254 return false;
255 }
256 }
1d8e1c75 257
79e53945 258 /*
71677043 259 * We have timings from the BIOS for the panel, put them in
79e53945
JB
260 * to the adjusted mode. The CRTC will be set up for this mode,
261 * with the panel scaling set up to source from the H/VDisplay
262 * of the original mode.
263 */
788319d4 264 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
1d8e1c75
CW
265
266 if (HAS_PCH_SPLIT(dev)) {
267 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
268 mode, adjusted_mode);
269 return true;
270 }
79e53945 271
3fbe18d6
ZY
272 /* Native modes don't need fitting */
273 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 274 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 275 goto out;
3fbe18d6
ZY
276
277 /* 965+ wants fuzzy fitting */
a6c45cf0 278 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
279 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
280 PFIT_FILTER_FUZZY);
281
3fbe18d6
ZY
282 /*
283 * Enable automatic panel scaling for non-native modes so that they fill
284 * the screen. Should be enabled before the pipe is enabled, according
285 * to register description and PRM.
286 * Change the value here to see the borders for debugging
287 */
9db4a9c7
JB
288 for_each_pipe(pipe)
289 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 290
f9bef081
DV
291 drm_mode_set_crtcinfo(adjusted_mode, 0);
292
ea5b213a 293 switch (intel_lvds->fitting_mode) {
53bd8389 294 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
295 /*
296 * For centered modes, we have to calculate border widths &
297 * heights and modify the values programmed into the CRTC.
298 */
49be663f
CW
299 centre_horizontally(adjusted_mode, mode->hdisplay);
300 centre_vertically(adjusted_mode, mode->vdisplay);
301 border = LVDS_BORDER_ENABLE;
3fbe18d6 302 break;
49be663f 303
3fbe18d6 304 case DRM_MODE_SCALE_ASPECT:
49be663f 305 /* Scale but preserve the aspect ratio */
a6c45cf0 306 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
307 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
308 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
309
3fbe18d6 310 /* 965+ is easy, it does everything in hw */
49be663f 311 if (scaled_width > scaled_height)
257e48f1 312 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 313 else if (scaled_width < scaled_height)
257e48f1
CW
314 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
315 else if (adjusted_mode->hdisplay != mode->hdisplay)
316 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 317 } else {
49be663f
CW
318 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
319 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
320 /*
321 * For earlier chips we have to calculate the scaling
322 * ratio by hand and program it into the
323 * PFIT_PGM_RATIO register
324 */
49be663f
CW
325 if (scaled_width > scaled_height) { /* pillar */
326 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
327
328 border = LVDS_BORDER_ENABLE;
329 if (mode->vdisplay != adjusted_mode->vdisplay) {
330 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
331 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
332 bits << PFIT_VERT_SCALE_SHIFT);
333 pfit_control |= (PFIT_ENABLE |
334 VERT_INTERP_BILINEAR |
335 HORIZ_INTERP_BILINEAR);
336 }
337 } else if (scaled_width < scaled_height) { /* letter */
338 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
339
340 border = LVDS_BORDER_ENABLE;
341 if (mode->hdisplay != adjusted_mode->hdisplay) {
342 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
343 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
344 bits << PFIT_VERT_SCALE_SHIFT);
345 pfit_control |= (PFIT_ENABLE |
346 VERT_INTERP_BILINEAR |
347 HORIZ_INTERP_BILINEAR);
348 }
349 } else
350 /* Aspects match, Let hw scale both directions */
351 pfit_control |= (PFIT_ENABLE |
352 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
353 VERT_INTERP_BILINEAR |
354 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
355 }
356 break;
357
358 case DRM_MODE_SCALE_FULLSCREEN:
359 /*
360 * Full scaling, even if it changes the aspect ratio.
361 * Fortunately this is all done for us in hw.
362 */
257e48f1
CW
363 if (mode->vdisplay != adjusted_mode->vdisplay ||
364 mode->hdisplay != adjusted_mode->hdisplay) {
365 pfit_control |= PFIT_ENABLE;
366 if (INTEL_INFO(dev)->gen >= 4)
367 pfit_control |= PFIT_SCALING_AUTO;
368 else
369 pfit_control |= (VERT_AUTO_SCALE |
370 VERT_INTERP_BILINEAR |
371 HORIZ_AUTO_SCALE |
372 HORIZ_INTERP_BILINEAR);
373 }
3fbe18d6 374 break;
49be663f 375
3fbe18d6
ZY
376 default:
377 break;
378 }
379
380out:
72389a33 381 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
382 if ((pfit_control & PFIT_ENABLE) == 0) {
383 pfit_control = 0;
384 pfit_pgm_ratios = 0;
385 }
72389a33
CW
386
387 /* Make sure pre-965 set dither correctly */
388 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
389 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
390
e9e331a8
CW
391 if (pfit_control != intel_lvds->pfit_control ||
392 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) {
393 intel_lvds->pfit_control = pfit_control;
394 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
395 intel_lvds->pfit_dirty = true;
396 }
49be663f
CW
397 dev_priv->lvds_border_bits = border;
398
79e53945
JB
399 /*
400 * XXX: It would be nice to support lower refresh rates on the
401 * panels to reduce power consumption, and perhaps match the
402 * user's requested refresh rate.
403 */
404
405 return true;
406}
407
408static void intel_lvds_prepare(struct drm_encoder *encoder)
409{
788319d4 410 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
79e53945 411
520c41cf 412 intel_lvds_disable(intel_lvds);
79e53945
JB
413}
414
e9e331a8 415static void intel_lvds_commit(struct drm_encoder *encoder)
79e53945 416{
788319d4 417 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
79e53945 418
e9e331a8
CW
419 /* Always do a full power on as we do not know what state
420 * we were left in.
421 */
2a1292fd 422 intel_lvds_enable(intel_lvds);
79e53945
JB
423}
424
425static void intel_lvds_mode_set(struct drm_encoder *encoder,
426 struct drm_display_mode *mode,
427 struct drm_display_mode *adjusted_mode)
428{
79e53945
JB
429 /*
430 * The LVDS pin pair will already have been turned on in the
431 * intel_crtc_mode_set since it has a large impact on the DPLL
432 * settings.
433 */
79e53945
JB
434}
435
436/**
437 * Detect the LVDS connection.
438 *
b42d4c5c
JB
439 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
440 * connected and closed means disconnected. We also send hotplug events as
441 * needed, using lid status notification from the input layer.
79e53945 442 */
7b334fcb 443static enum drm_connector_status
930a9e28 444intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 445{
7b9c5abe 446 struct drm_device *dev = connector->dev;
6ee3b5a1 447 enum drm_connector_status status;
b42d4c5c 448
fe16d949
CW
449 status = intel_panel_detect(dev);
450 if (status != connector_status_unknown)
451 return status;
01fe9dbd 452
6ee3b5a1 453 return connector_status_connected;
79e53945
JB
454}
455
456/**
457 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
458 */
459static int intel_lvds_get_modes(struct drm_connector *connector)
460{
788319d4 461 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
79e53945 462 struct drm_device *dev = connector->dev;
788319d4 463 struct drm_display_mode *mode;
79e53945 464
3f8ff0e7 465 if (intel_lvds->edid)
219adae1 466 return drm_add_edid_modes(connector, intel_lvds->edid);
79e53945 467
788319d4 468 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
311bd68e 469 if (mode == NULL)
788319d4 470 return 0;
79e53945 471
788319d4
CW
472 drm_mode_probed_add(connector, mode);
473 return 1;
79e53945
JB
474}
475
0544edfd
TB
476static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
477{
bc0daf48 478 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
479 return 1;
480}
481
482/* The GPU hangs up on these systems if modeset is performed on LID open */
483static const struct dmi_system_id intel_no_modeset_on_lid[] = {
484 {
485 .callback = intel_no_modeset_on_lid_dmi_callback,
486 .ident = "Toshiba Tecra A11",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
489 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
490 },
491 },
492
493 { } /* terminating entry */
494};
495
c9354c85
LT
496/*
497 * Lid events. Note the use of 'modeset_on_lid':
498 * - we set it on lid close, and reset it on open
499 * - we use it as a "only once" bit (ie we ignore
500 * duplicate events where it was already properly
501 * set/reset)
502 * - the suspend/resume paths will also set it to
503 * zero, since they restore the mode ("lid open").
504 */
c1c7af60
JB
505static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
506 void *unused)
507{
508 struct drm_i915_private *dev_priv =
509 container_of(nb, struct drm_i915_private, lid_notifier);
510 struct drm_device *dev = dev_priv->dev;
a2565377 511 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 512
2fb4e61d
AW
513 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
514 return NOTIFY_OK;
515
a2565377
ZY
516 /*
517 * check and update the status of LVDS connector after receiving
518 * the LID nofication event.
519 */
520 if (connector)
7b334fcb 521 connector->status = connector->funcs->detect(connector,
930a9e28 522 false);
7b334fcb 523
0544edfd
TB
524 /* Don't force modeset on machines where it causes a GPU lockup */
525 if (dmi_check_system(intel_no_modeset_on_lid))
526 return NOTIFY_OK;
c9354c85
LT
527 if (!acpi_lid_open()) {
528 dev_priv->modeset_on_lid = 1;
529 return NOTIFY_OK;
06891e27 530 }
c1c7af60 531
c9354c85
LT
532 if (!dev_priv->modeset_on_lid)
533 return NOTIFY_OK;
534
535 dev_priv->modeset_on_lid = 0;
536
537 mutex_lock(&dev->mode_config.mutex);
538 drm_helper_resume_force_mode(dev);
539 mutex_unlock(&dev->mode_config.mutex);
06324194 540
c1c7af60
JB
541 return NOTIFY_OK;
542}
543
79e53945
JB
544/**
545 * intel_lvds_destroy - unregister and free LVDS structures
546 * @connector: connector to free
547 *
548 * Unregister the DDC bus for this connector then free the driver private
549 * structure.
550 */
551static void intel_lvds_destroy(struct drm_connector *connector)
552{
c1c7af60 553 struct drm_device *dev = connector->dev;
c1c7af60 554 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 555
aaa6fd2a
MG
556 intel_panel_destroy_backlight(dev);
557
c1c7af60
JB
558 if (dev_priv->lid_notifier.notifier_call)
559 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
560 drm_sysfs_connector_remove(connector);
561 drm_connector_cleanup(connector);
562 kfree(connector);
563}
564
335041ed
JB
565static int intel_lvds_set_property(struct drm_connector *connector,
566 struct drm_property *property,
567 uint64_t value)
568{
788319d4 569 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
3fbe18d6 570 struct drm_device *dev = connector->dev;
3fbe18d6 571
788319d4
CW
572 if (property == dev->mode_config.scaling_mode_property) {
573 struct drm_crtc *crtc = intel_lvds->base.base.crtc;
bb8a3560 574
53bd8389
JB
575 if (value == DRM_MODE_SCALE_NONE) {
576 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 577 return -EINVAL;
3fbe18d6 578 }
788319d4 579
ea5b213a 580 if (intel_lvds->fitting_mode == value) {
3fbe18d6
ZY
581 /* the LVDS scaling property is not changed */
582 return 0;
583 }
ea5b213a 584 intel_lvds->fitting_mode = value;
3fbe18d6
ZY
585 if (crtc && crtc->enabled) {
586 /*
587 * If the CRTC is enabled, the display will be changed
588 * according to the new panel fitting mode.
589 */
590 drm_crtc_helper_set_mode(crtc, &crtc->mode,
591 crtc->x, crtc->y, crtc->fb);
592 }
593 }
594
335041ed
JB
595 return 0;
596}
597
79e53945
JB
598static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
599 .dpms = intel_lvds_dpms,
600 .mode_fixup = intel_lvds_mode_fixup,
601 .prepare = intel_lvds_prepare,
602 .mode_set = intel_lvds_mode_set,
603 .commit = intel_lvds_commit,
604};
605
606static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
607 .get_modes = intel_lvds_get_modes,
608 .mode_valid = intel_lvds_mode_valid,
df0e9248 609 .best_encoder = intel_best_encoder,
79e53945
JB
610};
611
612static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c9fb15f6 613 .dpms = drm_helper_connector_dpms,
79e53945
JB
614 .detect = intel_lvds_detect,
615 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 616 .set_property = intel_lvds_set_property,
79e53945
JB
617 .destroy = intel_lvds_destroy,
618};
619
79e53945 620static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 621 .destroy = intel_encoder_destroy,
79e53945
JB
622};
623
425d244c
JW
624static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
625{
bc0daf48 626 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
627 return 1;
628}
79e53945 629
425d244c 630/* These systems claim to have LVDS, but really don't */
93c05f22 631static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
632 {
633 .callback = intel_no_lvds_dmi_callback,
634 .ident = "Apple Mac Mini (Core series)",
635 .matches = {
98acd46f 636 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
637 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
638 },
639 },
640 {
641 .callback = intel_no_lvds_dmi_callback,
642 .ident = "Apple Mac Mini (Core 2 series)",
643 .matches = {
98acd46f 644 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
645 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
646 },
647 },
648 {
649 .callback = intel_no_lvds_dmi_callback,
650 .ident = "MSI IM-945GSE-A",
651 .matches = {
652 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
653 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
654 },
655 },
656 {
657 .callback = intel_no_lvds_dmi_callback,
658 .ident = "Dell Studio Hybrid",
659 .matches = {
660 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
661 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
662 },
663 },
70aa96ca
JW
664 {
665 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
666 .ident = "Dell OptiPlex FX170",
667 .matches = {
668 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
669 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
670 },
671 },
672 {
673 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
674 .ident = "AOpen Mini PC",
675 .matches = {
676 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
677 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
678 },
679 },
ed8c754b
TV
680 {
681 .callback = intel_no_lvds_dmi_callback,
682 .ident = "AOpen Mini PC MP915",
683 .matches = {
684 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
685 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
686 },
687 },
22ab70d3
KP
688 {
689 .callback = intel_no_lvds_dmi_callback,
690 .ident = "AOpen i915GMm-HFS",
691 .matches = {
692 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
693 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
694 },
695 },
e57b6886
DV
696 {
697 .callback = intel_no_lvds_dmi_callback,
698 .ident = "AOpen i45GMx-I",
699 .matches = {
700 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
701 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
702 },
703 },
fa0864b2
MC
704 {
705 .callback = intel_no_lvds_dmi_callback,
706 .ident = "Aopen i945GTt-VFA",
707 .matches = {
708 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
709 },
710 },
9875557e
SB
711 {
712 .callback = intel_no_lvds_dmi_callback,
713 .ident = "Clientron U800",
714 .matches = {
715 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
716 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
717 },
718 },
6a574b5b 719 {
44306ab3
JS
720 .callback = intel_no_lvds_dmi_callback,
721 .ident = "Clientron E830",
722 .matches = {
723 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
724 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
725 },
726 },
727 {
6a574b5b
HG
728 .callback = intel_no_lvds_dmi_callback,
729 .ident = "Asus EeeBox PC EB1007",
730 .matches = {
731 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
732 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
733 },
734 },
0999bbe0
AJ
735 {
736 .callback = intel_no_lvds_dmi_callback,
737 .ident = "Asus AT5NM10T-I",
738 .matches = {
739 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
740 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
741 },
742 },
33471119
JBG
743 {
744 .callback = intel_no_lvds_dmi_callback,
745 .ident = "Hewlett-Packard HP t5740e Thin Client",
746 .matches = {
747 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
748 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
749 },
750 },
f5b8a7ed
MG
751 {
752 .callback = intel_no_lvds_dmi_callback,
753 .ident = "Hewlett-Packard t5745",
754 .matches = {
755 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 756 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
757 },
758 },
759 {
760 .callback = intel_no_lvds_dmi_callback,
761 .ident = "Hewlett-Packard st5747",
762 .matches = {
763 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 764 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
765 },
766 },
97effadb
AA
767 {
768 .callback = intel_no_lvds_dmi_callback,
769 .ident = "MSI Wind Box DC500",
770 .matches = {
771 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
772 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
773 },
774 },
9756fe38
SS
775 {
776 .callback = intel_no_lvds_dmi_callback,
777 .ident = "ZOTAC ZBOXSD-ID12/ID13",
778 .matches = {
779 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
780 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
781 },
782 },
425d244c
JW
783
784 { } /* terminating entry */
785};
79e53945 786
18f9ed12
ZY
787/**
788 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
789 * @dev: drm device
790 * @connector: LVDS connector
791 *
792 * Find the reduced downclock for LVDS in EDID.
793 */
794static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
795 struct drm_display_mode *fixed_mode,
796 struct drm_connector *connector)
18f9ed12
ZY
797{
798 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 799 struct drm_display_mode *scan;
18f9ed12
ZY
800 int temp_downclock;
801
788319d4 802 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
803 list_for_each_entry(scan, &connector->probed_modes, head) {
804 /*
805 * If one mode has the same resolution with the fixed_panel
806 * mode while they have the different refresh rate, it means
807 * that the reduced downclock is found for the LVDS. In such
808 * case we can set the different FPx0/1 to dynamically select
809 * between low and high frequency.
810 */
788319d4
CW
811 if (scan->hdisplay == fixed_mode->hdisplay &&
812 scan->hsync_start == fixed_mode->hsync_start &&
813 scan->hsync_end == fixed_mode->hsync_end &&
814 scan->htotal == fixed_mode->htotal &&
815 scan->vdisplay == fixed_mode->vdisplay &&
816 scan->vsync_start == fixed_mode->vsync_start &&
817 scan->vsync_end == fixed_mode->vsync_end &&
818 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
819 if (scan->clock < temp_downclock) {
820 /*
821 * The downclock is already found. But we
822 * expect to find the lower downclock.
823 */
824 temp_downclock = scan->clock;
825 }
826 }
827 }
788319d4 828 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
829 /* We found the downclock for LVDS. */
830 dev_priv->lvds_downclock_avail = 1;
831 dev_priv->lvds_downclock = temp_downclock;
832 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
833 "Normal clock %dKhz, downclock %dKhz\n",
834 fixed_mode->clock, temp_downclock);
18f9ed12 835 }
18f9ed12
ZY
836}
837
7cf4f69d
ZY
838/*
839 * Enumerate the child dev array parsed from VBT to check whether
840 * the LVDS is present.
841 * If it is present, return 1.
842 * If it is not present, return false.
843 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 844 */
270eea0f
CW
845static bool lvds_is_present_in_vbt(struct drm_device *dev,
846 u8 *i2c_pin)
7cf4f69d
ZY
847{
848 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 849 int i;
7cf4f69d
ZY
850
851 if (!dev_priv->child_dev_num)
425904dd 852 return true;
7cf4f69d 853
7cf4f69d 854 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
855 struct child_device_config *child = dev_priv->child_dev + i;
856
857 /* If the device type is not LFP, continue.
858 * We have to check both the new identifiers as well as the
859 * old for compatibility with some BIOSes.
7cf4f69d 860 */
425904dd
CW
861 if (child->device_type != DEVICE_TYPE_INT_LFP &&
862 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
863 continue;
864
3bd7d909
DK
865 if (intel_gmbus_is_port_valid(child->i2c_pin))
866 *i2c_pin = child->i2c_pin;
270eea0f 867
425904dd
CW
868 /* However, we cannot trust the BIOS writers to populate
869 * the VBT correctly. Since LVDS requires additional
870 * information from AIM blocks, a non-zero addin offset is
871 * a good indicator that the LVDS is actually present.
7cf4f69d 872 */
425904dd
CW
873 if (child->addin_offset)
874 return true;
875
876 /* But even then some BIOS writers perform some black magic
877 * and instantiate the device without reference to any
878 * additional data. Trust that if the VBT was written into
879 * the OpRegion then they have validated the LVDS's existence.
880 */
881 if (dev_priv->opregion.vbt)
882 return true;
7cf4f69d 883 }
425904dd
CW
884
885 return false;
7cf4f69d
ZY
886}
887
f3cfcba6
CW
888static bool intel_lvds_supported(struct drm_device *dev)
889{
890 /* With the introduction of the PCH we gained a dedicated
891 * LVDS presence pin, use it. */
892 if (HAS_PCH_SPLIT(dev))
893 return true;
894
895 /* Otherwise LVDS was only attached to mobile products,
896 * except for the inglorious 830gm */
897 return IS_MOBILE(dev) && !IS_I830(dev);
898}
899
79e53945
JB
900/**
901 * intel_lvds_init - setup LVDS connectors on this device
902 * @dev: drm device
903 *
904 * Create the connector, register the LVDS DDC bus, and try to figure out what
905 * modes we can display on the LVDS panel (if present).
906 */
c5d1b51d 907bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
908{
909 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 910 struct intel_lvds *intel_lvds;
21d40d37 911 struct intel_encoder *intel_encoder;
bb8a3560 912 struct intel_connector *intel_connector;
79e53945
JB
913 struct drm_connector *connector;
914 struct drm_encoder *encoder;
915 struct drm_display_mode *scan; /* *modes, *bios_mode; */
916 struct drm_crtc *crtc;
917 u32 lvds;
270eea0f
CW
918 int pipe;
919 u8 pin;
79e53945 920
f3cfcba6
CW
921 if (!intel_lvds_supported(dev))
922 return false;
923
425d244c
JW
924 /* Skip init on machines we know falsely report LVDS */
925 if (dmi_check_system(intel_no_lvds))
c5d1b51d 926 return false;
565dcd46 927
270eea0f
CW
928 pin = GMBUS_PORT_PANEL;
929 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 930 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 931 return false;
38b3037e 932 }
e99da35f 933
c619eed4 934 if (HAS_PCH_SPLIT(dev)) {
541998a1 935 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 936 return false;
5ceb0f9b 937 if (dev_priv->edp.support) {
28c97730 938 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 939 return false;
32f9d658 940 }
541998a1
ZW
941 }
942
ea5b213a
CW
943 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
944 if (!intel_lvds) {
c5d1b51d 945 return false;
79e53945
JB
946 }
947
bb8a3560
ZW
948 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
949 if (!intel_connector) {
ea5b213a 950 kfree(intel_lvds);
c5d1b51d 951 return false;
bb8a3560
ZW
952 }
953
e9e331a8
CW
954 if (!HAS_PCH_SPLIT(dev)) {
955 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
956 }
957
ea5b213a 958 intel_encoder = &intel_lvds->base;
4ef69c7a 959 encoder = &intel_encoder->base;
ea5b213a 960 connector = &intel_connector->base;
bb8a3560 961 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
962 DRM_MODE_CONNECTOR_LVDS);
963
4ef69c7a 964 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
965 DRM_MODE_ENCODER_LVDS);
966
df0e9248 967 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 968 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 969
66a9278e 970 intel_encoder->cloneable = false;
27f8227b
JB
971 if (HAS_PCH_SPLIT(dev))
972 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
973 else if (IS_GEN4(dev))
974 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
975 else
976 intel_encoder->crtc_mask = (1 << 1);
977
79e53945
JB
978 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
979 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
980 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
981 connector->interlace_allowed = false;
982 connector->doublescan_allowed = false;
983
3fbe18d6
ZY
984 /* create the scaling mode property */
985 drm_mode_create_scaling_mode_property(dev);
986 /*
987 * the initial panel fitting mode will be FULL_SCREEN.
988 */
79e53945 989
bb8a3560 990 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 991 dev->mode_config.scaling_mode_property,
dd1ea37d 992 DRM_MODE_SCALE_ASPECT);
ea5b213a 993 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
994 /*
995 * LVDS discovery:
996 * 1) check for EDID on DDC
997 * 2) check for VBT data
998 * 3) check to see if LVDS is already on
999 * if none of the above, no panel
1000 * 4) make sure lid is open
1001 * if closed, act like it's not there for now
1002 */
1003
79e53945
JB
1004 /*
1005 * Attempt to get the fixed panel mode from DDC. Assume that the
1006 * preferred mode is the right one.
1007 */
219adae1 1008 intel_lvds->edid = drm_get_edid(connector,
3bd7d909
DK
1009 intel_gmbus_get_adapter(dev_priv,
1010 pin));
3f8ff0e7
CW
1011 if (intel_lvds->edid) {
1012 if (drm_add_edid_modes(connector,
1013 intel_lvds->edid)) {
1014 drm_mode_connector_update_edid_property(connector,
1015 intel_lvds->edid);
1016 } else {
1017 kfree(intel_lvds->edid);
1018 intel_lvds->edid = NULL;
1019 }
1020 }
219adae1 1021 if (!intel_lvds->edid) {
788319d4
CW
1022 /* Didn't get an EDID, so
1023 * Set wide sync ranges so we get all modes
1024 * handed to valid_mode for checking
1025 */
1026 connector->display_info.min_vfreq = 0;
1027 connector->display_info.max_vfreq = 200;
1028 connector->display_info.min_hfreq = 0;
1029 connector->display_info.max_hfreq = 200;
1030 }
79e53945
JB
1031
1032 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1033 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
788319d4 1034 intel_lvds->fixed_mode =
79e53945 1035 drm_mode_duplicate(dev, scan);
788319d4
CW
1036 intel_find_lvds_downclock(dev,
1037 intel_lvds->fixed_mode,
1038 connector);
565dcd46 1039 goto out;
79e53945 1040 }
79e53945
JB
1041 }
1042
1043 /* Failed to get EDID, what about VBT? */
88631706 1044 if (dev_priv->lfp_lvds_vbt_mode) {
788319d4 1045 intel_lvds->fixed_mode =
88631706 1046 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
788319d4
CW
1047 if (intel_lvds->fixed_mode) {
1048 intel_lvds->fixed_mode->type |=
e285f3cd 1049 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1050 goto out;
1051 }
79e53945
JB
1052 }
1053
1054 /*
1055 * If we didn't get EDID, try checking if the panel is already turned
1056 * on. If so, assume that whatever is currently programmed is the
1057 * correct mode.
1058 */
541998a1 1059
f2b115e6 1060 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1061 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1062 goto failed;
1063
79e53945
JB
1064 lvds = I915_READ(LVDS);
1065 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1066 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1067
1068 if (crtc && (lvds & LVDS_PORT_EN)) {
788319d4
CW
1069 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
1070 if (intel_lvds->fixed_mode) {
1071 intel_lvds->fixed_mode->type |=
79e53945 1072 DRM_MODE_TYPE_PREFERRED;
565dcd46 1073 goto out;
79e53945
JB
1074 }
1075 }
1076
1077 /* If we still don't have a mode after all that, give up. */
788319d4 1078 if (!intel_lvds->fixed_mode)
79e53945
JB
1079 goto failed;
1080
79e53945 1081out:
24ded204
DV
1082 /*
1083 * Unlock registers and just
1084 * leave them unlocked
1085 */
c619eed4 1086 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1087 I915_WRITE(PCH_PP_CONTROL,
1088 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1089 } else {
ed10fca9
KP
1090 I915_WRITE(PP_CONTROL,
1091 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1092 }
c1c7af60
JB
1093 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1094 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1095 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB
1096 dev_priv->lid_notifier.notifier_call = NULL;
1097 }
a2565377
ZY
1098 /* keep the LVDS connector */
1099 dev_priv->int_lvds_connector = connector;
79e53945 1100 drm_sysfs_connector_add(connector);
aaa6fd2a
MG
1101
1102 intel_panel_setup_backlight(dev);
1103
c5d1b51d 1104 return true;
79e53945
JB
1105
1106failed:
8a4c47f3 1107 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1108 drm_connector_cleanup(connector);
1991bdfa 1109 drm_encoder_cleanup(encoder);
ea5b213a 1110 kfree(intel_lvds);
bb8a3560 1111 kfree(intel_connector);
c5d1b51d 1112 return false;
79e53945 1113}
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