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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
788319d4 | 46 | |
219adae1 | 47 | struct edid *edid; |
788319d4 | 48 | |
3fbe18d6 ZY |
49 | int fitting_mode; |
50 | u32 pfit_control; | |
51 | u32 pfit_pgm_ratios; | |
e9e331a8 | 52 | bool pfit_dirty; |
788319d4 CW |
53 | |
54 | struct drm_display_mode *fixed_mode; | |
3fbe18d6 ZY |
55 | }; |
56 | ||
788319d4 | 57 | static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
60 | } |
61 | ||
788319d4 CW |
62 | static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_lvds, base); | |
66 | } | |
67 | ||
79e53945 JB |
68 | /** |
69 | * Sets the power state for the panel. | |
70 | */ | |
2a1292fd | 71 | static void intel_lvds_enable(struct intel_lvds *intel_lvds) |
79e53945 | 72 | { |
e9e331a8 | 73 | struct drm_device *dev = intel_lvds->base.base.dev; |
79e53945 | 74 | struct drm_i915_private *dev_priv = dev->dev_private; |
de842eff | 75 | u32 ctl_reg, lvds_reg, stat_reg; |
541998a1 | 76 | |
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 78 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 79 | lvds_reg = PCH_LVDS; |
de842eff | 80 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
81 | } else { |
82 | ctl_reg = PP_CONTROL; | |
469d1296 | 83 | lvds_reg = LVDS; |
de842eff | 84 | stat_reg = PP_STATUS; |
541998a1 | 85 | } |
79e53945 | 86 | |
2a1292fd | 87 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
e9e331a8 | 88 | |
2a1292fd CW |
89 | if (intel_lvds->pfit_dirty) { |
90 | /* | |
91 | * Enable automatic panel scaling so that non-native modes | |
92 | * fill the screen. The panel fitter should only be | |
93 | * adjusted whilst the pipe is disabled, according to | |
94 | * register description and PRM. | |
95 | */ | |
96 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
97 | intel_lvds->pfit_control, | |
98 | intel_lvds->pfit_pgm_ratios); | |
de842eff KP |
99 | |
100 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); | |
101 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
102 | intel_lvds->pfit_dirty = false; | |
2a1292fd CW |
103 | } |
104 | ||
105 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); | |
106 | POSTING_READ(lvds_reg); | |
de842eff KP |
107 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
108 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 109 | |
47356eb6 | 110 | intel_panel_enable_backlight(dev); |
2a1292fd CW |
111 | } |
112 | ||
113 | static void intel_lvds_disable(struct intel_lvds *intel_lvds) | |
114 | { | |
115 | struct drm_device *dev = intel_lvds->base.base.dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de842eff | 117 | u32 ctl_reg, lvds_reg, stat_reg; |
2a1292fd CW |
118 | |
119 | if (HAS_PCH_SPLIT(dev)) { | |
120 | ctl_reg = PCH_PP_CONTROL; | |
121 | lvds_reg = PCH_LVDS; | |
de842eff | 122 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
123 | } else { |
124 | ctl_reg = PP_CONTROL; | |
125 | lvds_reg = LVDS; | |
de842eff | 126 | stat_reg = PP_STATUS; |
2a1292fd CW |
127 | } |
128 | ||
47356eb6 | 129 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
130 | |
131 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
132 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
133 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd CW |
134 | |
135 | if (intel_lvds->pfit_control) { | |
2a1292fd CW |
136 | I915_WRITE(PFIT_CONTROL, 0); |
137 | intel_lvds->pfit_dirty = true; | |
79e53945 | 138 | } |
2a1292fd CW |
139 | |
140 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
c9f9ccc1 | 141 | POSTING_READ(lvds_reg); |
79e53945 JB |
142 | } |
143 | ||
144 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
145 | { | |
788319d4 | 146 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
147 | |
148 | if (mode == DRM_MODE_DPMS_ON) | |
2a1292fd | 149 | intel_lvds_enable(intel_lvds); |
79e53945 | 150 | else |
2a1292fd | 151 | intel_lvds_disable(intel_lvds); |
79e53945 JB |
152 | |
153 | /* XXX: We never power down the LVDS pairs. */ | |
154 | } | |
155 | ||
79e53945 JB |
156 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
157 | struct drm_display_mode *mode) | |
158 | { | |
788319d4 CW |
159 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
160 | struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; | |
79e53945 | 161 | |
788319d4 CW |
162 | if (mode->hdisplay > fixed_mode->hdisplay) |
163 | return MODE_PANEL; | |
164 | if (mode->vdisplay > fixed_mode->vdisplay) | |
165 | return MODE_PANEL; | |
79e53945 JB |
166 | |
167 | return MODE_OK; | |
168 | } | |
169 | ||
49be663f CW |
170 | static void |
171 | centre_horizontally(struct drm_display_mode *mode, | |
172 | int width) | |
173 | { | |
174 | u32 border, sync_pos, blank_width, sync_width; | |
175 | ||
176 | /* keep the hsync and hblank widths constant */ | |
177 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
178 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
179 | sync_pos = (blank_width - sync_width + 1) / 2; | |
180 | ||
181 | border = (mode->hdisplay - width + 1) / 2; | |
182 | border += border & 1; /* make the border even */ | |
183 | ||
184 | mode->crtc_hdisplay = width; | |
185 | mode->crtc_hblank_start = width + border; | |
186 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
187 | ||
188 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
189 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
f9bef081 DV |
190 | |
191 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
192 | } |
193 | ||
194 | static void | |
195 | centre_vertically(struct drm_display_mode *mode, | |
196 | int height) | |
197 | { | |
198 | u32 border, sync_pos, blank_width, sync_width; | |
199 | ||
200 | /* keep the vsync and vblank widths constant */ | |
201 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
202 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
203 | sync_pos = (blank_width - sync_width + 1) / 2; | |
204 | ||
205 | border = (mode->vdisplay - height + 1) / 2; | |
206 | ||
207 | mode->crtc_vdisplay = height; | |
208 | mode->crtc_vblank_start = height + border; | |
209 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
210 | ||
211 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
212 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
f9bef081 DV |
213 | |
214 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
215 | } |
216 | ||
217 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
218 | { | |
219 | /* | |
220 | * Floating point operation is not supported. So the FACTOR | |
221 | * is defined, which can avoid the floating point computation | |
222 | * when calculating the panel ratio. | |
223 | */ | |
224 | #define ACCURACY 12 | |
225 | #define FACTOR (1 << ACCURACY) | |
226 | u32 ratio = source * FACTOR / target; | |
227 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
228 | } | |
229 | ||
79e53945 JB |
230 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
231 | struct drm_display_mode *mode, | |
232 | struct drm_display_mode *adjusted_mode) | |
233 | { | |
234 | struct drm_device *dev = encoder->dev; | |
235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
236 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
788319d4 | 237 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 238 | struct drm_encoder *tmp_encoder; |
49be663f | 239 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
9db4a9c7 | 240 | int pipe; |
79e53945 JB |
241 | |
242 | /* Should never happen!! */ | |
a6c45cf0 | 243 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 244 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
245 | return false; |
246 | } | |
247 | ||
248 | /* Should never happen!! */ | |
249 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
250 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 251 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
252 | "encoder on the same pipe\n"); |
253 | return false; | |
254 | } | |
255 | } | |
1d8e1c75 | 256 | |
79e53945 | 257 | /* |
71677043 | 258 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
259 | * to the adjusted mode. The CRTC will be set up for this mode, |
260 | * with the panel scaling set up to source from the H/VDisplay | |
261 | * of the original mode. | |
262 | */ | |
788319d4 | 263 | intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); |
1d8e1c75 CW |
264 | |
265 | if (HAS_PCH_SPLIT(dev)) { | |
266 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
267 | mode, adjusted_mode); | |
268 | return true; | |
269 | } | |
79e53945 | 270 | |
3fbe18d6 ZY |
271 | /* Native modes don't need fitting */ |
272 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 273 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 274 | goto out; |
3fbe18d6 ZY |
275 | |
276 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 277 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
278 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
279 | PFIT_FILTER_FUZZY); | |
280 | ||
3fbe18d6 ZY |
281 | /* |
282 | * Enable automatic panel scaling for non-native modes so that they fill | |
283 | * the screen. Should be enabled before the pipe is enabled, according | |
284 | * to register description and PRM. | |
285 | * Change the value here to see the borders for debugging | |
286 | */ | |
9db4a9c7 JB |
287 | for_each_pipe(pipe) |
288 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 289 | |
f9bef081 DV |
290 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
291 | ||
ea5b213a | 292 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 293 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
294 | /* |
295 | * For centered modes, we have to calculate border widths & | |
296 | * heights and modify the values programmed into the CRTC. | |
297 | */ | |
49be663f CW |
298 | centre_horizontally(adjusted_mode, mode->hdisplay); |
299 | centre_vertically(adjusted_mode, mode->vdisplay); | |
300 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 301 | break; |
49be663f | 302 | |
3fbe18d6 | 303 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 304 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 305 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
306 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
307 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
308 | ||
3fbe18d6 | 309 | /* 965+ is easy, it does everything in hw */ |
49be663f | 310 | if (scaled_width > scaled_height) |
257e48f1 | 311 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 312 | else if (scaled_width < scaled_height) |
257e48f1 CW |
313 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
314 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
315 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 316 | } else { |
49be663f CW |
317 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
318 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
319 | /* |
320 | * For earlier chips we have to calculate the scaling | |
321 | * ratio by hand and program it into the | |
322 | * PFIT_PGM_RATIO register | |
323 | */ | |
49be663f CW |
324 | if (scaled_width > scaled_height) { /* pillar */ |
325 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
326 | ||
327 | border = LVDS_BORDER_ENABLE; | |
328 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
329 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
330 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
331 | bits << PFIT_VERT_SCALE_SHIFT); | |
332 | pfit_control |= (PFIT_ENABLE | | |
333 | VERT_INTERP_BILINEAR | | |
334 | HORIZ_INTERP_BILINEAR); | |
335 | } | |
336 | } else if (scaled_width < scaled_height) { /* letter */ | |
337 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
338 | ||
339 | border = LVDS_BORDER_ENABLE; | |
340 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
341 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
342 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
343 | bits << PFIT_VERT_SCALE_SHIFT); | |
344 | pfit_control |= (PFIT_ENABLE | | |
345 | VERT_INTERP_BILINEAR | | |
346 | HORIZ_INTERP_BILINEAR); | |
347 | } | |
348 | } else | |
349 | /* Aspects match, Let hw scale both directions */ | |
350 | pfit_control |= (PFIT_ENABLE | | |
351 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
352 | VERT_INTERP_BILINEAR | |
353 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
354 | } |
355 | break; | |
356 | ||
357 | case DRM_MODE_SCALE_FULLSCREEN: | |
358 | /* | |
359 | * Full scaling, even if it changes the aspect ratio. | |
360 | * Fortunately this is all done for us in hw. | |
361 | */ | |
257e48f1 CW |
362 | if (mode->vdisplay != adjusted_mode->vdisplay || |
363 | mode->hdisplay != adjusted_mode->hdisplay) { | |
364 | pfit_control |= PFIT_ENABLE; | |
365 | if (INTEL_INFO(dev)->gen >= 4) | |
366 | pfit_control |= PFIT_SCALING_AUTO; | |
367 | else | |
368 | pfit_control |= (VERT_AUTO_SCALE | | |
369 | VERT_INTERP_BILINEAR | | |
370 | HORIZ_AUTO_SCALE | | |
371 | HORIZ_INTERP_BILINEAR); | |
372 | } | |
3fbe18d6 | 373 | break; |
49be663f | 374 | |
3fbe18d6 ZY |
375 | default: |
376 | break; | |
377 | } | |
378 | ||
379 | out: | |
72389a33 | 380 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
381 | if ((pfit_control & PFIT_ENABLE) == 0) { |
382 | pfit_control = 0; | |
383 | pfit_pgm_ratios = 0; | |
384 | } | |
72389a33 CW |
385 | |
386 | /* Make sure pre-965 set dither correctly */ | |
387 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
388 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
389 | ||
e9e331a8 CW |
390 | if (pfit_control != intel_lvds->pfit_control || |
391 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | |
392 | intel_lvds->pfit_control = pfit_control; | |
393 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
394 | intel_lvds->pfit_dirty = true; | |
395 | } | |
49be663f CW |
396 | dev_priv->lvds_border_bits = border; |
397 | ||
79e53945 JB |
398 | /* |
399 | * XXX: It would be nice to support lower refresh rates on the | |
400 | * panels to reduce power consumption, and perhaps match the | |
401 | * user's requested refresh rate. | |
402 | */ | |
403 | ||
404 | return true; | |
405 | } | |
406 | ||
407 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
408 | { | |
788319d4 | 409 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 410 | |
ed10fca9 | 411 | /* |
e9e331a8 CW |
412 | * Prior to Ironlake, we must disable the pipe if we want to adjust |
413 | * the panel fitter. However at all other times we can just reset | |
414 | * the registers regardless. | |
415 | */ | |
ed10fca9 KP |
416 | if (!HAS_PCH_SPLIT(encoder->dev) && intel_lvds->pfit_dirty) |
417 | intel_lvds_disable(intel_lvds); | |
79e53945 JB |
418 | } |
419 | ||
e9e331a8 | 420 | static void intel_lvds_commit(struct drm_encoder *encoder) |
79e53945 | 421 | { |
788319d4 | 422 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 423 | |
e9e331a8 CW |
424 | /* Always do a full power on as we do not know what state |
425 | * we were left in. | |
426 | */ | |
2a1292fd | 427 | intel_lvds_enable(intel_lvds); |
79e53945 JB |
428 | } |
429 | ||
430 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
431 | struct drm_display_mode *mode, | |
432 | struct drm_display_mode *adjusted_mode) | |
433 | { | |
79e53945 JB |
434 | /* |
435 | * The LVDS pin pair will already have been turned on in the | |
436 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
437 | * settings. | |
438 | */ | |
79e53945 JB |
439 | } |
440 | ||
441 | /** | |
442 | * Detect the LVDS connection. | |
443 | * | |
b42d4c5c JB |
444 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
445 | * connected and closed means disconnected. We also send hotplug events as | |
446 | * needed, using lid status notification from the input layer. | |
79e53945 | 447 | */ |
7b334fcb | 448 | static enum drm_connector_status |
930a9e28 | 449 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 450 | { |
7b9c5abe | 451 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 452 | enum drm_connector_status status; |
b42d4c5c | 453 | |
fe16d949 CW |
454 | status = intel_panel_detect(dev); |
455 | if (status != connector_status_unknown) | |
456 | return status; | |
01fe9dbd | 457 | |
6ee3b5a1 | 458 | return connector_status_connected; |
79e53945 JB |
459 | } |
460 | ||
461 | /** | |
462 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
463 | */ | |
464 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
465 | { | |
788319d4 | 466 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
79e53945 | 467 | struct drm_device *dev = connector->dev; |
788319d4 | 468 | struct drm_display_mode *mode; |
79e53945 | 469 | |
3f8ff0e7 | 470 | if (intel_lvds->edid) |
219adae1 | 471 | return drm_add_edid_modes(connector, intel_lvds->edid); |
79e53945 | 472 | |
788319d4 | 473 | mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); |
311bd68e | 474 | if (mode == NULL) |
788319d4 | 475 | return 0; |
79e53945 | 476 | |
788319d4 CW |
477 | drm_mode_probed_add(connector, mode); |
478 | return 1; | |
79e53945 JB |
479 | } |
480 | ||
0544edfd TB |
481 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
482 | { | |
bc0daf48 | 483 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
484 | return 1; |
485 | } | |
486 | ||
487 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
488 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
489 | { | |
490 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
491 | .ident = "Toshiba Tecra A11", | |
492 | .matches = { | |
493 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
494 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
495 | }, | |
496 | }, | |
497 | ||
498 | { } /* terminating entry */ | |
499 | }; | |
500 | ||
c9354c85 LT |
501 | /* |
502 | * Lid events. Note the use of 'modeset_on_lid': | |
503 | * - we set it on lid close, and reset it on open | |
504 | * - we use it as a "only once" bit (ie we ignore | |
505 | * duplicate events where it was already properly | |
506 | * set/reset) | |
507 | * - the suspend/resume paths will also set it to | |
508 | * zero, since they restore the mode ("lid open"). | |
509 | */ | |
c1c7af60 JB |
510 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
511 | void *unused) | |
512 | { | |
513 | struct drm_i915_private *dev_priv = | |
514 | container_of(nb, struct drm_i915_private, lid_notifier); | |
515 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 516 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 517 | |
2fb4e61d AW |
518 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
519 | return NOTIFY_OK; | |
520 | ||
a2565377 ZY |
521 | /* |
522 | * check and update the status of LVDS connector after receiving | |
523 | * the LID nofication event. | |
524 | */ | |
525 | if (connector) | |
7b334fcb | 526 | connector->status = connector->funcs->detect(connector, |
930a9e28 | 527 | false); |
7b334fcb | 528 | |
0544edfd TB |
529 | /* Don't force modeset on machines where it causes a GPU lockup */ |
530 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
531 | return NOTIFY_OK; | |
c9354c85 LT |
532 | if (!acpi_lid_open()) { |
533 | dev_priv->modeset_on_lid = 1; | |
534 | return NOTIFY_OK; | |
06891e27 | 535 | } |
c1c7af60 | 536 | |
c9354c85 LT |
537 | if (!dev_priv->modeset_on_lid) |
538 | return NOTIFY_OK; | |
539 | ||
540 | dev_priv->modeset_on_lid = 0; | |
541 | ||
542 | mutex_lock(&dev->mode_config.mutex); | |
543 | drm_helper_resume_force_mode(dev); | |
544 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 545 | |
c1c7af60 JB |
546 | return NOTIFY_OK; |
547 | } | |
548 | ||
79e53945 JB |
549 | /** |
550 | * intel_lvds_destroy - unregister and free LVDS structures | |
551 | * @connector: connector to free | |
552 | * | |
553 | * Unregister the DDC bus for this connector then free the driver private | |
554 | * structure. | |
555 | */ | |
556 | static void intel_lvds_destroy(struct drm_connector *connector) | |
557 | { | |
c1c7af60 | 558 | struct drm_device *dev = connector->dev; |
c1c7af60 | 559 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 560 | |
aaa6fd2a MG |
561 | intel_panel_destroy_backlight(dev); |
562 | ||
c1c7af60 JB |
563 | if (dev_priv->lid_notifier.notifier_call) |
564 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
565 | drm_sysfs_connector_remove(connector); |
566 | drm_connector_cleanup(connector); | |
567 | kfree(connector); | |
568 | } | |
569 | ||
335041ed JB |
570 | static int intel_lvds_set_property(struct drm_connector *connector, |
571 | struct drm_property *property, | |
572 | uint64_t value) | |
573 | { | |
788319d4 | 574 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
3fbe18d6 | 575 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 576 | |
788319d4 CW |
577 | if (property == dev->mode_config.scaling_mode_property) { |
578 | struct drm_crtc *crtc = intel_lvds->base.base.crtc; | |
bb8a3560 | 579 | |
53bd8389 JB |
580 | if (value == DRM_MODE_SCALE_NONE) { |
581 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 582 | return -EINVAL; |
3fbe18d6 | 583 | } |
788319d4 | 584 | |
ea5b213a | 585 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
586 | /* the LVDS scaling property is not changed */ |
587 | return 0; | |
588 | } | |
ea5b213a | 589 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
590 | if (crtc && crtc->enabled) { |
591 | /* | |
592 | * If the CRTC is enabled, the display will be changed | |
593 | * according to the new panel fitting mode. | |
594 | */ | |
595 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
596 | crtc->x, crtc->y, crtc->fb); | |
597 | } | |
598 | } | |
599 | ||
335041ed JB |
600 | return 0; |
601 | } | |
602 | ||
79e53945 JB |
603 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
604 | .dpms = intel_lvds_dpms, | |
605 | .mode_fixup = intel_lvds_mode_fixup, | |
606 | .prepare = intel_lvds_prepare, | |
607 | .mode_set = intel_lvds_mode_set, | |
608 | .commit = intel_lvds_commit, | |
609 | }; | |
610 | ||
611 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
612 | .get_modes = intel_lvds_get_modes, | |
613 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 614 | .best_encoder = intel_best_encoder, |
79e53945 JB |
615 | }; |
616 | ||
617 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 618 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
619 | .detect = intel_lvds_detect, |
620 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 621 | .set_property = intel_lvds_set_property, |
79e53945 JB |
622 | .destroy = intel_lvds_destroy, |
623 | }; | |
624 | ||
79e53945 | 625 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 626 | .destroy = intel_encoder_destroy, |
79e53945 JB |
627 | }; |
628 | ||
425d244c JW |
629 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
630 | { | |
bc0daf48 | 631 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
632 | return 1; |
633 | } | |
79e53945 | 634 | |
425d244c | 635 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 636 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
637 | { |
638 | .callback = intel_no_lvds_dmi_callback, | |
639 | .ident = "Apple Mac Mini (Core series)", | |
640 | .matches = { | |
98acd46f | 641 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
642 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
643 | }, | |
644 | }, | |
645 | { | |
646 | .callback = intel_no_lvds_dmi_callback, | |
647 | .ident = "Apple Mac Mini (Core 2 series)", | |
648 | .matches = { | |
98acd46f | 649 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
650 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
651 | }, | |
652 | }, | |
653 | { | |
654 | .callback = intel_no_lvds_dmi_callback, | |
655 | .ident = "MSI IM-945GSE-A", | |
656 | .matches = { | |
657 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
658 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
659 | }, | |
660 | }, | |
661 | { | |
662 | .callback = intel_no_lvds_dmi_callback, | |
663 | .ident = "Dell Studio Hybrid", | |
664 | .matches = { | |
665 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
666 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
667 | }, | |
668 | }, | |
70aa96ca JW |
669 | { |
670 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
671 | .ident = "Dell OptiPlex FX170", |
672 | .matches = { | |
673 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
674 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
675 | }, | |
676 | }, | |
677 | { | |
678 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
679 | .ident = "AOpen Mini PC", |
680 | .matches = { | |
681 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
682 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
683 | }, | |
684 | }, | |
ed8c754b TV |
685 | { |
686 | .callback = intel_no_lvds_dmi_callback, | |
687 | .ident = "AOpen Mini PC MP915", | |
688 | .matches = { | |
689 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
690 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
691 | }, | |
692 | }, | |
22ab70d3 KP |
693 | { |
694 | .callback = intel_no_lvds_dmi_callback, | |
695 | .ident = "AOpen i915GMm-HFS", | |
696 | .matches = { | |
697 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
698 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
699 | }, | |
700 | }, | |
e57b6886 DV |
701 | { |
702 | .callback = intel_no_lvds_dmi_callback, | |
703 | .ident = "AOpen i45GMx-I", | |
704 | .matches = { | |
705 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
706 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
707 | }, | |
708 | }, | |
fa0864b2 MC |
709 | { |
710 | .callback = intel_no_lvds_dmi_callback, | |
711 | .ident = "Aopen i945GTt-VFA", | |
712 | .matches = { | |
713 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
714 | }, | |
715 | }, | |
9875557e SB |
716 | { |
717 | .callback = intel_no_lvds_dmi_callback, | |
718 | .ident = "Clientron U800", | |
719 | .matches = { | |
720 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
721 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
722 | }, | |
723 | }, | |
6a574b5b | 724 | { |
44306ab3 JS |
725 | .callback = intel_no_lvds_dmi_callback, |
726 | .ident = "Clientron E830", | |
727 | .matches = { | |
728 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
729 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
730 | }, | |
731 | }, | |
732 | { | |
6a574b5b HG |
733 | .callback = intel_no_lvds_dmi_callback, |
734 | .ident = "Asus EeeBox PC EB1007", | |
735 | .matches = { | |
736 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
737 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
738 | }, | |
739 | }, | |
0999bbe0 AJ |
740 | { |
741 | .callback = intel_no_lvds_dmi_callback, | |
742 | .ident = "Asus AT5NM10T-I", | |
743 | .matches = { | |
744 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
745 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
746 | }, | |
747 | }, | |
f5b8a7ed MG |
748 | { |
749 | .callback = intel_no_lvds_dmi_callback, | |
750 | .ident = "Hewlett-Packard t5745", | |
751 | .matches = { | |
752 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 753 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
754 | }, |
755 | }, | |
756 | { | |
757 | .callback = intel_no_lvds_dmi_callback, | |
758 | .ident = "Hewlett-Packard st5747", | |
759 | .matches = { | |
760 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 761 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
762 | }, |
763 | }, | |
97effadb AA |
764 | { |
765 | .callback = intel_no_lvds_dmi_callback, | |
766 | .ident = "MSI Wind Box DC500", | |
767 | .matches = { | |
768 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
769 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
770 | }, | |
771 | }, | |
425d244c JW |
772 | |
773 | { } /* terminating entry */ | |
774 | }; | |
79e53945 | 775 | |
18f9ed12 ZY |
776 | /** |
777 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
778 | * @dev: drm device | |
779 | * @connector: LVDS connector | |
780 | * | |
781 | * Find the reduced downclock for LVDS in EDID. | |
782 | */ | |
783 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
784 | struct drm_display_mode *fixed_mode, |
785 | struct drm_connector *connector) | |
18f9ed12 ZY |
786 | { |
787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 788 | struct drm_display_mode *scan; |
18f9ed12 ZY |
789 | int temp_downclock; |
790 | ||
788319d4 | 791 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
792 | list_for_each_entry(scan, &connector->probed_modes, head) { |
793 | /* | |
794 | * If one mode has the same resolution with the fixed_panel | |
795 | * mode while they have the different refresh rate, it means | |
796 | * that the reduced downclock is found for the LVDS. In such | |
797 | * case we can set the different FPx0/1 to dynamically select | |
798 | * between low and high frequency. | |
799 | */ | |
788319d4 CW |
800 | if (scan->hdisplay == fixed_mode->hdisplay && |
801 | scan->hsync_start == fixed_mode->hsync_start && | |
802 | scan->hsync_end == fixed_mode->hsync_end && | |
803 | scan->htotal == fixed_mode->htotal && | |
804 | scan->vdisplay == fixed_mode->vdisplay && | |
805 | scan->vsync_start == fixed_mode->vsync_start && | |
806 | scan->vsync_end == fixed_mode->vsync_end && | |
807 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
808 | if (scan->clock < temp_downclock) { |
809 | /* | |
810 | * The downclock is already found. But we | |
811 | * expect to find the lower downclock. | |
812 | */ | |
813 | temp_downclock = scan->clock; | |
814 | } | |
815 | } | |
816 | } | |
788319d4 | 817 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
818 | /* We found the downclock for LVDS. */ |
819 | dev_priv->lvds_downclock_avail = 1; | |
820 | dev_priv->lvds_downclock = temp_downclock; | |
821 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
822 | "Normal clock %dKhz, downclock %dKhz\n", |
823 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 824 | } |
18f9ed12 ZY |
825 | } |
826 | ||
7cf4f69d ZY |
827 | /* |
828 | * Enumerate the child dev array parsed from VBT to check whether | |
829 | * the LVDS is present. | |
830 | * If it is present, return 1. | |
831 | * If it is not present, return false. | |
832 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 833 | */ |
270eea0f CW |
834 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
835 | u8 *i2c_pin) | |
7cf4f69d ZY |
836 | { |
837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 838 | int i; |
7cf4f69d ZY |
839 | |
840 | if (!dev_priv->child_dev_num) | |
425904dd | 841 | return true; |
7cf4f69d | 842 | |
7cf4f69d | 843 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
844 | struct child_device_config *child = dev_priv->child_dev + i; |
845 | ||
846 | /* If the device type is not LFP, continue. | |
847 | * We have to check both the new identifiers as well as the | |
848 | * old for compatibility with some BIOSes. | |
7cf4f69d | 849 | */ |
425904dd CW |
850 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
851 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
852 | continue; |
853 | ||
3bd7d909 DK |
854 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
855 | *i2c_pin = child->i2c_pin; | |
270eea0f | 856 | |
425904dd CW |
857 | /* However, we cannot trust the BIOS writers to populate |
858 | * the VBT correctly. Since LVDS requires additional | |
859 | * information from AIM blocks, a non-zero addin offset is | |
860 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 861 | */ |
425904dd CW |
862 | if (child->addin_offset) |
863 | return true; | |
864 | ||
865 | /* But even then some BIOS writers perform some black magic | |
866 | * and instantiate the device without reference to any | |
867 | * additional data. Trust that if the VBT was written into | |
868 | * the OpRegion then they have validated the LVDS's existence. | |
869 | */ | |
870 | if (dev_priv->opregion.vbt) | |
871 | return true; | |
7cf4f69d | 872 | } |
425904dd CW |
873 | |
874 | return false; | |
7cf4f69d ZY |
875 | } |
876 | ||
f3cfcba6 CW |
877 | static bool intel_lvds_supported(struct drm_device *dev) |
878 | { | |
879 | /* With the introduction of the PCH we gained a dedicated | |
880 | * LVDS presence pin, use it. */ | |
881 | if (HAS_PCH_SPLIT(dev)) | |
882 | return true; | |
883 | ||
884 | /* Otherwise LVDS was only attached to mobile products, | |
885 | * except for the inglorious 830gm */ | |
886 | return IS_MOBILE(dev) && !IS_I830(dev); | |
887 | } | |
888 | ||
79e53945 JB |
889 | /** |
890 | * intel_lvds_init - setup LVDS connectors on this device | |
891 | * @dev: drm device | |
892 | * | |
893 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
894 | * modes we can display on the LVDS panel (if present). | |
895 | */ | |
c5d1b51d | 896 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
897 | { |
898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 899 | struct intel_lvds *intel_lvds; |
21d40d37 | 900 | struct intel_encoder *intel_encoder; |
bb8a3560 | 901 | struct intel_connector *intel_connector; |
79e53945 JB |
902 | struct drm_connector *connector; |
903 | struct drm_encoder *encoder; | |
904 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
905 | struct drm_crtc *crtc; | |
906 | u32 lvds; | |
270eea0f CW |
907 | int pipe; |
908 | u8 pin; | |
79e53945 | 909 | |
f3cfcba6 CW |
910 | if (!intel_lvds_supported(dev)) |
911 | return false; | |
912 | ||
425d244c JW |
913 | /* Skip init on machines we know falsely report LVDS */ |
914 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 915 | return false; |
565dcd46 | 916 | |
270eea0f CW |
917 | pin = GMBUS_PORT_PANEL; |
918 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 919 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 920 | return false; |
38b3037e | 921 | } |
e99da35f | 922 | |
c619eed4 | 923 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 924 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 925 | return false; |
5ceb0f9b | 926 | if (dev_priv->edp.support) { |
28c97730 | 927 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 928 | return false; |
32f9d658 | 929 | } |
541998a1 ZW |
930 | } |
931 | ||
ea5b213a CW |
932 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
933 | if (!intel_lvds) { | |
c5d1b51d | 934 | return false; |
79e53945 JB |
935 | } |
936 | ||
bb8a3560 ZW |
937 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
938 | if (!intel_connector) { | |
ea5b213a | 939 | kfree(intel_lvds); |
c5d1b51d | 940 | return false; |
bb8a3560 ZW |
941 | } |
942 | ||
e9e331a8 CW |
943 | if (!HAS_PCH_SPLIT(dev)) { |
944 | intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); | |
945 | } | |
946 | ||
ea5b213a | 947 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 948 | encoder = &intel_encoder->base; |
ea5b213a | 949 | connector = &intel_connector->base; |
bb8a3560 | 950 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
951 | DRM_MODE_CONNECTOR_LVDS); |
952 | ||
4ef69c7a | 953 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
954 | DRM_MODE_ENCODER_LVDS); |
955 | ||
df0e9248 | 956 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 957 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 958 | |
21d40d37 | 959 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
27f8227b JB |
960 | if (HAS_PCH_SPLIT(dev)) |
961 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
962 | else | |
963 | intel_encoder->crtc_mask = (1 << 1); | |
964 | ||
79e53945 JB |
965 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
966 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
967 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
968 | connector->interlace_allowed = false; | |
969 | connector->doublescan_allowed = false; | |
970 | ||
3fbe18d6 ZY |
971 | /* create the scaling mode property */ |
972 | drm_mode_create_scaling_mode_property(dev); | |
973 | /* | |
974 | * the initial panel fitting mode will be FULL_SCREEN. | |
975 | */ | |
79e53945 | 976 | |
bb8a3560 | 977 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 978 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 979 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 980 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
981 | /* |
982 | * LVDS discovery: | |
983 | * 1) check for EDID on DDC | |
984 | * 2) check for VBT data | |
985 | * 3) check to see if LVDS is already on | |
986 | * if none of the above, no panel | |
987 | * 4) make sure lid is open | |
988 | * if closed, act like it's not there for now | |
989 | */ | |
990 | ||
79e53945 JB |
991 | /* |
992 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
993 | * preferred mode is the right one. | |
994 | */ | |
219adae1 | 995 | intel_lvds->edid = drm_get_edid(connector, |
3bd7d909 DK |
996 | intel_gmbus_get_adapter(dev_priv, |
997 | pin)); | |
3f8ff0e7 CW |
998 | if (intel_lvds->edid) { |
999 | if (drm_add_edid_modes(connector, | |
1000 | intel_lvds->edid)) { | |
1001 | drm_mode_connector_update_edid_property(connector, | |
1002 | intel_lvds->edid); | |
1003 | } else { | |
1004 | kfree(intel_lvds->edid); | |
1005 | intel_lvds->edid = NULL; | |
1006 | } | |
1007 | } | |
219adae1 | 1008 | if (!intel_lvds->edid) { |
788319d4 CW |
1009 | /* Didn't get an EDID, so |
1010 | * Set wide sync ranges so we get all modes | |
1011 | * handed to valid_mode for checking | |
1012 | */ | |
1013 | connector->display_info.min_vfreq = 0; | |
1014 | connector->display_info.max_vfreq = 200; | |
1015 | connector->display_info.min_hfreq = 0; | |
1016 | connector->display_info.max_hfreq = 200; | |
1017 | } | |
79e53945 JB |
1018 | |
1019 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1020 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
788319d4 | 1021 | intel_lvds->fixed_mode = |
79e53945 | 1022 | drm_mode_duplicate(dev, scan); |
788319d4 CW |
1023 | intel_find_lvds_downclock(dev, |
1024 | intel_lvds->fixed_mode, | |
1025 | connector); | |
565dcd46 | 1026 | goto out; |
79e53945 | 1027 | } |
79e53945 JB |
1028 | } |
1029 | ||
1030 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1031 | if (dev_priv->lfp_lvds_vbt_mode) { |
788319d4 | 1032 | intel_lvds->fixed_mode = |
88631706 | 1033 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
788319d4 CW |
1034 | if (intel_lvds->fixed_mode) { |
1035 | intel_lvds->fixed_mode->type |= | |
e285f3cd | 1036 | DRM_MODE_TYPE_PREFERRED; |
e285f3cd JB |
1037 | goto out; |
1038 | } | |
79e53945 JB |
1039 | } |
1040 | ||
1041 | /* | |
1042 | * If we didn't get EDID, try checking if the panel is already turned | |
1043 | * on. If so, assume that whatever is currently programmed is the | |
1044 | * correct mode. | |
1045 | */ | |
541998a1 | 1046 | |
f2b115e6 | 1047 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1048 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1049 | goto failed; |
1050 | ||
79e53945 JB |
1051 | lvds = I915_READ(LVDS); |
1052 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1053 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1054 | |
1055 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
788319d4 CW |
1056 | intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); |
1057 | if (intel_lvds->fixed_mode) { | |
1058 | intel_lvds->fixed_mode->type |= | |
79e53945 | 1059 | DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1060 | goto out; |
79e53945 JB |
1061 | } |
1062 | } | |
1063 | ||
1064 | /* If we still don't have a mode after all that, give up. */ | |
788319d4 | 1065 | if (!intel_lvds->fixed_mode) |
79e53945 JB |
1066 | goto failed; |
1067 | ||
79e53945 | 1068 | out: |
c619eed4 | 1069 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1070 | u32 pwm; |
17fe6981 CW |
1071 | |
1072 | pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1073 | ||
1074 | /* make sure PWM is enabled and locked to the LVDS pipe */ | |
541998a1 | 1075 | pwm = I915_READ(BLC_PWM_CPU_CTL2); |
17fe6981 CW |
1076 | if (pipe == 0 && (pwm & PWM_PIPE_B)) |
1077 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); | |
1078 | if (pipe) | |
1079 | pwm |= PWM_PIPE_B; | |
1080 | else | |
1081 | pwm &= ~PWM_PIPE_B; | |
1082 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); | |
541998a1 ZW |
1083 | |
1084 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1085 | pwm |= PWM_PCH_ENABLE; | |
1086 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
ed10fca9 KP |
1087 | /* |
1088 | * Unlock registers and just | |
1089 | * leave them unlocked | |
1090 | */ | |
1091 | I915_WRITE(PCH_PP_CONTROL, | |
1092 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1093 | } else { | |
1094 | /* | |
1095 | * Unlock registers and just | |
1096 | * leave them unlocked | |
1097 | */ | |
1098 | I915_WRITE(PP_CONTROL, | |
1099 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1100 | } |
c1c7af60 JB |
1101 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1102 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1103 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1104 | dev_priv->lid_notifier.notifier_call = NULL; |
1105 | } | |
a2565377 ZY |
1106 | /* keep the LVDS connector */ |
1107 | dev_priv->int_lvds_connector = connector; | |
79e53945 | 1108 | drm_sysfs_connector_add(connector); |
aaa6fd2a MG |
1109 | |
1110 | intel_panel_setup_backlight(dev); | |
1111 | ||
c5d1b51d | 1112 | return true; |
79e53945 JB |
1113 | |
1114 | failed: | |
8a4c47f3 | 1115 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1116 | drm_connector_cleanup(connector); |
1991bdfa | 1117 | drm_encoder_cleanup(encoder); |
ea5b213a | 1118 | kfree(intel_lvds); |
bb8a3560 | 1119 | kfree(intel_connector); |
c5d1b51d | 1120 | return false; |
79e53945 | 1121 | } |