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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
565dcd46 | 30 | #include <linux/dmi.h> |
79e53945 JB |
31 | #include <linux/i2c.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
35 | #include "drm_edid.h" | |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e99da35f | 39 | #include <linux/acpi.h> |
79e53945 | 40 | |
7fb85bfb | 41 | #define I915_LVDS "i915_lvds" |
42 | ||
3fbe18d6 ZY |
43 | /* |
44 | * the following four scaling options are defined. | |
45 | * #define DRM_MODE_SCALE_NON_GPU 0 | |
46 | * #define DRM_MODE_SCALE_FULLSCREEN 1 | |
47 | * #define DRM_MODE_SCALE_NO_SCALE 2 | |
48 | * #define DRM_MODE_SCALE_ASPECT 3 | |
49 | */ | |
50 | ||
51 | /* Private structure for the integrated LVDS support */ | |
52 | struct intel_lvds_priv { | |
53 | int fitting_mode; | |
54 | u32 pfit_control; | |
55 | u32 pfit_pgm_ratios; | |
56 | }; | |
57 | ||
79e53945 JB |
58 | /** |
59 | * Sets the backlight level. | |
60 | * | |
61 | * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). | |
62 | */ | |
63 | static void intel_lvds_set_backlight(struct drm_device *dev, int level) | |
64 | { | |
65 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 66 | u32 blc_pwm_ctl, reg; |
79e53945 | 67 | |
541998a1 ZW |
68 | if (IS_IGDNG(dev)) |
69 | reg = BLC_PWM_CPU_CTL; | |
70 | else | |
71 | reg = BLC_PWM_CTL; | |
79e53945 | 72 | |
541998a1 ZW |
73 | blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
74 | I915_WRITE(reg, (blc_pwm_ctl | | |
79e53945 JB |
75 | (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); |
76 | } | |
77 | ||
78 | /** | |
79 | * Returns the maximum level of the backlight duty cycle field. | |
80 | */ | |
81 | static u32 intel_lvds_get_max_backlight(struct drm_device *dev) | |
82 | { | |
83 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
84 | u32 reg; |
85 | ||
86 | if (IS_IGDNG(dev)) | |
87 | reg = BLC_PWM_PCH_CTL2; | |
88 | else | |
89 | reg = BLC_PWM_CTL; | |
79e53945 | 90 | |
541998a1 | 91 | return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >> |
79e53945 JB |
92 | BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; |
93 | } | |
94 | ||
95 | /** | |
96 | * Sets the power state for the panel. | |
97 | */ | |
98 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
99 | { | |
100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
101 | u32 pp_status, ctl_reg, status_reg; |
102 | ||
103 | if (IS_IGDNG(dev)) { | |
104 | ctl_reg = PCH_PP_CONTROL; | |
105 | status_reg = PCH_PP_STATUS; | |
106 | } else { | |
107 | ctl_reg = PP_CONTROL; | |
108 | status_reg = PP_STATUS; | |
109 | } | |
79e53945 JB |
110 | |
111 | if (on) { | |
541998a1 | 112 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | |
79e53945 JB |
113 | POWER_TARGET_ON); |
114 | do { | |
541998a1 | 115 | pp_status = I915_READ(status_reg); |
79e53945 JB |
116 | } while ((pp_status & PP_ON) == 0); |
117 | ||
118 | intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); | |
119 | } else { | |
120 | intel_lvds_set_backlight(dev, 0); | |
121 | ||
541998a1 | 122 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & |
79e53945 JB |
123 | ~POWER_TARGET_ON); |
124 | do { | |
541998a1 | 125 | pp_status = I915_READ(status_reg); |
79e53945 JB |
126 | } while (pp_status & PP_ON); |
127 | } | |
128 | } | |
129 | ||
130 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
131 | { | |
132 | struct drm_device *dev = encoder->dev; | |
133 | ||
134 | if (mode == DRM_MODE_DPMS_ON) | |
135 | intel_lvds_set_power(dev, true); | |
136 | else | |
137 | intel_lvds_set_power(dev, false); | |
138 | ||
139 | /* XXX: We never power down the LVDS pairs. */ | |
140 | } | |
141 | ||
142 | static void intel_lvds_save(struct drm_connector *connector) | |
143 | { | |
144 | struct drm_device *dev = connector->dev; | |
145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
146 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
147 | u32 pwm_ctl_reg; | |
148 | ||
149 | if (IS_IGDNG(dev)) { | |
150 | pp_on_reg = PCH_PP_ON_DELAYS; | |
151 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
152 | pp_ctl_reg = PCH_PP_CONTROL; | |
153 | pp_div_reg = PCH_PP_DIVISOR; | |
154 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
155 | } else { | |
156 | pp_on_reg = PP_ON_DELAYS; | |
157 | pp_off_reg = PP_OFF_DELAYS; | |
158 | pp_ctl_reg = PP_CONTROL; | |
159 | pp_div_reg = PP_DIVISOR; | |
160 | pwm_ctl_reg = BLC_PWM_CTL; | |
161 | } | |
79e53945 | 162 | |
541998a1 ZW |
163 | dev_priv->savePP_ON = I915_READ(pp_on_reg); |
164 | dev_priv->savePP_OFF = I915_READ(pp_off_reg); | |
165 | dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg); | |
166 | dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg); | |
167 | dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg); | |
79e53945 JB |
168 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
169 | BACKLIGHT_DUTY_CYCLE_MASK); | |
170 | ||
171 | /* | |
172 | * If the light is off at server startup, just make it full brightness | |
173 | */ | |
174 | if (dev_priv->backlight_duty_cycle == 0) | |
175 | dev_priv->backlight_duty_cycle = | |
176 | intel_lvds_get_max_backlight(dev); | |
177 | } | |
178 | ||
179 | static void intel_lvds_restore(struct drm_connector *connector) | |
180 | { | |
181 | struct drm_device *dev = connector->dev; | |
182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
183 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
184 | u32 pwm_ctl_reg; | |
185 | ||
186 | if (IS_IGDNG(dev)) { | |
187 | pp_on_reg = PCH_PP_ON_DELAYS; | |
188 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
189 | pp_ctl_reg = PCH_PP_CONTROL; | |
190 | pp_div_reg = PCH_PP_DIVISOR; | |
191 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
192 | } else { | |
193 | pp_on_reg = PP_ON_DELAYS; | |
194 | pp_off_reg = PP_OFF_DELAYS; | |
195 | pp_ctl_reg = PP_CONTROL; | |
196 | pp_div_reg = PP_DIVISOR; | |
197 | pwm_ctl_reg = BLC_PWM_CTL; | |
198 | } | |
79e53945 | 199 | |
541998a1 ZW |
200 | I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL); |
201 | I915_WRITE(pp_on_reg, dev_priv->savePP_ON); | |
202 | I915_WRITE(pp_off_reg, dev_priv->savePP_OFF); | |
203 | I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR); | |
204 | I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL); | |
79e53945 JB |
205 | if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) |
206 | intel_lvds_set_power(dev, true); | |
207 | else | |
208 | intel_lvds_set_power(dev, false); | |
209 | } | |
210 | ||
211 | static int intel_lvds_mode_valid(struct drm_connector *connector, | |
212 | struct drm_display_mode *mode) | |
213 | { | |
214 | struct drm_device *dev = connector->dev; | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
217 | ||
218 | if (fixed_mode) { | |
219 | if (mode->hdisplay > fixed_mode->hdisplay) | |
220 | return MODE_PANEL; | |
221 | if (mode->vdisplay > fixed_mode->vdisplay) | |
222 | return MODE_PANEL; | |
223 | } | |
224 | ||
225 | return MODE_OK; | |
226 | } | |
227 | ||
228 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |
229 | struct drm_display_mode *mode, | |
230 | struct drm_display_mode *adjusted_mode) | |
231 | { | |
3fbe18d6 ZY |
232 | /* |
233 | * float point operation is not supported . So the PANEL_RATIO_FACTOR | |
234 | * is defined, which can avoid the float point computation when | |
235 | * calculating the panel ratio. | |
236 | */ | |
237 | #define PANEL_RATIO_FACTOR 8192 | |
79e53945 JB |
238 | struct drm_device *dev = encoder->dev; |
239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
240 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
241 | struct drm_encoder *tmp_encoder; | |
3fbe18d6 ZY |
242 | struct intel_output *intel_output = enc_to_intel_output(encoder); |
243 | struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; | |
244 | u32 pfit_control = 0, pfit_pgm_ratios = 0; | |
245 | int left_border = 0, right_border = 0, top_border = 0; | |
246 | int bottom_border = 0; | |
247 | bool border = 0; | |
248 | int panel_ratio, desired_ratio, vert_scale, horiz_scale; | |
249 | int horiz_ratio, vert_ratio; | |
aa0261f2 ZY |
250 | u32 hsync_width, vsync_width; |
251 | u32 hblank_width, vblank_width; | |
252 | u32 hsync_pos, vsync_pos; | |
79e53945 JB |
253 | |
254 | /* Should never happen!! */ | |
255 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
1ae8c0a5 | 256 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
257 | return false; |
258 | } | |
259 | ||
260 | /* Should never happen!! */ | |
261 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
262 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 263 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
264 | "encoder on the same pipe\n"); |
265 | return false; | |
266 | } | |
267 | } | |
3fbe18d6 ZY |
268 | /* If we don't have a panel mode, there is nothing we can do */ |
269 | if (dev_priv->panel_fixed_mode == NULL) | |
270 | return true; | |
79e53945 JB |
271 | /* |
272 | * If we have timings from the BIOS for the panel, put them in | |
273 | * to the adjusted mode. The CRTC will be set up for this mode, | |
274 | * with the panel scaling set up to source from the H/VDisplay | |
275 | * of the original mode. | |
276 | */ | |
277 | if (dev_priv->panel_fixed_mode != NULL) { | |
278 | adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; | |
279 | adjusted_mode->hsync_start = | |
280 | dev_priv->panel_fixed_mode->hsync_start; | |
281 | adjusted_mode->hsync_end = | |
282 | dev_priv->panel_fixed_mode->hsync_end; | |
283 | adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; | |
284 | adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; | |
285 | adjusted_mode->vsync_start = | |
286 | dev_priv->panel_fixed_mode->vsync_start; | |
287 | adjusted_mode->vsync_end = | |
288 | dev_priv->panel_fixed_mode->vsync_end; | |
289 | adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; | |
290 | adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; | |
291 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
292 | } | |
293 | ||
3fbe18d6 ZY |
294 | /* Make sure pre-965s set dither correctly */ |
295 | if (!IS_I965G(dev)) { | |
296 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) | |
297 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
298 | } | |
299 | ||
300 | /* Native modes don't need fitting */ | |
301 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
302 | adjusted_mode->vdisplay == mode->vdisplay) { | |
303 | pfit_pgm_ratios = 0; | |
304 | border = 0; | |
305 | goto out; | |
306 | } | |
307 | ||
308 | /* 965+ wants fuzzy fitting */ | |
309 | if (IS_I965G(dev)) | |
310 | pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
311 | PFIT_FILTER_FUZZY; | |
312 | ||
aa0261f2 ZY |
313 | hsync_width = adjusted_mode->crtc_hsync_end - |
314 | adjusted_mode->crtc_hsync_start; | |
315 | vsync_width = adjusted_mode->crtc_vsync_end - | |
316 | adjusted_mode->crtc_vsync_start; | |
317 | hblank_width = adjusted_mode->crtc_hblank_end - | |
318 | adjusted_mode->crtc_hblank_start; | |
319 | vblank_width = adjusted_mode->crtc_vblank_end - | |
320 | adjusted_mode->crtc_vblank_start; | |
3fbe18d6 ZY |
321 | /* |
322 | * Deal with panel fitting options. Figure out how to stretch the | |
323 | * image based on its aspect ratio & the current panel fitting mode. | |
324 | */ | |
325 | panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR / | |
326 | adjusted_mode->vdisplay; | |
327 | desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR / | |
328 | mode->vdisplay; | |
329 | /* | |
330 | * Enable automatic panel scaling for non-native modes so that they fill | |
331 | * the screen. Should be enabled before the pipe is enabled, according | |
332 | * to register description and PRM. | |
333 | * Change the value here to see the borders for debugging | |
334 | */ | |
335 | I915_WRITE(BCLRPAT_A, 0); | |
336 | I915_WRITE(BCLRPAT_B, 0); | |
337 | ||
338 | switch (lvds_priv->fitting_mode) { | |
339 | case DRM_MODE_SCALE_NO_SCALE: | |
340 | /* | |
341 | * For centered modes, we have to calculate border widths & | |
342 | * heights and modify the values programmed into the CRTC. | |
343 | */ | |
344 | left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2; | |
345 | right_border = left_border; | |
346 | if (mode->hdisplay & 1) | |
347 | right_border++; | |
348 | top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2; | |
349 | bottom_border = top_border; | |
350 | if (mode->vdisplay & 1) | |
351 | bottom_border++; | |
352 | /* Set active & border values */ | |
353 | adjusted_mode->crtc_hdisplay = mode->hdisplay; | |
aa0261f2 ZY |
354 | /* Keep the boder be even */ |
355 | if (right_border & 1) | |
356 | right_border++; | |
357 | /* use the border directly instead of border minuse one */ | |
3fbe18d6 | 358 | adjusted_mode->crtc_hblank_start = mode->hdisplay + |
aa0261f2 ZY |
359 | right_border; |
360 | /* keep the blank width constant */ | |
361 | adjusted_mode->crtc_hblank_end = | |
362 | adjusted_mode->crtc_hblank_start + hblank_width; | |
363 | /* get the hsync pos relative to hblank start */ | |
364 | hsync_pos = (hblank_width - hsync_width) / 2; | |
365 | /* keep the hsync pos be even */ | |
366 | if (hsync_pos & 1) | |
367 | hsync_pos++; | |
3fbe18d6 | 368 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
369 | adjusted_mode->crtc_hblank_start + hsync_pos; |
370 | /* keep the hsync width constant */ | |
3fbe18d6 | 371 | adjusted_mode->crtc_hsync_end = |
aa0261f2 | 372 | adjusted_mode->crtc_hsync_start + hsync_width; |
3fbe18d6 | 373 | adjusted_mode->crtc_vdisplay = mode->vdisplay; |
aa0261f2 | 374 | /* use the border instead of border minus one */ |
3fbe18d6 | 375 | adjusted_mode->crtc_vblank_start = mode->vdisplay + |
aa0261f2 ZY |
376 | bottom_border; |
377 | /* keep the vblank width constant */ | |
378 | adjusted_mode->crtc_vblank_end = | |
379 | adjusted_mode->crtc_vblank_start + vblank_width; | |
380 | /* get the vsync start postion relative to vblank start */ | |
381 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 382 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
383 | adjusted_mode->crtc_vblank_start + vsync_pos; |
384 | /* keep the vsync width constant */ | |
3fbe18d6 | 385 | adjusted_mode->crtc_vsync_end = |
aa0261f2 | 386 | adjusted_mode->crtc_vblank_start + vsync_width; |
3fbe18d6 ZY |
387 | border = 1; |
388 | break; | |
389 | case DRM_MODE_SCALE_ASPECT: | |
390 | /* Scale but preserve the spect ratio */ | |
391 | pfit_control |= PFIT_ENABLE; | |
392 | if (IS_I965G(dev)) { | |
393 | /* 965+ is easy, it does everything in hw */ | |
394 | if (panel_ratio > desired_ratio) | |
395 | pfit_control |= PFIT_SCALING_PILLAR; | |
396 | else if (panel_ratio < desired_ratio) | |
397 | pfit_control |= PFIT_SCALING_LETTER; | |
398 | else | |
399 | pfit_control |= PFIT_SCALING_AUTO; | |
400 | } else { | |
401 | /* | |
402 | * For earlier chips we have to calculate the scaling | |
403 | * ratio by hand and program it into the | |
404 | * PFIT_PGM_RATIO register | |
405 | */ | |
406 | u32 horiz_bits, vert_bits, bits = 12; | |
407 | horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/ | |
408 | adjusted_mode->hdisplay; | |
409 | vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/ | |
410 | adjusted_mode->vdisplay; | |
411 | horiz_scale = adjusted_mode->hdisplay * | |
412 | PANEL_RATIO_FACTOR / mode->hdisplay; | |
413 | vert_scale = adjusted_mode->vdisplay * | |
414 | PANEL_RATIO_FACTOR / mode->vdisplay; | |
415 | ||
416 | /* retain aspect ratio */ | |
417 | if (panel_ratio > desired_ratio) { /* Pillar */ | |
418 | u32 scaled_width; | |
419 | scaled_width = mode->hdisplay * vert_scale / | |
420 | PANEL_RATIO_FACTOR; | |
421 | horiz_ratio = vert_ratio; | |
422 | pfit_control |= (VERT_AUTO_SCALE | | |
423 | VERT_INTERP_BILINEAR | | |
424 | HORIZ_INTERP_BILINEAR); | |
425 | /* Pillar will have left/right borders */ | |
426 | left_border = (adjusted_mode->hdisplay - | |
427 | scaled_width) / 2; | |
428 | right_border = left_border; | |
429 | if (mode->hdisplay & 1) /* odd resolutions */ | |
430 | right_border++; | |
aa0261f2 ZY |
431 | /* keep the border be even */ |
432 | if (right_border & 1) | |
433 | right_border++; | |
3fbe18d6 | 434 | adjusted_mode->crtc_hdisplay = scaled_width; |
aa0261f2 | 435 | /* use border instead of border minus one */ |
3fbe18d6 | 436 | adjusted_mode->crtc_hblank_start = |
aa0261f2 ZY |
437 | scaled_width + right_border; |
438 | /* keep the hblank width constant */ | |
3fbe18d6 | 439 | adjusted_mode->crtc_hblank_end = |
aa0261f2 ZY |
440 | adjusted_mode->crtc_hblank_start + |
441 | hblank_width; | |
442 | /* | |
443 | * get the hsync start pos relative to | |
444 | * hblank start | |
445 | */ | |
446 | hsync_pos = (hblank_width - hsync_width) / 2; | |
447 | /* keep the hsync_pos be even */ | |
448 | if (hsync_pos & 1) | |
449 | hsync_pos++; | |
3fbe18d6 | 450 | adjusted_mode->crtc_hsync_start = |
aa0261f2 ZY |
451 | adjusted_mode->crtc_hblank_start + |
452 | hsync_pos; | |
453 | /* keept hsync width constant */ | |
3fbe18d6 | 454 | adjusted_mode->crtc_hsync_end = |
aa0261f2 ZY |
455 | adjusted_mode->crtc_hsync_start + |
456 | hsync_width; | |
3fbe18d6 ZY |
457 | border = 1; |
458 | } else if (panel_ratio < desired_ratio) { /* letter */ | |
459 | u32 scaled_height = mode->vdisplay * | |
460 | horiz_scale / PANEL_RATIO_FACTOR; | |
461 | vert_ratio = horiz_ratio; | |
462 | pfit_control |= (HORIZ_AUTO_SCALE | | |
463 | VERT_INTERP_BILINEAR | | |
464 | HORIZ_INTERP_BILINEAR); | |
465 | /* Letterbox will have top/bottom border */ | |
466 | top_border = (adjusted_mode->vdisplay - | |
467 | scaled_height) / 2; | |
468 | bottom_border = top_border; | |
469 | if (mode->vdisplay & 1) | |
470 | bottom_border++; | |
471 | adjusted_mode->crtc_vdisplay = scaled_height; | |
aa0261f2 | 472 | /* use border instead of border minus one */ |
3fbe18d6 | 473 | adjusted_mode->crtc_vblank_start = |
aa0261f2 ZY |
474 | scaled_height + bottom_border; |
475 | /* keep the vblank width constant */ | |
3fbe18d6 | 476 | adjusted_mode->crtc_vblank_end = |
aa0261f2 ZY |
477 | adjusted_mode->crtc_vblank_start + |
478 | vblank_width; | |
479 | /* | |
480 | * get the vsync start pos relative to | |
481 | * vblank start | |
482 | */ | |
483 | vsync_pos = (vblank_width - vsync_width) / 2; | |
3fbe18d6 | 484 | adjusted_mode->crtc_vsync_start = |
aa0261f2 ZY |
485 | adjusted_mode->crtc_vblank_start + |
486 | vsync_pos; | |
487 | /* keep the vsync width constant */ | |
3fbe18d6 | 488 | adjusted_mode->crtc_vsync_end = |
aa0261f2 ZY |
489 | adjusted_mode->crtc_vsync_start + |
490 | vsync_width; | |
3fbe18d6 ZY |
491 | border = 1; |
492 | } else { | |
493 | /* Aspects match, Let hw scale both directions */ | |
494 | pfit_control |= (VERT_AUTO_SCALE | | |
495 | HORIZ_AUTO_SCALE | | |
496 | VERT_INTERP_BILINEAR | | |
497 | HORIZ_INTERP_BILINEAR); | |
498 | } | |
499 | horiz_bits = (1 << bits) * horiz_ratio / | |
500 | PANEL_RATIO_FACTOR; | |
501 | vert_bits = (1 << bits) * vert_ratio / | |
502 | PANEL_RATIO_FACTOR; | |
503 | pfit_pgm_ratios = | |
504 | ((vert_bits << PFIT_VERT_SCALE_SHIFT) & | |
505 | PFIT_VERT_SCALE_MASK) | | |
506 | ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) & | |
507 | PFIT_HORIZ_SCALE_MASK); | |
508 | } | |
509 | break; | |
510 | ||
511 | case DRM_MODE_SCALE_FULLSCREEN: | |
512 | /* | |
513 | * Full scaling, even if it changes the aspect ratio. | |
514 | * Fortunately this is all done for us in hw. | |
515 | */ | |
516 | pfit_control |= PFIT_ENABLE; | |
517 | if (IS_I965G(dev)) | |
518 | pfit_control |= PFIT_SCALING_AUTO; | |
519 | else | |
520 | pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
521 | VERT_INTERP_BILINEAR | | |
522 | HORIZ_INTERP_BILINEAR); | |
523 | break; | |
524 | default: | |
525 | break; | |
526 | } | |
527 | ||
528 | out: | |
529 | lvds_priv->pfit_control = pfit_control; | |
530 | lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; | |
79e53945 JB |
531 | /* |
532 | * XXX: It would be nice to support lower refresh rates on the | |
533 | * panels to reduce power consumption, and perhaps match the | |
534 | * user's requested refresh rate. | |
535 | */ | |
536 | ||
537 | return true; | |
538 | } | |
539 | ||
540 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
541 | { | |
542 | struct drm_device *dev = encoder->dev; | |
543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 544 | u32 reg; |
79e53945 | 545 | |
541998a1 ZW |
546 | if (IS_IGDNG(dev)) |
547 | reg = BLC_PWM_CPU_CTL; | |
548 | else | |
549 | reg = BLC_PWM_CTL; | |
79e53945 | 550 | |
541998a1 | 551 | dev_priv->saveBLC_PWM_CTL = I915_READ(reg); |
79e53945 JB |
552 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
553 | BACKLIGHT_DUTY_CYCLE_MASK); | |
554 | ||
555 | intel_lvds_set_power(dev, false); | |
556 | } | |
557 | ||
558 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
559 | { | |
560 | struct drm_device *dev = encoder->dev; | |
561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
562 | ||
563 | if (dev_priv->backlight_duty_cycle == 0) | |
564 | dev_priv->backlight_duty_cycle = | |
565 | intel_lvds_get_max_backlight(dev); | |
566 | ||
567 | intel_lvds_set_power(dev, true); | |
568 | } | |
569 | ||
570 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
571 | struct drm_display_mode *mode, | |
572 | struct drm_display_mode *adjusted_mode) | |
573 | { | |
574 | struct drm_device *dev = encoder->dev; | |
575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3fbe18d6 ZY |
576 | struct intel_output *intel_output = enc_to_intel_output(encoder); |
577 | struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; | |
79e53945 JB |
578 | |
579 | /* | |
580 | * The LVDS pin pair will already have been turned on in the | |
581 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
582 | * settings. | |
583 | */ | |
584 | ||
541998a1 ZW |
585 | /* No panel fitting yet, fixme */ |
586 | if (IS_IGDNG(dev)) | |
587 | return; | |
588 | ||
79e53945 JB |
589 | /* |
590 | * Enable automatic panel scaling so that non-native modes fill the | |
591 | * screen. Should be enabled before the pipe is enabled, according to | |
592 | * register description and PRM. | |
593 | */ | |
3fbe18d6 ZY |
594 | I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios); |
595 | I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); | |
79e53945 JB |
596 | } |
597 | ||
598 | /** | |
599 | * Detect the LVDS connection. | |
600 | * | |
601 | * This always returns CONNECTOR_STATUS_CONNECTED. This connector should only have | |
602 | * been set up if the LVDS was actually connected anyway. | |
603 | */ | |
604 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
605 | { | |
606 | return connector_status_connected; | |
607 | } | |
608 | ||
609 | /** | |
610 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
611 | */ | |
612 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
613 | { | |
614 | struct drm_device *dev = connector->dev; | |
615 | struct intel_output *intel_output = to_intel_output(connector); | |
616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
617 | int ret = 0; | |
618 | ||
619 | ret = intel_ddc_get_modes(intel_output); | |
620 | ||
621 | if (ret) | |
622 | return ret; | |
623 | ||
624 | /* Didn't get an EDID, so | |
625 | * Set wide sync ranges so we get all modes | |
626 | * handed to valid_mode for checking | |
627 | */ | |
628 | connector->display_info.min_vfreq = 0; | |
629 | connector->display_info.max_vfreq = 200; | |
630 | connector->display_info.min_hfreq = 0; | |
631 | connector->display_info.max_hfreq = 200; | |
632 | ||
633 | if (dev_priv->panel_fixed_mode != NULL) { | |
634 | struct drm_display_mode *mode; | |
635 | ||
79e53945 JB |
636 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
637 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
638 | |
639 | return 1; | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | /** | |
646 | * intel_lvds_destroy - unregister and free LVDS structures | |
647 | * @connector: connector to free | |
648 | * | |
649 | * Unregister the DDC bus for this connector then free the driver private | |
650 | * structure. | |
651 | */ | |
652 | static void intel_lvds_destroy(struct drm_connector *connector) | |
653 | { | |
654 | struct intel_output *intel_output = to_intel_output(connector); | |
655 | ||
656 | if (intel_output->ddc_bus) | |
657 | intel_i2c_destroy(intel_output->ddc_bus); | |
658 | drm_sysfs_connector_remove(connector); | |
659 | drm_connector_cleanup(connector); | |
660 | kfree(connector); | |
661 | } | |
662 | ||
335041ed JB |
663 | static int intel_lvds_set_property(struct drm_connector *connector, |
664 | struct drm_property *property, | |
665 | uint64_t value) | |
666 | { | |
3fbe18d6 ZY |
667 | struct drm_device *dev = connector->dev; |
668 | struct intel_output *intel_output = | |
669 | to_intel_output(connector); | |
670 | ||
671 | if (property == dev->mode_config.scaling_mode_property && | |
672 | connector->encoder) { | |
673 | struct drm_crtc *crtc = connector->encoder->crtc; | |
674 | struct intel_lvds_priv *lvds_priv = intel_output->dev_priv; | |
675 | if (value == DRM_MODE_SCALE_NON_GPU) { | |
676 | DRM_DEBUG_KMS(I915_LVDS, | |
677 | "non_GPU property is unsupported\n"); | |
678 | return 0; | |
679 | } | |
680 | if (lvds_priv->fitting_mode == value) { | |
681 | /* the LVDS scaling property is not changed */ | |
682 | return 0; | |
683 | } | |
684 | lvds_priv->fitting_mode = value; | |
685 | if (crtc && crtc->enabled) { | |
686 | /* | |
687 | * If the CRTC is enabled, the display will be changed | |
688 | * according to the new panel fitting mode. | |
689 | */ | |
690 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
691 | crtc->x, crtc->y, crtc->fb); | |
692 | } | |
693 | } | |
694 | ||
335041ed JB |
695 | return 0; |
696 | } | |
697 | ||
79e53945 JB |
698 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
699 | .dpms = intel_lvds_dpms, | |
700 | .mode_fixup = intel_lvds_mode_fixup, | |
701 | .prepare = intel_lvds_prepare, | |
702 | .mode_set = intel_lvds_mode_set, | |
703 | .commit = intel_lvds_commit, | |
704 | }; | |
705 | ||
706 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
707 | .get_modes = intel_lvds_get_modes, | |
708 | .mode_valid = intel_lvds_mode_valid, | |
709 | .best_encoder = intel_best_encoder, | |
710 | }; | |
711 | ||
712 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 713 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
714 | .save = intel_lvds_save, |
715 | .restore = intel_lvds_restore, | |
716 | .detect = intel_lvds_detect, | |
717 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 718 | .set_property = intel_lvds_set_property, |
79e53945 JB |
719 | .destroy = intel_lvds_destroy, |
720 | }; | |
721 | ||
722 | ||
723 | static void intel_lvds_enc_destroy(struct drm_encoder *encoder) | |
724 | { | |
725 | drm_encoder_cleanup(encoder); | |
726 | } | |
727 | ||
728 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
729 | .destroy = intel_lvds_enc_destroy, | |
730 | }; | |
731 | ||
425d244c JW |
732 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
733 | { | |
7fb85bfb | 734 | DRM_DEBUG_KMS(I915_LVDS, |
735 | "Skipping LVDS initialization for %s\n", id->ident); | |
425d244c JW |
736 | return 1; |
737 | } | |
79e53945 | 738 | |
425d244c | 739 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 740 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
741 | { |
742 | .callback = intel_no_lvds_dmi_callback, | |
743 | .ident = "Apple Mac Mini (Core series)", | |
744 | .matches = { | |
98acd46f | 745 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
746 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
747 | }, | |
748 | }, | |
749 | { | |
750 | .callback = intel_no_lvds_dmi_callback, | |
751 | .ident = "Apple Mac Mini (Core 2 series)", | |
752 | .matches = { | |
98acd46f | 753 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
754 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
755 | }, | |
756 | }, | |
757 | { | |
758 | .callback = intel_no_lvds_dmi_callback, | |
759 | .ident = "MSI IM-945GSE-A", | |
760 | .matches = { | |
761 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
762 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
763 | }, | |
764 | }, | |
765 | { | |
766 | .callback = intel_no_lvds_dmi_callback, | |
767 | .ident = "Dell Studio Hybrid", | |
768 | .matches = { | |
769 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
770 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
771 | }, | |
772 | }, | |
70aa96ca JW |
773 | { |
774 | .callback = intel_no_lvds_dmi_callback, | |
775 | .ident = "AOpen Mini PC", | |
776 | .matches = { | |
777 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
778 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
779 | }, | |
780 | }, | |
ed8c754b TV |
781 | { |
782 | .callback = intel_no_lvds_dmi_callback, | |
783 | .ident = "AOpen Mini PC MP915", | |
784 | .matches = { | |
785 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
786 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
787 | }, | |
788 | }, | |
fa0864b2 MC |
789 | { |
790 | .callback = intel_no_lvds_dmi_callback, | |
791 | .ident = "Aopen i945GTt-VFA", | |
792 | .matches = { | |
793 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
794 | }, | |
795 | }, | |
425d244c JW |
796 | |
797 | { } /* terminating entry */ | |
798 | }; | |
79e53945 | 799 | |
e99da35f ZY |
800 | #ifdef CONFIG_ACPI |
801 | /* | |
802 | * check_lid_device -- check whether @handle is an ACPI LID device. | |
803 | * @handle: ACPI device handle | |
804 | * @level : depth in the ACPI namespace tree | |
805 | * @context: the number of LID device when we find the device | |
806 | * @rv: a return value to fill if desired (Not use) | |
807 | */ | |
808 | static acpi_status | |
809 | check_lid_device(acpi_handle handle, u32 level, void *context, | |
810 | void **return_value) | |
811 | { | |
812 | struct acpi_device *acpi_dev; | |
813 | int *lid_present = context; | |
814 | ||
815 | acpi_dev = NULL; | |
816 | /* Get the acpi device for device handle */ | |
817 | if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) { | |
818 | /* If there is no ACPI device for handle, return */ | |
819 | return AE_OK; | |
820 | } | |
821 | ||
822 | if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7)) | |
823 | *lid_present = 1; | |
824 | ||
825 | return AE_OK; | |
826 | } | |
827 | ||
828 | /** | |
829 | * check whether there exists the ACPI LID device by enumerating the ACPI | |
830 | * device tree. | |
831 | */ | |
832 | static int intel_lid_present(void) | |
833 | { | |
834 | int lid_present = 0; | |
835 | ||
836 | if (acpi_disabled) { | |
837 | /* If ACPI is disabled, there is no ACPI device tree to | |
838 | * check, so assume the LID device would have been present. | |
839 | */ | |
840 | return 1; | |
841 | } | |
842 | ||
843 | acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, | |
844 | ACPI_UINT32_MAX, | |
845 | check_lid_device, &lid_present, NULL); | |
846 | ||
847 | return lid_present; | |
848 | } | |
849 | #else | |
850 | static int intel_lid_present(void) | |
851 | { | |
852 | /* In the absence of ACPI built in, assume that the LID device would | |
853 | * have been present. | |
854 | */ | |
855 | return 1; | |
856 | } | |
857 | #endif | |
858 | ||
79e53945 JB |
859 | /** |
860 | * intel_lvds_init - setup LVDS connectors on this device | |
861 | * @dev: drm device | |
862 | * | |
863 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
864 | * modes we can display on the LVDS panel (if present). | |
865 | */ | |
866 | void intel_lvds_init(struct drm_device *dev) | |
867 | { | |
868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
869 | struct intel_output *intel_output; | |
870 | struct drm_connector *connector; | |
871 | struct drm_encoder *encoder; | |
872 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
873 | struct drm_crtc *crtc; | |
3fbe18d6 | 874 | struct intel_lvds_priv *lvds_priv; |
79e53945 | 875 | u32 lvds; |
541998a1 | 876 | int pipe, gpio = GPIOC; |
79e53945 | 877 | |
425d244c JW |
878 | /* Skip init on machines we know falsely report LVDS */ |
879 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 880 | return; |
565dcd46 | 881 | |
e99da35f ZY |
882 | /* Assume that any device without an ACPI LID device also doesn't |
883 | * have an integrated LVDS. We would be better off parsing the BIOS | |
884 | * to get a reliable indicator, but that code isn't written yet. | |
885 | * | |
886 | * In the case of all-in-one desktops using LVDS that we've seen, | |
887 | * they're using SDVO LVDS. | |
888 | */ | |
889 | if (!intel_lid_present()) | |
890 | return; | |
891 | ||
541998a1 ZW |
892 | if (IS_IGDNG(dev)) { |
893 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) | |
894 | return; | |
32f9d658 ZW |
895 | if (dev_priv->edp_support) { |
896 | DRM_DEBUG("disable LVDS for eDP support\n"); | |
897 | return; | |
898 | } | |
541998a1 ZW |
899 | gpio = PCH_GPIOC; |
900 | } | |
901 | ||
3fbe18d6 ZY |
902 | intel_output = kzalloc(sizeof(struct intel_output) + |
903 | sizeof(struct intel_lvds_priv), GFP_KERNEL); | |
79e53945 JB |
904 | if (!intel_output) { |
905 | return; | |
906 | } | |
907 | ||
908 | connector = &intel_output->base; | |
909 | encoder = &intel_output->enc; | |
910 | drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs, | |
911 | DRM_MODE_CONNECTOR_LVDS); | |
912 | ||
913 | drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, | |
914 | DRM_MODE_ENCODER_LVDS); | |
915 | ||
916 | drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); | |
917 | intel_output->type = INTEL_OUTPUT_LVDS; | |
918 | ||
919 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); | |
920 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
921 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
922 | connector->interlace_allowed = false; | |
923 | connector->doublescan_allowed = false; | |
924 | ||
3fbe18d6 ZY |
925 | lvds_priv = (struct intel_lvds_priv *)(intel_output + 1); |
926 | intel_output->dev_priv = lvds_priv; | |
927 | /* create the scaling mode property */ | |
928 | drm_mode_create_scaling_mode_property(dev); | |
929 | /* | |
930 | * the initial panel fitting mode will be FULL_SCREEN. | |
931 | */ | |
79e53945 | 932 | |
3fbe18d6 ZY |
933 | drm_connector_attach_property(&intel_output->base, |
934 | dev->mode_config.scaling_mode_property, | |
935 | DRM_MODE_SCALE_FULLSCREEN); | |
936 | lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN; | |
79e53945 JB |
937 | /* |
938 | * LVDS discovery: | |
939 | * 1) check for EDID on DDC | |
940 | * 2) check for VBT data | |
941 | * 3) check to see if LVDS is already on | |
942 | * if none of the above, no panel | |
943 | * 4) make sure lid is open | |
944 | * if closed, act like it's not there for now | |
945 | */ | |
946 | ||
947 | /* Set up the DDC bus. */ | |
541998a1 | 948 | intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
79e53945 JB |
949 | if (!intel_output->ddc_bus) { |
950 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | |
951 | "failed.\n"); | |
952 | goto failed; | |
953 | } | |
954 | ||
955 | /* | |
956 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
957 | * preferred mode is the right one. | |
958 | */ | |
959 | intel_ddc_get_modes(intel_output); | |
960 | ||
961 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
962 | mutex_lock(&dev->mode_config.mutex); | |
963 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
964 | dev_priv->panel_fixed_mode = | |
965 | drm_mode_duplicate(dev, scan); | |
966 | mutex_unlock(&dev->mode_config.mutex); | |
565dcd46 | 967 | goto out; |
79e53945 JB |
968 | } |
969 | mutex_unlock(&dev->mode_config.mutex); | |
970 | } | |
971 | ||
972 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 973 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
974 | mutex_lock(&dev->mode_config.mutex); |
975 | dev_priv->panel_fixed_mode = | |
88631706 | 976 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 977 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
978 | if (dev_priv->panel_fixed_mode) { |
979 | dev_priv->panel_fixed_mode->type |= | |
980 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
981 | goto out; |
982 | } | |
79e53945 JB |
983 | } |
984 | ||
985 | /* | |
986 | * If we didn't get EDID, try checking if the panel is already turned | |
987 | * on. If so, assume that whatever is currently programmed is the | |
988 | * correct mode. | |
989 | */ | |
541998a1 ZW |
990 | |
991 | /* IGDNG: FIXME if still fail, not try pipe mode now */ | |
992 | if (IS_IGDNG(dev)) | |
993 | goto failed; | |
994 | ||
79e53945 JB |
995 | lvds = I915_READ(LVDS); |
996 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
997 | crtc = intel_get_crtc_from_pipe(dev, pipe); | |
998 | ||
999 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
1000 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
1001 | if (dev_priv->panel_fixed_mode) { | |
1002 | dev_priv->panel_fixed_mode->type |= | |
1003 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 1004 | goto out; |
79e53945 JB |
1005 | } |
1006 | } | |
1007 | ||
1008 | /* If we still don't have a mode after all that, give up. */ | |
1009 | if (!dev_priv->panel_fixed_mode) | |
1010 | goto failed; | |
1011 | ||
79e53945 | 1012 | out: |
541998a1 ZW |
1013 | if (IS_IGDNG(dev)) { |
1014 | u32 pwm; | |
1015 | /* make sure PWM is enabled */ | |
1016 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
1017 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
1018 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
1019 | ||
1020 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1021 | pwm |= PWM_PCH_ENABLE; | |
1022 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
1023 | } | |
79e53945 JB |
1024 | drm_sysfs_connector_add(connector); |
1025 | return; | |
1026 | ||
1027 | failed: | |
7fb85bfb | 1028 | DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n"); |
79e53945 JB |
1029 | if (intel_output->ddc_bus) |
1030 | intel_i2c_destroy(intel_output->ddc_bus); | |
1031 | drm_connector_cleanup(connector); | |
3fbe18d6 | 1032 | kfree(intel_output); |
79e53945 | 1033 | } |