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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
3fbe18d6 ZY |
46 | int fitting_mode; |
47 | u32 pfit_control; | |
48 | u32 pfit_pgm_ratios; | |
49 | }; | |
50 | ||
ea5b213a CW |
51 | static struct intel_lvds *enc_to_intel_lvds(struct drm_encoder *encoder) |
52 | { | |
4ef69c7a | 53 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
54 | } |
55 | ||
309b1e3a MG |
56 | static void intel_lvds_lock_panel(struct drm_device *dev, bool lock) |
57 | { | |
58 | struct drm_i915_private *dev_priv = dev->dev_private; | |
59 | ||
60 | if (lock) | |
61 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
62 | else | |
63 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
64 | } | |
65 | ||
79e53945 JB |
66 | /** |
67 | * Sets the power state for the panel. | |
68 | */ | |
69 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
70 | { | |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 72 | u32 ctl_reg, status_reg, lvds_reg; |
541998a1 | 73 | |
c619eed4 | 74 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
75 | ctl_reg = PCH_PP_CONTROL; |
76 | status_reg = PCH_PP_STATUS; | |
469d1296 | 77 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
78 | } else { |
79 | ctl_reg = PP_CONTROL; | |
80 | status_reg = PP_STATUS; | |
469d1296 | 81 | lvds_reg = LVDS; |
541998a1 | 82 | } |
79e53945 JB |
83 | |
84 | if (on) { | |
469d1296 | 85 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
77d07fd9 | 86 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
481b6af3 | 87 | if (wait_for(I915_READ(status_reg) & PP_ON, 1000)) |
913d8d11 | 88 | DRM_ERROR("timed out waiting to enable LVDS pipe"); |
79e53945 | 89 | |
a9573556 | 90 | intel_panel_set_backlight(dev, dev_priv->backlight_level); |
79e53945 | 91 | } else { |
a9573556 | 92 | intel_panel_set_backlight(dev, 0); |
79e53945 | 93 | |
77d07fd9 | 94 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
469d1296 JB |
95 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); |
96 | POSTING_READ(lvds_reg); | |
79e53945 JB |
97 | } |
98 | } | |
99 | ||
100 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
101 | { | |
102 | struct drm_device *dev = encoder->dev; | |
103 | ||
104 | if (mode == DRM_MODE_DPMS_ON) | |
105 | intel_lvds_set_power(dev, true); | |
106 | else | |
107 | intel_lvds_set_power(dev, false); | |
108 | ||
109 | /* XXX: We never power down the LVDS pairs. */ | |
110 | } | |
111 | ||
79e53945 JB |
112 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
113 | struct drm_display_mode *mode) | |
114 | { | |
115 | struct drm_device *dev = connector->dev; | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
118 | ||
119 | if (fixed_mode) { | |
120 | if (mode->hdisplay > fixed_mode->hdisplay) | |
121 | return MODE_PANEL; | |
122 | if (mode->vdisplay > fixed_mode->vdisplay) | |
123 | return MODE_PANEL; | |
124 | } | |
125 | ||
126 | return MODE_OK; | |
127 | } | |
128 | ||
49be663f CW |
129 | static void |
130 | centre_horizontally(struct drm_display_mode *mode, | |
131 | int width) | |
132 | { | |
133 | u32 border, sync_pos, blank_width, sync_width; | |
134 | ||
135 | /* keep the hsync and hblank widths constant */ | |
136 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
137 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
138 | sync_pos = (blank_width - sync_width + 1) / 2; | |
139 | ||
140 | border = (mode->hdisplay - width + 1) / 2; | |
141 | border += border & 1; /* make the border even */ | |
142 | ||
143 | mode->crtc_hdisplay = width; | |
144 | mode->crtc_hblank_start = width + border; | |
145 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
146 | ||
147 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
148 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
149 | } | |
150 | ||
151 | static void | |
152 | centre_vertically(struct drm_display_mode *mode, | |
153 | int height) | |
154 | { | |
155 | u32 border, sync_pos, blank_width, sync_width; | |
156 | ||
157 | /* keep the vsync and vblank widths constant */ | |
158 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
159 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
160 | sync_pos = (blank_width - sync_width + 1) / 2; | |
161 | ||
162 | border = (mode->vdisplay - height + 1) / 2; | |
163 | ||
164 | mode->crtc_vdisplay = height; | |
165 | mode->crtc_vblank_start = height + border; | |
166 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
167 | ||
168 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
169 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
170 | } | |
171 | ||
172 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
173 | { | |
174 | /* | |
175 | * Floating point operation is not supported. So the FACTOR | |
176 | * is defined, which can avoid the floating point computation | |
177 | * when calculating the panel ratio. | |
178 | */ | |
179 | #define ACCURACY 12 | |
180 | #define FACTOR (1 << ACCURACY) | |
181 | u32 ratio = source * FACTOR / target; | |
182 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
183 | } | |
184 | ||
79e53945 JB |
185 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
186 | struct drm_display_mode *mode, | |
187 | struct drm_display_mode *adjusted_mode) | |
188 | { | |
189 | struct drm_device *dev = encoder->dev; | |
190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
191 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
ea5b213a | 192 | struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); |
79e53945 | 193 | struct drm_encoder *tmp_encoder; |
49be663f | 194 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
79e53945 JB |
195 | |
196 | /* Should never happen!! */ | |
197 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
1ae8c0a5 | 198 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
199 | return false; |
200 | } | |
201 | ||
202 | /* Should never happen!! */ | |
203 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
204 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 205 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
206 | "encoder on the same pipe\n"); |
207 | return false; | |
208 | } | |
209 | } | |
3fbe18d6 ZY |
210 | /* If we don't have a panel mode, there is nothing we can do */ |
211 | if (dev_priv->panel_fixed_mode == NULL) | |
212 | return true; | |
1d8e1c75 | 213 | |
79e53945 | 214 | /* |
71677043 | 215 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
216 | * to the adjusted mode. The CRTC will be set up for this mode, |
217 | * with the panel scaling set up to source from the H/VDisplay | |
218 | * of the original mode. | |
219 | */ | |
1d8e1c75 CW |
220 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
221 | ||
222 | if (HAS_PCH_SPLIT(dev)) { | |
223 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
224 | mode, adjusted_mode); | |
225 | return true; | |
226 | } | |
79e53945 | 227 | |
3fbe18d6 ZY |
228 | /* Make sure pre-965s set dither correctly */ |
229 | if (!IS_I965G(dev)) { | |
230 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) | |
231 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
232 | } | |
233 | ||
234 | /* Native modes don't need fitting */ | |
235 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 236 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 237 | goto out; |
3fbe18d6 ZY |
238 | |
239 | /* 965+ wants fuzzy fitting */ | |
240 | if (IS_I965G(dev)) | |
49be663f CW |
241 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
242 | PFIT_FILTER_FUZZY); | |
243 | ||
3fbe18d6 ZY |
244 | /* |
245 | * Enable automatic panel scaling for non-native modes so that they fill | |
246 | * the screen. Should be enabled before the pipe is enabled, according | |
247 | * to register description and PRM. | |
248 | * Change the value here to see the borders for debugging | |
249 | */ | |
1d8e1c75 CW |
250 | I915_WRITE(BCLRPAT_A, 0); |
251 | I915_WRITE(BCLRPAT_B, 0); | |
3fbe18d6 | 252 | |
ea5b213a | 253 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 254 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
255 | /* |
256 | * For centered modes, we have to calculate border widths & | |
257 | * heights and modify the values programmed into the CRTC. | |
258 | */ | |
49be663f CW |
259 | centre_horizontally(adjusted_mode, mode->hdisplay); |
260 | centre_vertically(adjusted_mode, mode->vdisplay); | |
261 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 262 | break; |
49be663f | 263 | |
3fbe18d6 | 264 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 265 | /* Scale but preserve the aspect ratio */ |
3fbe18d6 | 266 | if (IS_I965G(dev)) { |
49be663f CW |
267 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
268 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
269 | ||
270 | pfit_control |= PFIT_ENABLE; | |
3fbe18d6 | 271 | /* 965+ is easy, it does everything in hw */ |
49be663f | 272 | if (scaled_width > scaled_height) |
3fbe18d6 | 273 | pfit_control |= PFIT_SCALING_PILLAR; |
49be663f | 274 | else if (scaled_width < scaled_height) |
3fbe18d6 ZY |
275 | pfit_control |= PFIT_SCALING_LETTER; |
276 | else | |
277 | pfit_control |= PFIT_SCALING_AUTO; | |
278 | } else { | |
49be663f CW |
279 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
280 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
281 | /* |
282 | * For earlier chips we have to calculate the scaling | |
283 | * ratio by hand and program it into the | |
284 | * PFIT_PGM_RATIO register | |
285 | */ | |
49be663f CW |
286 | if (scaled_width > scaled_height) { /* pillar */ |
287 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
288 | ||
289 | border = LVDS_BORDER_ENABLE; | |
290 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
291 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
292 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
293 | bits << PFIT_VERT_SCALE_SHIFT); | |
294 | pfit_control |= (PFIT_ENABLE | | |
295 | VERT_INTERP_BILINEAR | | |
296 | HORIZ_INTERP_BILINEAR); | |
297 | } | |
298 | } else if (scaled_width < scaled_height) { /* letter */ | |
299 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
300 | ||
301 | border = LVDS_BORDER_ENABLE; | |
302 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
303 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
304 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
305 | bits << PFIT_VERT_SCALE_SHIFT); | |
306 | pfit_control |= (PFIT_ENABLE | | |
307 | VERT_INTERP_BILINEAR | | |
308 | HORIZ_INTERP_BILINEAR); | |
309 | } | |
310 | } else | |
311 | /* Aspects match, Let hw scale both directions */ | |
312 | pfit_control |= (PFIT_ENABLE | | |
313 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
314 | VERT_INTERP_BILINEAR | |
315 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
316 | } |
317 | break; | |
318 | ||
319 | case DRM_MODE_SCALE_FULLSCREEN: | |
320 | /* | |
321 | * Full scaling, even if it changes the aspect ratio. | |
322 | * Fortunately this is all done for us in hw. | |
323 | */ | |
324 | pfit_control |= PFIT_ENABLE; | |
325 | if (IS_I965G(dev)) | |
326 | pfit_control |= PFIT_SCALING_AUTO; | |
327 | else | |
328 | pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
329 | VERT_INTERP_BILINEAR | | |
330 | HORIZ_INTERP_BILINEAR); | |
331 | break; | |
49be663f | 332 | |
3fbe18d6 ZY |
333 | default: |
334 | break; | |
335 | } | |
336 | ||
337 | out: | |
ea5b213a CW |
338 | intel_lvds->pfit_control = pfit_control; |
339 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
49be663f CW |
340 | dev_priv->lvds_border_bits = border; |
341 | ||
79e53945 JB |
342 | /* |
343 | * XXX: It would be nice to support lower refresh rates on the | |
344 | * panels to reduce power consumption, and perhaps match the | |
345 | * user's requested refresh rate. | |
346 | */ | |
347 | ||
348 | return true; | |
349 | } | |
350 | ||
351 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
352 | { | |
353 | struct drm_device *dev = encoder->dev; | |
354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
309b1e3a | 355 | struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); |
79e53945 | 356 | |
a9573556 | 357 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
79e53945 | 358 | |
309b1e3a MG |
359 | if (intel_lvds->pfit_control == I915_READ(PFIT_CONTROL)) |
360 | intel_lvds_lock_panel(dev, false); | |
361 | else | |
362 | intel_lvds_set_power(dev, false); | |
79e53945 JB |
363 | } |
364 | ||
365 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
366 | { | |
367 | struct drm_device *dev = encoder->dev; | |
368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369 | ||
a9573556 CW |
370 | if (dev_priv->backlight_level == 0) |
371 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); | |
79e53945 | 372 | |
309b1e3a MG |
373 | if ((I915_READ(PP_CONTROL) & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) |
374 | intel_lvds_lock_panel(dev, true); | |
375 | else | |
376 | intel_lvds_set_power(dev, true); | |
79e53945 JB |
377 | } |
378 | ||
379 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
380 | struct drm_display_mode *mode, | |
381 | struct drm_display_mode *adjusted_mode) | |
382 | { | |
383 | struct drm_device *dev = encoder->dev; | |
384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 385 | struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); |
79e53945 JB |
386 | |
387 | /* | |
388 | * The LVDS pin pair will already have been turned on in the | |
389 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
390 | * settings. | |
391 | */ | |
392 | ||
c619eed4 | 393 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
394 | return; |
395 | ||
79e53945 JB |
396 | /* |
397 | * Enable automatic panel scaling so that non-native modes fill the | |
398 | * screen. Should be enabled before the pipe is enabled, according to | |
399 | * register description and PRM. | |
400 | */ | |
ea5b213a CW |
401 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); |
402 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
79e53945 JB |
403 | } |
404 | ||
405 | /** | |
406 | * Detect the LVDS connection. | |
407 | * | |
b42d4c5c JB |
408 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
409 | * connected and closed means disconnected. We also send hotplug events as | |
410 | * needed, using lid status notification from the input layer. | |
79e53945 JB |
411 | */ |
412 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
413 | { | |
7b9c5abe | 414 | struct drm_device *dev = connector->dev; |
b42d4c5c JB |
415 | enum drm_connector_status status = connector_status_connected; |
416 | ||
7b9c5abe JB |
417 | /* ACPI lid methods were generally unreliable in this generation, so |
418 | * don't even bother. | |
419 | */ | |
6e6c8228 | 420 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
421 | return connector_status_connected; |
422 | ||
b42d4c5c | 423 | return status; |
79e53945 JB |
424 | } |
425 | ||
426 | /** | |
427 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
428 | */ | |
429 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
430 | { | |
431 | struct drm_device *dev = connector->dev; | |
79e53945 | 432 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 433 | |
bfac4d67 | 434 | if (dev_priv->lvds_edid_good) { |
df0e9248 CW |
435 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
436 | int ret = intel_ddc_get_modes(connector, encoder->ddc_bus); | |
bfac4d67 ZY |
437 | if (ret) |
438 | return ret; | |
439 | } | |
79e53945 JB |
440 | |
441 | /* Didn't get an EDID, so | |
442 | * Set wide sync ranges so we get all modes | |
443 | * handed to valid_mode for checking | |
444 | */ | |
445 | connector->display_info.min_vfreq = 0; | |
446 | connector->display_info.max_vfreq = 200; | |
447 | connector->display_info.min_hfreq = 0; | |
448 | connector->display_info.max_hfreq = 200; | |
449 | ||
450 | if (dev_priv->panel_fixed_mode != NULL) { | |
451 | struct drm_display_mode *mode; | |
452 | ||
79e53945 JB |
453 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
454 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
455 | |
456 | return 1; | |
457 | } | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
0544edfd TB |
462 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
463 | { | |
464 | DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); | |
465 | return 1; | |
466 | } | |
467 | ||
468 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
469 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
470 | { | |
471 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
472 | .ident = "Toshiba Tecra A11", | |
473 | .matches = { | |
474 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
475 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
476 | }, | |
477 | }, | |
478 | ||
479 | { } /* terminating entry */ | |
480 | }; | |
481 | ||
c9354c85 LT |
482 | /* |
483 | * Lid events. Note the use of 'modeset_on_lid': | |
484 | * - we set it on lid close, and reset it on open | |
485 | * - we use it as a "only once" bit (ie we ignore | |
486 | * duplicate events where it was already properly | |
487 | * set/reset) | |
488 | * - the suspend/resume paths will also set it to | |
489 | * zero, since they restore the mode ("lid open"). | |
490 | */ | |
c1c7af60 JB |
491 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
492 | void *unused) | |
493 | { | |
494 | struct drm_i915_private *dev_priv = | |
495 | container_of(nb, struct drm_i915_private, lid_notifier); | |
496 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 497 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 498 | |
a2565377 ZY |
499 | /* |
500 | * check and update the status of LVDS connector after receiving | |
501 | * the LID nofication event. | |
502 | */ | |
503 | if (connector) | |
504 | connector->status = connector->funcs->detect(connector); | |
0544edfd TB |
505 | /* Don't force modeset on machines where it causes a GPU lockup */ |
506 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
507 | return NOTIFY_OK; | |
c9354c85 LT |
508 | if (!acpi_lid_open()) { |
509 | dev_priv->modeset_on_lid = 1; | |
510 | return NOTIFY_OK; | |
06891e27 | 511 | } |
c1c7af60 | 512 | |
c9354c85 LT |
513 | if (!dev_priv->modeset_on_lid) |
514 | return NOTIFY_OK; | |
515 | ||
516 | dev_priv->modeset_on_lid = 0; | |
517 | ||
518 | mutex_lock(&dev->mode_config.mutex); | |
519 | drm_helper_resume_force_mode(dev); | |
520 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 521 | |
c1c7af60 JB |
522 | return NOTIFY_OK; |
523 | } | |
524 | ||
79e53945 JB |
525 | /** |
526 | * intel_lvds_destroy - unregister and free LVDS structures | |
527 | * @connector: connector to free | |
528 | * | |
529 | * Unregister the DDC bus for this connector then free the driver private | |
530 | * structure. | |
531 | */ | |
532 | static void intel_lvds_destroy(struct drm_connector *connector) | |
533 | { | |
c1c7af60 | 534 | struct drm_device *dev = connector->dev; |
c1c7af60 | 535 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 536 | |
c1c7af60 JB |
537 | if (dev_priv->lid_notifier.notifier_call) |
538 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
539 | drm_sysfs_connector_remove(connector); |
540 | drm_connector_cleanup(connector); | |
541 | kfree(connector); | |
542 | } | |
543 | ||
335041ed JB |
544 | static int intel_lvds_set_property(struct drm_connector *connector, |
545 | struct drm_property *property, | |
546 | uint64_t value) | |
547 | { | |
3fbe18d6 | 548 | struct drm_device *dev = connector->dev; |
3fbe18d6 ZY |
549 | |
550 | if (property == dev->mode_config.scaling_mode_property && | |
551 | connector->encoder) { | |
552 | struct drm_crtc *crtc = connector->encoder->crtc; | |
bb8a3560 | 553 | struct drm_encoder *encoder = connector->encoder; |
ea5b213a | 554 | struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder); |
bb8a3560 | 555 | |
53bd8389 JB |
556 | if (value == DRM_MODE_SCALE_NONE) { |
557 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3fbe18d6 ZY |
558 | return 0; |
559 | } | |
ea5b213a | 560 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
561 | /* the LVDS scaling property is not changed */ |
562 | return 0; | |
563 | } | |
ea5b213a | 564 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
565 | if (crtc && crtc->enabled) { |
566 | /* | |
567 | * If the CRTC is enabled, the display will be changed | |
568 | * according to the new panel fitting mode. | |
569 | */ | |
570 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
571 | crtc->x, crtc->y, crtc->fb); | |
572 | } | |
573 | } | |
574 | ||
335041ed JB |
575 | return 0; |
576 | } | |
577 | ||
79e53945 JB |
578 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
579 | .dpms = intel_lvds_dpms, | |
580 | .mode_fixup = intel_lvds_mode_fixup, | |
581 | .prepare = intel_lvds_prepare, | |
582 | .mode_set = intel_lvds_mode_set, | |
583 | .commit = intel_lvds_commit, | |
584 | }; | |
585 | ||
586 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
587 | .get_modes = intel_lvds_get_modes, | |
588 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 589 | .best_encoder = intel_best_encoder, |
79e53945 JB |
590 | }; |
591 | ||
592 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 593 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
594 | .detect = intel_lvds_detect, |
595 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 596 | .set_property = intel_lvds_set_property, |
79e53945 JB |
597 | .destroy = intel_lvds_destroy, |
598 | }; | |
599 | ||
79e53945 | 600 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 601 | .destroy = intel_encoder_destroy, |
79e53945 JB |
602 | }; |
603 | ||
425d244c JW |
604 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
605 | { | |
8a4c47f3 | 606 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
607 | return 1; |
608 | } | |
79e53945 | 609 | |
425d244c | 610 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 611 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
612 | { |
613 | .callback = intel_no_lvds_dmi_callback, | |
614 | .ident = "Apple Mac Mini (Core series)", | |
615 | .matches = { | |
98acd46f | 616 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
617 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
618 | }, | |
619 | }, | |
620 | { | |
621 | .callback = intel_no_lvds_dmi_callback, | |
622 | .ident = "Apple Mac Mini (Core 2 series)", | |
623 | .matches = { | |
98acd46f | 624 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
625 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
626 | }, | |
627 | }, | |
628 | { | |
629 | .callback = intel_no_lvds_dmi_callback, | |
630 | .ident = "MSI IM-945GSE-A", | |
631 | .matches = { | |
632 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
633 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
634 | }, | |
635 | }, | |
636 | { | |
637 | .callback = intel_no_lvds_dmi_callback, | |
638 | .ident = "Dell Studio Hybrid", | |
639 | .matches = { | |
640 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
641 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
642 | }, | |
643 | }, | |
70aa96ca JW |
644 | { |
645 | .callback = intel_no_lvds_dmi_callback, | |
646 | .ident = "AOpen Mini PC", | |
647 | .matches = { | |
648 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
649 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
650 | }, | |
651 | }, | |
ed8c754b TV |
652 | { |
653 | .callback = intel_no_lvds_dmi_callback, | |
654 | .ident = "AOpen Mini PC MP915", | |
655 | .matches = { | |
656 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
657 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
658 | }, | |
659 | }, | |
fa0864b2 MC |
660 | { |
661 | .callback = intel_no_lvds_dmi_callback, | |
662 | .ident = "Aopen i945GTt-VFA", | |
663 | .matches = { | |
664 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
665 | }, | |
666 | }, | |
9875557e SB |
667 | { |
668 | .callback = intel_no_lvds_dmi_callback, | |
669 | .ident = "Clientron U800", | |
670 | .matches = { | |
671 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
672 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
673 | }, | |
674 | }, | |
425d244c JW |
675 | |
676 | { } /* terminating entry */ | |
677 | }; | |
79e53945 | 678 | |
18f9ed12 ZY |
679 | /** |
680 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
681 | * @dev: drm device | |
682 | * @connector: LVDS connector | |
683 | * | |
684 | * Find the reduced downclock for LVDS in EDID. | |
685 | */ | |
686 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
687 | struct drm_connector *connector) | |
688 | { | |
689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
690 | struct drm_display_mode *scan, *panel_fixed_mode; | |
691 | int temp_downclock; | |
692 | ||
693 | panel_fixed_mode = dev_priv->panel_fixed_mode; | |
694 | temp_downclock = panel_fixed_mode->clock; | |
695 | ||
696 | mutex_lock(&dev->mode_config.mutex); | |
697 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
698 | /* | |
699 | * If one mode has the same resolution with the fixed_panel | |
700 | * mode while they have the different refresh rate, it means | |
701 | * that the reduced downclock is found for the LVDS. In such | |
702 | * case we can set the different FPx0/1 to dynamically select | |
703 | * between low and high frequency. | |
704 | */ | |
705 | if (scan->hdisplay == panel_fixed_mode->hdisplay && | |
706 | scan->hsync_start == panel_fixed_mode->hsync_start && | |
707 | scan->hsync_end == panel_fixed_mode->hsync_end && | |
708 | scan->htotal == panel_fixed_mode->htotal && | |
709 | scan->vdisplay == panel_fixed_mode->vdisplay && | |
710 | scan->vsync_start == panel_fixed_mode->vsync_start && | |
711 | scan->vsync_end == panel_fixed_mode->vsync_end && | |
712 | scan->vtotal == panel_fixed_mode->vtotal) { | |
713 | if (scan->clock < temp_downclock) { | |
714 | /* | |
715 | * The downclock is already found. But we | |
716 | * expect to find the lower downclock. | |
717 | */ | |
718 | temp_downclock = scan->clock; | |
719 | } | |
720 | } | |
721 | } | |
722 | mutex_unlock(&dev->mode_config.mutex); | |
33814341 JB |
723 | if (temp_downclock < panel_fixed_mode->clock && |
724 | i915_lvds_downclock) { | |
18f9ed12 ZY |
725 | /* We found the downclock for LVDS. */ |
726 | dev_priv->lvds_downclock_avail = 1; | |
727 | dev_priv->lvds_downclock = temp_downclock; | |
728 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
729 | "Normal clock %dKhz, downclock %dKhz\n", | |
730 | panel_fixed_mode->clock, temp_downclock); | |
731 | } | |
732 | return; | |
733 | } | |
734 | ||
7cf4f69d ZY |
735 | /* |
736 | * Enumerate the child dev array parsed from VBT to check whether | |
737 | * the LVDS is present. | |
738 | * If it is present, return 1. | |
739 | * If it is not present, return false. | |
740 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 741 | */ |
425904dd | 742 | static bool lvds_is_present_in_vbt(struct drm_device *dev) |
7cf4f69d ZY |
743 | { |
744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 745 | int i; |
7cf4f69d ZY |
746 | |
747 | if (!dev_priv->child_dev_num) | |
425904dd | 748 | return true; |
7cf4f69d | 749 | |
7cf4f69d | 750 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
751 | struct child_device_config *child = dev_priv->child_dev + i; |
752 | ||
753 | /* If the device type is not LFP, continue. | |
754 | * We have to check both the new identifiers as well as the | |
755 | * old for compatibility with some BIOSes. | |
7cf4f69d | 756 | */ |
425904dd CW |
757 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
758 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
759 | continue; |
760 | ||
425904dd CW |
761 | /* However, we cannot trust the BIOS writers to populate |
762 | * the VBT correctly. Since LVDS requires additional | |
763 | * information from AIM blocks, a non-zero addin offset is | |
764 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 765 | */ |
425904dd CW |
766 | if (child->addin_offset) |
767 | return true; | |
768 | ||
769 | /* But even then some BIOS writers perform some black magic | |
770 | * and instantiate the device without reference to any | |
771 | * additional data. Trust that if the VBT was written into | |
772 | * the OpRegion then they have validated the LVDS's existence. | |
773 | */ | |
774 | if (dev_priv->opregion.vbt) | |
775 | return true; | |
7cf4f69d | 776 | } |
425904dd CW |
777 | |
778 | return false; | |
7cf4f69d ZY |
779 | } |
780 | ||
79e53945 JB |
781 | /** |
782 | * intel_lvds_init - setup LVDS connectors on this device | |
783 | * @dev: drm device | |
784 | * | |
785 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
786 | * modes we can display on the LVDS panel (if present). | |
787 | */ | |
788 | void intel_lvds_init(struct drm_device *dev) | |
789 | { | |
790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 791 | struct intel_lvds *intel_lvds; |
21d40d37 | 792 | struct intel_encoder *intel_encoder; |
bb8a3560 | 793 | struct intel_connector *intel_connector; |
79e53945 JB |
794 | struct drm_connector *connector; |
795 | struct drm_encoder *encoder; | |
796 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
797 | struct drm_crtc *crtc; | |
798 | u32 lvds; | |
541998a1 | 799 | int pipe, gpio = GPIOC; |
79e53945 | 800 | |
425d244c JW |
801 | /* Skip init on machines we know falsely report LVDS */ |
802 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 803 | return; |
565dcd46 | 804 | |
11ba1592 MG |
805 | if (!lvds_is_present_in_vbt(dev)) { |
806 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); | |
e99da35f | 807 | return; |
38b3037e | 808 | } |
e99da35f | 809 | |
c619eed4 | 810 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
811 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
812 | return; | |
32f9d658 | 813 | if (dev_priv->edp_support) { |
28c97730 | 814 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
32f9d658 ZW |
815 | return; |
816 | } | |
541998a1 ZW |
817 | gpio = PCH_GPIOC; |
818 | } | |
819 | ||
ea5b213a CW |
820 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
821 | if (!intel_lvds) { | |
79e53945 JB |
822 | return; |
823 | } | |
824 | ||
bb8a3560 ZW |
825 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
826 | if (!intel_connector) { | |
ea5b213a | 827 | kfree(intel_lvds); |
bb8a3560 ZW |
828 | return; |
829 | } | |
830 | ||
ea5b213a | 831 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 832 | encoder = &intel_encoder->base; |
ea5b213a | 833 | connector = &intel_connector->base; |
bb8a3560 | 834 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
835 | DRM_MODE_CONNECTOR_LVDS); |
836 | ||
4ef69c7a | 837 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
838 | DRM_MODE_ENCODER_LVDS); |
839 | ||
df0e9248 | 840 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 841 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 842 | |
21d40d37 EA |
843 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
844 | intel_encoder->crtc_mask = (1 << 1); | |
79e53945 JB |
845 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
846 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
847 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
848 | connector->interlace_allowed = false; | |
849 | connector->doublescan_allowed = false; | |
850 | ||
3fbe18d6 ZY |
851 | /* create the scaling mode property */ |
852 | drm_mode_create_scaling_mode_property(dev); | |
853 | /* | |
854 | * the initial panel fitting mode will be FULL_SCREEN. | |
855 | */ | |
79e53945 | 856 | |
bb8a3560 | 857 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 858 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 859 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 860 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
861 | /* |
862 | * LVDS discovery: | |
863 | * 1) check for EDID on DDC | |
864 | * 2) check for VBT data | |
865 | * 3) check to see if LVDS is already on | |
866 | * if none of the above, no panel | |
867 | * 4) make sure lid is open | |
868 | * if closed, act like it's not there for now | |
869 | */ | |
870 | ||
871 | /* Set up the DDC bus. */ | |
21d40d37 EA |
872 | intel_encoder->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
873 | if (!intel_encoder->ddc_bus) { | |
79e53945 JB |
874 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " |
875 | "failed.\n"); | |
876 | goto failed; | |
877 | } | |
878 | ||
879 | /* | |
880 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
881 | * preferred mode is the right one. | |
882 | */ | |
bfac4d67 ZY |
883 | dev_priv->lvds_edid_good = true; |
884 | ||
335af9a2 | 885 | if (!intel_ddc_get_modes(connector, intel_encoder->ddc_bus)) |
bfac4d67 | 886 | dev_priv->lvds_edid_good = false; |
79e53945 JB |
887 | |
888 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
889 | mutex_lock(&dev->mode_config.mutex); | |
890 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
891 | dev_priv->panel_fixed_mode = | |
892 | drm_mode_duplicate(dev, scan); | |
893 | mutex_unlock(&dev->mode_config.mutex); | |
18f9ed12 | 894 | intel_find_lvds_downclock(dev, connector); |
565dcd46 | 895 | goto out; |
79e53945 JB |
896 | } |
897 | mutex_unlock(&dev->mode_config.mutex); | |
898 | } | |
899 | ||
900 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 901 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
902 | mutex_lock(&dev->mode_config.mutex); |
903 | dev_priv->panel_fixed_mode = | |
88631706 | 904 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 905 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
906 | if (dev_priv->panel_fixed_mode) { |
907 | dev_priv->panel_fixed_mode->type |= | |
908 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
909 | goto out; |
910 | } | |
79e53945 JB |
911 | } |
912 | ||
913 | /* | |
914 | * If we didn't get EDID, try checking if the panel is already turned | |
915 | * on. If so, assume that whatever is currently programmed is the | |
916 | * correct mode. | |
917 | */ | |
541998a1 | 918 | |
f2b115e6 | 919 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 920 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
921 | goto failed; |
922 | ||
79e53945 JB |
923 | lvds = I915_READ(LVDS); |
924 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 925 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
926 | |
927 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
928 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
929 | if (dev_priv->panel_fixed_mode) { | |
930 | dev_priv->panel_fixed_mode->type |= | |
931 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 932 | goto out; |
79e53945 JB |
933 | } |
934 | } | |
935 | ||
936 | /* If we still don't have a mode after all that, give up. */ | |
937 | if (!dev_priv->panel_fixed_mode) | |
938 | goto failed; | |
939 | ||
79e53945 | 940 | out: |
c619eed4 | 941 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 ZW |
942 | u32 pwm; |
943 | /* make sure PWM is enabled */ | |
944 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
945 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
946 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
947 | ||
948 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
949 | pwm |= PWM_PCH_ENABLE; | |
950 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
951 | } | |
c1c7af60 JB |
952 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
953 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 954 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
955 | dev_priv->lid_notifier.notifier_call = NULL; |
956 | } | |
a2565377 ZY |
957 | /* keep the LVDS connector */ |
958 | dev_priv->int_lvds_connector = connector; | |
79e53945 JB |
959 | drm_sysfs_connector_add(connector); |
960 | return; | |
961 | ||
962 | failed: | |
8a4c47f3 | 963 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
21d40d37 EA |
964 | if (intel_encoder->ddc_bus) |
965 | intel_i2c_destroy(intel_encoder->ddc_bus); | |
79e53945 | 966 | drm_connector_cleanup(connector); |
1991bdfa | 967 | drm_encoder_cleanup(encoder); |
ea5b213a | 968 | kfree(intel_lvds); |
bb8a3560 | 969 | kfree(intel_connector); |
79e53945 | 970 | } |