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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
565dcd46 | 30 | #include <linux/dmi.h> |
79e53945 JB |
31 | #include <linux/i2c.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
35 | #include "drm_edid.h" | |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
40 | /** | |
41 | * Sets the backlight level. | |
42 | * | |
43 | * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). | |
44 | */ | |
45 | static void intel_lvds_set_backlight(struct drm_device *dev, int level) | |
46 | { | |
47 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 48 | u32 blc_pwm_ctl, reg; |
79e53945 | 49 | |
541998a1 ZW |
50 | if (IS_IGDNG(dev)) |
51 | reg = BLC_PWM_CPU_CTL; | |
52 | else | |
53 | reg = BLC_PWM_CTL; | |
54 | ||
55 | blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
56 | I915_WRITE(reg, (blc_pwm_ctl | | |
79e53945 JB |
57 | (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); |
58 | } | |
59 | ||
60 | /** | |
61 | * Returns the maximum level of the backlight duty cycle field. | |
62 | */ | |
63 | static u32 intel_lvds_get_max_backlight(struct drm_device *dev) | |
64 | { | |
65 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
66 | u32 reg; |
67 | ||
68 | if (IS_IGDNG(dev)) | |
69 | reg = BLC_PWM_PCH_CTL2; | |
70 | else | |
71 | reg = BLC_PWM_CTL; | |
79e53945 | 72 | |
541998a1 | 73 | return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >> |
79e53945 JB |
74 | BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; |
75 | } | |
76 | ||
77 | /** | |
78 | * Sets the power state for the panel. | |
79 | */ | |
80 | static void intel_lvds_set_power(struct drm_device *dev, bool on) | |
81 | { | |
82 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
83 | u32 pp_status, ctl_reg, status_reg; |
84 | ||
85 | if (IS_IGDNG(dev)) { | |
86 | ctl_reg = PCH_PP_CONTROL; | |
87 | status_reg = PCH_PP_STATUS; | |
88 | } else { | |
89 | ctl_reg = PP_CONTROL; | |
90 | status_reg = PP_STATUS; | |
91 | } | |
79e53945 JB |
92 | |
93 | if (on) { | |
541998a1 | 94 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | |
79e53945 JB |
95 | POWER_TARGET_ON); |
96 | do { | |
541998a1 | 97 | pp_status = I915_READ(status_reg); |
79e53945 JB |
98 | } while ((pp_status & PP_ON) == 0); |
99 | ||
100 | intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); | |
101 | } else { | |
102 | intel_lvds_set_backlight(dev, 0); | |
103 | ||
541998a1 | 104 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & |
79e53945 JB |
105 | ~POWER_TARGET_ON); |
106 | do { | |
541998a1 | 107 | pp_status = I915_READ(status_reg); |
79e53945 JB |
108 | } while (pp_status & PP_ON); |
109 | } | |
110 | } | |
111 | ||
112 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
113 | { | |
114 | struct drm_device *dev = encoder->dev; | |
115 | ||
116 | if (mode == DRM_MODE_DPMS_ON) | |
117 | intel_lvds_set_power(dev, true); | |
118 | else | |
119 | intel_lvds_set_power(dev, false); | |
120 | ||
121 | /* XXX: We never power down the LVDS pairs. */ | |
122 | } | |
123 | ||
124 | static void intel_lvds_save(struct drm_connector *connector) | |
125 | { | |
126 | struct drm_device *dev = connector->dev; | |
127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
128 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
129 | u32 pwm_ctl_reg; | |
130 | ||
131 | if (IS_IGDNG(dev)) { | |
132 | pp_on_reg = PCH_PP_ON_DELAYS; | |
133 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
134 | pp_ctl_reg = PCH_PP_CONTROL; | |
135 | pp_div_reg = PCH_PP_DIVISOR; | |
136 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
137 | } else { | |
138 | pp_on_reg = PP_ON_DELAYS; | |
139 | pp_off_reg = PP_OFF_DELAYS; | |
140 | pp_ctl_reg = PP_CONTROL; | |
141 | pp_div_reg = PP_DIVISOR; | |
142 | pwm_ctl_reg = BLC_PWM_CTL; | |
143 | } | |
79e53945 | 144 | |
541998a1 ZW |
145 | dev_priv->savePP_ON = I915_READ(pp_on_reg); |
146 | dev_priv->savePP_OFF = I915_READ(pp_off_reg); | |
147 | dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg); | |
148 | dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg); | |
149 | dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg); | |
79e53945 JB |
150 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
151 | BACKLIGHT_DUTY_CYCLE_MASK); | |
152 | ||
153 | /* | |
154 | * If the light is off at server startup, just make it full brightness | |
155 | */ | |
156 | if (dev_priv->backlight_duty_cycle == 0) | |
157 | dev_priv->backlight_duty_cycle = | |
158 | intel_lvds_get_max_backlight(dev); | |
159 | } | |
160 | ||
161 | static void intel_lvds_restore(struct drm_connector *connector) | |
162 | { | |
163 | struct drm_device *dev = connector->dev; | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 ZW |
165 | u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg; |
166 | u32 pwm_ctl_reg; | |
167 | ||
168 | if (IS_IGDNG(dev)) { | |
169 | pp_on_reg = PCH_PP_ON_DELAYS; | |
170 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
171 | pp_ctl_reg = PCH_PP_CONTROL; | |
172 | pp_div_reg = PCH_PP_DIVISOR; | |
173 | pwm_ctl_reg = BLC_PWM_CPU_CTL; | |
174 | } else { | |
175 | pp_on_reg = PP_ON_DELAYS; | |
176 | pp_off_reg = PP_OFF_DELAYS; | |
177 | pp_ctl_reg = PP_CONTROL; | |
178 | pp_div_reg = PP_DIVISOR; | |
179 | pwm_ctl_reg = BLC_PWM_CTL; | |
180 | } | |
79e53945 | 181 | |
541998a1 ZW |
182 | I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL); |
183 | I915_WRITE(pp_on_reg, dev_priv->savePP_ON); | |
184 | I915_WRITE(pp_off_reg, dev_priv->savePP_OFF); | |
185 | I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR); | |
186 | I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL); | |
79e53945 JB |
187 | if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) |
188 | intel_lvds_set_power(dev, true); | |
189 | else | |
190 | intel_lvds_set_power(dev, false); | |
191 | } | |
192 | ||
193 | static int intel_lvds_mode_valid(struct drm_connector *connector, | |
194 | struct drm_display_mode *mode) | |
195 | { | |
196 | struct drm_device *dev = connector->dev; | |
197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
198 | struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; | |
199 | ||
200 | if (fixed_mode) { | |
201 | if (mode->hdisplay > fixed_mode->hdisplay) | |
202 | return MODE_PANEL; | |
203 | if (mode->vdisplay > fixed_mode->vdisplay) | |
204 | return MODE_PANEL; | |
205 | } | |
206 | ||
207 | return MODE_OK; | |
208 | } | |
209 | ||
210 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, | |
211 | struct drm_display_mode *mode, | |
212 | struct drm_display_mode *adjusted_mode) | |
213 | { | |
214 | struct drm_device *dev = encoder->dev; | |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
216 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
217 | struct drm_encoder *tmp_encoder; | |
218 | ||
219 | /* Should never happen!! */ | |
220 | if (!IS_I965G(dev) && intel_crtc->pipe == 0) { | |
221 | printk(KERN_ERR "Can't support LVDS on pipe A\n"); | |
222 | return false; | |
223 | } | |
224 | ||
225 | /* Should never happen!! */ | |
226 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
227 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
228 | printk(KERN_ERR "Can't enable LVDS and another " | |
229 | "encoder on the same pipe\n"); | |
230 | return false; | |
231 | } | |
232 | } | |
233 | ||
234 | /* | |
235 | * If we have timings from the BIOS for the panel, put them in | |
236 | * to the adjusted mode. The CRTC will be set up for this mode, | |
237 | * with the panel scaling set up to source from the H/VDisplay | |
238 | * of the original mode. | |
239 | */ | |
240 | if (dev_priv->panel_fixed_mode != NULL) { | |
241 | adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; | |
242 | adjusted_mode->hsync_start = | |
243 | dev_priv->panel_fixed_mode->hsync_start; | |
244 | adjusted_mode->hsync_end = | |
245 | dev_priv->panel_fixed_mode->hsync_end; | |
246 | adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; | |
247 | adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; | |
248 | adjusted_mode->vsync_start = | |
249 | dev_priv->panel_fixed_mode->vsync_start; | |
250 | adjusted_mode->vsync_end = | |
251 | dev_priv->panel_fixed_mode->vsync_end; | |
252 | adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal; | |
253 | adjusted_mode->clock = dev_priv->panel_fixed_mode->clock; | |
254 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); | |
255 | } | |
256 | ||
257 | /* | |
258 | * XXX: It would be nice to support lower refresh rates on the | |
259 | * panels to reduce power consumption, and perhaps match the | |
260 | * user's requested refresh rate. | |
261 | */ | |
262 | ||
263 | return true; | |
264 | } | |
265 | ||
266 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
267 | { | |
268 | struct drm_device *dev = encoder->dev; | |
269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
541998a1 | 270 | u32 reg; |
79e53945 | 271 | |
541998a1 ZW |
272 | if (IS_IGDNG(dev)) |
273 | reg = BLC_PWM_CPU_CTL; | |
274 | else | |
275 | reg = BLC_PWM_CTL; | |
276 | ||
277 | dev_priv->saveBLC_PWM_CTL = I915_READ(reg); | |
79e53945 JB |
278 | dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & |
279 | BACKLIGHT_DUTY_CYCLE_MASK); | |
280 | ||
281 | intel_lvds_set_power(dev, false); | |
282 | } | |
283 | ||
284 | static void intel_lvds_commit( struct drm_encoder *encoder) | |
285 | { | |
286 | struct drm_device *dev = encoder->dev; | |
287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
288 | ||
289 | if (dev_priv->backlight_duty_cycle == 0) | |
290 | dev_priv->backlight_duty_cycle = | |
291 | intel_lvds_get_max_backlight(dev); | |
292 | ||
293 | intel_lvds_set_power(dev, true); | |
294 | } | |
295 | ||
296 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
297 | struct drm_display_mode *mode, | |
298 | struct drm_display_mode *adjusted_mode) | |
299 | { | |
300 | struct drm_device *dev = encoder->dev; | |
301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
302 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
303 | u32 pfit_control; | |
304 | ||
305 | /* | |
306 | * The LVDS pin pair will already have been turned on in the | |
307 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
308 | * settings. | |
309 | */ | |
310 | ||
541998a1 ZW |
311 | /* No panel fitting yet, fixme */ |
312 | if (IS_IGDNG(dev)) | |
313 | return; | |
314 | ||
79e53945 JB |
315 | /* |
316 | * Enable automatic panel scaling so that non-native modes fill the | |
317 | * screen. Should be enabled before the pipe is enabled, according to | |
318 | * register description and PRM. | |
319 | */ | |
320 | if (mode->hdisplay != adjusted_mode->hdisplay || | |
321 | mode->vdisplay != adjusted_mode->vdisplay) | |
322 | pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | | |
323 | HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | | |
324 | HORIZ_INTERP_BILINEAR); | |
325 | else | |
326 | pfit_control = 0; | |
327 | ||
328 | if (!IS_I965G(dev)) { | |
2b5cde2b | 329 | if (dev_priv->panel_wants_dither || dev_priv->lvds_dither) |
79e53945 JB |
330 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
331 | } | |
332 | else | |
333 | pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT; | |
334 | ||
335 | I915_WRITE(PFIT_CONTROL, pfit_control); | |
336 | } | |
337 | ||
338 | /** | |
339 | * Detect the LVDS connection. | |
340 | * | |
341 | * This always returns CONNECTOR_STATUS_CONNECTED. This connector should only have | |
342 | * been set up if the LVDS was actually connected anyway. | |
343 | */ | |
344 | static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector) | |
345 | { | |
346 | return connector_status_connected; | |
347 | } | |
348 | ||
349 | /** | |
350 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
351 | */ | |
352 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
353 | { | |
354 | struct drm_device *dev = connector->dev; | |
355 | struct intel_output *intel_output = to_intel_output(connector); | |
356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
357 | int ret = 0; | |
358 | ||
359 | ret = intel_ddc_get_modes(intel_output); | |
360 | ||
361 | if (ret) | |
362 | return ret; | |
363 | ||
364 | /* Didn't get an EDID, so | |
365 | * Set wide sync ranges so we get all modes | |
366 | * handed to valid_mode for checking | |
367 | */ | |
368 | connector->display_info.min_vfreq = 0; | |
369 | connector->display_info.max_vfreq = 200; | |
370 | connector->display_info.min_hfreq = 0; | |
371 | connector->display_info.max_hfreq = 200; | |
372 | ||
373 | if (dev_priv->panel_fixed_mode != NULL) { | |
374 | struct drm_display_mode *mode; | |
375 | ||
79e53945 JB |
376 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); |
377 | drm_mode_probed_add(connector, mode); | |
79e53945 JB |
378 | |
379 | return 1; | |
380 | } | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
385 | /** | |
386 | * intel_lvds_destroy - unregister and free LVDS structures | |
387 | * @connector: connector to free | |
388 | * | |
389 | * Unregister the DDC bus for this connector then free the driver private | |
390 | * structure. | |
391 | */ | |
392 | static void intel_lvds_destroy(struct drm_connector *connector) | |
393 | { | |
394 | struct intel_output *intel_output = to_intel_output(connector); | |
395 | ||
396 | if (intel_output->ddc_bus) | |
397 | intel_i2c_destroy(intel_output->ddc_bus); | |
398 | drm_sysfs_connector_remove(connector); | |
399 | drm_connector_cleanup(connector); | |
400 | kfree(connector); | |
401 | } | |
402 | ||
335041ed JB |
403 | static int intel_lvds_set_property(struct drm_connector *connector, |
404 | struct drm_property *property, | |
405 | uint64_t value) | |
406 | { | |
407 | struct drm_device *dev = connector->dev; | |
408 | ||
409 | if (property == dev->mode_config.dpms_property && connector->encoder) | |
410 | intel_lvds_dpms(connector->encoder, (uint32_t)(value & 0xf)); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
79e53945 JB |
415 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
416 | .dpms = intel_lvds_dpms, | |
417 | .mode_fixup = intel_lvds_mode_fixup, | |
418 | .prepare = intel_lvds_prepare, | |
419 | .mode_set = intel_lvds_mode_set, | |
420 | .commit = intel_lvds_commit, | |
421 | }; | |
422 | ||
423 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
424 | .get_modes = intel_lvds_get_modes, | |
425 | .mode_valid = intel_lvds_mode_valid, | |
426 | .best_encoder = intel_best_encoder, | |
427 | }; | |
428 | ||
429 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
430 | .save = intel_lvds_save, | |
431 | .restore = intel_lvds_restore, | |
432 | .detect = intel_lvds_detect, | |
433 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 434 | .set_property = intel_lvds_set_property, |
79e53945 JB |
435 | .destroy = intel_lvds_destroy, |
436 | }; | |
437 | ||
438 | ||
439 | static void intel_lvds_enc_destroy(struct drm_encoder *encoder) | |
440 | { | |
441 | drm_encoder_cleanup(encoder); | |
442 | } | |
443 | ||
444 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { | |
445 | .destroy = intel_lvds_enc_destroy, | |
446 | }; | |
447 | ||
425d244c JW |
448 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
449 | { | |
450 | DRM_DEBUG("Skipping LVDS initialization for %s\n", id->ident); | |
451 | return 1; | |
452 | } | |
79e53945 | 453 | |
425d244c JW |
454 | /* These systems claim to have LVDS, but really don't */ |
455 | static const struct dmi_system_id __initdata intel_no_lvds[] = { | |
456 | { | |
457 | .callback = intel_no_lvds_dmi_callback, | |
458 | .ident = "Apple Mac Mini (Core series)", | |
459 | .matches = { | |
460 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
461 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), | |
462 | }, | |
463 | }, | |
464 | { | |
465 | .callback = intel_no_lvds_dmi_callback, | |
466 | .ident = "Apple Mac Mini (Core 2 series)", | |
467 | .matches = { | |
468 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
469 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), | |
470 | }, | |
471 | }, | |
472 | { | |
473 | .callback = intel_no_lvds_dmi_callback, | |
474 | .ident = "MSI IM-945GSE-A", | |
475 | .matches = { | |
476 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
477 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
478 | }, | |
479 | }, | |
480 | { | |
481 | .callback = intel_no_lvds_dmi_callback, | |
482 | .ident = "Dell Studio Hybrid", | |
483 | .matches = { | |
484 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
485 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
486 | }, | |
487 | }, | |
70aa96ca JW |
488 | { |
489 | .callback = intel_no_lvds_dmi_callback, | |
490 | .ident = "AOpen Mini PC", | |
491 | .matches = { | |
492 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
493 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
494 | }, | |
495 | }, | |
425d244c JW |
496 | |
497 | { } /* terminating entry */ | |
498 | }; | |
79e53945 JB |
499 | |
500 | /** | |
501 | * intel_lvds_init - setup LVDS connectors on this device | |
502 | * @dev: drm device | |
503 | * | |
504 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
505 | * modes we can display on the LVDS panel (if present). | |
506 | */ | |
507 | void intel_lvds_init(struct drm_device *dev) | |
508 | { | |
509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
510 | struct intel_output *intel_output; | |
511 | struct drm_connector *connector; | |
512 | struct drm_encoder *encoder; | |
513 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
514 | struct drm_crtc *crtc; | |
515 | u32 lvds; | |
541998a1 | 516 | int pipe, gpio = GPIOC; |
79e53945 | 517 | |
425d244c JW |
518 | /* Skip init on machines we know falsely report LVDS */ |
519 | if (dmi_check_system(intel_no_lvds)) | |
565dcd46 | 520 | return; |
565dcd46 | 521 | |
541998a1 ZW |
522 | if (IS_IGDNG(dev)) { |
523 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) | |
524 | return; | |
525 | gpio = PCH_GPIOC; | |
526 | } | |
527 | ||
79e53945 JB |
528 | intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); |
529 | if (!intel_output) { | |
530 | return; | |
531 | } | |
532 | ||
533 | connector = &intel_output->base; | |
534 | encoder = &intel_output->enc; | |
535 | drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs, | |
536 | DRM_MODE_CONNECTOR_LVDS); | |
537 | ||
538 | drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, | |
539 | DRM_MODE_ENCODER_LVDS); | |
540 | ||
541 | drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc); | |
542 | intel_output->type = INTEL_OUTPUT_LVDS; | |
543 | ||
544 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); | |
545 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
546 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
547 | connector->interlace_allowed = false; | |
548 | connector->doublescan_allowed = false; | |
549 | ||
550 | ||
551 | /* | |
552 | * LVDS discovery: | |
553 | * 1) check for EDID on DDC | |
554 | * 2) check for VBT data | |
555 | * 3) check to see if LVDS is already on | |
556 | * if none of the above, no panel | |
557 | * 4) make sure lid is open | |
558 | * if closed, act like it's not there for now | |
559 | */ | |
560 | ||
561 | /* Set up the DDC bus. */ | |
541998a1 | 562 | intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C"); |
79e53945 JB |
563 | if (!intel_output->ddc_bus) { |
564 | dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " | |
565 | "failed.\n"); | |
566 | goto failed; | |
567 | } | |
568 | ||
569 | /* | |
570 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
571 | * preferred mode is the right one. | |
572 | */ | |
573 | intel_ddc_get_modes(intel_output); | |
574 | ||
575 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
576 | mutex_lock(&dev->mode_config.mutex); | |
577 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { | |
578 | dev_priv->panel_fixed_mode = | |
579 | drm_mode_duplicate(dev, scan); | |
580 | mutex_unlock(&dev->mode_config.mutex); | |
565dcd46 | 581 | goto out; |
79e53945 JB |
582 | } |
583 | mutex_unlock(&dev->mode_config.mutex); | |
584 | } | |
585 | ||
586 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 587 | if (dev_priv->lfp_lvds_vbt_mode) { |
79e53945 JB |
588 | mutex_lock(&dev->mode_config.mutex); |
589 | dev_priv->panel_fixed_mode = | |
88631706 | 590 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
79e53945 | 591 | mutex_unlock(&dev->mode_config.mutex); |
e285f3cd JB |
592 | if (dev_priv->panel_fixed_mode) { |
593 | dev_priv->panel_fixed_mode->type |= | |
594 | DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
595 | goto out; |
596 | } | |
79e53945 JB |
597 | } |
598 | ||
599 | /* | |
600 | * If we didn't get EDID, try checking if the panel is already turned | |
601 | * on. If so, assume that whatever is currently programmed is the | |
602 | * correct mode. | |
603 | */ | |
541998a1 ZW |
604 | |
605 | /* IGDNG: FIXME if still fail, not try pipe mode now */ | |
606 | if (IS_IGDNG(dev)) | |
607 | goto failed; | |
608 | ||
79e53945 JB |
609 | lvds = I915_READ(LVDS); |
610 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
611 | crtc = intel_get_crtc_from_pipe(dev, pipe); | |
612 | ||
613 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
614 | dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc); | |
615 | if (dev_priv->panel_fixed_mode) { | |
616 | dev_priv->panel_fixed_mode->type |= | |
617 | DRM_MODE_TYPE_PREFERRED; | |
565dcd46 | 618 | goto out; |
79e53945 JB |
619 | } |
620 | } | |
621 | ||
622 | /* If we still don't have a mode after all that, give up. */ | |
623 | if (!dev_priv->panel_fixed_mode) | |
624 | goto failed; | |
625 | ||
79e53945 | 626 | out: |
541998a1 ZW |
627 | if (IS_IGDNG(dev)) { |
628 | u32 pwm; | |
629 | /* make sure PWM is enabled */ | |
630 | pwm = I915_READ(BLC_PWM_CPU_CTL2); | |
631 | pwm |= (PWM_ENABLE | PWM_PIPE_B); | |
632 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm); | |
633 | ||
634 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
635 | pwm |= PWM_PCH_ENABLE; | |
636 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
637 | } | |
79e53945 JB |
638 | drm_sysfs_connector_add(connector); |
639 | return; | |
640 | ||
641 | failed: | |
642 | DRM_DEBUG("No LVDS modes found, disabling.\n"); | |
643 | if (intel_output->ddc_bus) | |
644 | intel_i2c_destroy(intel_output->ddc_bus); | |
645 | drm_connector_cleanup(connector); | |
646 | kfree(connector); | |
647 | } |