Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
79e53945
JB
34#include "drmP.h"
35#include "drm.h"
36#include "drm_crtc.h"
37#include "drm_edid.h"
38#include "intel_drv.h"
39#include "i915_drm.h"
40#include "i915_drv.h"
e99da35f 41#include <linux/acpi.h>
79e53945 42
3fbe18d6 43/* Private structure for the integrated LVDS support */
ea5b213a
CW
44struct intel_lvds {
45 struct intel_encoder base;
788319d4 46
219adae1 47 struct edid *edid;
788319d4 48
3fbe18d6
ZY
49 int fitting_mode;
50 u32 pfit_control;
51 u32 pfit_pgm_ratios;
e9e331a8 52 bool pfit_dirty;
788319d4
CW
53
54 struct drm_display_mode *fixed_mode;
3fbe18d6
ZY
55};
56
788319d4 57static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder)
ea5b213a 58{
4ef69c7a 59 return container_of(encoder, struct intel_lvds, base.base);
ea5b213a
CW
60}
61
788319d4
CW
62static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
63{
64 return container_of(intel_attached_encoder(connector),
65 struct intel_lvds, base);
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 u32 lvds_reg, tmp;
74
75 if (HAS_PCH_SPLIT(dev)) {
76 lvds_reg = PCH_LVDS;
77 } else {
78 lvds_reg = LVDS;
79 }
80
81 tmp = I915_READ(lvds_reg);
82
83 if (!(tmp & LVDS_PORT_EN))
84 return false;
85
86 if (HAS_PCH_CPT(dev))
87 *pipe = PORT_TO_PIPE_CPT(tmp);
88 else
89 *pipe = PORT_TO_PIPE(tmp);
90
91 return true;
92}
93
79e53945
JB
94/**
95 * Sets the power state for the panel.
96 */
c22834ec 97static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 98{
c22834ec
DV
99 struct drm_device *dev = encoder->base.dev;
100 struct intel_lvds *intel_lvds = to_intel_lvds(&encoder->base);
101 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 102 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 103 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 104
c619eed4 105 if (HAS_PCH_SPLIT(dev)) {
541998a1 106 ctl_reg = PCH_PP_CONTROL;
469d1296 107 lvds_reg = PCH_LVDS;
de842eff 108 stat_reg = PCH_PP_STATUS;
541998a1
ZW
109 } else {
110 ctl_reg = PP_CONTROL;
469d1296 111 lvds_reg = LVDS;
de842eff 112 stat_reg = PP_STATUS;
541998a1 113 }
79e53945 114
2a1292fd 115 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 116
2a1292fd
CW
117 if (intel_lvds->pfit_dirty) {
118 /*
119 * Enable automatic panel scaling so that non-native modes
120 * fill the screen. The panel fitter should only be
121 * adjusted whilst the pipe is disabled, according to
122 * register description and PRM.
123 */
124 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
125 intel_lvds->pfit_control,
126 intel_lvds->pfit_pgm_ratios);
de842eff
KP
127
128 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
129 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
130 intel_lvds->pfit_dirty = false;
2a1292fd
CW
131 }
132
133 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
134 POSTING_READ(lvds_reg);
de842eff
KP
135 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
136 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 137
24ded204 138 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
139}
140
c22834ec 141static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 142{
c22834ec
DV
143 struct drm_device *dev = encoder->base.dev;
144 struct intel_lvds *intel_lvds = to_intel_lvds(&encoder->base);
2a1292fd 145 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 146 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
147
148 if (HAS_PCH_SPLIT(dev)) {
149 ctl_reg = PCH_PP_CONTROL;
150 lvds_reg = PCH_LVDS;
de842eff 151 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
152 } else {
153 ctl_reg = PP_CONTROL;
154 lvds_reg = LVDS;
de842eff 155 stat_reg = PP_STATUS;
2a1292fd
CW
156 }
157
47356eb6 158 intel_panel_disable_backlight(dev);
2a1292fd
CW
159
160 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
161 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
162 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd
CW
163
164 if (intel_lvds->pfit_control) {
2a1292fd
CW
165 I915_WRITE(PFIT_CONTROL, 0);
166 intel_lvds->pfit_dirty = true;
79e53945 167 }
2a1292fd
CW
168
169 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 170 POSTING_READ(lvds_reg);
79e53945
JB
171}
172
79e53945
JB
173static int intel_lvds_mode_valid(struct drm_connector *connector,
174 struct drm_display_mode *mode)
175{
788319d4
CW
176 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
177 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode;
79e53945 178
788319d4
CW
179 if (mode->hdisplay > fixed_mode->hdisplay)
180 return MODE_PANEL;
181 if (mode->vdisplay > fixed_mode->vdisplay)
182 return MODE_PANEL;
79e53945
JB
183
184 return MODE_OK;
185}
186
49be663f
CW
187static void
188centre_horizontally(struct drm_display_mode *mode,
189 int width)
190{
191 u32 border, sync_pos, blank_width, sync_width;
192
193 /* keep the hsync and hblank widths constant */
194 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
195 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
196 sync_pos = (blank_width - sync_width + 1) / 2;
197
198 border = (mode->hdisplay - width + 1) / 2;
199 border += border & 1; /* make the border even */
200
201 mode->crtc_hdisplay = width;
202 mode->crtc_hblank_start = width + border;
203 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
204
205 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
206 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
207
208 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
209}
210
211static void
212centre_vertically(struct drm_display_mode *mode,
213 int height)
214{
215 u32 border, sync_pos, blank_width, sync_width;
216
217 /* keep the vsync and vblank widths constant */
218 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
219 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
220 sync_pos = (blank_width - sync_width + 1) / 2;
221
222 border = (mode->vdisplay - height + 1) / 2;
223
224 mode->crtc_vdisplay = height;
225 mode->crtc_vblank_start = height + border;
226 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
227
228 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
229 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
230
231 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
232}
233
234static inline u32 panel_fitter_scaling(u32 source, u32 target)
235{
236 /*
237 * Floating point operation is not supported. So the FACTOR
238 * is defined, which can avoid the floating point computation
239 * when calculating the panel ratio.
240 */
241#define ACCURACY 12
242#define FACTOR (1 << ACCURACY)
243 u32 ratio = source * FACTOR / target;
244 return (FACTOR * ratio + FACTOR/2) / FACTOR;
245}
246
79e53945 247static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 248 const struct drm_display_mode *mode,
79e53945
JB
249 struct drm_display_mode *adjusted_mode)
250{
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 253 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
e24c5c29 254 struct intel_crtc *intel_crtc = intel_lvds->base.new_crtc;
49be663f 255 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 256 int pipe;
79e53945
JB
257
258 /* Should never happen!! */
a6c45cf0 259 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 260 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
261 return false;
262 }
263
e24c5c29
DV
264 if (intel_encoder_check_is_cloned(&intel_lvds->base))
265 return false;
1d8e1c75 266
79e53945 267 /*
71677043 268 * We have timings from the BIOS for the panel, put them in
79e53945
JB
269 * to the adjusted mode. The CRTC will be set up for this mode,
270 * with the panel scaling set up to source from the H/VDisplay
271 * of the original mode.
272 */
788319d4 273 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
1d8e1c75
CW
274
275 if (HAS_PCH_SPLIT(dev)) {
276 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
277 mode, adjusted_mode);
278 return true;
279 }
79e53945 280
3fbe18d6
ZY
281 /* Native modes don't need fitting */
282 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 283 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 284 goto out;
3fbe18d6
ZY
285
286 /* 965+ wants fuzzy fitting */
a6c45cf0 287 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
288 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
289 PFIT_FILTER_FUZZY);
290
3fbe18d6
ZY
291 /*
292 * Enable automatic panel scaling for non-native modes so that they fill
293 * the screen. Should be enabled before the pipe is enabled, according
294 * to register description and PRM.
295 * Change the value here to see the borders for debugging
296 */
9db4a9c7
JB
297 for_each_pipe(pipe)
298 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 299
f9bef081
DV
300 drm_mode_set_crtcinfo(adjusted_mode, 0);
301
ea5b213a 302 switch (intel_lvds->fitting_mode) {
53bd8389 303 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
304 /*
305 * For centered modes, we have to calculate border widths &
306 * heights and modify the values programmed into the CRTC.
307 */
49be663f
CW
308 centre_horizontally(adjusted_mode, mode->hdisplay);
309 centre_vertically(adjusted_mode, mode->vdisplay);
310 border = LVDS_BORDER_ENABLE;
3fbe18d6 311 break;
49be663f 312
3fbe18d6 313 case DRM_MODE_SCALE_ASPECT:
49be663f 314 /* Scale but preserve the aspect ratio */
a6c45cf0 315 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
316 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
317 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
318
3fbe18d6 319 /* 965+ is easy, it does everything in hw */
49be663f 320 if (scaled_width > scaled_height)
257e48f1 321 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 322 else if (scaled_width < scaled_height)
257e48f1
CW
323 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
324 else if (adjusted_mode->hdisplay != mode->hdisplay)
325 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 326 } else {
49be663f
CW
327 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
328 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
329 /*
330 * For earlier chips we have to calculate the scaling
331 * ratio by hand and program it into the
332 * PFIT_PGM_RATIO register
333 */
49be663f
CW
334 if (scaled_width > scaled_height) { /* pillar */
335 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
336
337 border = LVDS_BORDER_ENABLE;
338 if (mode->vdisplay != adjusted_mode->vdisplay) {
339 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
340 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
341 bits << PFIT_VERT_SCALE_SHIFT);
342 pfit_control |= (PFIT_ENABLE |
343 VERT_INTERP_BILINEAR |
344 HORIZ_INTERP_BILINEAR);
345 }
346 } else if (scaled_width < scaled_height) { /* letter */
347 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
348
349 border = LVDS_BORDER_ENABLE;
350 if (mode->hdisplay != adjusted_mode->hdisplay) {
351 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
352 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
353 bits << PFIT_VERT_SCALE_SHIFT);
354 pfit_control |= (PFIT_ENABLE |
355 VERT_INTERP_BILINEAR |
356 HORIZ_INTERP_BILINEAR);
357 }
358 } else
359 /* Aspects match, Let hw scale both directions */
360 pfit_control |= (PFIT_ENABLE |
361 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
362 VERT_INTERP_BILINEAR |
363 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
364 }
365 break;
366
367 case DRM_MODE_SCALE_FULLSCREEN:
368 /*
369 * Full scaling, even if it changes the aspect ratio.
370 * Fortunately this is all done for us in hw.
371 */
257e48f1
CW
372 if (mode->vdisplay != adjusted_mode->vdisplay ||
373 mode->hdisplay != adjusted_mode->hdisplay) {
374 pfit_control |= PFIT_ENABLE;
375 if (INTEL_INFO(dev)->gen >= 4)
376 pfit_control |= PFIT_SCALING_AUTO;
377 else
378 pfit_control |= (VERT_AUTO_SCALE |
379 VERT_INTERP_BILINEAR |
380 HORIZ_AUTO_SCALE |
381 HORIZ_INTERP_BILINEAR);
382 }
3fbe18d6 383 break;
49be663f 384
3fbe18d6
ZY
385 default:
386 break;
387 }
388
389out:
72389a33 390 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
391 if ((pfit_control & PFIT_ENABLE) == 0) {
392 pfit_control = 0;
393 pfit_pgm_ratios = 0;
394 }
72389a33
CW
395
396 /* Make sure pre-965 set dither correctly */
397 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
398 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
399
e9e331a8
CW
400 if (pfit_control != intel_lvds->pfit_control ||
401 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) {
402 intel_lvds->pfit_control = pfit_control;
403 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
404 intel_lvds->pfit_dirty = true;
405 }
49be663f
CW
406 dev_priv->lvds_border_bits = border;
407
79e53945
JB
408 /*
409 * XXX: It would be nice to support lower refresh rates on the
410 * panels to reduce power consumption, and perhaps match the
411 * user's requested refresh rate.
412 */
413
414 return true;
415}
416
79e53945
JB
417static void intel_lvds_mode_set(struct drm_encoder *encoder,
418 struct drm_display_mode *mode,
419 struct drm_display_mode *adjusted_mode)
420{
79e53945
JB
421 /*
422 * The LVDS pin pair will already have been turned on in the
423 * intel_crtc_mode_set since it has a large impact on the DPLL
424 * settings.
425 */
79e53945
JB
426}
427
428/**
429 * Detect the LVDS connection.
430 *
b42d4c5c
JB
431 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
432 * connected and closed means disconnected. We also send hotplug events as
433 * needed, using lid status notification from the input layer.
79e53945 434 */
7b334fcb 435static enum drm_connector_status
930a9e28 436intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 437{
7b9c5abe 438 struct drm_device *dev = connector->dev;
6ee3b5a1 439 enum drm_connector_status status;
b42d4c5c 440
fe16d949
CW
441 status = intel_panel_detect(dev);
442 if (status != connector_status_unknown)
443 return status;
01fe9dbd 444
6ee3b5a1 445 return connector_status_connected;
79e53945
JB
446}
447
448/**
449 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
450 */
451static int intel_lvds_get_modes(struct drm_connector *connector)
452{
788319d4 453 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
79e53945 454 struct drm_device *dev = connector->dev;
788319d4 455 struct drm_display_mode *mode;
79e53945 456
3f8ff0e7 457 if (intel_lvds->edid)
219adae1 458 return drm_add_edid_modes(connector, intel_lvds->edid);
79e53945 459
788319d4 460 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
311bd68e 461 if (mode == NULL)
788319d4 462 return 0;
79e53945 463
788319d4
CW
464 drm_mode_probed_add(connector, mode);
465 return 1;
79e53945
JB
466}
467
0544edfd
TB
468static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
469{
bc0daf48 470 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
471 return 1;
472}
473
474/* The GPU hangs up on these systems if modeset is performed on LID open */
475static const struct dmi_system_id intel_no_modeset_on_lid[] = {
476 {
477 .callback = intel_no_modeset_on_lid_dmi_callback,
478 .ident = "Toshiba Tecra A11",
479 .matches = {
480 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
481 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
482 },
483 },
484
485 { } /* terminating entry */
486};
487
c9354c85
LT
488/*
489 * Lid events. Note the use of 'modeset_on_lid':
490 * - we set it on lid close, and reset it on open
491 * - we use it as a "only once" bit (ie we ignore
492 * duplicate events where it was already properly
493 * set/reset)
494 * - the suspend/resume paths will also set it to
495 * zero, since they restore the mode ("lid open").
496 */
c1c7af60
JB
497static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
498 void *unused)
499{
500 struct drm_i915_private *dev_priv =
501 container_of(nb, struct drm_i915_private, lid_notifier);
502 struct drm_device *dev = dev_priv->dev;
a2565377 503 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 504
2fb4e61d
AW
505 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
506 return NOTIFY_OK;
507
a2565377
ZY
508 /*
509 * check and update the status of LVDS connector after receiving
510 * the LID nofication event.
511 */
512 if (connector)
7b334fcb 513 connector->status = connector->funcs->detect(connector,
930a9e28 514 false);
7b334fcb 515
0544edfd
TB
516 /* Don't force modeset on machines where it causes a GPU lockup */
517 if (dmi_check_system(intel_no_modeset_on_lid))
518 return NOTIFY_OK;
c9354c85
LT
519 if (!acpi_lid_open()) {
520 dev_priv->modeset_on_lid = 1;
521 return NOTIFY_OK;
06891e27 522 }
c1c7af60 523
c9354c85
LT
524 if (!dev_priv->modeset_on_lid)
525 return NOTIFY_OK;
526
527 dev_priv->modeset_on_lid = 0;
528
529 mutex_lock(&dev->mode_config.mutex);
3b7a89fc 530 intel_modeset_check_state(dev);
c9354c85 531 mutex_unlock(&dev->mode_config.mutex);
06324194 532
c1c7af60
JB
533 return NOTIFY_OK;
534}
535
79e53945
JB
536/**
537 * intel_lvds_destroy - unregister and free LVDS structures
538 * @connector: connector to free
539 *
540 * Unregister the DDC bus for this connector then free the driver private
541 * structure.
542 */
543static void intel_lvds_destroy(struct drm_connector *connector)
544{
c1c7af60 545 struct drm_device *dev = connector->dev;
c1c7af60 546 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 547
aaa6fd2a
MG
548 intel_panel_destroy_backlight(dev);
549
c1c7af60
JB
550 if (dev_priv->lid_notifier.notifier_call)
551 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
552 drm_sysfs_connector_remove(connector);
553 drm_connector_cleanup(connector);
554 kfree(connector);
555}
556
335041ed
JB
557static int intel_lvds_set_property(struct drm_connector *connector,
558 struct drm_property *property,
559 uint64_t value)
560{
788319d4 561 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
3fbe18d6 562 struct drm_device *dev = connector->dev;
3fbe18d6 563
788319d4
CW
564 if (property == dev->mode_config.scaling_mode_property) {
565 struct drm_crtc *crtc = intel_lvds->base.base.crtc;
bb8a3560 566
53bd8389
JB
567 if (value == DRM_MODE_SCALE_NONE) {
568 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 569 return -EINVAL;
3fbe18d6 570 }
788319d4 571
ea5b213a 572 if (intel_lvds->fitting_mode == value) {
3fbe18d6
ZY
573 /* the LVDS scaling property is not changed */
574 return 0;
575 }
ea5b213a 576 intel_lvds->fitting_mode = value;
3fbe18d6
ZY
577 if (crtc && crtc->enabled) {
578 /*
579 * If the CRTC is enabled, the display will be changed
580 * according to the new panel fitting mode.
581 */
a6778b3c
DV
582 intel_set_mode(crtc, &crtc->mode,
583 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
584 }
585 }
586
335041ed
JB
587 return 0;
588}
589
79e53945 590static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 591 .mode_fixup = intel_lvds_mode_fixup,
79e53945 592 .mode_set = intel_lvds_mode_set,
1f703855 593 .disable = intel_encoder_noop,
79e53945
JB
594};
595
596static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
597 .get_modes = intel_lvds_get_modes,
598 .mode_valid = intel_lvds_mode_valid,
df0e9248 599 .best_encoder = intel_best_encoder,
79e53945
JB
600};
601
602static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 603 .dpms = intel_connector_dpms,
79e53945
JB
604 .detect = intel_lvds_detect,
605 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 606 .set_property = intel_lvds_set_property,
79e53945
JB
607 .destroy = intel_lvds_destroy,
608};
609
79e53945 610static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 611 .destroy = intel_encoder_destroy,
79e53945
JB
612};
613
425d244c
JW
614static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
615{
bc0daf48 616 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
617 return 1;
618}
79e53945 619
425d244c 620/* These systems claim to have LVDS, but really don't */
93c05f22 621static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
622 {
623 .callback = intel_no_lvds_dmi_callback,
624 .ident = "Apple Mac Mini (Core series)",
625 .matches = {
98acd46f 626 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
627 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
628 },
629 },
630 {
631 .callback = intel_no_lvds_dmi_callback,
632 .ident = "Apple Mac Mini (Core 2 series)",
633 .matches = {
98acd46f 634 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
635 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
636 },
637 },
638 {
639 .callback = intel_no_lvds_dmi_callback,
640 .ident = "MSI IM-945GSE-A",
641 .matches = {
642 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
643 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
644 },
645 },
646 {
647 .callback = intel_no_lvds_dmi_callback,
648 .ident = "Dell Studio Hybrid",
649 .matches = {
650 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
651 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
652 },
653 },
70aa96ca
JW
654 {
655 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
656 .ident = "Dell OptiPlex FX170",
657 .matches = {
658 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
659 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
660 },
661 },
662 {
663 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
664 .ident = "AOpen Mini PC",
665 .matches = {
666 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
667 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
668 },
669 },
ed8c754b
TV
670 {
671 .callback = intel_no_lvds_dmi_callback,
672 .ident = "AOpen Mini PC MP915",
673 .matches = {
674 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
675 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
676 },
677 },
22ab70d3
KP
678 {
679 .callback = intel_no_lvds_dmi_callback,
680 .ident = "AOpen i915GMm-HFS",
681 .matches = {
682 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
683 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
684 },
685 },
e57b6886
DV
686 {
687 .callback = intel_no_lvds_dmi_callback,
688 .ident = "AOpen i45GMx-I",
689 .matches = {
690 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
691 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
692 },
693 },
fa0864b2
MC
694 {
695 .callback = intel_no_lvds_dmi_callback,
696 .ident = "Aopen i945GTt-VFA",
697 .matches = {
698 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
699 },
700 },
9875557e
SB
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Clientron U800",
704 .matches = {
705 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
706 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
707 },
708 },
6a574b5b 709 {
44306ab3
JS
710 .callback = intel_no_lvds_dmi_callback,
711 .ident = "Clientron E830",
712 .matches = {
713 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
714 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
715 },
716 },
717 {
6a574b5b
HG
718 .callback = intel_no_lvds_dmi_callback,
719 .ident = "Asus EeeBox PC EB1007",
720 .matches = {
721 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
722 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
723 },
724 },
0999bbe0
AJ
725 {
726 .callback = intel_no_lvds_dmi_callback,
727 .ident = "Asus AT5NM10T-I",
728 .matches = {
729 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
730 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
731 },
732 },
33471119
JBG
733 {
734 .callback = intel_no_lvds_dmi_callback,
735 .ident = "Hewlett-Packard HP t5740e Thin Client",
736 .matches = {
737 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
738 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
739 },
740 },
f5b8a7ed
MG
741 {
742 .callback = intel_no_lvds_dmi_callback,
743 .ident = "Hewlett-Packard t5745",
744 .matches = {
745 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 746 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
747 },
748 },
749 {
750 .callback = intel_no_lvds_dmi_callback,
751 .ident = "Hewlett-Packard st5747",
752 .matches = {
753 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 754 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
755 },
756 },
97effadb
AA
757 {
758 .callback = intel_no_lvds_dmi_callback,
759 .ident = "MSI Wind Box DC500",
760 .matches = {
761 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
762 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
763 },
764 },
9756fe38
SS
765 {
766 .callback = intel_no_lvds_dmi_callback,
767 .ident = "ZOTAC ZBOXSD-ID12/ID13",
768 .matches = {
769 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
770 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
771 },
772 },
a51d4ed0
CW
773 {
774 .callback = intel_no_lvds_dmi_callback,
775 .ident = "Gigabyte GA-D525TUD",
776 .matches = {
777 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
778 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
779 },
780 },
425d244c
JW
781
782 { } /* terminating entry */
783};
79e53945 784
18f9ed12
ZY
785/**
786 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
787 * @dev: drm device
788 * @connector: LVDS connector
789 *
790 * Find the reduced downclock for LVDS in EDID.
791 */
792static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
793 struct drm_display_mode *fixed_mode,
794 struct drm_connector *connector)
18f9ed12
ZY
795{
796 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 797 struct drm_display_mode *scan;
18f9ed12
ZY
798 int temp_downclock;
799
788319d4 800 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
801 list_for_each_entry(scan, &connector->probed_modes, head) {
802 /*
803 * If one mode has the same resolution with the fixed_panel
804 * mode while they have the different refresh rate, it means
805 * that the reduced downclock is found for the LVDS. In such
806 * case we can set the different FPx0/1 to dynamically select
807 * between low and high frequency.
808 */
788319d4
CW
809 if (scan->hdisplay == fixed_mode->hdisplay &&
810 scan->hsync_start == fixed_mode->hsync_start &&
811 scan->hsync_end == fixed_mode->hsync_end &&
812 scan->htotal == fixed_mode->htotal &&
813 scan->vdisplay == fixed_mode->vdisplay &&
814 scan->vsync_start == fixed_mode->vsync_start &&
815 scan->vsync_end == fixed_mode->vsync_end &&
816 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
817 if (scan->clock < temp_downclock) {
818 /*
819 * The downclock is already found. But we
820 * expect to find the lower downclock.
821 */
822 temp_downclock = scan->clock;
823 }
824 }
825 }
788319d4 826 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
827 /* We found the downclock for LVDS. */
828 dev_priv->lvds_downclock_avail = 1;
829 dev_priv->lvds_downclock = temp_downclock;
830 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
831 "Normal clock %dKhz, downclock %dKhz\n",
832 fixed_mode->clock, temp_downclock);
18f9ed12 833 }
18f9ed12
ZY
834}
835
7cf4f69d
ZY
836/*
837 * Enumerate the child dev array parsed from VBT to check whether
838 * the LVDS is present.
839 * If it is present, return 1.
840 * If it is not present, return false.
841 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 842 */
270eea0f
CW
843static bool lvds_is_present_in_vbt(struct drm_device *dev,
844 u8 *i2c_pin)
7cf4f69d
ZY
845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 847 int i;
7cf4f69d
ZY
848
849 if (!dev_priv->child_dev_num)
425904dd 850 return true;
7cf4f69d 851
7cf4f69d 852 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
853 struct child_device_config *child = dev_priv->child_dev + i;
854
855 /* If the device type is not LFP, continue.
856 * We have to check both the new identifiers as well as the
857 * old for compatibility with some BIOSes.
7cf4f69d 858 */
425904dd
CW
859 if (child->device_type != DEVICE_TYPE_INT_LFP &&
860 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
861 continue;
862
3bd7d909
DK
863 if (intel_gmbus_is_port_valid(child->i2c_pin))
864 *i2c_pin = child->i2c_pin;
270eea0f 865
425904dd
CW
866 /* However, we cannot trust the BIOS writers to populate
867 * the VBT correctly. Since LVDS requires additional
868 * information from AIM blocks, a non-zero addin offset is
869 * a good indicator that the LVDS is actually present.
7cf4f69d 870 */
425904dd
CW
871 if (child->addin_offset)
872 return true;
873
874 /* But even then some BIOS writers perform some black magic
875 * and instantiate the device without reference to any
876 * additional data. Trust that if the VBT was written into
877 * the OpRegion then they have validated the LVDS's existence.
878 */
879 if (dev_priv->opregion.vbt)
880 return true;
7cf4f69d 881 }
425904dd
CW
882
883 return false;
7cf4f69d
ZY
884}
885
f3cfcba6
CW
886static bool intel_lvds_supported(struct drm_device *dev)
887{
888 /* With the introduction of the PCH we gained a dedicated
889 * LVDS presence pin, use it. */
890 if (HAS_PCH_SPLIT(dev))
891 return true;
892
893 /* Otherwise LVDS was only attached to mobile products,
894 * except for the inglorious 830gm */
895 return IS_MOBILE(dev) && !IS_I830(dev);
896}
897
79e53945
JB
898/**
899 * intel_lvds_init - setup LVDS connectors on this device
900 * @dev: drm device
901 *
902 * Create the connector, register the LVDS DDC bus, and try to figure out what
903 * modes we can display on the LVDS panel (if present).
904 */
c5d1b51d 905bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
906{
907 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 908 struct intel_lvds *intel_lvds;
21d40d37 909 struct intel_encoder *intel_encoder;
bb8a3560 910 struct intel_connector *intel_connector;
79e53945
JB
911 struct drm_connector *connector;
912 struct drm_encoder *encoder;
913 struct drm_display_mode *scan; /* *modes, *bios_mode; */
914 struct drm_crtc *crtc;
915 u32 lvds;
270eea0f
CW
916 int pipe;
917 u8 pin;
79e53945 918
f3cfcba6
CW
919 if (!intel_lvds_supported(dev))
920 return false;
921
425d244c
JW
922 /* Skip init on machines we know falsely report LVDS */
923 if (dmi_check_system(intel_no_lvds))
c5d1b51d 924 return false;
565dcd46 925
270eea0f
CW
926 pin = GMBUS_PORT_PANEL;
927 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 928 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 929 return false;
38b3037e 930 }
e99da35f 931
c619eed4 932 if (HAS_PCH_SPLIT(dev)) {
541998a1 933 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 934 return false;
5ceb0f9b 935 if (dev_priv->edp.support) {
28c97730 936 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 937 return false;
32f9d658 938 }
541998a1
ZW
939 }
940
ea5b213a
CW
941 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
942 if (!intel_lvds) {
c5d1b51d 943 return false;
79e53945
JB
944 }
945
bb8a3560
ZW
946 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
947 if (!intel_connector) {
ea5b213a 948 kfree(intel_lvds);
c5d1b51d 949 return false;
bb8a3560
ZW
950 }
951
e9e331a8
CW
952 if (!HAS_PCH_SPLIT(dev)) {
953 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
954 }
955
ea5b213a 956 intel_encoder = &intel_lvds->base;
4ef69c7a 957 encoder = &intel_encoder->base;
ea5b213a 958 connector = &intel_connector->base;
bb8a3560 959 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
960 DRM_MODE_CONNECTOR_LVDS);
961
4ef69c7a 962 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
963 DRM_MODE_ENCODER_LVDS);
964
c22834ec
DV
965 intel_encoder->enable = intel_enable_lvds;
966 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
967 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
968 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 969
df0e9248 970 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 971 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 972
66a9278e 973 intel_encoder->cloneable = false;
27f8227b
JB
974 if (HAS_PCH_SPLIT(dev))
975 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
976 else if (IS_GEN4(dev))
977 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
978 else
979 intel_encoder->crtc_mask = (1 << 1);
980
79e53945
JB
981 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
982 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
983 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
984 connector->interlace_allowed = false;
985 connector->doublescan_allowed = false;
986
3fbe18d6
ZY
987 /* create the scaling mode property */
988 drm_mode_create_scaling_mode_property(dev);
989 /*
990 * the initial panel fitting mode will be FULL_SCREEN.
991 */
79e53945 992
bb8a3560 993 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 994 dev->mode_config.scaling_mode_property,
dd1ea37d 995 DRM_MODE_SCALE_ASPECT);
ea5b213a 996 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
997 /*
998 * LVDS discovery:
999 * 1) check for EDID on DDC
1000 * 2) check for VBT data
1001 * 3) check to see if LVDS is already on
1002 * if none of the above, no panel
1003 * 4) make sure lid is open
1004 * if closed, act like it's not there for now
1005 */
1006
79e53945
JB
1007 /*
1008 * Attempt to get the fixed panel mode from DDC. Assume that the
1009 * preferred mode is the right one.
1010 */
219adae1 1011 intel_lvds->edid = drm_get_edid(connector,
3bd7d909
DK
1012 intel_gmbus_get_adapter(dev_priv,
1013 pin));
3f8ff0e7
CW
1014 if (intel_lvds->edid) {
1015 if (drm_add_edid_modes(connector,
1016 intel_lvds->edid)) {
1017 drm_mode_connector_update_edid_property(connector,
1018 intel_lvds->edid);
1019 } else {
1020 kfree(intel_lvds->edid);
1021 intel_lvds->edid = NULL;
1022 }
1023 }
219adae1 1024 if (!intel_lvds->edid) {
788319d4
CW
1025 /* Didn't get an EDID, so
1026 * Set wide sync ranges so we get all modes
1027 * handed to valid_mode for checking
1028 */
1029 connector->display_info.min_vfreq = 0;
1030 connector->display_info.max_vfreq = 200;
1031 connector->display_info.min_hfreq = 0;
1032 connector->display_info.max_hfreq = 200;
1033 }
79e53945
JB
1034
1035 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1036 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
788319d4 1037 intel_lvds->fixed_mode =
79e53945 1038 drm_mode_duplicate(dev, scan);
788319d4
CW
1039 intel_find_lvds_downclock(dev,
1040 intel_lvds->fixed_mode,
1041 connector);
565dcd46 1042 goto out;
79e53945 1043 }
79e53945
JB
1044 }
1045
1046 /* Failed to get EDID, what about VBT? */
88631706 1047 if (dev_priv->lfp_lvds_vbt_mode) {
788319d4 1048 intel_lvds->fixed_mode =
88631706 1049 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
788319d4
CW
1050 if (intel_lvds->fixed_mode) {
1051 intel_lvds->fixed_mode->type |=
e285f3cd 1052 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1053 goto out;
1054 }
79e53945
JB
1055 }
1056
1057 /*
1058 * If we didn't get EDID, try checking if the panel is already turned
1059 * on. If so, assume that whatever is currently programmed is the
1060 * correct mode.
1061 */
541998a1 1062
f2b115e6 1063 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1064 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1065 goto failed;
1066
79e53945
JB
1067 lvds = I915_READ(LVDS);
1068 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1069 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1070
1071 if (crtc && (lvds & LVDS_PORT_EN)) {
788319d4
CW
1072 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
1073 if (intel_lvds->fixed_mode) {
1074 intel_lvds->fixed_mode->type |=
79e53945 1075 DRM_MODE_TYPE_PREFERRED;
565dcd46 1076 goto out;
79e53945
JB
1077 }
1078 }
1079
1080 /* If we still don't have a mode after all that, give up. */
788319d4 1081 if (!intel_lvds->fixed_mode)
79e53945
JB
1082 goto failed;
1083
79e53945 1084out:
24ded204
DV
1085 /*
1086 * Unlock registers and just
1087 * leave them unlocked
1088 */
c619eed4 1089 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1090 I915_WRITE(PCH_PP_CONTROL,
1091 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1092 } else {
ed10fca9
KP
1093 I915_WRITE(PP_CONTROL,
1094 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1095 }
c1c7af60
JB
1096 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1097 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1098 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB
1099 dev_priv->lid_notifier.notifier_call = NULL;
1100 }
a2565377
ZY
1101 /* keep the LVDS connector */
1102 dev_priv->int_lvds_connector = connector;
79e53945 1103 drm_sysfs_connector_add(connector);
aaa6fd2a
MG
1104
1105 intel_panel_setup_backlight(dev);
1106
c5d1b51d 1107 return true;
79e53945
JB
1108
1109failed:
8a4c47f3 1110 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1111 drm_connector_cleanup(connector);
1991bdfa 1112 drm_encoder_cleanup(encoder);
ea5b213a 1113 kfree(intel_lvds);
bb8a3560 1114 kfree(intel_connector);
c5d1b51d 1115 return false;
79e53945 1116}
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