Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
13c7d870 | 52 | bool is_dual_link; |
7dec0606 | 53 | u32 reg; |
788319d4 | 54 | |
62165e0d | 55 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
56 | }; |
57 | ||
29b99b48 | 58 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
29b99b48 | 60 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
61 | } |
62 | ||
c7362c4d | 63 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 64 | { |
c7362c4d | 65 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
66 | } |
67 | ||
b1dc332c DV |
68 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
69 | enum pipe *pipe) | |
70 | { | |
71 | struct drm_device *dev = encoder->base.dev; | |
72 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
73 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
74 | u32 tmp; | |
b1dc332c | 75 | |
7dec0606 | 76 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
77 | |
78 | if (!(tmp & LVDS_PORT_EN)) | |
79 | return false; | |
80 | ||
81 | if (HAS_PCH_CPT(dev)) | |
82 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
83 | else | |
84 | *pipe = PORT_TO_PIPE(tmp); | |
85 | ||
86 | return true; | |
87 | } | |
88 | ||
045ac3b5 JB |
89 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
90 | struct intel_crtc_config *pipe_config) | |
91 | { | |
92 | struct drm_device *dev = encoder->base.dev; | |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | u32 lvds_reg, tmp, flags = 0; | |
18442d08 | 95 | int dotclock; |
045ac3b5 JB |
96 | |
97 | if (HAS_PCH_SPLIT(dev)) | |
98 | lvds_reg = PCH_LVDS; | |
99 | else | |
100 | lvds_reg = LVDS; | |
101 | ||
102 | tmp = I915_READ(lvds_reg); | |
103 | if (tmp & LVDS_HSYNC_POLARITY) | |
104 | flags |= DRM_MODE_FLAG_NHSYNC; | |
105 | else | |
106 | flags |= DRM_MODE_FLAG_PHSYNC; | |
107 | if (tmp & LVDS_VSYNC_POLARITY) | |
108 | flags |= DRM_MODE_FLAG_NVSYNC; | |
109 | else | |
110 | flags |= DRM_MODE_FLAG_PVSYNC; | |
111 | ||
112 | pipe_config->adjusted_mode.flags |= flags; | |
06922821 | 113 | |
18442d08 VS |
114 | dotclock = pipe_config->port_clock; |
115 | ||
116 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
117 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
118 | ||
241bfc38 | 119 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
120 | } |
121 | ||
f6736a1a | 122 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
123 | { |
124 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
125 | struct drm_device *dev = encoder->base.dev; | |
126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 127 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
4c6df4b4 VS |
128 | const struct drm_display_mode *adjusted_mode = |
129 | &crtc->config.adjusted_mode; | |
55607e8a | 130 | int pipe = crtc->pipe; |
fc683091 DV |
131 | u32 temp; |
132 | ||
55607e8a DV |
133 | if (HAS_PCH_SPLIT(dev)) { |
134 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
135 | assert_shared_dpll_disabled(dev_priv, | |
136 | intel_crtc_to_shared_dpll(crtc)); | |
137 | } else { | |
138 | assert_pll_disabled(dev_priv, pipe); | |
139 | } | |
140 | ||
fc683091 DV |
141 | temp = I915_READ(lvds_encoder->reg); |
142 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
143 | |
144 | if (HAS_PCH_CPT(dev)) { | |
145 | temp &= ~PORT_TRANS_SEL_MASK; | |
146 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 147 | } else { |
62810e5a DV |
148 | if (pipe == 1) { |
149 | temp |= LVDS_PIPEB_SELECT; | |
150 | } else { | |
151 | temp &= ~LVDS_PIPEB_SELECT; | |
152 | } | |
fc683091 | 153 | } |
62810e5a | 154 | |
fc683091 | 155 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 156 | temp &= ~LVDS_BORDER_ENABLE; |
55607e8a | 157 | temp |= crtc->config.gmch_pfit.lvds_border_bits; |
fc683091 DV |
158 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
159 | * set the DPLLs for dual-channel mode or not. | |
160 | */ | |
161 | if (lvds_encoder->is_dual_link) | |
162 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
163 | else | |
164 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
165 | ||
166 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
167 | * appropriately here, but we need to look more thoroughly into how | |
168 | * panels behave in the two modes. | |
169 | */ | |
62810e5a DV |
170 | |
171 | /* Set the dithering flag on LVDS as needed, note that there is no | |
172 | * special lvds dither control bit on pch-split platforms, dithering is | |
173 | * only controlled through the PIPECONF reg. */ | |
174 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
175 | /* Bspec wording suggests that LVDS port dithering only exists |
176 | * for 18bpp panels. */ | |
55607e8a | 177 | if (crtc->config.dither && crtc->config.pipe_bpp == 18) |
fc683091 DV |
178 | temp |= LVDS_ENABLE_DITHER; |
179 | else | |
180 | temp &= ~LVDS_ENABLE_DITHER; | |
181 | } | |
182 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 183 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 184 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 185 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
186 | temp |= LVDS_VSYNC_POLARITY; |
187 | ||
188 | I915_WRITE(lvds_encoder->reg, temp); | |
189 | } | |
190 | ||
79e53945 JB |
191 | /** |
192 | * Sets the power state for the panel. | |
193 | */ | |
c22834ec | 194 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 195 | { |
c22834ec | 196 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 197 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
198 | struct intel_connector *intel_connector = |
199 | &lvds_encoder->attached_connector->base; | |
79e53945 | 200 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 201 | u32 ctl_reg, stat_reg; |
541998a1 | 202 | |
c619eed4 | 203 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 204 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 205 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
206 | } else { |
207 | ctl_reg = PP_CONTROL; | |
de842eff | 208 | stat_reg = PP_STATUS; |
541998a1 | 209 | } |
79e53945 | 210 | |
7dec0606 | 211 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 212 | |
2a1292fd | 213 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 214 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
215 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
216 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 217 | |
752aa88a | 218 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
219 | } |
220 | ||
c22834ec | 221 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 222 | { |
c22834ec | 223 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 224 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
225 | struct intel_connector *intel_connector = |
226 | &lvds_encoder->attached_connector->base; | |
2a1292fd | 227 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 228 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
229 | |
230 | if (HAS_PCH_SPLIT(dev)) { | |
231 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 232 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
233 | } else { |
234 | ctl_reg = PP_CONTROL; | |
de842eff | 235 | stat_reg = PP_STATUS; |
2a1292fd CW |
236 | } |
237 | ||
752aa88a | 238 | intel_panel_disable_backlight(intel_connector); |
2a1292fd CW |
239 | |
240 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
241 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
242 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 243 | |
7dec0606 DV |
244 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
245 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
246 | } |
247 | ||
c19de8eb DL |
248 | static enum drm_mode_status |
249 | intel_lvds_mode_valid(struct drm_connector *connector, | |
250 | struct drm_display_mode *mode) | |
79e53945 | 251 | { |
dd06f90e JN |
252 | struct intel_connector *intel_connector = to_intel_connector(connector); |
253 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 254 | |
788319d4 CW |
255 | if (mode->hdisplay > fixed_mode->hdisplay) |
256 | return MODE_PANEL; | |
257 | if (mode->vdisplay > fixed_mode->vdisplay) | |
258 | return MODE_PANEL; | |
79e53945 JB |
259 | |
260 | return MODE_OK; | |
261 | } | |
262 | ||
7ae89233 DV |
263 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
264 | struct intel_crtc_config *pipe_config) | |
79e53945 | 265 | { |
7ae89233 | 266 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 267 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
268 | struct intel_lvds_encoder *lvds_encoder = |
269 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
270 | struct intel_connector *intel_connector = |
271 | &lvds_encoder->attached_connector->base; | |
7ae89233 | 272 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
29b99b48 | 273 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
4e53c2e0 | 274 | unsigned int lvds_bpp; |
79e53945 JB |
275 | |
276 | /* Should never happen!! */ | |
a6c45cf0 | 277 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 278 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
279 | return false; |
280 | } | |
281 | ||
4e53c2e0 DV |
282 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
283 | LVDS_A3_POWER_UP) | |
284 | lvds_bpp = 8*3; | |
285 | else | |
286 | lvds_bpp = 6*3; | |
287 | ||
e29c22c0 | 288 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
289 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
290 | pipe_config->pipe_bpp, lvds_bpp); | |
291 | pipe_config->pipe_bpp = lvds_bpp; | |
292 | } | |
d8b32247 | 293 | |
79e53945 | 294 | /* |
71677043 | 295 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
296 | * to the adjusted mode. The CRTC will be set up for this mode, |
297 | * with the panel scaling set up to source from the H/VDisplay | |
298 | * of the original mode. | |
299 | */ | |
4d891523 | 300 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 301 | adjusted_mode); |
1d8e1c75 CW |
302 | |
303 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
304 | pipe_config->has_pch_encoder = true; |
305 | ||
b074cec8 JB |
306 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
307 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
308 | } else { |
309 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
310 | intel_connector->panel.fitting_mode); | |
79e53945 | 311 | |
21d8a475 | 312 | } |
f9bef081 | 313 | |
79e53945 JB |
314 | /* |
315 | * XXX: It would be nice to support lower refresh rates on the | |
316 | * panels to reduce power consumption, and perhaps match the | |
317 | * user's requested refresh rate. | |
318 | */ | |
319 | ||
320 | return true; | |
321 | } | |
322 | ||
79e53945 JB |
323 | /** |
324 | * Detect the LVDS connection. | |
325 | * | |
b42d4c5c JB |
326 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
327 | * connected and closed means disconnected. We also send hotplug events as | |
328 | * needed, using lid status notification from the input layer. | |
79e53945 | 329 | */ |
7b334fcb | 330 | static enum drm_connector_status |
930a9e28 | 331 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 332 | { |
7b9c5abe | 333 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 334 | enum drm_connector_status status; |
b42d4c5c | 335 | |
164c8598 | 336 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 337 | connector->base.id, connector->name); |
164c8598 | 338 | |
fe16d949 CW |
339 | status = intel_panel_detect(dev); |
340 | if (status != connector_status_unknown) | |
341 | return status; | |
01fe9dbd | 342 | |
6ee3b5a1 | 343 | return connector_status_connected; |
79e53945 JB |
344 | } |
345 | ||
346 | /** | |
347 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
348 | */ | |
349 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
350 | { | |
62165e0d | 351 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 352 | struct drm_device *dev = connector->dev; |
788319d4 | 353 | struct drm_display_mode *mode; |
79e53945 | 354 | |
9cd300e0 | 355 | /* use cached edid if we have one */ |
2aa4f099 | 356 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 357 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 358 | |
dd06f90e | 359 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 360 | if (mode == NULL) |
788319d4 | 361 | return 0; |
79e53945 | 362 | |
788319d4 CW |
363 | drm_mode_probed_add(connector, mode); |
364 | return 1; | |
79e53945 JB |
365 | } |
366 | ||
0544edfd TB |
367 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
368 | { | |
bc0daf48 | 369 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
370 | return 1; |
371 | } | |
372 | ||
373 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
374 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
375 | { | |
376 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
377 | .ident = "Toshiba Tecra A11", | |
378 | .matches = { | |
379 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
380 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
381 | }, | |
382 | }, | |
383 | ||
384 | { } /* terminating entry */ | |
385 | }; | |
386 | ||
c9354c85 | 387 | /* |
b8efb17b ZR |
388 | * Lid events. Note the use of 'modeset': |
389 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
390 | * and set it to MODESET_DONE on open | |
c9354c85 | 391 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
392 | * duplicate events where it was already properly set) |
393 | * - the suspend/resume paths will set it to | |
394 | * MODESET_SUSPENDED and ignore the lid open event, | |
395 | * because they restore the mode ("lid open"). | |
c9354c85 | 396 | */ |
c1c7af60 JB |
397 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
398 | void *unused) | |
399 | { | |
db1740a0 JN |
400 | struct intel_lvds_connector *lvds_connector = |
401 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
402 | struct drm_connector *connector = &lvds_connector->base.base; | |
403 | struct drm_device *dev = connector->dev; | |
404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 405 | |
2fb4e61d AW |
406 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
407 | return NOTIFY_OK; | |
408 | ||
b8efb17b ZR |
409 | mutex_lock(&dev_priv->modeset_restore_lock); |
410 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
411 | goto exit; | |
a2565377 ZY |
412 | /* |
413 | * check and update the status of LVDS connector after receiving | |
414 | * the LID nofication event. | |
415 | */ | |
db1740a0 | 416 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 417 | |
0544edfd TB |
418 | /* Don't force modeset on machines where it causes a GPU lockup */ |
419 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 420 | goto exit; |
c9354c85 | 421 | if (!acpi_lid_open()) { |
b8efb17b ZR |
422 | /* do modeset on next lid open event */ |
423 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
424 | goto exit; | |
06891e27 | 425 | } |
c1c7af60 | 426 | |
b8efb17b ZR |
427 | if (dev_priv->modeset_restore == MODESET_DONE) |
428 | goto exit; | |
c9354c85 | 429 | |
5be19d91 DV |
430 | /* |
431 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
432 | * We try to detect this here and undo any damage. The split for PCH | |
433 | * platforms is rather conservative and a bit arbitrary expect that on | |
434 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
435 | * and as part of the cleanup in the hw state restore we also redisable | |
436 | * the vga plane. | |
437 | */ | |
438 | if (!HAS_PCH_SPLIT(dev)) { | |
439 | drm_modeset_lock_all(dev); | |
440 | intel_modeset_setup_hw_state(dev, true); | |
441 | drm_modeset_unlock_all(dev); | |
442 | } | |
06324194 | 443 | |
b8efb17b ZR |
444 | dev_priv->modeset_restore = MODESET_DONE; |
445 | ||
446 | exit: | |
447 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
448 | return NOTIFY_OK; |
449 | } | |
450 | ||
79e53945 JB |
451 | /** |
452 | * intel_lvds_destroy - unregister and free LVDS structures | |
453 | * @connector: connector to free | |
454 | * | |
455 | * Unregister the DDC bus for this connector then free the driver private | |
456 | * structure. | |
457 | */ | |
458 | static void intel_lvds_destroy(struct drm_connector *connector) | |
459 | { | |
db1740a0 JN |
460 | struct intel_lvds_connector *lvds_connector = |
461 | to_lvds_connector(connector); | |
79e53945 | 462 | |
db1740a0 JN |
463 | if (lvds_connector->lid_notifier.notifier_call) |
464 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 465 | |
9cd300e0 JN |
466 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
467 | kfree(lvds_connector->base.edid); | |
468 | ||
1d508706 | 469 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 470 | |
79e53945 JB |
471 | drm_connector_cleanup(connector); |
472 | kfree(connector); | |
473 | } | |
474 | ||
335041ed JB |
475 | static int intel_lvds_set_property(struct drm_connector *connector, |
476 | struct drm_property *property, | |
477 | uint64_t value) | |
478 | { | |
4d891523 | 479 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 480 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 481 | |
788319d4 | 482 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 483 | struct drm_crtc *crtc; |
bb8a3560 | 484 | |
53bd8389 JB |
485 | if (value == DRM_MODE_SCALE_NONE) { |
486 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 487 | return -EINVAL; |
3fbe18d6 | 488 | } |
788319d4 | 489 | |
4d891523 | 490 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
491 | /* the LVDS scaling property is not changed */ |
492 | return 0; | |
493 | } | |
4d891523 | 494 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
495 | |
496 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
497 | if (crtc && crtc->enabled) { |
498 | /* | |
499 | * If the CRTC is enabled, the display will be changed | |
500 | * according to the new panel fitting mode. | |
501 | */ | |
c0c36b94 | 502 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
503 | } |
504 | } | |
505 | ||
335041ed JB |
506 | return 0; |
507 | } | |
508 | ||
79e53945 JB |
509 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
510 | .get_modes = intel_lvds_get_modes, | |
511 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 512 | .best_encoder = intel_best_encoder, |
79e53945 JB |
513 | }; |
514 | ||
515 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 516 | .dpms = intel_connector_dpms, |
79e53945 JB |
517 | .detect = intel_lvds_detect, |
518 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 519 | .set_property = intel_lvds_set_property, |
79e53945 JB |
520 | .destroy = intel_lvds_destroy, |
521 | }; | |
522 | ||
79e53945 | 523 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 524 | .destroy = intel_encoder_destroy, |
79e53945 JB |
525 | }; |
526 | ||
425d244c JW |
527 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
528 | { | |
bc0daf48 | 529 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
530 | return 1; |
531 | } | |
79e53945 | 532 | |
425d244c | 533 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 534 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
535 | { |
536 | .callback = intel_no_lvds_dmi_callback, | |
537 | .ident = "Apple Mac Mini (Core series)", | |
538 | .matches = { | |
98acd46f | 539 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
540 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
541 | }, | |
542 | }, | |
543 | { | |
544 | .callback = intel_no_lvds_dmi_callback, | |
545 | .ident = "Apple Mac Mini (Core 2 series)", | |
546 | .matches = { | |
98acd46f | 547 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
548 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
549 | }, | |
550 | }, | |
551 | { | |
552 | .callback = intel_no_lvds_dmi_callback, | |
553 | .ident = "MSI IM-945GSE-A", | |
554 | .matches = { | |
555 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
556 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
557 | }, | |
558 | }, | |
559 | { | |
560 | .callback = intel_no_lvds_dmi_callback, | |
561 | .ident = "Dell Studio Hybrid", | |
562 | .matches = { | |
563 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
564 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
565 | }, | |
566 | }, | |
70aa96ca JW |
567 | { |
568 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
569 | .ident = "Dell OptiPlex FX170", |
570 | .matches = { | |
571 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
572 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
573 | }, | |
574 | }, | |
575 | { | |
576 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
577 | .ident = "AOpen Mini PC", |
578 | .matches = { | |
579 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
580 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
581 | }, | |
582 | }, | |
ed8c754b TV |
583 | { |
584 | .callback = intel_no_lvds_dmi_callback, | |
585 | .ident = "AOpen Mini PC MP915", | |
586 | .matches = { | |
587 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
588 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
589 | }, | |
590 | }, | |
22ab70d3 KP |
591 | { |
592 | .callback = intel_no_lvds_dmi_callback, | |
593 | .ident = "AOpen i915GMm-HFS", | |
594 | .matches = { | |
595 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
596 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
597 | }, | |
598 | }, | |
e57b6886 DV |
599 | { |
600 | .callback = intel_no_lvds_dmi_callback, | |
601 | .ident = "AOpen i45GMx-I", | |
602 | .matches = { | |
603 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
604 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
605 | }, | |
606 | }, | |
fa0864b2 MC |
607 | { |
608 | .callback = intel_no_lvds_dmi_callback, | |
609 | .ident = "Aopen i945GTt-VFA", | |
610 | .matches = { | |
611 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
612 | }, | |
613 | }, | |
9875557e SB |
614 | { |
615 | .callback = intel_no_lvds_dmi_callback, | |
616 | .ident = "Clientron U800", | |
617 | .matches = { | |
618 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
619 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
620 | }, | |
621 | }, | |
6a574b5b | 622 | { |
44306ab3 JS |
623 | .callback = intel_no_lvds_dmi_callback, |
624 | .ident = "Clientron E830", | |
625 | .matches = { | |
626 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
627 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
628 | }, | |
629 | }, | |
630 | { | |
6a574b5b HG |
631 | .callback = intel_no_lvds_dmi_callback, |
632 | .ident = "Asus EeeBox PC EB1007", | |
633 | .matches = { | |
634 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
635 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
636 | }, | |
637 | }, | |
0999bbe0 AJ |
638 | { |
639 | .callback = intel_no_lvds_dmi_callback, | |
640 | .ident = "Asus AT5NM10T-I", | |
641 | .matches = { | |
642 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
643 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
644 | }, | |
645 | }, | |
33471119 JBG |
646 | { |
647 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 648 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
649 | .matches = { |
650 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 651 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
652 | }, |
653 | }, | |
f5b8a7ed MG |
654 | { |
655 | .callback = intel_no_lvds_dmi_callback, | |
656 | .ident = "Hewlett-Packard t5745", | |
657 | .matches = { | |
658 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 659 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
660 | }, |
661 | }, | |
662 | { | |
663 | .callback = intel_no_lvds_dmi_callback, | |
664 | .ident = "Hewlett-Packard st5747", | |
665 | .matches = { | |
666 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 667 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
668 | }, |
669 | }, | |
97effadb AA |
670 | { |
671 | .callback = intel_no_lvds_dmi_callback, | |
672 | .ident = "MSI Wind Box DC500", | |
673 | .matches = { | |
674 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
675 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
676 | }, | |
677 | }, | |
a51d4ed0 CW |
678 | { |
679 | .callback = intel_no_lvds_dmi_callback, | |
680 | .ident = "Gigabyte GA-D525TUD", | |
681 | .matches = { | |
682 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
683 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
684 | }, | |
685 | }, | |
c31407a3 CW |
686 | { |
687 | .callback = intel_no_lvds_dmi_callback, | |
688 | .ident = "Supermicro X7SPA-H", | |
689 | .matches = { | |
690 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
691 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
692 | }, | |
693 | }, | |
9e9dd0e8 CL |
694 | { |
695 | .callback = intel_no_lvds_dmi_callback, | |
696 | .ident = "Fujitsu Esprimo Q900", | |
697 | .matches = { | |
698 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
699 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
700 | }, | |
701 | }, | |
645378d8 RP |
702 | { |
703 | .callback = intel_no_lvds_dmi_callback, | |
704 | .ident = "Intel D410PT", | |
705 | .matches = { | |
706 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
707 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
708 | }, | |
709 | }, | |
710 | { | |
711 | .callback = intel_no_lvds_dmi_callback, | |
712 | .ident = "Intel D425KT", | |
713 | .matches = { | |
714 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
715 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
716 | }, | |
717 | }, | |
e5614f0c CW |
718 | { |
719 | .callback = intel_no_lvds_dmi_callback, | |
720 | .ident = "Intel D510MO", | |
721 | .matches = { | |
722 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
723 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
724 | }, | |
725 | }, | |
dcf6d294 JN |
726 | { |
727 | .callback = intel_no_lvds_dmi_callback, | |
728 | .ident = "Intel D525MW", | |
729 | .matches = { | |
730 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
731 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
732 | }, | |
733 | }, | |
425d244c JW |
734 | |
735 | { } /* terminating entry */ | |
736 | }; | |
79e53945 | 737 | |
7cf4f69d ZY |
738 | /* |
739 | * Enumerate the child dev array parsed from VBT to check whether | |
740 | * the LVDS is present. | |
741 | * If it is present, return 1. | |
742 | * If it is not present, return false. | |
743 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 744 | */ |
270eea0f CW |
745 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
746 | u8 *i2c_pin) | |
7cf4f69d ZY |
747 | { |
748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 749 | int i; |
7cf4f69d | 750 | |
41aa3448 | 751 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 752 | return true; |
7cf4f69d | 753 | |
41aa3448 | 754 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
755 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
756 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
757 | |
758 | /* If the device type is not LFP, continue. | |
759 | * We have to check both the new identifiers as well as the | |
760 | * old for compatibility with some BIOSes. | |
7cf4f69d | 761 | */ |
425904dd CW |
762 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
763 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
764 | continue; |
765 | ||
3bd7d909 DK |
766 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
767 | *i2c_pin = child->i2c_pin; | |
270eea0f | 768 | |
425904dd CW |
769 | /* However, we cannot trust the BIOS writers to populate |
770 | * the VBT correctly. Since LVDS requires additional | |
771 | * information from AIM blocks, a non-zero addin offset is | |
772 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 773 | */ |
425904dd CW |
774 | if (child->addin_offset) |
775 | return true; | |
776 | ||
777 | /* But even then some BIOS writers perform some black magic | |
778 | * and instantiate the device without reference to any | |
779 | * additional data. Trust that if the VBT was written into | |
780 | * the OpRegion then they have validated the LVDS's existence. | |
781 | */ | |
782 | if (dev_priv->opregion.vbt) | |
783 | return true; | |
7cf4f69d | 784 | } |
425904dd CW |
785 | |
786 | return false; | |
7cf4f69d ZY |
787 | } |
788 | ||
1974cad0 DV |
789 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
790 | { | |
791 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
792 | return 1; | |
793 | } | |
794 | ||
795 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
796 | { | |
797 | .callback = intel_dual_link_lvds_callback, | |
798 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
799 | .matches = { | |
800 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
801 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
802 | }, | |
803 | }, | |
804 | { } /* terminating entry */ | |
805 | }; | |
806 | ||
807 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
808 | { |
809 | struct intel_encoder *encoder; | |
810 | struct intel_lvds_encoder *lvds_encoder; | |
811 | ||
812 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
813 | base.head) { | |
814 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
815 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
816 | ||
817 | return lvds_encoder->is_dual_link; | |
818 | } | |
819 | } | |
820 | ||
821 | return false; | |
822 | } | |
823 | ||
7dec0606 | 824 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 825 | { |
7dec0606 | 826 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
827 | unsigned int val; |
828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
829 | |
830 | /* use the module option value if specified */ | |
d330a953 JN |
831 | if (i915.lvds_channel_mode > 0) |
832 | return i915.lvds_channel_mode == 2; | |
1974cad0 DV |
833 | |
834 | if (dmi_check_system(intel_dual_link_lvds)) | |
835 | return true; | |
836 | ||
13c7d870 DV |
837 | /* BIOS should set the proper LVDS register value at boot, but |
838 | * in reality, it doesn't set the value when the lid is closed; | |
839 | * we need to check "the value to be set" in VBT when LVDS | |
840 | * register is uninitialized. | |
841 | */ | |
7dec0606 | 842 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 843 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 844 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 845 | |
1974cad0 DV |
846 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
847 | } | |
848 | ||
f3cfcba6 CW |
849 | static bool intel_lvds_supported(struct drm_device *dev) |
850 | { | |
851 | /* With the introduction of the PCH we gained a dedicated | |
852 | * LVDS presence pin, use it. */ | |
311e359c | 853 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
854 | return true; |
855 | ||
856 | /* Otherwise LVDS was only attached to mobile products, | |
857 | * except for the inglorious 830gm */ | |
311e359c PZ |
858 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
859 | return true; | |
860 | ||
861 | return false; | |
f3cfcba6 CW |
862 | } |
863 | ||
79e53945 JB |
864 | /** |
865 | * intel_lvds_init - setup LVDS connectors on this device | |
866 | * @dev: drm device | |
867 | * | |
868 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
869 | * modes we can display on the LVDS panel (if present). | |
870 | */ | |
c9093354 | 871 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
872 | { |
873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 874 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 875 | struct intel_encoder *intel_encoder; |
c7362c4d | 876 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 877 | struct intel_connector *intel_connector; |
79e53945 JB |
878 | struct drm_connector *connector; |
879 | struct drm_encoder *encoder; | |
880 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 881 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 882 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 883 | struct edid *edid; |
79e53945 JB |
884 | struct drm_crtc *crtc; |
885 | u32 lvds; | |
270eea0f CW |
886 | int pipe; |
887 | u8 pin; | |
79e53945 | 888 | |
f3cfcba6 | 889 | if (!intel_lvds_supported(dev)) |
c9093354 | 890 | return; |
f3cfcba6 | 891 | |
425d244c JW |
892 | /* Skip init on machines we know falsely report LVDS */ |
893 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 894 | return; |
565dcd46 | 895 | |
270eea0f CW |
896 | pin = GMBUS_PORT_PANEL; |
897 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 898 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 899 | return; |
38b3037e | 900 | } |
e99da35f | 901 | |
c619eed4 | 902 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 903 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 904 | return; |
41aa3448 | 905 | if (dev_priv->vbt.edp_support) { |
28c97730 | 906 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 907 | return; |
32f9d658 | 908 | } |
541998a1 ZW |
909 | } |
910 | ||
b14c5679 | 911 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 912 | if (!lvds_encoder) |
c9093354 | 913 | return; |
79e53945 | 914 | |
b14c5679 | 915 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 916 | if (!lvds_connector) { |
29b99b48 | 917 | kfree(lvds_encoder); |
c9093354 | 918 | return; |
bb8a3560 ZW |
919 | } |
920 | ||
62165e0d JN |
921 | lvds_encoder->attached_connector = lvds_connector; |
922 | ||
29b99b48 | 923 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 924 | encoder = &intel_encoder->base; |
c7362c4d | 925 | intel_connector = &lvds_connector->base; |
ea5b213a | 926 | connector = &intel_connector->base; |
bb8a3560 | 927 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
928 | DRM_MODE_CONNECTOR_LVDS); |
929 | ||
4ef69c7a | 930 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
931 | DRM_MODE_ENCODER_LVDS); |
932 | ||
c22834ec | 933 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 934 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 935 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 936 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 937 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 938 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 939 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 940 | intel_connector->unregister = intel_connector_unregister; |
c22834ec | 941 | |
df0e9248 | 942 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 943 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 944 | |
bc079e8b | 945 | intel_encoder->cloneable = 0; |
27f8227b JB |
946 | if (HAS_PCH_SPLIT(dev)) |
947 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
948 | else if (IS_GEN4(dev)) |
949 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
950 | else |
951 | intel_encoder->crtc_mask = (1 << 1); | |
952 | ||
79e53945 JB |
953 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
954 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
955 | connector->interlace_allowed = false; | |
956 | connector->doublescan_allowed = false; | |
957 | ||
7dec0606 DV |
958 | if (HAS_PCH_SPLIT(dev)) { |
959 | lvds_encoder->reg = PCH_LVDS; | |
960 | } else { | |
961 | lvds_encoder->reg = LVDS; | |
962 | } | |
963 | ||
3fbe18d6 ZY |
964 | /* create the scaling mode property */ |
965 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 966 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 967 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 968 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 969 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
970 | /* |
971 | * LVDS discovery: | |
972 | * 1) check for EDID on DDC | |
973 | * 2) check for VBT data | |
974 | * 3) check to see if LVDS is already on | |
975 | * if none of the above, no panel | |
976 | * 4) make sure lid is open | |
977 | * if closed, act like it's not there for now | |
978 | */ | |
979 | ||
79e53945 JB |
980 | /* |
981 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
982 | * preferred mode is the right one. | |
983 | */ | |
4da98541 | 984 | mutex_lock(&dev->mode_config.mutex); |
9cd300e0 JN |
985 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
986 | if (edid) { | |
987 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 988 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 989 | edid); |
3f8ff0e7 | 990 | } else { |
9cd300e0 JN |
991 | kfree(edid); |
992 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 993 | } |
9cd300e0 JN |
994 | } else { |
995 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 996 | } |
9cd300e0 JN |
997 | lvds_connector->base.edid = edid; |
998 | ||
999 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1000 | /* Didn't get an EDID, so |
1001 | * Set wide sync ranges so we get all modes | |
1002 | * handed to valid_mode for checking | |
1003 | */ | |
1004 | connector->display_info.min_vfreq = 0; | |
1005 | connector->display_info.max_vfreq = 200; | |
1006 | connector->display_info.min_hfreq = 0; | |
1007 | connector->display_info.max_hfreq = 200; | |
1008 | } | |
79e53945 JB |
1009 | |
1010 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1011 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1012 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1013 | drm_mode_debug_printmodeline(scan); | |
1014 | ||
dd06f90e | 1015 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 | 1016 | if (fixed_mode) { |
4b6ed685 | 1017 | downclock_mode = |
ec9ed197 VK |
1018 | intel_find_panel_downclock(dev, |
1019 | fixed_mode, connector); | |
4b6ed685 VK |
1020 | if (downclock_mode != NULL && |
1021 | i915.lvds_downclock) { | |
ec9ed197 VK |
1022 | /* We found the downclock for LVDS. */ |
1023 | dev_priv->lvds_downclock_avail = true; | |
1024 | dev_priv->lvds_downclock = | |
ec9ed197 VK |
1025 | downclock_mode->clock; |
1026 | DRM_DEBUG_KMS("LVDS downclock is found" | |
1027 | " in EDID. Normal clock %dKhz, " | |
1028 | "downclock %dKhz\n", | |
1029 | fixed_mode->clock, | |
1030 | dev_priv->lvds_downclock); | |
1031 | } | |
6a9d51b7 CW |
1032 | goto out; |
1033 | } | |
79e53945 | 1034 | } |
79e53945 JB |
1035 | } |
1036 | ||
1037 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1038 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1039 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1040 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1041 | |
41aa3448 | 1042 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1043 | if (fixed_mode) { |
1044 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1045 | goto out; |
1046 | } | |
79e53945 JB |
1047 | } |
1048 | ||
1049 | /* | |
1050 | * If we didn't get EDID, try checking if the panel is already turned | |
1051 | * on. If so, assume that whatever is currently programmed is the | |
1052 | * correct mode. | |
1053 | */ | |
541998a1 | 1054 | |
f2b115e6 | 1055 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1056 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1057 | goto failed; |
1058 | ||
79e53945 JB |
1059 | lvds = I915_READ(LVDS); |
1060 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1061 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1062 | |
1063 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1064 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1065 | if (fixed_mode) { | |
6a9d51b7 CW |
1066 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1067 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1068 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1069 | goto out; |
79e53945 JB |
1070 | } |
1071 | } | |
1072 | ||
1073 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1074 | if (!fixed_mode) |
79e53945 JB |
1075 | goto failed; |
1076 | ||
79e53945 | 1077 | out: |
4da98541 DV |
1078 | mutex_unlock(&dev->mode_config.mutex); |
1079 | ||
7dec0606 | 1080 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1081 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1082 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1083 | ||
24ded204 DV |
1084 | /* |
1085 | * Unlock registers and just | |
1086 | * leave them unlocked | |
1087 | */ | |
c619eed4 | 1088 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1089 | I915_WRITE(PCH_PP_CONTROL, |
1090 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1091 | } else { | |
ed10fca9 KP |
1092 | I915_WRITE(PP_CONTROL, |
1093 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1094 | } |
db1740a0 JN |
1095 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1096 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1097 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1098 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1099 | } |
79e53945 | 1100 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1101 | |
4b6ed685 | 1102 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
0657b6b1 | 1103 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1104 | |
c9093354 | 1105 | return; |
79e53945 JB |
1106 | |
1107 | failed: | |
4da98541 DV |
1108 | mutex_unlock(&dev->mode_config.mutex); |
1109 | ||
8a4c47f3 | 1110 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1111 | drm_connector_cleanup(connector); |
1991bdfa | 1112 | drm_encoder_cleanup(encoder); |
29b99b48 | 1113 | kfree(lvds_encoder); |
c7362c4d | 1114 | kfree(lvds_connector); |
c9093354 | 1115 | return; |
79e53945 | 1116 | } |