Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
13c7d870 | 52 | bool is_dual_link; |
7dec0606 | 53 | u32 reg; |
1f835a77 | 54 | u32 a3_power; |
788319d4 | 55 | |
62165e0d | 56 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
57 | }; |
58 | ||
29b99b48 | 59 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
29b99b48 | 61 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
62 | } |
63 | ||
c7362c4d | 64 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 65 | { |
c7362c4d | 66 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
67 | } |
68 | ||
b1dc332c DV |
69 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
70 | enum pipe *pipe) | |
71 | { | |
72 | struct drm_device *dev = encoder->base.dev; | |
73 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 | 74 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 75 | enum intel_display_power_domain power_domain; |
7dec0606 | 76 | u32 tmp; |
b1dc332c | 77 | |
34a6c70f | 78 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 79 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
34a6c70f PZ |
80 | return false; |
81 | ||
7dec0606 | 82 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
83 | |
84 | if (!(tmp & LVDS_PORT_EN)) | |
85 | return false; | |
86 | ||
87 | if (HAS_PCH_CPT(dev)) | |
88 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
89 | else | |
90 | *pipe = PORT_TO_PIPE(tmp); | |
91 | ||
92 | return true; | |
93 | } | |
94 | ||
045ac3b5 JB |
95 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
96 | struct intel_crtc_config *pipe_config) | |
97 | { | |
98 | struct drm_device *dev = encoder->base.dev; | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | u32 lvds_reg, tmp, flags = 0; | |
18442d08 | 101 | int dotclock; |
045ac3b5 JB |
102 | |
103 | if (HAS_PCH_SPLIT(dev)) | |
104 | lvds_reg = PCH_LVDS; | |
105 | else | |
106 | lvds_reg = LVDS; | |
107 | ||
108 | tmp = I915_READ(lvds_reg); | |
109 | if (tmp & LVDS_HSYNC_POLARITY) | |
110 | flags |= DRM_MODE_FLAG_NHSYNC; | |
111 | else | |
112 | flags |= DRM_MODE_FLAG_PHSYNC; | |
113 | if (tmp & LVDS_VSYNC_POLARITY) | |
114 | flags |= DRM_MODE_FLAG_NVSYNC; | |
115 | else | |
116 | flags |= DRM_MODE_FLAG_PVSYNC; | |
117 | ||
118 | pipe_config->adjusted_mode.flags |= flags; | |
06922821 | 119 | |
6b89cdde DV |
120 | /* gen2/3 store dither state in pfit control, needs to match */ |
121 | if (INTEL_INFO(dev)->gen < 4) { | |
122 | tmp = I915_READ(PFIT_CONTROL); | |
123 | ||
124 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
125 | } | |
126 | ||
18442d08 VS |
127 | dotclock = pipe_config->port_clock; |
128 | ||
129 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
130 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
131 | ||
241bfc38 | 132 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
133 | } |
134 | ||
f6736a1a | 135 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
136 | { |
137 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
138 | struct drm_device *dev = encoder->base.dev; | |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 140 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
4c6df4b4 VS |
141 | const struct drm_display_mode *adjusted_mode = |
142 | &crtc->config.adjusted_mode; | |
55607e8a | 143 | int pipe = crtc->pipe; |
fc683091 DV |
144 | u32 temp; |
145 | ||
55607e8a DV |
146 | if (HAS_PCH_SPLIT(dev)) { |
147 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
148 | assert_shared_dpll_disabled(dev_priv, | |
149 | intel_crtc_to_shared_dpll(crtc)); | |
150 | } else { | |
151 | assert_pll_disabled(dev_priv, pipe); | |
152 | } | |
153 | ||
fc683091 DV |
154 | temp = I915_READ(lvds_encoder->reg); |
155 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
156 | |
157 | if (HAS_PCH_CPT(dev)) { | |
158 | temp &= ~PORT_TRANS_SEL_MASK; | |
159 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 160 | } else { |
62810e5a DV |
161 | if (pipe == 1) { |
162 | temp |= LVDS_PIPEB_SELECT; | |
163 | } else { | |
164 | temp &= ~LVDS_PIPEB_SELECT; | |
165 | } | |
fc683091 | 166 | } |
62810e5a | 167 | |
fc683091 | 168 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 169 | temp &= ~LVDS_BORDER_ENABLE; |
55607e8a | 170 | temp |= crtc->config.gmch_pfit.lvds_border_bits; |
fc683091 DV |
171 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
172 | * set the DPLLs for dual-channel mode or not. | |
173 | */ | |
174 | if (lvds_encoder->is_dual_link) | |
175 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
176 | else | |
177 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
178 | ||
179 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
180 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
181 | * panels behave in the two modes. For now, let's just maintain the |
182 | * value we got from the BIOS. | |
fc683091 | 183 | */ |
1f835a77 PZ |
184 | temp &= ~LVDS_A3_POWER_MASK; |
185 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
186 | |
187 | /* Set the dithering flag on LVDS as needed, note that there is no | |
188 | * special lvds dither control bit on pch-split platforms, dithering is | |
189 | * only controlled through the PIPECONF reg. */ | |
190 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
191 | /* Bspec wording suggests that LVDS port dithering only exists |
192 | * for 18bpp panels. */ | |
55607e8a | 193 | if (crtc->config.dither && crtc->config.pipe_bpp == 18) |
fc683091 DV |
194 | temp |= LVDS_ENABLE_DITHER; |
195 | else | |
196 | temp &= ~LVDS_ENABLE_DITHER; | |
197 | } | |
198 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 199 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 200 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 201 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
202 | temp |= LVDS_VSYNC_POLARITY; |
203 | ||
204 | I915_WRITE(lvds_encoder->reg, temp); | |
205 | } | |
206 | ||
79e53945 JB |
207 | /** |
208 | * Sets the power state for the panel. | |
209 | */ | |
c22834ec | 210 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 211 | { |
c22834ec | 212 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 213 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
214 | struct intel_connector *intel_connector = |
215 | &lvds_encoder->attached_connector->base; | |
79e53945 | 216 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 217 | u32 ctl_reg, stat_reg; |
541998a1 | 218 | |
c619eed4 | 219 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 220 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 221 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
222 | } else { |
223 | ctl_reg = PP_CONTROL; | |
de842eff | 224 | stat_reg = PP_STATUS; |
541998a1 | 225 | } |
79e53945 | 226 | |
7dec0606 | 227 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 228 | |
2a1292fd | 229 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 230 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
231 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
232 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 233 | |
752aa88a | 234 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
235 | } |
236 | ||
c22834ec | 237 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 238 | { |
c22834ec | 239 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 240 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
241 | struct intel_connector *intel_connector = |
242 | &lvds_encoder->attached_connector->base; | |
2a1292fd | 243 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 244 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
245 | |
246 | if (HAS_PCH_SPLIT(dev)) { | |
247 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 248 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
249 | } else { |
250 | ctl_reg = PP_CONTROL; | |
de842eff | 251 | stat_reg = PP_STATUS; |
2a1292fd CW |
252 | } |
253 | ||
752aa88a | 254 | intel_panel_disable_backlight(intel_connector); |
2a1292fd CW |
255 | |
256 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
257 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
258 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 259 | |
7dec0606 DV |
260 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
261 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
262 | } |
263 | ||
c19de8eb DL |
264 | static enum drm_mode_status |
265 | intel_lvds_mode_valid(struct drm_connector *connector, | |
266 | struct drm_display_mode *mode) | |
79e53945 | 267 | { |
dd06f90e JN |
268 | struct intel_connector *intel_connector = to_intel_connector(connector); |
269 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 270 | |
788319d4 CW |
271 | if (mode->hdisplay > fixed_mode->hdisplay) |
272 | return MODE_PANEL; | |
273 | if (mode->vdisplay > fixed_mode->vdisplay) | |
274 | return MODE_PANEL; | |
79e53945 JB |
275 | |
276 | return MODE_OK; | |
277 | } | |
278 | ||
7ae89233 DV |
279 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
280 | struct intel_crtc_config *pipe_config) | |
79e53945 | 281 | { |
7ae89233 | 282 | struct drm_device *dev = intel_encoder->base.dev; |
7ae89233 DV |
283 | struct intel_lvds_encoder *lvds_encoder = |
284 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
285 | struct intel_connector *intel_connector = |
286 | &lvds_encoder->attached_connector->base; | |
7ae89233 | 287 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
29b99b48 | 288 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
4e53c2e0 | 289 | unsigned int lvds_bpp; |
79e53945 JB |
290 | |
291 | /* Should never happen!! */ | |
a6c45cf0 | 292 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 293 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
294 | return false; |
295 | } | |
296 | ||
1f835a77 | 297 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
298 | lvds_bpp = 8*3; |
299 | else | |
300 | lvds_bpp = 6*3; | |
301 | ||
e29c22c0 | 302 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
303 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
304 | pipe_config->pipe_bpp, lvds_bpp); | |
305 | pipe_config->pipe_bpp = lvds_bpp; | |
306 | } | |
d8b32247 | 307 | |
79e53945 | 308 | /* |
71677043 | 309 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
310 | * to the adjusted mode. The CRTC will be set up for this mode, |
311 | * with the panel scaling set up to source from the H/VDisplay | |
312 | * of the original mode. | |
313 | */ | |
4d891523 | 314 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 315 | adjusted_mode); |
1d8e1c75 CW |
316 | |
317 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
318 | pipe_config->has_pch_encoder = true; |
319 | ||
b074cec8 JB |
320 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
321 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
322 | } else { |
323 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
324 | intel_connector->panel.fitting_mode); | |
79e53945 | 325 | |
21d8a475 | 326 | } |
f9bef081 | 327 | |
79e53945 JB |
328 | /* |
329 | * XXX: It would be nice to support lower refresh rates on the | |
330 | * panels to reduce power consumption, and perhaps match the | |
331 | * user's requested refresh rate. | |
332 | */ | |
333 | ||
334 | return true; | |
335 | } | |
336 | ||
79e53945 JB |
337 | /** |
338 | * Detect the LVDS connection. | |
339 | * | |
b42d4c5c JB |
340 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
341 | * connected and closed means disconnected. We also send hotplug events as | |
342 | * needed, using lid status notification from the input layer. | |
79e53945 | 343 | */ |
7b334fcb | 344 | static enum drm_connector_status |
930a9e28 | 345 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 346 | { |
7b9c5abe | 347 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 348 | enum drm_connector_status status; |
b42d4c5c | 349 | |
164c8598 | 350 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 351 | connector->base.id, connector->name); |
164c8598 | 352 | |
fe16d949 CW |
353 | status = intel_panel_detect(dev); |
354 | if (status != connector_status_unknown) | |
355 | return status; | |
01fe9dbd | 356 | |
6ee3b5a1 | 357 | return connector_status_connected; |
79e53945 JB |
358 | } |
359 | ||
360 | /** | |
361 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
362 | */ | |
363 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
364 | { | |
62165e0d | 365 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 366 | struct drm_device *dev = connector->dev; |
788319d4 | 367 | struct drm_display_mode *mode; |
79e53945 | 368 | |
9cd300e0 | 369 | /* use cached edid if we have one */ |
2aa4f099 | 370 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 371 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 372 | |
dd06f90e | 373 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 374 | if (mode == NULL) |
788319d4 | 375 | return 0; |
79e53945 | 376 | |
788319d4 CW |
377 | drm_mode_probed_add(connector, mode); |
378 | return 1; | |
79e53945 JB |
379 | } |
380 | ||
0544edfd TB |
381 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
382 | { | |
bc0daf48 | 383 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
384 | return 1; |
385 | } | |
386 | ||
387 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
388 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
389 | { | |
390 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
391 | .ident = "Toshiba Tecra A11", | |
392 | .matches = { | |
393 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
394 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
395 | }, | |
396 | }, | |
397 | ||
398 | { } /* terminating entry */ | |
399 | }; | |
400 | ||
c9354c85 | 401 | /* |
b8efb17b ZR |
402 | * Lid events. Note the use of 'modeset': |
403 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
404 | * and set it to MODESET_DONE on open | |
c9354c85 | 405 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
406 | * duplicate events where it was already properly set) |
407 | * - the suspend/resume paths will set it to | |
408 | * MODESET_SUSPENDED and ignore the lid open event, | |
409 | * because they restore the mode ("lid open"). | |
c9354c85 | 410 | */ |
c1c7af60 JB |
411 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
412 | void *unused) | |
413 | { | |
db1740a0 JN |
414 | struct intel_lvds_connector *lvds_connector = |
415 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
416 | struct drm_connector *connector = &lvds_connector->base.base; | |
417 | struct drm_device *dev = connector->dev; | |
418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 419 | |
2fb4e61d AW |
420 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
421 | return NOTIFY_OK; | |
422 | ||
b8efb17b ZR |
423 | mutex_lock(&dev_priv->modeset_restore_lock); |
424 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
425 | goto exit; | |
a2565377 ZY |
426 | /* |
427 | * check and update the status of LVDS connector after receiving | |
428 | * the LID nofication event. | |
429 | */ | |
db1740a0 | 430 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 431 | |
0544edfd TB |
432 | /* Don't force modeset on machines where it causes a GPU lockup */ |
433 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 434 | goto exit; |
c9354c85 | 435 | if (!acpi_lid_open()) { |
b8efb17b ZR |
436 | /* do modeset on next lid open event */ |
437 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
438 | goto exit; | |
06891e27 | 439 | } |
c1c7af60 | 440 | |
b8efb17b ZR |
441 | if (dev_priv->modeset_restore == MODESET_DONE) |
442 | goto exit; | |
c9354c85 | 443 | |
5be19d91 DV |
444 | /* |
445 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
446 | * We try to detect this here and undo any damage. The split for PCH | |
447 | * platforms is rather conservative and a bit arbitrary expect that on | |
448 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
449 | * and as part of the cleanup in the hw state restore we also redisable | |
450 | * the vga plane. | |
451 | */ | |
452 | if (!HAS_PCH_SPLIT(dev)) { | |
453 | drm_modeset_lock_all(dev); | |
454 | intel_modeset_setup_hw_state(dev, true); | |
455 | drm_modeset_unlock_all(dev); | |
456 | } | |
06324194 | 457 | |
b8efb17b ZR |
458 | dev_priv->modeset_restore = MODESET_DONE; |
459 | ||
460 | exit: | |
461 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
462 | return NOTIFY_OK; |
463 | } | |
464 | ||
79e53945 JB |
465 | /** |
466 | * intel_lvds_destroy - unregister and free LVDS structures | |
467 | * @connector: connector to free | |
468 | * | |
469 | * Unregister the DDC bus for this connector then free the driver private | |
470 | * structure. | |
471 | */ | |
472 | static void intel_lvds_destroy(struct drm_connector *connector) | |
473 | { | |
db1740a0 JN |
474 | struct intel_lvds_connector *lvds_connector = |
475 | to_lvds_connector(connector); | |
79e53945 | 476 | |
db1740a0 JN |
477 | if (lvds_connector->lid_notifier.notifier_call) |
478 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 479 | |
9cd300e0 JN |
480 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
481 | kfree(lvds_connector->base.edid); | |
482 | ||
1d508706 | 483 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 484 | |
79e53945 JB |
485 | drm_connector_cleanup(connector); |
486 | kfree(connector); | |
487 | } | |
488 | ||
335041ed JB |
489 | static int intel_lvds_set_property(struct drm_connector *connector, |
490 | struct drm_property *property, | |
491 | uint64_t value) | |
492 | { | |
4d891523 | 493 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 494 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 495 | |
788319d4 | 496 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 497 | struct drm_crtc *crtc; |
bb8a3560 | 498 | |
53bd8389 JB |
499 | if (value == DRM_MODE_SCALE_NONE) { |
500 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 501 | return -EINVAL; |
3fbe18d6 | 502 | } |
788319d4 | 503 | |
4d891523 | 504 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
505 | /* the LVDS scaling property is not changed */ |
506 | return 0; | |
507 | } | |
4d891523 | 508 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
509 | |
510 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
511 | if (crtc && crtc->enabled) { |
512 | /* | |
513 | * If the CRTC is enabled, the display will be changed | |
514 | * according to the new panel fitting mode. | |
515 | */ | |
c0c36b94 | 516 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
517 | } |
518 | } | |
519 | ||
335041ed JB |
520 | return 0; |
521 | } | |
522 | ||
79e53945 JB |
523 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
524 | .get_modes = intel_lvds_get_modes, | |
525 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 526 | .best_encoder = intel_best_encoder, |
79e53945 JB |
527 | }; |
528 | ||
529 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 530 | .dpms = intel_connector_dpms, |
79e53945 JB |
531 | .detect = intel_lvds_detect, |
532 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 533 | .set_property = intel_lvds_set_property, |
79e53945 JB |
534 | .destroy = intel_lvds_destroy, |
535 | }; | |
536 | ||
79e53945 | 537 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 538 | .destroy = intel_encoder_destroy, |
79e53945 JB |
539 | }; |
540 | ||
bbe1c274 | 541 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 542 | { |
bc0daf48 | 543 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
544 | return 1; |
545 | } | |
79e53945 | 546 | |
425d244c | 547 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 548 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
549 | { |
550 | .callback = intel_no_lvds_dmi_callback, | |
551 | .ident = "Apple Mac Mini (Core series)", | |
552 | .matches = { | |
98acd46f | 553 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
554 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
555 | }, | |
556 | }, | |
557 | { | |
558 | .callback = intel_no_lvds_dmi_callback, | |
559 | .ident = "Apple Mac Mini (Core 2 series)", | |
560 | .matches = { | |
98acd46f | 561 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
562 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
563 | }, | |
564 | }, | |
565 | { | |
566 | .callback = intel_no_lvds_dmi_callback, | |
567 | .ident = "MSI IM-945GSE-A", | |
568 | .matches = { | |
569 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
570 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
571 | }, | |
572 | }, | |
573 | { | |
574 | .callback = intel_no_lvds_dmi_callback, | |
575 | .ident = "Dell Studio Hybrid", | |
576 | .matches = { | |
577 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
578 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
579 | }, | |
580 | }, | |
70aa96ca JW |
581 | { |
582 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
583 | .ident = "Dell OptiPlex FX170", |
584 | .matches = { | |
585 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
586 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
587 | }, | |
588 | }, | |
589 | { | |
590 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
591 | .ident = "AOpen Mini PC", |
592 | .matches = { | |
593 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
594 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
595 | }, | |
596 | }, | |
ed8c754b TV |
597 | { |
598 | .callback = intel_no_lvds_dmi_callback, | |
599 | .ident = "AOpen Mini PC MP915", | |
600 | .matches = { | |
601 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
602 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
603 | }, | |
604 | }, | |
22ab70d3 KP |
605 | { |
606 | .callback = intel_no_lvds_dmi_callback, | |
607 | .ident = "AOpen i915GMm-HFS", | |
608 | .matches = { | |
609 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
610 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
611 | }, | |
612 | }, | |
e57b6886 DV |
613 | { |
614 | .callback = intel_no_lvds_dmi_callback, | |
615 | .ident = "AOpen i45GMx-I", | |
616 | .matches = { | |
617 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
618 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
619 | }, | |
620 | }, | |
fa0864b2 MC |
621 | { |
622 | .callback = intel_no_lvds_dmi_callback, | |
623 | .ident = "Aopen i945GTt-VFA", | |
624 | .matches = { | |
625 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
626 | }, | |
627 | }, | |
9875557e SB |
628 | { |
629 | .callback = intel_no_lvds_dmi_callback, | |
630 | .ident = "Clientron U800", | |
631 | .matches = { | |
632 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
633 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
634 | }, | |
635 | }, | |
6a574b5b | 636 | { |
44306ab3 JS |
637 | .callback = intel_no_lvds_dmi_callback, |
638 | .ident = "Clientron E830", | |
639 | .matches = { | |
640 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
641 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
642 | }, | |
643 | }, | |
644 | { | |
6a574b5b HG |
645 | .callback = intel_no_lvds_dmi_callback, |
646 | .ident = "Asus EeeBox PC EB1007", | |
647 | .matches = { | |
648 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
649 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
650 | }, | |
651 | }, | |
0999bbe0 AJ |
652 | { |
653 | .callback = intel_no_lvds_dmi_callback, | |
654 | .ident = "Asus AT5NM10T-I", | |
655 | .matches = { | |
656 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
657 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
658 | }, | |
659 | }, | |
33471119 JBG |
660 | { |
661 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 662 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
663 | .matches = { |
664 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 665 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
666 | }, |
667 | }, | |
f5b8a7ed MG |
668 | { |
669 | .callback = intel_no_lvds_dmi_callback, | |
670 | .ident = "Hewlett-Packard t5745", | |
671 | .matches = { | |
672 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 673 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
674 | }, |
675 | }, | |
676 | { | |
677 | .callback = intel_no_lvds_dmi_callback, | |
678 | .ident = "Hewlett-Packard st5747", | |
679 | .matches = { | |
680 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 681 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
682 | }, |
683 | }, | |
97effadb AA |
684 | { |
685 | .callback = intel_no_lvds_dmi_callback, | |
686 | .ident = "MSI Wind Box DC500", | |
687 | .matches = { | |
688 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
689 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
690 | }, | |
691 | }, | |
a51d4ed0 CW |
692 | { |
693 | .callback = intel_no_lvds_dmi_callback, | |
694 | .ident = "Gigabyte GA-D525TUD", | |
695 | .matches = { | |
696 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
697 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
698 | }, | |
699 | }, | |
c31407a3 CW |
700 | { |
701 | .callback = intel_no_lvds_dmi_callback, | |
702 | .ident = "Supermicro X7SPA-H", | |
703 | .matches = { | |
704 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
705 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
706 | }, | |
707 | }, | |
9e9dd0e8 CL |
708 | { |
709 | .callback = intel_no_lvds_dmi_callback, | |
710 | .ident = "Fujitsu Esprimo Q900", | |
711 | .matches = { | |
712 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
713 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
714 | }, | |
715 | }, | |
645378d8 RP |
716 | { |
717 | .callback = intel_no_lvds_dmi_callback, | |
718 | .ident = "Intel D410PT", | |
719 | .matches = { | |
720 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
721 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
722 | }, | |
723 | }, | |
724 | { | |
725 | .callback = intel_no_lvds_dmi_callback, | |
726 | .ident = "Intel D425KT", | |
727 | .matches = { | |
728 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
729 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
730 | }, | |
731 | }, | |
e5614f0c CW |
732 | { |
733 | .callback = intel_no_lvds_dmi_callback, | |
734 | .ident = "Intel D510MO", | |
735 | .matches = { | |
736 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
737 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
738 | }, | |
739 | }, | |
dcf6d294 JN |
740 | { |
741 | .callback = intel_no_lvds_dmi_callback, | |
742 | .ident = "Intel D525MW", | |
743 | .matches = { | |
744 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
745 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
746 | }, | |
747 | }, | |
425d244c JW |
748 | |
749 | { } /* terminating entry */ | |
750 | }; | |
79e53945 | 751 | |
7cf4f69d ZY |
752 | /* |
753 | * Enumerate the child dev array parsed from VBT to check whether | |
754 | * the LVDS is present. | |
755 | * If it is present, return 1. | |
756 | * If it is not present, return false. | |
757 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 758 | */ |
270eea0f CW |
759 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
760 | u8 *i2c_pin) | |
7cf4f69d ZY |
761 | { |
762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 763 | int i; |
7cf4f69d | 764 | |
41aa3448 | 765 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 766 | return true; |
7cf4f69d | 767 | |
41aa3448 | 768 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
769 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
770 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
771 | |
772 | /* If the device type is not LFP, continue. | |
773 | * We have to check both the new identifiers as well as the | |
774 | * old for compatibility with some BIOSes. | |
7cf4f69d | 775 | */ |
425904dd CW |
776 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
777 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
778 | continue; |
779 | ||
3bd7d909 DK |
780 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
781 | *i2c_pin = child->i2c_pin; | |
270eea0f | 782 | |
425904dd CW |
783 | /* However, we cannot trust the BIOS writers to populate |
784 | * the VBT correctly. Since LVDS requires additional | |
785 | * information from AIM blocks, a non-zero addin offset is | |
786 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 787 | */ |
425904dd CW |
788 | if (child->addin_offset) |
789 | return true; | |
790 | ||
791 | /* But even then some BIOS writers perform some black magic | |
792 | * and instantiate the device without reference to any | |
793 | * additional data. Trust that if the VBT was written into | |
794 | * the OpRegion then they have validated the LVDS's existence. | |
795 | */ | |
796 | if (dev_priv->opregion.vbt) | |
797 | return true; | |
7cf4f69d | 798 | } |
425904dd CW |
799 | |
800 | return false; | |
7cf4f69d ZY |
801 | } |
802 | ||
1974cad0 DV |
803 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
804 | { | |
805 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
806 | return 1; | |
807 | } | |
808 | ||
809 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
810 | { | |
811 | .callback = intel_dual_link_lvds_callback, | |
812 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
813 | .matches = { | |
814 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
815 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
816 | }, | |
817 | }, | |
818 | { } /* terminating entry */ | |
819 | }; | |
820 | ||
821 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
822 | { |
823 | struct intel_encoder *encoder; | |
824 | struct intel_lvds_encoder *lvds_encoder; | |
825 | ||
b2784e15 | 826 | for_each_intel_encoder(dev, encoder) { |
13c7d870 DV |
827 | if (encoder->type == INTEL_OUTPUT_LVDS) { |
828 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
829 | ||
830 | return lvds_encoder->is_dual_link; | |
831 | } | |
832 | } | |
833 | ||
834 | return false; | |
835 | } | |
836 | ||
7dec0606 | 837 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 838 | { |
7dec0606 | 839 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
840 | unsigned int val; |
841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
842 | |
843 | /* use the module option value if specified */ | |
d330a953 JN |
844 | if (i915.lvds_channel_mode > 0) |
845 | return i915.lvds_channel_mode == 2; | |
1974cad0 DV |
846 | |
847 | if (dmi_check_system(intel_dual_link_lvds)) | |
848 | return true; | |
849 | ||
13c7d870 DV |
850 | /* BIOS should set the proper LVDS register value at boot, but |
851 | * in reality, it doesn't set the value when the lid is closed; | |
852 | * we need to check "the value to be set" in VBT when LVDS | |
853 | * register is uninitialized. | |
854 | */ | |
7dec0606 | 855 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 856 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 857 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 858 | |
1974cad0 DV |
859 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
860 | } | |
861 | ||
f3cfcba6 CW |
862 | static bool intel_lvds_supported(struct drm_device *dev) |
863 | { | |
864 | /* With the introduction of the PCH we gained a dedicated | |
865 | * LVDS presence pin, use it. */ | |
311e359c | 866 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
867 | return true; |
868 | ||
869 | /* Otherwise LVDS was only attached to mobile products, | |
870 | * except for the inglorious 830gm */ | |
311e359c PZ |
871 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
872 | return true; | |
873 | ||
874 | return false; | |
f3cfcba6 CW |
875 | } |
876 | ||
79e53945 JB |
877 | /** |
878 | * intel_lvds_init - setup LVDS connectors on this device | |
879 | * @dev: drm device | |
880 | * | |
881 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
882 | * modes we can display on the LVDS panel (if present). | |
883 | */ | |
c9093354 | 884 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
885 | { |
886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 887 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 888 | struct intel_encoder *intel_encoder; |
c7362c4d | 889 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 890 | struct intel_connector *intel_connector; |
79e53945 JB |
891 | struct drm_connector *connector; |
892 | struct drm_encoder *encoder; | |
893 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 894 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 895 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 896 | struct edid *edid; |
79e53945 JB |
897 | struct drm_crtc *crtc; |
898 | u32 lvds; | |
270eea0f CW |
899 | int pipe; |
900 | u8 pin; | |
79e53945 | 901 | |
b0616c53 DV |
902 | /* |
903 | * Unlock registers and just leave them unlocked. Do this before | |
904 | * checking quirk lists to avoid bogus WARNINGs. | |
905 | */ | |
906 | if (HAS_PCH_SPLIT(dev)) { | |
907 | I915_WRITE(PCH_PP_CONTROL, | |
908 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
909 | } else { | |
910 | I915_WRITE(PP_CONTROL, | |
911 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
912 | } | |
f3cfcba6 | 913 | if (!intel_lvds_supported(dev)) |
c9093354 | 914 | return; |
f3cfcba6 | 915 | |
425d244c JW |
916 | /* Skip init on machines we know falsely report LVDS */ |
917 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 918 | return; |
565dcd46 | 919 | |
270eea0f CW |
920 | pin = GMBUS_PORT_PANEL; |
921 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 922 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 923 | return; |
38b3037e | 924 | } |
e99da35f | 925 | |
c619eed4 | 926 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 927 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 928 | return; |
41aa3448 | 929 | if (dev_priv->vbt.edp_support) { |
28c97730 | 930 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 931 | return; |
32f9d658 | 932 | } |
541998a1 ZW |
933 | } |
934 | ||
b14c5679 | 935 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 936 | if (!lvds_encoder) |
c9093354 | 937 | return; |
79e53945 | 938 | |
b14c5679 | 939 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 940 | if (!lvds_connector) { |
29b99b48 | 941 | kfree(lvds_encoder); |
c9093354 | 942 | return; |
bb8a3560 ZW |
943 | } |
944 | ||
62165e0d JN |
945 | lvds_encoder->attached_connector = lvds_connector; |
946 | ||
29b99b48 | 947 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 948 | encoder = &intel_encoder->base; |
c7362c4d | 949 | intel_connector = &lvds_connector->base; |
ea5b213a | 950 | connector = &intel_connector->base; |
bb8a3560 | 951 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
952 | DRM_MODE_CONNECTOR_LVDS); |
953 | ||
4ef69c7a | 954 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
955 | DRM_MODE_ENCODER_LVDS); |
956 | ||
c22834ec | 957 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 958 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 959 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 960 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 961 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 962 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 963 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 964 | intel_connector->unregister = intel_connector_unregister; |
c22834ec | 965 | |
df0e9248 | 966 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 967 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 968 | |
bc079e8b | 969 | intel_encoder->cloneable = 0; |
27f8227b JB |
970 | if (HAS_PCH_SPLIT(dev)) |
971 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
972 | else if (IS_GEN4(dev)) |
973 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
974 | else |
975 | intel_encoder->crtc_mask = (1 << 1); | |
976 | ||
79e53945 JB |
977 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
978 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
979 | connector->interlace_allowed = false; | |
980 | connector->doublescan_allowed = false; | |
981 | ||
7dec0606 DV |
982 | if (HAS_PCH_SPLIT(dev)) { |
983 | lvds_encoder->reg = PCH_LVDS; | |
984 | } else { | |
985 | lvds_encoder->reg = LVDS; | |
986 | } | |
987 | ||
3fbe18d6 ZY |
988 | /* create the scaling mode property */ |
989 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 990 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 991 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 992 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 993 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
994 | /* |
995 | * LVDS discovery: | |
996 | * 1) check for EDID on DDC | |
997 | * 2) check for VBT data | |
998 | * 3) check to see if LVDS is already on | |
999 | * if none of the above, no panel | |
1000 | * 4) make sure lid is open | |
1001 | * if closed, act like it's not there for now | |
1002 | */ | |
1003 | ||
79e53945 JB |
1004 | /* |
1005 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1006 | * preferred mode is the right one. | |
1007 | */ | |
4da98541 | 1008 | mutex_lock(&dev->mode_config.mutex); |
9cd300e0 JN |
1009 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1010 | if (edid) { | |
1011 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1012 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1013 | edid); |
3f8ff0e7 | 1014 | } else { |
9cd300e0 JN |
1015 | kfree(edid); |
1016 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1017 | } |
9cd300e0 JN |
1018 | } else { |
1019 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1020 | } |
9cd300e0 JN |
1021 | lvds_connector->base.edid = edid; |
1022 | ||
1023 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1024 | /* Didn't get an EDID, so |
1025 | * Set wide sync ranges so we get all modes | |
1026 | * handed to valid_mode for checking | |
1027 | */ | |
1028 | connector->display_info.min_vfreq = 0; | |
1029 | connector->display_info.max_vfreq = 200; | |
1030 | connector->display_info.min_hfreq = 0; | |
1031 | connector->display_info.max_hfreq = 200; | |
1032 | } | |
79e53945 JB |
1033 | |
1034 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1035 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1036 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1037 | drm_mode_debug_printmodeline(scan); | |
1038 | ||
dd06f90e | 1039 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 | 1040 | if (fixed_mode) { |
4b6ed685 | 1041 | downclock_mode = |
ec9ed197 VK |
1042 | intel_find_panel_downclock(dev, |
1043 | fixed_mode, connector); | |
4b6ed685 VK |
1044 | if (downclock_mode != NULL && |
1045 | i915.lvds_downclock) { | |
ec9ed197 VK |
1046 | /* We found the downclock for LVDS. */ |
1047 | dev_priv->lvds_downclock_avail = true; | |
1048 | dev_priv->lvds_downclock = | |
ec9ed197 VK |
1049 | downclock_mode->clock; |
1050 | DRM_DEBUG_KMS("LVDS downclock is found" | |
1051 | " in EDID. Normal clock %dKhz, " | |
1052 | "downclock %dKhz\n", | |
1053 | fixed_mode->clock, | |
1054 | dev_priv->lvds_downclock); | |
1055 | } | |
6a9d51b7 CW |
1056 | goto out; |
1057 | } | |
79e53945 | 1058 | } |
79e53945 JB |
1059 | } |
1060 | ||
1061 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1062 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1063 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1064 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1065 | |
41aa3448 | 1066 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1067 | if (fixed_mode) { |
1068 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1069 | goto out; |
1070 | } | |
79e53945 JB |
1071 | } |
1072 | ||
1073 | /* | |
1074 | * If we didn't get EDID, try checking if the panel is already turned | |
1075 | * on. If so, assume that whatever is currently programmed is the | |
1076 | * correct mode. | |
1077 | */ | |
541998a1 | 1078 | |
f2b115e6 | 1079 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1080 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1081 | goto failed; |
1082 | ||
79e53945 JB |
1083 | lvds = I915_READ(LVDS); |
1084 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1085 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1086 | |
1087 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1088 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1089 | if (fixed_mode) { | |
6a9d51b7 CW |
1090 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1091 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1092 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1093 | goto out; |
79e53945 JB |
1094 | } |
1095 | } | |
1096 | ||
1097 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1098 | if (!fixed_mode) |
79e53945 JB |
1099 | goto failed; |
1100 | ||
79e53945 | 1101 | out: |
4da98541 DV |
1102 | mutex_unlock(&dev->mode_config.mutex); |
1103 | ||
7dec0606 | 1104 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1105 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1106 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1107 | ||
1f835a77 PZ |
1108 | lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) & |
1109 | LVDS_A3_POWER_MASK; | |
1110 | ||
db1740a0 JN |
1111 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1112 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1113 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1114 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1115 | } |
34ea3d38 | 1116 | drm_connector_register(connector); |
aaa6fd2a | 1117 | |
4b6ed685 | 1118 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
6517d273 | 1119 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
aaa6fd2a | 1120 | |
c9093354 | 1121 | return; |
79e53945 JB |
1122 | |
1123 | failed: | |
4da98541 DV |
1124 | mutex_unlock(&dev->mode_config.mutex); |
1125 | ||
8a4c47f3 | 1126 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1127 | drm_connector_cleanup(connector); |
1991bdfa | 1128 | drm_encoder_cleanup(encoder); |
29b99b48 | 1129 | kfree(lvds_encoder); |
c7362c4d | 1130 | kfree(lvds_connector); |
c9093354 | 1131 | return; |
79e53945 | 1132 | } |