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drm/i915: Propagate errors from writing to ringbuffer
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
23f09ce3
CW		 173struct intel_overlay {
174 struct drm_device *dev;
175 struct intel_crtc *crtc;
176 struct drm_i915_gem_object *vid_bo;
177 struct drm_i915_gem_object *old_vid_bo;
178 int active;
179 int pfit_active;
180 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
181 u32 color_key;
182 u32 brightness, contrast, saturation;
183 u32 old_xscale, old_yscale;
184 /* register access */
185 u32 flip_addr;
186 struct drm_i915_gem_object *reg_bo;
187 /* flip handling */
188 uint32_t last_flip_req;
b303cf95 189 void (*flip_tail)(struct intel_overlay *);
23f09ce3 190};
02e792fb 191
8d74f656
CW		 192static struct overlay_registers *
193intel_overlay_map_regs(struct intel_overlay *overlay)
02e792fb
DV		 194{
195 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
196 struct overlay_registers *regs;
197
9bb2ff73 198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656 199 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 200 else
8d74f656
CW		 201 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
202 overlay->reg_bo->gtt_offset);
02e792fb 203
9bb2ff73 204 return regs;
8d74f656 205}
02e792fb 206
9bb2ff73
CW		 207static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
208 struct overlay_registers *regs)
8d74f656
CW		 209{
210 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 211 io_mapping_unmap(regs);
02e792fb
DV		 212}
213
b6c028e0 214static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
8dc5d147 215 struct drm_i915_gem_request *request,
b6c028e0 216 bool interruptible,
b303cf95 217 void (*tail)(struct intel_overlay *))
02e792fb
DV		 218{
219 struct drm_device *dev = overlay->dev;
852835f3 220 drm_i915_private_t *dev_priv = dev->dev_private;
b6c028e0 221 int ret;
02e792fb 222
b303cf95 223 BUG_ON(overlay->last_flip_req);
852835f3 224 overlay->last_flip_req =
8dc5d147 225 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
03f77ea5
DV		 226 if (overlay->last_flip_req == 0)
227 return -ENOMEM;
02e792fb 228
b303cf95 229 overlay->flip_tail = tail;
852835f3 230 ret = i915_do_wait_request(dev,
722506f0
CW		 231 overlay->last_flip_req, true,
232 &dev_priv->render_ring);
b6c028e0 233 if (ret)
03f77ea5 234 return ret;
02e792fb 235
03f77ea5 236 overlay->last_flip_req = 0;
02e792fb 237 return 0;
02e792fb
DV		 238}
239
106dadac
CW		 240/* Workaround for i830 bug where pipe a must be enable to change control regs */
241static int
242i830_activate_pipe_a(struct drm_device *dev)
02e792fb 243{
106dadac
CW		 244 drm_i915_private_t *dev_priv = dev->dev_private;
245 struct intel_crtc *crtc;
246 struct drm_crtc_helper_funcs *crtc_funcs;
247 struct drm_display_mode vesa_640x480 = {
248 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
249 752, 800, 0, 480, 489, 492, 525, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
251 }, *mode;
252
253 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
254 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
255 return 0;
02e792fb 256
106dadac 257 /* most i8xx have pipe a forced on, so don't trust dpms mode */
5eddb70b 258 if (I915_READ(PIPEACONF) & PIPECONF_ENABLE)
106dadac 259 return 0;
02e792fb 260
106dadac
CW		 261 crtc_funcs = crtc->base.helper_private;
262 if (crtc_funcs->dpms == NULL)
263 return 0;
264
265 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
266
267 mode = drm_mode_duplicate(dev, &vesa_640x480);
268 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
269 if(!drm_crtc_helper_set_mode(&crtc->base, mode,
270 crtc->base.x, crtc->base.y,
271 crtc->base.fb))
272 return 0;
273
274 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
275 return 1;
276}
277
278static void
279i830_deactivate_pipe_a(struct drm_device *dev)
280{
281 drm_i915_private_t *dev_priv = dev->dev_private;
282 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
283 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
284
285 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
02e792fb
DV		 286}
287
288/* overlay needs to be disable in OCMD reg */
289static int intel_overlay_on(struct intel_overlay *overlay)
290{
291 struct drm_device *dev = overlay->dev;
e1f99ce6 292 struct drm_i915_private *dev_priv = dev->dev_private;
8dc5d147 293 struct drm_i915_gem_request *request;
106dadac 294 int pipe_a_quirk = 0;
02e792fb 295 int ret;
02e792fb
DV		 296
297 BUG_ON(overlay->active);
03f77ea5 298 overlay->active = 1;
b6c028e0 299
106dadac
CW		 300 if (IS_I830(dev)) {
301 pipe_a_quirk = i830_activate_pipe_a(dev);
302 if (pipe_a_quirk < 0)
303 return pipe_a_quirk;
304 }
305
8dc5d147 306 request = kzalloc(sizeof(*request), GFP_KERNEL);
106dadac
CW		 307 if (request == NULL) {
308 ret = -ENOMEM;
309 goto out;
310 }
03f77ea5 311
e1f99ce6
CW		 312 ret = BEGIN_LP_RING(4);
313 if (ret) {
314 kfree(request);
315 goto out;
316 }
317
02e792fb
DV		 318 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
319 OUT_RING(overlay->flip_addr | OFC_UPDATE);
320 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
321 OUT_RING(MI_NOOP);
322 ADVANCE_LP_RING();
323
b303cf95 324 ret = intel_overlay_do_wait_request(overlay, request, true, NULL);
106dadac
CW		 325out:
326 if (pipe_a_quirk)
327 i830_deactivate_pipe_a(dev);
02e792fb 328
106dadac 329 return ret;
02e792fb
DV		 330}
331
332/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 333static int intel_overlay_continue(struct intel_overlay *overlay,
334 bool load_polyphase_filter)
02e792fb
DV		 335{
336 struct drm_device *dev = overlay->dev;
337 drm_i915_private_t *dev_priv = dev->dev_private;
8dc5d147 338 struct drm_i915_gem_request *request;
02e792fb
DV		 339 u32 flip_addr = overlay->flip_addr;
340 u32 tmp;
e1f99ce6 341 int ret;
02e792fb
DV		 342
343 BUG_ON(!overlay->active);
344
8dc5d147
CW		 345 request = kzalloc(sizeof(*request), GFP_KERNEL);
346 if (request == NULL)
347 return -ENOMEM;
348
02e792fb
DV		 349 if (load_polyphase_filter)
350 flip_addr |= OFC_UPDATE;
351
352 /* check for underruns */
353 tmp = I915_READ(DOVSTA);
354 if (tmp & (1 << 17))
355 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
356
e1f99ce6
CW		 357 ret = BEGIN_LP_RING(2);
358 if (ret) {
359 kfree(request);
360 return ret;
361 }
02e792fb
DV		 362 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
363 OUT_RING(flip_addr);
5a5a0c64
DV		 364 ADVANCE_LP_RING();
365
852835f3 366 overlay->last_flip_req =
8dc5d147
CW		 367 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
368 return 0;
5a5a0c64
DV		 369}
370
b303cf95 371static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
5a5a0c64 372{
b303cf95 373 struct drm_gem_object *obj = &overlay->old_vid_bo->base;
5a5a0c64 374
b303cf95
CW		 375 i915_gem_object_unpin(obj);
376 drm_gem_object_unreference(obj);
5a5a0c64 377
b303cf95
CW		 378 overlay->old_vid_bo = NULL;
379}
03f77ea5 380
b303cf95
CW		 381static void intel_overlay_off_tail(struct intel_overlay *overlay)
382{
383 struct drm_gem_object *obj;
02e792fb 384
b303cf95
CW		 385 /* never have the overlay hw on without showing a frame */
386 BUG_ON(!overlay->vid_bo);
387 obj = &overlay->vid_bo->base;
02e792fb 388
b303cf95
CW		 389 i915_gem_object_unpin(obj);
390 drm_gem_object_unreference(obj);
391 overlay->vid_bo = NULL;
03f77ea5 392
b303cf95
CW		 393 overlay->crtc->overlay = NULL;
394 overlay->crtc = NULL;
395 overlay->active = 0;
02e792fb
DV		 396}
397
398/* overlay needs to be disabled in OCMD reg */
5dcdbcb0
CW		 399static int intel_overlay_off(struct intel_overlay *overlay,
400 bool interruptible)
02e792fb 401{
02e792fb 402 struct drm_device *dev = overlay->dev;
e1f99ce6 403 struct drm_i915_private *dev_priv = dev->dev_private;
8dc5d147
CW		 404 u32 flip_addr = overlay->flip_addr;
405 struct drm_i915_gem_request *request;
e1f99ce6 406 int ret;
02e792fb
DV		 407
408 BUG_ON(!overlay->active);
409
8dc5d147
CW		 410 request = kzalloc(sizeof(*request), GFP_KERNEL);
411 if (request == NULL)
412 return -ENOMEM;
413
02e792fb
DV		 414 /* According to intel docs the overlay hw may hang (when switching
415 * off) without loading the filter coeffs. It is however unclear whether
416 * this applies to the disabling of the overlay or to the switching off
417 * of the hw. Do it in both cases */
418 flip_addr |= OFC_UPDATE;
419
e1f99ce6
CW		 420 ret = BEGIN_LP_RING(6);
421 if (ret) {
422 kfree(request);
423 return ret;
424 }
02e792fb 425 /* wait for overlay to go idle */
02e792fb
DV		 426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
427 OUT_RING(flip_addr);
722506f0 428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 429 /* turn overlay off */
722506f0 430 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 431 OUT_RING(flip_addr);
722506f0 432 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb
DV		 433 ADVANCE_LP_RING();
434
5dcdbcb0 435 return intel_overlay_do_wait_request(overlay, request, interruptible,
b303cf95 436 intel_overlay_off_tail);
12ca45fe
DV		 437}
438
03f77ea5
DV		 439/* recover from an interruption due to a signal
440 * We have to be careful not to repeat work forever an make forward progess. */
5dcdbcb0
CW		 441static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
442 bool interruptible)
03f77ea5
DV		 443{
444 struct drm_device *dev = overlay->dev;
852835f3 445 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5 446 int ret;
03f77ea5 447
b303cf95
CW		 448 if (overlay->last_flip_req == 0)
449 return 0;
03f77ea5 450
852835f3 451 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 452 interruptible, &dev_priv->render_ring);
b6c028e0 453 if (ret)
03f77ea5
DV		 454 return ret;
455
b303cf95
CW		 456 if (overlay->flip_tail)
457 overlay->flip_tail(overlay);
03f77ea5 458
03f77ea5
DV		 459 overlay->last_flip_req = 0;
460 return 0;
461}
462
5a5a0c64
DV		 463/* Wait for pending overlay flip and release old frame.
464 * Needs to be called before the overlay register are changed
8d74f656
CW		 465 * via intel_overlay_(un)map_regs
466 */
02e792fb
DV		 467static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
468{
5cd68c98
CW		 469 struct drm_device *dev = overlay->dev;
470 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 471 int ret;
02e792fb 472
5cd68c98
CW		 473 /* Only wait if there is actually an old frame to release to
474 * guarantee forward progress.
475 */
03f77ea5
DV		 476 if (!overlay->old_vid_bo)
477 return 0;
478
5cd68c98 479 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
8dc5d147 480 struct drm_i915_gem_request *request;
02e792fb 481
5cd68c98 482 /* synchronous slowpath */
8dc5d147
CW		 483 request = kzalloc(sizeof(*request), GFP_KERNEL);
484 if (request == NULL)
485 return -ENOMEM;
02e792fb 486
e1f99ce6
CW		 487 ret = BEGIN_LP_RING(2);
488 if (ret) {
489 kfree(request);
490 return ret;
491 }
492
5cd68c98
CW		 493 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
494 OUT_RING(MI_NOOP);
495 ADVANCE_LP_RING();
496
8dc5d147 497 ret = intel_overlay_do_wait_request(overlay, request, true,
b303cf95 498 intel_overlay_release_old_vid_tail);
5cd68c98
CW		 499 if (ret)
500 return ret;
501 }
02e792fb 502
5cd68c98 503 intel_overlay_release_old_vid_tail(overlay);
02e792fb
DV		 504 return 0;
505}
506
507struct put_image_params {
508 int format;
509 short dst_x;
510 short dst_y;
511 short dst_w;
512 short dst_h;
513 short src_w;
514 short src_scan_h;
515 short src_scan_w;
516 short src_h;
517 short stride_Y;
518 short stride_UV;
519 int offset_Y;
520 int offset_U;
521 int offset_V;
522};
523
524static int packed_depth_bytes(u32 format)
525{
526 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 527 case I915_OVERLAY_YUV422:
528 return 4;
529 case I915_OVERLAY_YUV411:
530 /* return 6; not implemented */
531 default:
532 return -EINVAL;
02e792fb
DV		 533 }
534}
535
536static int packed_width_bytes(u32 format, short width)
537{
538 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 539 case I915_OVERLAY_YUV422:
540 return width << 1;
541 default:
542 return -EINVAL;
02e792fb
DV		 543 }
544}
545
546static int uv_hsubsampling(u32 format)
547{
548 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 549 case I915_OVERLAY_YUV422:
550 case I915_OVERLAY_YUV420:
551 return 2;
552 case I915_OVERLAY_YUV411:
553 case I915_OVERLAY_YUV410:
554 return 4;
555 default:
556 return -EINVAL;
02e792fb
DV		 557 }
558}
559
560static int uv_vsubsampling(u32 format)
561{
562 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 563 case I915_OVERLAY_YUV420:
564 case I915_OVERLAY_YUV410:
565 return 2;
566 case I915_OVERLAY_YUV422:
567 case I915_OVERLAY_YUV411:
568 return 1;
569 default:
570 return -EINVAL;
02e792fb
DV		 571 }
572}
573
574static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
575{
576 u32 mask, shift, ret;
a6c45cf0 577 if (IS_GEN2(dev)) {
02e792fb
DV		 578 mask = 0x1f;
579 shift = 5;
a6c45cf0
CW		 580 } else {
581 mask = 0x3f;
582 shift = 6;
02e792fb
DV		 583 }
584 ret = ((offset + width + mask) >> shift) - (offset >> shift);
a6c45cf0 585 if (!IS_GEN2(dev))
02e792fb
DV		 586 ret <<= 1;
587 ret -=1;
588 return ret << 2;
589}
590
591static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
592 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
593 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
594 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
595 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
596 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
597 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
598 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
599 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
600 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
601 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
602 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
603 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
604 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
605 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
606 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
607 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 608 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
609};
610
02e792fb
DV		 611static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
612 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
613 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
614 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
615 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
616 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
617 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
618 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
619 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 620 0x3000, 0x0800, 0x3000
621};
02e792fb
DV		 622
623static void update_polyphase_filter(struct overlay_registers *regs)
624{
625 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
626 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
627}
628
629static bool update_scaling_factors(struct intel_overlay *overlay,
630 struct overlay_registers *regs,
631 struct put_image_params *params)
632{
633 /* fixed point with a 12 bit shift */
634 u32 xscale, yscale, xscale_UV, yscale_UV;
635#define FP_SHIFT 12
636#define FRACT_MASK 0xfff
637 bool scale_changed = false;
638 int uv_hscale = uv_hsubsampling(params->format);
639 int uv_vscale = uv_vsubsampling(params->format);
640
641 if (params->dst_w > 1)
642 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
643 /(params->dst_w);
644 else
645 xscale = 1 << FP_SHIFT;
646
647 if (params->dst_h > 1)
648 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
649 /(params->dst_h);
650 else
651 yscale = 1 << FP_SHIFT;
652
653 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 654 xscale_UV = xscale/uv_hscale;
655 yscale_UV = yscale/uv_vscale;
656 /* make the Y scale to UV scale ratio an exact multiply */
657 xscale = xscale_UV * uv_hscale;
658 yscale = yscale_UV * uv_vscale;
02e792fb 659 /*} else {
722506f0
CW		 660 xscale_UV = 0;
661 yscale_UV = 0;
662 }*/
02e792fb
DV		 663
664 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
665 scale_changed = true;
666 overlay->old_xscale = xscale;
667 overlay->old_yscale = yscale;
668
722506f0
CW		 669 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
670 ((xscale >> FP_SHIFT) << 16) |
671 ((xscale & FRACT_MASK) << 3));
672
673 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
674 ((xscale_UV >> FP_SHIFT) << 16) |
675 ((xscale_UV & FRACT_MASK) << 3));
676
677 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
678 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 679
680 if (scale_changed)
681 update_polyphase_filter(regs);
682
683 return scale_changed;
684}
685
686static void update_colorkey(struct intel_overlay *overlay,
687 struct overlay_registers *regs)
688{
689 u32 key = overlay->color_key;
6ba3ddd9 690
02e792fb 691 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 692 case 8:
693 regs->DCLRKV = 0;
694 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 695 break;
696
722506f0
CW		 697 case 16:
698 if (overlay->crtc->base.fb->depth == 15) {
699 regs->DCLRKV = RGB15_TO_COLORKEY(key);
700 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
701 } else {
702 regs->DCLRKV = RGB16_TO_COLORKEY(key);
703 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
704 }
6ba3ddd9
CW		 705 break;
706
722506f0
CW		 707 case 24:
708 case 32:
709 regs->DCLRKV = key;
710 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 711 break;
02e792fb
DV		 712 }
713}
714
715static u32 overlay_cmd_reg(struct put_image_params *params)
716{
717 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
718
719 if (params->format & I915_OVERLAY_YUV_PLANAR) {
720 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 721 case I915_OVERLAY_YUV422:
722 cmd |= OCMD_YUV_422_PLANAR;
723 break;
724 case I915_OVERLAY_YUV420:
725 cmd |= OCMD_YUV_420_PLANAR;
726 break;
727 case I915_OVERLAY_YUV411:
728 case I915_OVERLAY_YUV410:
729 cmd |= OCMD_YUV_410_PLANAR;
730 break;
02e792fb
DV		 731 }
732 } else { /* YUV packed */
733 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 734 case I915_OVERLAY_YUV422:
735 cmd |= OCMD_YUV_422_PACKED;
736 break;
737 case I915_OVERLAY_YUV411:
738 cmd |= OCMD_YUV_411_PACKED;
739 break;
02e792fb
DV		 740 }
741
742 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 743 case I915_OVERLAY_NO_SWAP:
744 break;
745 case I915_OVERLAY_UV_SWAP:
746 cmd |= OCMD_UV_SWAP;
747 break;
748 case I915_OVERLAY_Y_SWAP:
749 cmd |= OCMD_Y_SWAP;
750 break;
751 case I915_OVERLAY_Y_AND_UV_SWAP:
752 cmd |= OCMD_Y_AND_UV_SWAP;
753 break;
02e792fb
DV		 754 }
755 }
756
757 return cmd;
758}
759
5fe82c5e
CW		 760static int intel_overlay_do_put_image(struct intel_overlay *overlay,
761 struct drm_gem_object *new_bo,
762 struct put_image_params *params)
02e792fb
DV		 763{
764 int ret, tmp_width;
765 struct overlay_registers *regs;
766 bool scale_changed = false;
23010e43 767 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 768 struct drm_device *dev = overlay->dev;
769
770 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
771 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
772 BUG_ON(!overlay);
773
02e792fb
DV		 774 ret = intel_overlay_release_old_vid(overlay);
775 if (ret != 0)
776 return ret;
777
778 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
779 if (ret != 0)
780 return ret;
781
782 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
783 if (ret != 0)
784 goto out_unpin;
785
786 if (!overlay->active) {
8d74f656 787 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 788 if (!regs) {
789 ret = -ENOMEM;
790 goto out_unpin;
791 }
792 regs->OCONFIG = OCONF_CC_OUT_8BIT;
a6c45cf0 793 if (IS_GEN4(overlay->dev))
02e792fb
DV		 794 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
795 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
796 OCONF_PIPE_A : OCONF_PIPE_B;
9bb2ff73 797 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 798
799 ret = intel_overlay_on(overlay);
800 if (ret != 0)
801 goto out_unpin;
802 }
803
8d74f656 804 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 805 if (!regs) {
806 ret = -ENOMEM;
807 goto out_unpin;
808 }
809
810 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
811 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
812
813 if (params->format & I915_OVERLAY_YUV_PACKED)
814 tmp_width = packed_width_bytes(params->format, params->src_w);
815 else
816 tmp_width = params->src_w;
817
818 regs->SWIDTH = params->src_w;
819 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 820 params->offset_Y, tmp_width);
02e792fb
DV		 821 regs->SHEIGHT = params->src_h;
822 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
823 regs->OSTRIDE = params->stride_Y;
824
825 if (params->format & I915_OVERLAY_YUV_PLANAR) {
826 int uv_hscale = uv_hsubsampling(params->format);
827 int uv_vscale = uv_vsubsampling(params->format);
828 u32 tmp_U, tmp_V;
829 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
830 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 831 params->src_w/uv_hscale);
02e792fb 832 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 833 params->src_w/uv_hscale);
02e792fb
DV		 834 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
835 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
836 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
837 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
838 regs->OSTRIDE |= params->stride_UV << 16;
839 }
840
841 scale_changed = update_scaling_factors(overlay, regs, params);
842
843 update_colorkey(overlay, regs);
844
845 regs->OCMD = overlay_cmd_reg(params);
846
9bb2ff73 847 intel_overlay_unmap_regs(overlay, regs);
02e792fb 848
8dc5d147
CW		 849 ret = intel_overlay_continue(overlay, scale_changed);
850 if (ret)
851 goto out_unpin;
02e792fb
DV		 852
853 overlay->old_vid_bo = overlay->vid_bo;
23010e43 854 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 855
856 return 0;
857
858out_unpin:
859 i915_gem_object_unpin(new_bo);
860 return ret;
861}
862
5dcdbcb0
CW		 863int intel_overlay_switch_off(struct intel_overlay *overlay,
864 bool interruptible)
02e792fb 865{
02e792fb 866 struct overlay_registers *regs;
02e792fb 867 struct drm_device *dev = overlay->dev;
5dcdbcb0 868 int ret;
02e792fb
DV		 869
870 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
871 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
872
b303cf95
CW		 873 ret = intel_overlay_recover_from_interrupt(overlay, interruptible);
874 if (ret != 0)
875 return ret;
9bedb974 876
02e792fb
DV		 877 if (!overlay->active)
878 return 0;
879
02e792fb
DV		 880 ret = intel_overlay_release_old_vid(overlay);
881 if (ret != 0)
882 return ret;
883
8d74f656 884 regs = intel_overlay_map_regs(overlay);
02e792fb 885 regs->OCMD = 0;
9bb2ff73 886 intel_overlay_unmap_regs(overlay, regs);
02e792fb 887
5dcdbcb0 888 ret = intel_overlay_off(overlay, interruptible);
03f77ea5
DV		 889 if (ret != 0)
890 return ret;
891
12ca45fe 892 intel_overlay_off_tail(overlay);
02e792fb
DV		 893 return 0;
894}
895
896static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
897 struct intel_crtc *crtc)
898{
722506f0 899 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb 900
f7abfe8b 901 if (!crtc->active)
02e792fb
DV		 902 return -EINVAL;
903
02e792fb 904 /* can't use the overlay with double wide pipe */
a6c45cf0 905 if (INTEL_INFO(overlay->dev)->gen < 4 &&
f7abfe8b 906 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
02e792fb
DV		 907 return -EINVAL;
908
909 return 0;
910}
911
912static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
913{
914 struct drm_device *dev = overlay->dev;
722506f0 915 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 916 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 917 u32 ratio;
02e792fb
DV		 918
919 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 920 * line with the intel documentation for the i965
921 */
a6c45cf0
CW		 922 if (INTEL_INFO(dev)->gen >= 4) {
923 /* on i965 use the PGM reg to read out the autoscaler values */
924 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
925 } else {
446d2183
CW		 926 if (pfit_control & VERT_AUTO_SCALE)
927 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 928 else
446d2183
CW		 929 ratio = I915_READ(PFIT_PGM_RATIOS);
930 ratio >>= PFIT_VERT_SCALE_SHIFT;
02e792fb
DV		 931 }
932
933 overlay->pfit_vscale_ratio = ratio;
934}
935
936static int check_overlay_dst(struct intel_overlay *overlay,
937 struct drm_intel_overlay_put_image *rec)
938{
939 struct drm_display_mode *mode = &overlay->crtc->base.mode;
940
722506f0
CW		 941 if (rec->dst_x < mode->crtc_hdisplay &&
942 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
943 rec->dst_y < mode->crtc_vdisplay &&
944 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 945 return 0;
946 else
947 return -EINVAL;
948}
949
950static int check_overlay_scaling(struct put_image_params *rec)
951{
952 u32 tmp;
953
954 /* downscaling limit is 8.0 */
955 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
956 if (tmp > 7)
957 return -EINVAL;
958 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
959 if (tmp > 7)
960 return -EINVAL;
961
962 return 0;
963}
964
965static int check_overlay_src(struct drm_device *dev,
966 struct drm_intel_overlay_put_image *rec,
967 struct drm_gem_object *new_bo)
968{
02e792fb
DV		 969 int uv_hscale = uv_hsubsampling(rec->flags);
970 int uv_vscale = uv_vsubsampling(rec->flags);
9f7c3f44 971 u32 stride_mask, depth, tmp;
02e792fb
DV		 972
973 /* check src dimensions */
974 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 975 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 976 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 977 return -EINVAL;
978 } else {
722506f0 979 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 980 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 981 return -EINVAL;
982 }
9f7c3f44 983
02e792fb 984 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 985 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 986 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 987 return -EINVAL;
988
a1efd14a 989 /* check alignment constraints */
02e792fb 990 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 991 case I915_OVERLAY_RGB:
992 /* not implemented */
993 return -EINVAL;
9f7c3f44 994
722506f0 995 case I915_OVERLAY_YUV_PACKED:
722506f0 996 if (uv_vscale != 1)
02e792fb 997 return -EINVAL;
9f7c3f44
CW		 998
999 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 1000 if (depth < 0)
1001 return depth;
9f7c3f44 1002
722506f0
CW		 1003 /* ignore UV planes */
1004 rec->stride_UV = 0;
1005 rec->offset_U = 0;
1006 rec->offset_V = 0;
1007 /* check pixel alignment */
1008 if (rec->offset_Y % depth)
1009 return -EINVAL;
1010 break;
9f7c3f44 1011
722506f0
CW		 1012 case I915_OVERLAY_YUV_PLANAR:
1013 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 1014 return -EINVAL;
722506f0
CW		 1015 /* no offset restrictions for planar formats */
1016 break;
9f7c3f44 1017
722506f0
CW		 1018 default:
1019 return -EINVAL;
02e792fb
DV		 1020 }
1021
1022 if (rec->src_width % uv_hscale)
1023 return -EINVAL;
1024
1025 /* stride checking */
a1efd14a
CW		 1026 if (IS_I830(dev) || IS_845G(dev))
1027 stride_mask = 255;
1028 else
1029 stride_mask = 63;
02e792fb
DV		 1030
1031 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1032 return -EINVAL;
a6c45cf0 1033 if (IS_GEN4(dev) && rec->stride_Y < 512)
02e792fb
DV		 1034 return -EINVAL;
1035
1036 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 1037 4096 : 8192;
1038 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 1039 return -EINVAL;
1040
1041 /* check buffer dimensions */
1042 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1043 case I915_OVERLAY_RGB:
1044 case I915_OVERLAY_YUV_PACKED:
1045 /* always 4 Y values per depth pixels */
1046 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1047 return -EINVAL;
1048
1049 tmp = rec->stride_Y*rec->src_height;
1050 if (rec->offset_Y + tmp > new_bo->size)
1051 return -EINVAL;
1052 break;
1053
1054 case I915_OVERLAY_YUV_PLANAR:
1055 if (rec->src_width > rec->stride_Y)
1056 return -EINVAL;
1057 if (rec->src_width/uv_hscale > rec->stride_UV)
1058 return -EINVAL;
1059
9f7c3f44 1060 tmp = rec->stride_Y * rec->src_height;
722506f0
CW		 1061 if (rec->offset_Y + tmp > new_bo->size)
1062 return -EINVAL;
9f7c3f44
CW		 1063
1064 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
722506f0
CW		 1065 if (rec->offset_U + tmp > new_bo->size ||
1066 rec->offset_V + tmp > new_bo->size)
1067 return -EINVAL;
1068 break;
02e792fb
DV		 1069 }
1070
1071 return 0;
1072}
1073
e9e331a8
CW		 1074/**
1075 * Return the pipe currently connected to the panel fitter,
1076 * or -1 if the panel fitter is not present or not in use
1077 */
1078static int intel_panel_fitter_pipe(struct drm_device *dev)
1079{
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 u32 pfit_control;
1082
1083 /* i830 doesn't have a panel fitter */
1084 if (IS_I830(dev))
1085 return -1;
1086
1087 pfit_control = I915_READ(PFIT_CONTROL);
1088
1089 /* See if the panel fitter is in use */
1090 if ((pfit_control & PFIT_ENABLE) == 0)
1091 return -1;
1092
1093 /* 965 can place panel fitter on either pipe */
a6c45cf0 1094 if (IS_GEN4(dev))
e9e331a8
CW		 1095 return (pfit_control >> 29) & 0x3;
1096
1097 /* older chips can only use pipe 1 */
1098 return 1;
1099}
1100
02e792fb
DV		 1101int intel_overlay_put_image(struct drm_device *dev, void *data,
1102 struct drm_file *file_priv)
1103{
1104 struct drm_intel_overlay_put_image *put_image_rec = data;
1105 drm_i915_private_t *dev_priv = dev->dev_private;
1106 struct intel_overlay *overlay;
1107 struct drm_mode_object *drmmode_obj;
1108 struct intel_crtc *crtc;
1109 struct drm_gem_object *new_bo;
1110 struct put_image_params *params;
1111 int ret;
1112
1113 if (!dev_priv) {
1114 DRM_ERROR("called with no initialization\n");
1115 return -EINVAL;
1116 }
1117
1118 overlay = dev_priv->overlay;
1119 if (!overlay) {
1120 DRM_DEBUG("userspace bug: no overlay\n");
1121 return -ENODEV;
1122 }
1123
1124 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1125 mutex_lock(&dev->mode_config.mutex);
1126 mutex_lock(&dev->struct_mutex);
1127
5dcdbcb0 1128 ret = intel_overlay_switch_off(overlay, true);
02e792fb
DV		 1129
1130 mutex_unlock(&dev->struct_mutex);
1131 mutex_unlock(&dev->mode_config.mutex);
1132
1133 return ret;
1134 }
1135
1136 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1137 if (!params)
1138 return -ENOMEM;
1139
1140 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1141 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1142 if (!drmmode_obj) {
1143 ret = -ENOENT;
1144 goto out_free;
1145 }
02e792fb
DV		 1146 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1147
1148 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1149 put_image_rec->bo_handle);
915a428e
DC		 1150 if (!new_bo) {
1151 ret = -ENOENT;
1152 goto out_free;
1153 }
02e792fb
DV		 1154
1155 mutex_lock(&dev->mode_config.mutex);
1156 mutex_lock(&dev->struct_mutex);
1157
b303cf95
CW		 1158 ret = intel_overlay_recover_from_interrupt(overlay, true);
1159 if (ret != 0)
1160 goto out_unlock;
03f77ea5 1161
02e792fb
DV		 1162 if (overlay->crtc != crtc) {
1163 struct drm_display_mode *mode = &crtc->base.mode;
5dcdbcb0 1164 ret = intel_overlay_switch_off(overlay, true);
02e792fb
DV		 1165 if (ret != 0)
1166 goto out_unlock;
1167
1168 ret = check_overlay_possible_on_crtc(overlay, crtc);
1169 if (ret != 0)
1170 goto out_unlock;
1171
1172 overlay->crtc = crtc;
1173 crtc->overlay = overlay;
1174
e9e331a8
CW		 1175 /* line too wide, i.e. one-line-mode */
1176 if (mode->hdisplay > 1024 &&
1177 intel_panel_fitter_pipe(dev) == crtc->pipe) {
02e792fb
DV		 1178 overlay->pfit_active = 1;
1179 update_pfit_vscale_ratio(overlay);
1180 } else
1181 overlay->pfit_active = 0;
1182 }
1183
1184 ret = check_overlay_dst(overlay, put_image_rec);
1185 if (ret != 0)
1186 goto out_unlock;
1187
1188 if (overlay->pfit_active) {
1189 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1190 overlay->pfit_vscale_ratio);
02e792fb
DV		 1191 /* shifting right rounds downwards, so add 1 */
1192 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1193 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1194 } else {
1195 params->dst_y = put_image_rec->dst_y;
1196 params->dst_h = put_image_rec->dst_height;
1197 }
1198 params->dst_x = put_image_rec->dst_x;
1199 params->dst_w = put_image_rec->dst_width;
1200
1201 params->src_w = put_image_rec->src_width;
1202 params->src_h = put_image_rec->src_height;
1203 params->src_scan_w = put_image_rec->src_scan_width;
1204 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1205 if (params->src_scan_h > params->src_h ||
1206 params->src_scan_w > params->src_w) {
02e792fb
DV		 1207 ret = -EINVAL;
1208 goto out_unlock;
1209 }
1210
1211 ret = check_overlay_src(dev, put_image_rec, new_bo);
1212 if (ret != 0)
1213 goto out_unlock;
1214 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1215 params->stride_Y = put_image_rec->stride_Y;
1216 params->stride_UV = put_image_rec->stride_UV;
1217 params->offset_Y = put_image_rec->offset_Y;
1218 params->offset_U = put_image_rec->offset_U;
1219 params->offset_V = put_image_rec->offset_V;
1220
1221 /* Check scaling after src size to prevent a divide-by-zero. */
1222 ret = check_overlay_scaling(params);
1223 if (ret != 0)
1224 goto out_unlock;
1225
1226 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1227 if (ret != 0)
1228 goto out_unlock;
1229
1230 mutex_unlock(&dev->struct_mutex);
1231 mutex_unlock(&dev->mode_config.mutex);
1232
1233 kfree(params);
1234
1235 return 0;
1236
1237out_unlock:
1238 mutex_unlock(&dev->struct_mutex);
1239 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1240 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1241out_free:
02e792fb
DV		 1242 kfree(params);
1243
1244 return ret;
1245}
1246
1247static void update_reg_attrs(struct intel_overlay *overlay,
1248 struct overlay_registers *regs)
1249{
1250 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1251 regs->OCLRC1 = overlay->saturation;
1252}
1253
1254static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1255{
1256 int i;
1257
1258 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1259 return false;
1260
1261 for (i = 0; i < 3; i++) {
722506f0 1262 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1263 return false;
1264 }
1265
1266 return true;
1267}
1268
1269static bool check_gamma5_errata(u32 gamma5)
1270{
1271 int i;
1272
1273 for (i = 0; i < 3; i++) {
1274 if (((gamma5 >> i*8) & 0xff) == 0x80)
1275 return false;
1276 }
1277
1278 return true;
1279}
1280
1281static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1282{
722506f0
CW		 1283 if (!check_gamma_bounds(0, attrs->gamma0) ||
1284 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1285 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1286 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1287 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1288 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1289 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1290 return -EINVAL;
722506f0 1291
02e792fb
DV		 1292 if (!check_gamma5_errata(attrs->gamma5))
1293 return -EINVAL;
722506f0 1294
02e792fb
DV		 1295 return 0;
1296}
1297
1298int intel_overlay_attrs(struct drm_device *dev, void *data,
1299 struct drm_file *file_priv)
1300{
1301 struct drm_intel_overlay_attrs *attrs = data;
1302 drm_i915_private_t *dev_priv = dev->dev_private;
1303 struct intel_overlay *overlay;
1304 struct overlay_registers *regs;
1305 int ret;
1306
1307 if (!dev_priv) {
1308 DRM_ERROR("called with no initialization\n");
1309 return -EINVAL;
1310 }
1311
1312 overlay = dev_priv->overlay;
1313 if (!overlay) {
1314 DRM_DEBUG("userspace bug: no overlay\n");
1315 return -ENODEV;
1316 }
1317
1318 mutex_lock(&dev->mode_config.mutex);
1319 mutex_lock(&dev->struct_mutex);
1320
60fc332c 1321 ret = -EINVAL;
02e792fb 1322 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1323 attrs->color_key = overlay->color_key;
02e792fb 1324 attrs->brightness = overlay->brightness;
60fc332c 1325 attrs->contrast = overlay->contrast;
02e792fb
DV		 1326 attrs->saturation = overlay->saturation;
1327
a6c45cf0 1328 if (!IS_GEN2(dev)) {
02e792fb
DV		 1329 attrs->gamma0 = I915_READ(OGAMC0);
1330 attrs->gamma1 = I915_READ(OGAMC1);
1331 attrs->gamma2 = I915_READ(OGAMC2);
1332 attrs->gamma3 = I915_READ(OGAMC3);
1333 attrs->gamma4 = I915_READ(OGAMC4);
1334 attrs->gamma5 = I915_READ(OGAMC5);
1335 }
02e792fb 1336 } else {
60fc332c 1337 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1338 goto out_unlock;
60fc332c 1339 if (attrs->contrast > 255)
02e792fb 1340 goto out_unlock;
60fc332c 1341 if (attrs->saturation > 1023)
02e792fb 1342 goto out_unlock;
02e792fb 1343
60fc332c
CW		 1344 overlay->color_key = attrs->color_key;
1345 overlay->brightness = attrs->brightness;
1346 overlay->contrast = attrs->contrast;
1347 overlay->saturation = attrs->saturation;
02e792fb 1348
8d74f656 1349 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1350 if (!regs) {
1351 ret = -ENOMEM;
1352 goto out_unlock;
1353 }
1354
1355 update_reg_attrs(overlay, regs);
1356
9bb2ff73 1357 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1358
1359 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
a6c45cf0 1360 if (IS_GEN2(dev))
02e792fb 1361 goto out_unlock;
02e792fb
DV		 1362
1363 if (overlay->active) {
1364 ret = -EBUSY;
1365 goto out_unlock;
1366 }
1367
1368 ret = check_gamma(attrs);
60fc332c 1369 if (ret)
02e792fb
DV		 1370 goto out_unlock;
1371
1372 I915_WRITE(OGAMC0, attrs->gamma0);
1373 I915_WRITE(OGAMC1, attrs->gamma1);
1374 I915_WRITE(OGAMC2, attrs->gamma2);
1375 I915_WRITE(OGAMC3, attrs->gamma3);
1376 I915_WRITE(OGAMC4, attrs->gamma4);
1377 I915_WRITE(OGAMC5, attrs->gamma5);
1378 }
02e792fb
DV		 1379 }
1380
60fc332c 1381 ret = 0;
02e792fb
DV		 1382out_unlock:
1383 mutex_unlock(&dev->struct_mutex);
1384 mutex_unlock(&dev->mode_config.mutex);
1385
1386 return ret;
1387}
1388
1389void intel_setup_overlay(struct drm_device *dev)
1390{
1391 drm_i915_private_t *dev_priv = dev->dev_private;
1392 struct intel_overlay *overlay;
1393 struct drm_gem_object *reg_bo;
1394 struct overlay_registers *regs;
1395 int ret;
1396
31578148 1397 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1398 return;
1399
1400 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1401 if (!overlay)
1402 return;
1403 overlay->dev = dev;
1404
ac52bc56 1405 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1406 if (!reg_bo)
1407 goto out_free;
23010e43 1408 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1409
31578148 1410 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
02e792fb 1411 ret = i915_gem_attach_phys_object(dev, reg_bo,
6eeefaf3 1412 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1413 PAGE_SIZE);
02e792fb
DV		 1414 if (ret) {
1415 DRM_ERROR("failed to attach phys overlay regs\n");
1416 goto out_free_bo;
1417 }
1418 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
31578148 1419 } else {
02e792fb
DV		 1420 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1421 if (ret) {
1422 DRM_ERROR("failed to pin overlay register bo\n");
1423 goto out_free_bo;
1424 }
1425 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1426
1427 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1428 if (ret) {
1429 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1430 goto out_unpin_bo;
1431 }
02e792fb
DV		 1432 }
1433
1434 /* init all values */
1435 overlay->color_key = 0x0101fe;
1436 overlay->brightness = -19;
1437 overlay->contrast = 75;
1438 overlay->saturation = 146;
1439
8d74f656 1440 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1441 if (!regs)
1442 goto out_free_bo;
1443
1444 memset(regs, 0, sizeof(struct overlay_registers));
1445 update_polyphase_filter(regs);
02e792fb
DV		 1446 update_reg_attrs(overlay, regs);
1447
9bb2ff73 1448 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1449
1450 dev_priv->overlay = overlay;
1451 DRM_INFO("initialized overlay support\n");
1452 return;
1453
0ddc1289
CW		 1454out_unpin_bo:
1455 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1456out_free_bo:
1457 drm_gem_object_unreference(reg_bo);
1458out_free:
1459 kfree(overlay);
1460 return;
1461}
1462
1463void intel_cleanup_overlay(struct drm_device *dev)
1464{
722506f0 1465 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1466
62cf4e6f
CW		 1467 if (!dev_priv->overlay)
1468 return;
02e792fb 1469
62cf4e6f
CW		 1470 /* The bo's should be free'd by the generic code already.
1471 * Furthermore modesetting teardown happens beforehand so the
1472 * hardware should be off already */
1473 BUG_ON(dev_priv->overlay->active);
1474
1475 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1476 kfree(dev_priv->overlay);
02e792fb 1477}
6ef3d427 1478
3bd3c932
CW		 1479#ifdef CONFIG_DEBUG_FS
1480#include <linux/seq_file.h>
1481
6ef3d427
CW		 1482struct intel_overlay_error_state {
1483 struct overlay_registers regs;
1484 unsigned long base;
1485 u32 dovsta;
1486 u32 isr;
1487};
1488
3bd3c932 1489static struct overlay_registers *
c48c43e4 1490intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
3bd3c932 1491{
c48c43e4 1492 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
3bd3c932
CW		 1493 struct overlay_registers *regs;
1494
1495 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1496 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1497 else
1498 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
c48c43e4 1499 overlay->reg_bo->gtt_offset);
3bd3c932
CW		 1500
1501 return regs;
1502}
1503
1504static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
3bd3c932
CW		 1505 struct overlay_registers *regs)
1506{
1507 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
c48c43e4 1508 io_mapping_unmap_atomic(regs);
3bd3c932
CW		 1509}
1510
1511
6ef3d427
CW		 1512struct intel_overlay_error_state *
1513intel_overlay_capture_error_state(struct drm_device *dev)
1514{
1515 drm_i915_private_t *dev_priv = dev->dev_private;
1516 struct intel_overlay *overlay = dev_priv->overlay;
1517 struct intel_overlay_error_state *error;
1518 struct overlay_registers __iomem *regs;
1519
1520 if (!overlay || !overlay->active)
1521 return NULL;
1522
1523 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1524 if (error == NULL)
1525 return NULL;
1526
1527 error->dovsta = I915_READ(DOVSTA);
1528 error->isr = I915_READ(ISR);
31578148 1529 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1530 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1531 else
1532 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427
CW		 1533
1534 regs = intel_overlay_map_regs_atomic(overlay);
1535 if (!regs)
1536 goto err;
1537
1538 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
c48c43e4 1539 intel_overlay_unmap_regs_atomic(overlay, regs);
6ef3d427
CW		 1540
1541 return error;
1542
1543err:
1544 kfree(error);
1545 return NULL;
1546}
1547
1548void
1549intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1550{
1551 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1552 error->dovsta, error->isr);
1553 seq_printf(m, " Register file at 0x%08lx:\n",
1554 error->base);
1555
1556#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1557 P(OBUF_0Y);
1558 P(OBUF_1Y);
1559 P(OBUF_0U);
1560 P(OBUF_0V);
1561 P(OBUF_1U);
1562 P(OBUF_1V);
1563 P(OSTRIDE);
1564 P(YRGB_VPH);
1565 P(UV_VPH);
1566 P(HORZ_PH);
1567 P(INIT_PHS);
1568 P(DWINPOS);
1569 P(DWINSZ);
1570 P(SWIDTH);
1571 P(SWIDTHSW);
1572 P(SHEIGHT);
1573 P(YRGBSCALE);
1574 P(UVSCALE);
1575 P(OCLRC0);
1576 P(OCLRC1);
1577 P(DCLRKV);
1578 P(DCLRKM);
1579 P(SCLRKVH);
1580 P(SCLRKVL);
1581 P(SCLRKEN);
1582 P(OCONFIG);
1583 P(OCMD);
1584 P(OSTART_0Y);
1585 P(OSTART_1Y);
1586 P(OSTART_0U);
1587 P(OSTART_0V);
1588 P(OSTART_1U);
1589 P(OSTART_1V);
1590 P(OTILEOFF_0Y);
1591 P(OTILEOFF_1Y);
1592 P(OTILEOFF_0U);
1593 P(OTILEOFF_0V);
1594 P(OTILEOFF_1U);
1595 P(OTILEOFF_1V);
1596 P(FASTHSCALE);
1597 P(UVSCALEV);
1598#undef P
1599}
3bd3c932 1600#endif
Linux kernel - Deliverables
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