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Merge git://git.kernel.org/pub/scm/virt/kvm/kvm
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
02e792fb
DV		 30#include "i915_drv.h"
31#include "i915_reg.h"
32#include "intel_drv.h"
33
34/* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38#define IMAGE_MAX_WIDTH 2048
39#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40/* on 830 and 845 these large limits result in the card hanging */
41#define IMAGE_MAX_WIDTH_LEGACY 1024
42#define IMAGE_MAX_HEIGHT_LEGACY 1088
43
44/* overlay register definitions */
45/* OCMD register */
46#define OCMD_TILED_SURFACE (0x1<<19)
47#define OCMD_MIRROR_MASK (0x3<<17)
48#define OCMD_MIRROR_MODE (0x3<<17)
49#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50#define OCMD_MIRROR_VERTICAL (0x2<<17)
51#define OCMD_MIRROR_BOTH (0x3<<17)
52#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60#define OCMD_YUV_422_PACKED (0x8<<10)
61#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62#define OCMD_YUV_420_PLANAR (0xc<<10)
63#define OCMD_YUV_422_PLANAR (0xd<<10)
64#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 67#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 68#define OCMD_BUF_TYPE_FRAME (0x0<<5)
69#define OCMD_BUF_TYPE_FIELD (0x1<<5)
70#define OCMD_TEST_MODE (0x1<<4)
71#define OCMD_BUFFER_SELECT (0x3<<2)
72#define OCMD_BUFFER0 (0x0<<2)
73#define OCMD_BUFFER1 (0x1<<2)
74#define OCMD_FIELD_SELECT (0x1<<2)
75#define OCMD_FIELD0 (0x0<<1)
76#define OCMD_FIELD1 (0x1<<1)
77#define OCMD_ENABLE (0x1<<0)
78
79/* OCONFIG register */
80#define OCONF_PIPE_MASK (0x1<<18)
81#define OCONF_PIPE_A (0x0<<18)
82#define OCONF_PIPE_B (0x1<<18)
83#define OCONF_GAMMA2_ENABLE (0x1<<16)
84#define OCONF_CSC_MODE_BT601 (0x0<<5)
85#define OCONF_CSC_MODE_BT709 (0x1<<5)
86#define OCONF_CSC_BYPASS (0x1<<4)
87#define OCONF_CC_OUT_8BIT (0x1<<3)
88#define OCONF_TEST_MODE (0x1<<2)
89#define OCONF_THREE_LINE_BUFFER (0x1<<0)
90#define OCONF_TWO_LINE_BUFFER (0x0<<0)
91
92/* DCLRKM (dst-key) register */
93#define DST_KEY_ENABLE (0x1<<31)
94#define CLK_RGB24_MASK 0x0
95#define CLK_RGB16_MASK 0x070307
96#define CLK_RGB15_MASK 0x070707
97#define CLK_RGB8I_MASK 0xffffff
98
99#define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101#define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
103
104/* overlay flip addr flag */
105#define OFC_UPDATE 0x1
106
107/* polyphase filter coefficients */
108#define N_HORIZ_Y_TAPS 5
109#define N_VERT_Y_TAPS 3
110#define N_HORIZ_UV_TAPS 3
111#define N_VERT_UV_TAPS 3
112#define N_PHASES 17
113#define MAX_TAPS 5
114
115/* memory bufferd overlay registers */
116struct overlay_registers {
0206e353
AJ		 117 u32 OBUF_0Y;
118 u32 OBUF_1Y;
119 u32 OBUF_0U;
120 u32 OBUF_0V;
121 u32 OBUF_1U;
122 u32 OBUF_1V;
123 u32 OSTRIDE;
124 u32 YRGB_VPH;
125 u32 UV_VPH;
126 u32 HORZ_PH;
127 u32 INIT_PHS;
128 u32 DWINPOS;
129 u32 DWINSZ;
130 u32 SWIDTH;
131 u32 SWIDTHSW;
132 u32 SHEIGHT;
133 u32 YRGBSCALE;
134 u32 UVSCALE;
135 u32 OCLRC0;
136 u32 OCLRC1;
137 u32 DCLRKV;
138 u32 DCLRKM;
139 u32 SCLRKVH;
140 u32 SCLRKVL;
141 u32 SCLRKEN;
142 u32 OCONFIG;
143 u32 OCMD;
144 u32 RESERVED1; /* 0x6C */
145 u32 OSTART_0Y;
146 u32 OSTART_1Y;
147 u32 OSTART_0U;
148 u32 OSTART_0V;
149 u32 OSTART_1U;
150 u32 OSTART_1V;
151 u32 OTILEOFF_0Y;
152 u32 OTILEOFF_1Y;
153 u32 OTILEOFF_0U;
154 u32 OTILEOFF_0V;
155 u32 OTILEOFF_1U;
156 u32 OTILEOFF_1V;
157 u32 FASTHSCALE; /* 0xA0 */
158 u32 UVSCALEV; /* 0xA4 */
159 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
161 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
162 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
163 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
164 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
165 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
166 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
167 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
02e792fb
DV		 168};
169
23f09ce3
CW		 170struct intel_overlay {
171 struct drm_device *dev;
172 struct intel_crtc *crtc;
173 struct drm_i915_gem_object *vid_bo;
174 struct drm_i915_gem_object *old_vid_bo;
175 int active;
176 int pfit_active;
177 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
178 u32 color_key;
179 u32 brightness, contrast, saturation;
180 u32 old_xscale, old_yscale;
181 /* register access */
182 u32 flip_addr;
183 struct drm_i915_gem_object *reg_bo;
184 /* flip handling */
9bfc01a2 185 struct drm_i915_gem_request *last_flip_req;
b303cf95 186 void (*flip_tail)(struct intel_overlay *);
23f09ce3 187};
02e792fb 188
75020bc1 189static struct overlay_registers __iomem *
8d74f656 190intel_overlay_map_regs(struct intel_overlay *overlay)
02e792fb 191{
d5d45cc5 192 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 193 struct overlay_registers __iomem *regs;
02e792fb 194
9bb2ff73 195 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 196 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
9bb2ff73 197 else
5d4545ae 198 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
f343c5f6 199 i915_gem_obj_ggtt_offset(overlay->reg_bo));
02e792fb 200
9bb2ff73 201 return regs;
8d74f656 202}
02e792fb 203
9bb2ff73 204static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
75020bc1 205 struct overlay_registers __iomem *regs)
8d74f656
CW		 206{
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 208 io_mapping_unmap(regs);
02e792fb
DV		 209}
210
b6c028e0 211static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
b303cf95 212 void (*tail)(struct intel_overlay *))
02e792fb
DV		 213{
214 struct drm_device *dev = overlay->dev;
d5d45cc5 215 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 216 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
b6c028e0 217 int ret;
02e792fb 218
b303cf95 219 BUG_ON(overlay->last_flip_req);
9bfc01a2
JH		 220 i915_gem_request_assign(&overlay->last_flip_req,
221 ring->outstanding_lazy_request);
9400ae5c 222 ret = i915_add_request(ring);
acb868d3
CW		 223 if (ret)
224 return ret;
225
b303cf95 226 overlay->flip_tail = tail;
a4b3a571 227 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 228 if (ret)
03f77ea5 229 return ret;
b2da9fe5 230 i915_gem_retire_requests(dev);
02e792fb 231
9bfc01a2 232 i915_gem_request_assign(&overlay->last_flip_req, NULL);
02e792fb 233 return 0;
02e792fb
DV		 234}
235
02e792fb
DV		 236/* overlay needs to be disable in OCMD reg */
237static int intel_overlay_on(struct intel_overlay *overlay)
238{
239 struct drm_device *dev = overlay->dev;
e1f99ce6 240 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 241 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb 242 int ret;
02e792fb
DV		 243
244 BUG_ON(overlay->active);
03f77ea5 245 overlay->active = 1;
b6c028e0 246
6306cb4f 247 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
106dadac 248
6d90c952 249 ret = intel_ring_begin(ring, 4);
acb868d3
CW		 250 if (ret)
251 return ret;
e1f99ce6 252
6d90c952
DV		 253 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
254 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
255 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
256 intel_ring_emit(ring, MI_NOOP);
257 intel_ring_advance(ring);
02e792fb 258
acb868d3 259 return intel_overlay_do_wait_request(overlay, NULL);
02e792fb
DV		 260}
261
262/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 263static int intel_overlay_continue(struct intel_overlay *overlay,
264 bool load_polyphase_filter)
02e792fb
DV		 265{
266 struct drm_device *dev = overlay->dev;
d5d45cc5 267 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 268 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb
DV		 269 u32 flip_addr = overlay->flip_addr;
270 u32 tmp;
e1f99ce6 271 int ret;
02e792fb
DV		 272
273 BUG_ON(!overlay->active);
274
275 if (load_polyphase_filter)
276 flip_addr |= OFC_UPDATE;
277
278 /* check for underruns */
279 tmp = I915_READ(DOVSTA);
280 if (tmp & (1 << 17))
281 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
282
6d90c952 283 ret = intel_ring_begin(ring, 2);
acb868d3 284 if (ret)
e1f99ce6 285 return ret;
acb868d3 286
6d90c952
DV		 287 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
288 intel_ring_emit(ring, flip_addr);
289 intel_ring_advance(ring);
5a5a0c64 290
9bfc01a2
JH		 291 WARN_ON(overlay->last_flip_req);
292 i915_gem_request_assign(&overlay->last_flip_req,
293 ring->outstanding_lazy_request);
9400ae5c 294 return i915_add_request(ring);
5a5a0c64
DV		 295}
296
b303cf95 297static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
5a5a0c64 298{
05394f39 299 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
5a5a0c64 300
d7f46fc4 301 i915_gem_object_ggtt_unpin(obj);
05394f39 302 drm_gem_object_unreference(&obj->base);
5a5a0c64 303
b303cf95
CW		 304 overlay->old_vid_bo = NULL;
305}
03f77ea5 306
b303cf95
CW		 307static void intel_overlay_off_tail(struct intel_overlay *overlay)
308{
05394f39 309 struct drm_i915_gem_object *obj = overlay->vid_bo;
02e792fb 310
b303cf95
CW		 311 /* never have the overlay hw on without showing a frame */
312 BUG_ON(!overlay->vid_bo);
02e792fb 313
d7f46fc4 314 i915_gem_object_ggtt_unpin(obj);
05394f39 315 drm_gem_object_unreference(&obj->base);
b303cf95 316 overlay->vid_bo = NULL;
03f77ea5 317
b303cf95
CW		 318 overlay->crtc->overlay = NULL;
319 overlay->crtc = NULL;
320 overlay->active = 0;
02e792fb
DV		 321}
322
323/* overlay needs to be disabled in OCMD reg */
ce453d81 324static int intel_overlay_off(struct intel_overlay *overlay)
02e792fb 325{
02e792fb 326 struct drm_device *dev = overlay->dev;
e1f99ce6 327 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 328 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
8dc5d147 329 u32 flip_addr = overlay->flip_addr;
e1f99ce6 330 int ret;
02e792fb
DV		 331
332 BUG_ON(!overlay->active);
333
334 /* According to intel docs the overlay hw may hang (when switching
335 * off) without loading the filter coeffs. It is however unclear whether
336 * this applies to the disabling of the overlay or to the switching off
337 * of the hw. Do it in both cases */
338 flip_addr |= OFC_UPDATE;
339
6d90c952 340 ret = intel_ring_begin(ring, 6);
acb868d3 341 if (ret)
e1f99ce6 342 return ret;
acb868d3 343
02e792fb 344 /* wait for overlay to go idle */
6d90c952
DV		 345 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
346 intel_ring_emit(ring, flip_addr);
347 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 348 /* turn overlay off */
a9193983
DV		 349 if (IS_I830(dev)) {
350 /* Workaround: Don't disable the overlay fully, since otherwise
351 * it dies on the next OVERLAY_ON cmd. */
352 intel_ring_emit(ring, MI_NOOP);
353 intel_ring_emit(ring, MI_NOOP);
354 intel_ring_emit(ring, MI_NOOP);
355 } else {
356 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
357 intel_ring_emit(ring, flip_addr);
358 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
359 }
6d90c952 360 intel_ring_advance(ring);
02e792fb 361
acb868d3 362 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
12ca45fe
DV		 363}
364
03f77ea5
DV		 365/* recover from an interruption due to a signal
366 * We have to be careful not to repeat work forever an make forward progess. */
ce453d81 367static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
03f77ea5 368{
03f77ea5 369 int ret;
03f77ea5 370
9bfc01a2 371 if (overlay->last_flip_req == NULL)
b303cf95 372 return 0;
03f77ea5 373
a4b3a571 374 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 375 if (ret)
03f77ea5 376 return ret;
a4b3a571 377 i915_gem_retire_requests(overlay->dev);
03f77ea5 378
b303cf95
CW		 379 if (overlay->flip_tail)
380 overlay->flip_tail(overlay);
03f77ea5 381
9bfc01a2 382 i915_gem_request_assign(&overlay->last_flip_req, NULL);
03f77ea5
DV		 383 return 0;
384}
385
5a5a0c64
DV		 386/* Wait for pending overlay flip and release old frame.
387 * Needs to be called before the overlay register are changed
8d74f656
CW		 388 * via intel_overlay_(un)map_regs
389 */
02e792fb
DV		 390static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
391{
5cd68c98 392 struct drm_device *dev = overlay->dev;
d5d45cc5 393 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 394 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb 395 int ret;
02e792fb 396
1362b776
VS		 397 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
398
5cd68c98
CW		 399 /* Only wait if there is actually an old frame to release to
400 * guarantee forward progress.
401 */
03f77ea5
DV		 402 if (!overlay->old_vid_bo)
403 return 0;
404
5cd68c98
CW		 405 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
406 /* synchronous slowpath */
6d90c952 407 ret = intel_ring_begin(ring, 2);
acb868d3 408 if (ret)
e1f99ce6 409 return ret;
e1f99ce6 410
6d90c952
DV		 411 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
412 intel_ring_emit(ring, MI_NOOP);
413 intel_ring_advance(ring);
5cd68c98 414
acb868d3 415 ret = intel_overlay_do_wait_request(overlay,
b303cf95 416 intel_overlay_release_old_vid_tail);
5cd68c98
CW		 417 if (ret)
418 return ret;
419 }
02e792fb 420
5cd68c98 421 intel_overlay_release_old_vid_tail(overlay);
a071fa00
DV		 422
423
424 i915_gem_track_fb(overlay->old_vid_bo, NULL,
425 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
02e792fb
DV		 426 return 0;
427}
428
1362b776
VS		 429void intel_overlay_reset(struct drm_i915_private *dev_priv)
430{
431 struct intel_overlay *overlay = dev_priv->overlay;
432
433 if (!overlay)
434 return;
435
436 intel_overlay_release_old_vid(overlay);
437
438 overlay->last_flip_req = NULL;
439 overlay->old_xscale = 0;
440 overlay->old_yscale = 0;
441 overlay->crtc = NULL;
442 overlay->active = false;
443}
444
02e792fb
DV		 445struct put_image_params {
446 int format;
447 short dst_x;
448 short dst_y;
449 short dst_w;
450 short dst_h;
451 short src_w;
452 short src_scan_h;
453 short src_scan_w;
454 short src_h;
455 short stride_Y;
456 short stride_UV;
457 int offset_Y;
458 int offset_U;
459 int offset_V;
460};
461
462static int packed_depth_bytes(u32 format)
463{
464 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 465 case I915_OVERLAY_YUV422:
466 return 4;
467 case I915_OVERLAY_YUV411:
468 /* return 6; not implemented */
469 default:
470 return -EINVAL;
02e792fb
DV		 471 }
472}
473
474static int packed_width_bytes(u32 format, short width)
475{
476 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 477 case I915_OVERLAY_YUV422:
478 return width << 1;
479 default:
480 return -EINVAL;
02e792fb
DV		 481 }
482}
483
484static int uv_hsubsampling(u32 format)
485{
486 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 487 case I915_OVERLAY_YUV422:
488 case I915_OVERLAY_YUV420:
489 return 2;
490 case I915_OVERLAY_YUV411:
491 case I915_OVERLAY_YUV410:
492 return 4;
493 default:
494 return -EINVAL;
02e792fb
DV		 495 }
496}
497
498static int uv_vsubsampling(u32 format)
499{
500 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 501 case I915_OVERLAY_YUV420:
502 case I915_OVERLAY_YUV410:
503 return 2;
504 case I915_OVERLAY_YUV422:
505 case I915_OVERLAY_YUV411:
506 return 1;
507 default:
508 return -EINVAL;
02e792fb
DV		 509 }
510}
511
512static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
513{
514 u32 mask, shift, ret;
a6c45cf0 515 if (IS_GEN2(dev)) {
02e792fb
DV		 516 mask = 0x1f;
517 shift = 5;
a6c45cf0
CW		 518 } else {
519 mask = 0x3f;
520 shift = 6;
02e792fb
DV		 521 }
522 ret = ((offset + width + mask) >> shift) - (offset >> shift);
a6c45cf0 523 if (!IS_GEN2(dev))
02e792fb 524 ret <<= 1;
0206e353 525 ret -= 1;
02e792fb
DV		 526 return ret << 2;
527}
528
529static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
530 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
531 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
532 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
533 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
534 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
535 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
536 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
537 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
538 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
539 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
540 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
541 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
542 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
543 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
544 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
545 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 546 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
547};
548
02e792fb
DV		 549static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
550 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
551 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
552 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
553 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
554 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
555 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
556 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
557 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 558 0x3000, 0x0800, 0x3000
559};
02e792fb 560
75020bc1 561static void update_polyphase_filter(struct overlay_registers __iomem *regs)
02e792fb 562{
75020bc1
BW		 563 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
564 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
565 sizeof(uv_static_hcoeffs));
02e792fb
DV		 566}
567
568static bool update_scaling_factors(struct intel_overlay *overlay,
75020bc1 569 struct overlay_registers __iomem *regs,
02e792fb
DV		 570 struct put_image_params *params)
571{
572 /* fixed point with a 12 bit shift */
573 u32 xscale, yscale, xscale_UV, yscale_UV;
574#define FP_SHIFT 12
575#define FRACT_MASK 0xfff
576 bool scale_changed = false;
577 int uv_hscale = uv_hsubsampling(params->format);
578 int uv_vscale = uv_vsubsampling(params->format);
579
580 if (params->dst_w > 1)
581 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
582 /(params->dst_w);
583 else
584 xscale = 1 << FP_SHIFT;
585
586 if (params->dst_h > 1)
587 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
588 /(params->dst_h);
589 else
590 yscale = 1 << FP_SHIFT;
591
592 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 593 xscale_UV = xscale/uv_hscale;
594 yscale_UV = yscale/uv_vscale;
595 /* make the Y scale to UV scale ratio an exact multiply */
596 xscale = xscale_UV * uv_hscale;
597 yscale = yscale_UV * uv_vscale;
02e792fb 598 /*} else {
722506f0
CW		 599 xscale_UV = 0;
600 yscale_UV = 0;
601 }*/
02e792fb
DV		 602
603 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
604 scale_changed = true;
605 overlay->old_xscale = xscale;
606 overlay->old_yscale = yscale;
607
75020bc1
BW		 608 iowrite32(((yscale & FRACT_MASK) << 20) |
609 ((xscale >> FP_SHIFT) << 16) |
610 ((xscale & FRACT_MASK) << 3),
611 &regs->YRGBSCALE);
722506f0 612
75020bc1
BW		 613 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
614 ((xscale_UV >> FP_SHIFT) << 16) |
615 ((xscale_UV & FRACT_MASK) << 3),
616 &regs->UVSCALE);
722506f0 617
75020bc1
BW		 618 iowrite32((((yscale >> FP_SHIFT) << 16) |
619 ((yscale_UV >> FP_SHIFT) << 0)),
620 &regs->UVSCALEV);
02e792fb
DV		 621
622 if (scale_changed)
623 update_polyphase_filter(regs);
624
625 return scale_changed;
626}
627
628static void update_colorkey(struct intel_overlay *overlay,
75020bc1 629 struct overlay_registers __iomem *regs)
02e792fb
DV		 630{
631 u32 key = overlay->color_key;
6ba3ddd9 632
f4510a27 633 switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
722506f0 634 case 8:
75020bc1
BW		 635 iowrite32(0, &regs->DCLRKV);
636 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
6ba3ddd9
CW		 637 break;
638
722506f0 639 case 16:
f4510a27 640 if (overlay->crtc->base.primary->fb->depth == 15) {
75020bc1
BW		 641 iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
642 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
643 &regs->DCLRKM);
722506f0 644 } else {
75020bc1
BW		 645 iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
646 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
647 &regs->DCLRKM);
722506f0 648 }
6ba3ddd9
CW		 649 break;
650
722506f0
CW		 651 case 24:
652 case 32:
75020bc1
BW		 653 iowrite32(key, &regs->DCLRKV);
654 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
6ba3ddd9 655 break;
02e792fb
DV		 656 }
657}
658
659static u32 overlay_cmd_reg(struct put_image_params *params)
660{
661 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
662
663 if (params->format & I915_OVERLAY_YUV_PLANAR) {
664 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 665 case I915_OVERLAY_YUV422:
666 cmd |= OCMD_YUV_422_PLANAR;
667 break;
668 case I915_OVERLAY_YUV420:
669 cmd |= OCMD_YUV_420_PLANAR;
670 break;
671 case I915_OVERLAY_YUV411:
672 case I915_OVERLAY_YUV410:
673 cmd |= OCMD_YUV_410_PLANAR;
674 break;
02e792fb
DV		 675 }
676 } else { /* YUV packed */
677 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 678 case I915_OVERLAY_YUV422:
679 cmd |= OCMD_YUV_422_PACKED;
680 break;
681 case I915_OVERLAY_YUV411:
682 cmd |= OCMD_YUV_411_PACKED;
683 break;
02e792fb
DV		 684 }
685
686 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 687 case I915_OVERLAY_NO_SWAP:
688 break;
689 case I915_OVERLAY_UV_SWAP:
690 cmd |= OCMD_UV_SWAP;
691 break;
692 case I915_OVERLAY_Y_SWAP:
693 cmd |= OCMD_Y_SWAP;
694 break;
695 case I915_OVERLAY_Y_AND_UV_SWAP:
696 cmd |= OCMD_Y_AND_UV_SWAP;
697 break;
02e792fb
DV		 698 }
699 }
700
701 return cmd;
702}
703
5fe82c5e 704static int intel_overlay_do_put_image(struct intel_overlay *overlay,
05394f39 705 struct drm_i915_gem_object *new_bo,
5fe82c5e 706 struct put_image_params *params)
02e792fb
DV		 707{
708 int ret, tmp_width;
75020bc1 709 struct overlay_registers __iomem *regs;
02e792fb 710 bool scale_changed = false;
02e792fb 711 struct drm_device *dev = overlay->dev;
75020bc1 712 u32 swidth, swidthsw, sheight, ostride;
a071fa00 713 enum pipe pipe = overlay->crtc->pipe;
02e792fb
DV		 714
715 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
51fd371b 716 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb
DV		 717 BUG_ON(!overlay);
718
02e792fb
DV		 719 ret = intel_overlay_release_old_vid(overlay);
720 if (ret != 0)
721 return ret;
722
2da3b9b9 723 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
02e792fb
DV		 724 if (ret != 0)
725 return ret;
726
d9e86c0e
CW		 727 ret = i915_gem_object_put_fence(new_bo);
728 if (ret)
729 goto out_unpin;
730
02e792fb 731 if (!overlay->active) {
75020bc1 732 u32 oconfig;
8d74f656 733 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 734 if (!regs) {
735 ret = -ENOMEM;
736 goto out_unpin;
737 }
75020bc1 738 oconfig = OCONF_CC_OUT_8BIT;
a6c45cf0 739 if (IS_GEN4(overlay->dev))
75020bc1 740 oconfig |= OCONF_CSC_MODE_BT709;
a071fa00 741 oconfig |= pipe == 0 ?
02e792fb 742 OCONF_PIPE_A : OCONF_PIPE_B;
75020bc1 743 iowrite32(oconfig, &regs->OCONFIG);
9bb2ff73 744 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 745
746 ret = intel_overlay_on(overlay);
747 if (ret != 0)
748 goto out_unpin;
749 }
750
8d74f656 751 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 752 if (!regs) {
753 ret = -ENOMEM;
754 goto out_unpin;
755 }
756
75020bc1
BW		 757 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
758 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
02e792fb
DV		 759
760 if (params->format & I915_OVERLAY_YUV_PACKED)
761 tmp_width = packed_width_bytes(params->format, params->src_w);
762 else
763 tmp_width = params->src_w;
764
75020bc1
BW		 765 swidth = params->src_w;
766 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
767 sheight = params->src_h;
f343c5f6 768 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y);
75020bc1 769 ostride = params->stride_Y;
02e792fb
DV		 770
771 if (params->format & I915_OVERLAY_YUV_PLANAR) {
772 int uv_hscale = uv_hsubsampling(params->format);
773 int uv_vscale = uv_vsubsampling(params->format);
774 u32 tmp_U, tmp_V;
75020bc1 775 swidth |= (params->src_w/uv_hscale) << 16;
02e792fb 776 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 777 params->src_w/uv_hscale);
02e792fb 778 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 779 params->src_w/uv_hscale);
75020bc1
BW		 780 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
781 sheight |= (params->src_h/uv_vscale) << 16;
f343c5f6
BW		 782 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U);
783 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V);
75020bc1 784 ostride |= params->stride_UV << 16;
02e792fb
DV		 785 }
786
75020bc1
BW		 787 iowrite32(swidth, &regs->SWIDTH);
788 iowrite32(swidthsw, &regs->SWIDTHSW);
789 iowrite32(sheight, &regs->SHEIGHT);
790 iowrite32(ostride, &regs->OSTRIDE);
791
02e792fb
DV		 792 scale_changed = update_scaling_factors(overlay, regs, params);
793
794 update_colorkey(overlay, regs);
795
75020bc1 796 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
02e792fb 797
9bb2ff73 798 intel_overlay_unmap_regs(overlay, regs);
02e792fb 799
8dc5d147
CW		 800 ret = intel_overlay_continue(overlay, scale_changed);
801 if (ret)
802 goto out_unpin;
02e792fb 803
a071fa00
DV		 804 i915_gem_track_fb(overlay->vid_bo, new_bo,
805 INTEL_FRONTBUFFER_OVERLAY(pipe));
806
02e792fb 807 overlay->old_vid_bo = overlay->vid_bo;
05394f39 808 overlay->vid_bo = new_bo;
02e792fb 809
f99d7069
DV		 810 intel_frontbuffer_flip(dev,
811 INTEL_FRONTBUFFER_OVERLAY(pipe));
812
02e792fb
DV		 813 return 0;
814
815out_unpin:
d7f46fc4 816 i915_gem_object_ggtt_unpin(new_bo);
02e792fb
DV		 817 return ret;
818}
819
ce453d81 820int intel_overlay_switch_off(struct intel_overlay *overlay)
02e792fb 821{
75020bc1 822 struct overlay_registers __iomem *regs;
02e792fb 823 struct drm_device *dev = overlay->dev;
5dcdbcb0 824 int ret;
02e792fb
DV		 825
826 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
51fd371b 827 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb 828
ce453d81 829 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 830 if (ret != 0)
831 return ret;
9bedb974 832
02e792fb
DV		 833 if (!overlay->active)
834 return 0;
835
02e792fb
DV		 836 ret = intel_overlay_release_old_vid(overlay);
837 if (ret != 0)
838 return ret;
839
8d74f656 840 regs = intel_overlay_map_regs(overlay);
75020bc1 841 iowrite32(0, &regs->OCMD);
9bb2ff73 842 intel_overlay_unmap_regs(overlay, regs);
02e792fb 843
ce453d81 844 ret = intel_overlay_off(overlay);
03f77ea5
DV		 845 if (ret != 0)
846 return ret;
847
12ca45fe 848 intel_overlay_off_tail(overlay);
02e792fb
DV		 849 return 0;
850}
851
852static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
853 struct intel_crtc *crtc)
854{
f7abfe8b 855 if (!crtc->active)
02e792fb
DV		 856 return -EINVAL;
857
02e792fb 858 /* can't use the overlay with double wide pipe */
6e3c9717 859 if (crtc->config->double_wide)
02e792fb
DV		 860 return -EINVAL;
861
862 return 0;
863}
864
865static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
866{
867 struct drm_device *dev = overlay->dev;
d5d45cc5 868 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 869 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 870 u32 ratio;
02e792fb
DV		 871
872 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 873 * line with the intel documentation for the i965
874 */
a6c45cf0 875 if (INTEL_INFO(dev)->gen >= 4) {
0206e353 876 /* on i965 use the PGM reg to read out the autoscaler values */
a6c45cf0
CW		 877 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
878 } else {
446d2183
CW		 879 if (pfit_control & VERT_AUTO_SCALE)
880 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 881 else
446d2183
CW		 882 ratio = I915_READ(PFIT_PGM_RATIOS);
883 ratio >>= PFIT_VERT_SCALE_SHIFT;
02e792fb
DV		 884 }
885
886 overlay->pfit_vscale_ratio = ratio;
887}
888
889static int check_overlay_dst(struct intel_overlay *overlay,
890 struct drm_intel_overlay_put_image *rec)
891{
892 struct drm_display_mode *mode = &overlay->crtc->base.mode;
893
75c13993
DV		 894 if (rec->dst_x < mode->hdisplay &&
895 rec->dst_x + rec->dst_width <= mode->hdisplay &&
896 rec->dst_y < mode->vdisplay &&
897 rec->dst_y + rec->dst_height <= mode->vdisplay)
02e792fb
DV		 898 return 0;
899 else
900 return -EINVAL;
901}
902
903static int check_overlay_scaling(struct put_image_params *rec)
904{
905 u32 tmp;
906
907 /* downscaling limit is 8.0 */
908 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
909 if (tmp > 7)
910 return -EINVAL;
911 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
912 if (tmp > 7)
913 return -EINVAL;
914
915 return 0;
916}
917
918static int check_overlay_src(struct drm_device *dev,
919 struct drm_intel_overlay_put_image *rec,
05394f39 920 struct drm_i915_gem_object *new_bo)
02e792fb 921{
02e792fb
DV		 922 int uv_hscale = uv_hsubsampling(rec->flags);
923 int uv_vscale = uv_vsubsampling(rec->flags);
8f28f54a
DC		 924 u32 stride_mask;
925 int depth;
926 u32 tmp;
02e792fb
DV		 927
928 /* check src dimensions */
929 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 930 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 931 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 932 return -EINVAL;
933 } else {
722506f0 934 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 935 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 936 return -EINVAL;
937 }
9f7c3f44 938
02e792fb 939 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 940 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 941 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 942 return -EINVAL;
943
a1efd14a 944 /* check alignment constraints */
02e792fb 945 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 946 case I915_OVERLAY_RGB:
947 /* not implemented */
948 return -EINVAL;
9f7c3f44 949
722506f0 950 case I915_OVERLAY_YUV_PACKED:
722506f0 951 if (uv_vscale != 1)
02e792fb 952 return -EINVAL;
9f7c3f44
CW		 953
954 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 955 if (depth < 0)
956 return depth;
9f7c3f44 957
722506f0
CW		 958 /* ignore UV planes */
959 rec->stride_UV = 0;
960 rec->offset_U = 0;
961 rec->offset_V = 0;
962 /* check pixel alignment */
963 if (rec->offset_Y % depth)
964 return -EINVAL;
965 break;
9f7c3f44 966
722506f0
CW		 967 case I915_OVERLAY_YUV_PLANAR:
968 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 969 return -EINVAL;
722506f0
CW		 970 /* no offset restrictions for planar formats */
971 break;
9f7c3f44 972
722506f0
CW		 973 default:
974 return -EINVAL;
02e792fb
DV		 975 }
976
977 if (rec->src_width % uv_hscale)
978 return -EINVAL;
979
980 /* stride checking */
a1efd14a
CW		 981 if (IS_I830(dev) || IS_845G(dev))
982 stride_mask = 255;
983 else
984 stride_mask = 63;
02e792fb
DV		 985
986 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
987 return -EINVAL;
a6c45cf0 988 if (IS_GEN4(dev) && rec->stride_Y < 512)
02e792fb
DV		 989 return -EINVAL;
990
991 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 992 4096 : 8192;
993 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 994 return -EINVAL;
995
996 /* check buffer dimensions */
997 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 998 case I915_OVERLAY_RGB:
999 case I915_OVERLAY_YUV_PACKED:
1000 /* always 4 Y values per depth pixels */
1001 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1002 return -EINVAL;
1003
1004 tmp = rec->stride_Y*rec->src_height;
05394f39 1005 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0
CW		 1006 return -EINVAL;
1007 break;
1008
1009 case I915_OVERLAY_YUV_PLANAR:
1010 if (rec->src_width > rec->stride_Y)
1011 return -EINVAL;
1012 if (rec->src_width/uv_hscale > rec->stride_UV)
1013 return -EINVAL;
1014
9f7c3f44 1015 tmp = rec->stride_Y * rec->src_height;
05394f39 1016 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0 1017 return -EINVAL;
9f7c3f44
CW		 1018
1019 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
05394f39
CW		 1020 if (rec->offset_U + tmp > new_bo->base.size ||
1021 rec->offset_V + tmp > new_bo->base.size)
722506f0
CW		 1022 return -EINVAL;
1023 break;
02e792fb
DV		 1024 }
1025
1026 return 0;
1027}
1028
e9e331a8
CW		 1029/**
1030 * Return the pipe currently connected to the panel fitter,
1031 * or -1 if the panel fitter is not present or not in use
1032 */
1033static int intel_panel_fitter_pipe(struct drm_device *dev)
1034{
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 u32 pfit_control;
1037
1038 /* i830 doesn't have a panel fitter */
dc9e7dec 1039 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
e9e331a8
CW		 1040 return -1;
1041
1042 pfit_control = I915_READ(PFIT_CONTROL);
1043
1044 /* See if the panel fitter is in use */
1045 if ((pfit_control & PFIT_ENABLE) == 0)
1046 return -1;
1047
1048 /* 965 can place panel fitter on either pipe */
a6c45cf0 1049 if (IS_GEN4(dev))
e9e331a8
CW		 1050 return (pfit_control >> 29) & 0x3;
1051
1052 /* older chips can only use pipe 1 */
1053 return 1;
1054}
1055
02e792fb 1056int intel_overlay_put_image(struct drm_device *dev, void *data,
0206e353 1057 struct drm_file *file_priv)
02e792fb
DV		 1058{
1059 struct drm_intel_overlay_put_image *put_image_rec = data;
d5d45cc5 1060 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1061 struct intel_overlay *overlay;
7707e653 1062 struct drm_crtc *drmmode_crtc;
02e792fb 1063 struct intel_crtc *crtc;
05394f39 1064 struct drm_i915_gem_object *new_bo;
02e792fb
DV		 1065 struct put_image_params *params;
1066 int ret;
1067
1cff8f6b 1068 /* No need to check for DRIVER_MODESET - we don't set it up then. */
02e792fb
DV		 1069 overlay = dev_priv->overlay;
1070 if (!overlay) {
1071 DRM_DEBUG("userspace bug: no overlay\n");
1072 return -ENODEV;
1073 }
1074
1075 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
a0e99e68 1076 drm_modeset_lock_all(dev);
02e792fb
DV		 1077 mutex_lock(&dev->struct_mutex);
1078
ce453d81 1079 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1080
1081 mutex_unlock(&dev->struct_mutex);
a0e99e68 1082 drm_modeset_unlock_all(dev);
02e792fb
DV		 1083
1084 return ret;
1085 }
1086
b14c5679 1087 params = kmalloc(sizeof(*params), GFP_KERNEL);
02e792fb
DV		 1088 if (!params)
1089 return -ENOMEM;
1090
7707e653
RC		 1091 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1092 if (!drmmode_crtc) {
915a428e
DC		 1093 ret = -ENOENT;
1094 goto out_free;
1095 }
7707e653 1096 crtc = to_intel_crtc(drmmode_crtc);
02e792fb 1097
05394f39
CW		 1098 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1099 put_image_rec->bo_handle));
c8725226 1100 if (&new_bo->base == NULL) {
915a428e
DC		 1101 ret = -ENOENT;
1102 goto out_free;
1103 }
02e792fb 1104
a0e99e68 1105 drm_modeset_lock_all(dev);
02e792fb
DV		 1106 mutex_lock(&dev->struct_mutex);
1107
d9e86c0e 1108 if (new_bo->tiling_mode) {
3b25b31f 1109 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
d9e86c0e
CW		 1110 ret = -EINVAL;
1111 goto out_unlock;
1112 }
1113
ce453d81 1114 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 1115 if (ret != 0)
1116 goto out_unlock;
03f77ea5 1117
02e792fb
DV		 1118 if (overlay->crtc != crtc) {
1119 struct drm_display_mode *mode = &crtc->base.mode;
ce453d81 1120 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1121 if (ret != 0)
1122 goto out_unlock;
1123
1124 ret = check_overlay_possible_on_crtc(overlay, crtc);
1125 if (ret != 0)
1126 goto out_unlock;
1127
1128 overlay->crtc = crtc;
1129 crtc->overlay = overlay;
1130
e9e331a8
CW		 1131 /* line too wide, i.e. one-line-mode */
1132 if (mode->hdisplay > 1024 &&
1133 intel_panel_fitter_pipe(dev) == crtc->pipe) {
02e792fb
DV		 1134 overlay->pfit_active = 1;
1135 update_pfit_vscale_ratio(overlay);
1136 } else
1137 overlay->pfit_active = 0;
1138 }
1139
1140 ret = check_overlay_dst(overlay, put_image_rec);
1141 if (ret != 0)
1142 goto out_unlock;
1143
1144 if (overlay->pfit_active) {
1145 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1146 overlay->pfit_vscale_ratio);
02e792fb
DV		 1147 /* shifting right rounds downwards, so add 1 */
1148 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1149 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1150 } else {
1151 params->dst_y = put_image_rec->dst_y;
1152 params->dst_h = put_image_rec->dst_height;
1153 }
1154 params->dst_x = put_image_rec->dst_x;
1155 params->dst_w = put_image_rec->dst_width;
1156
1157 params->src_w = put_image_rec->src_width;
1158 params->src_h = put_image_rec->src_height;
1159 params->src_scan_w = put_image_rec->src_scan_width;
1160 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1161 if (params->src_scan_h > params->src_h ||
1162 params->src_scan_w > params->src_w) {
02e792fb
DV		 1163 ret = -EINVAL;
1164 goto out_unlock;
1165 }
1166
1167 ret = check_overlay_src(dev, put_image_rec, new_bo);
1168 if (ret != 0)
1169 goto out_unlock;
1170 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1171 params->stride_Y = put_image_rec->stride_Y;
1172 params->stride_UV = put_image_rec->stride_UV;
1173 params->offset_Y = put_image_rec->offset_Y;
1174 params->offset_U = put_image_rec->offset_U;
1175 params->offset_V = put_image_rec->offset_V;
1176
1177 /* Check scaling after src size to prevent a divide-by-zero. */
1178 ret = check_overlay_scaling(params);
1179 if (ret != 0)
1180 goto out_unlock;
1181
1182 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1183 if (ret != 0)
1184 goto out_unlock;
1185
1186 mutex_unlock(&dev->struct_mutex);
a0e99e68 1187 drm_modeset_unlock_all(dev);
02e792fb
DV		 1188
1189 kfree(params);
1190
1191 return 0;
1192
1193out_unlock:
1194 mutex_unlock(&dev->struct_mutex);
a0e99e68 1195 drm_modeset_unlock_all(dev);
05394f39 1196 drm_gem_object_unreference_unlocked(&new_bo->base);
915a428e 1197out_free:
02e792fb
DV		 1198 kfree(params);
1199
1200 return ret;
1201}
1202
1203static void update_reg_attrs(struct intel_overlay *overlay,
75020bc1 1204 struct overlay_registers __iomem *regs)
02e792fb 1205{
75020bc1
BW		 1206 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1207 &regs->OCLRC0);
1208 iowrite32(overlay->saturation, &regs->OCLRC1);
02e792fb
DV		 1209}
1210
1211static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1212{
1213 int i;
1214
1215 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1216 return false;
1217
1218 for (i = 0; i < 3; i++) {
722506f0 1219 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1220 return false;
1221 }
1222
1223 return true;
1224}
1225
1226static bool check_gamma5_errata(u32 gamma5)
1227{
1228 int i;
1229
1230 for (i = 0; i < 3; i++) {
1231 if (((gamma5 >> i*8) & 0xff) == 0x80)
1232 return false;
1233 }
1234
1235 return true;
1236}
1237
1238static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1239{
722506f0
CW		 1240 if (!check_gamma_bounds(0, attrs->gamma0) ||
1241 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1242 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1243 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1244 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1245 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1246 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1247 return -EINVAL;
722506f0 1248
02e792fb
DV		 1249 if (!check_gamma5_errata(attrs->gamma5))
1250 return -EINVAL;
722506f0 1251
02e792fb
DV		 1252 return 0;
1253}
1254
1255int intel_overlay_attrs(struct drm_device *dev, void *data,
0206e353 1256 struct drm_file *file_priv)
02e792fb
DV		 1257{
1258 struct drm_intel_overlay_attrs *attrs = data;
d5d45cc5 1259 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1260 struct intel_overlay *overlay;
75020bc1 1261 struct overlay_registers __iomem *regs;
02e792fb
DV		 1262 int ret;
1263
1cff8f6b 1264 /* No need to check for DRIVER_MODESET - we don't set it up then. */
02e792fb
DV		 1265 overlay = dev_priv->overlay;
1266 if (!overlay) {
1267 DRM_DEBUG("userspace bug: no overlay\n");
1268 return -ENODEV;
1269 }
1270
a0e99e68 1271 drm_modeset_lock_all(dev);
02e792fb
DV		 1272 mutex_lock(&dev->struct_mutex);
1273
60fc332c 1274 ret = -EINVAL;
02e792fb 1275 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1276 attrs->color_key = overlay->color_key;
02e792fb 1277 attrs->brightness = overlay->brightness;
60fc332c 1278 attrs->contrast = overlay->contrast;
02e792fb
DV		 1279 attrs->saturation = overlay->saturation;
1280
a6c45cf0 1281 if (!IS_GEN2(dev)) {
02e792fb
DV		 1282 attrs->gamma0 = I915_READ(OGAMC0);
1283 attrs->gamma1 = I915_READ(OGAMC1);
1284 attrs->gamma2 = I915_READ(OGAMC2);
1285 attrs->gamma3 = I915_READ(OGAMC3);
1286 attrs->gamma4 = I915_READ(OGAMC4);
1287 attrs->gamma5 = I915_READ(OGAMC5);
1288 }
02e792fb 1289 } else {
60fc332c 1290 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1291 goto out_unlock;
60fc332c 1292 if (attrs->contrast > 255)
02e792fb 1293 goto out_unlock;
60fc332c 1294 if (attrs->saturation > 1023)
02e792fb 1295 goto out_unlock;
02e792fb 1296
60fc332c
CW		 1297 overlay->color_key = attrs->color_key;
1298 overlay->brightness = attrs->brightness;
1299 overlay->contrast = attrs->contrast;
1300 overlay->saturation = attrs->saturation;
02e792fb 1301
8d74f656 1302 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1303 if (!regs) {
1304 ret = -ENOMEM;
1305 goto out_unlock;
1306 }
1307
1308 update_reg_attrs(overlay, regs);
1309
9bb2ff73 1310 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1311
1312 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
a6c45cf0 1313 if (IS_GEN2(dev))
02e792fb 1314 goto out_unlock;
02e792fb
DV		 1315
1316 if (overlay->active) {
1317 ret = -EBUSY;
1318 goto out_unlock;
1319 }
1320
1321 ret = check_gamma(attrs);
60fc332c 1322 if (ret)
02e792fb
DV		 1323 goto out_unlock;
1324
1325 I915_WRITE(OGAMC0, attrs->gamma0);
1326 I915_WRITE(OGAMC1, attrs->gamma1);
1327 I915_WRITE(OGAMC2, attrs->gamma2);
1328 I915_WRITE(OGAMC3, attrs->gamma3);
1329 I915_WRITE(OGAMC4, attrs->gamma4);
1330 I915_WRITE(OGAMC5, attrs->gamma5);
1331 }
02e792fb
DV		 1332 }
1333
60fc332c 1334 ret = 0;
02e792fb
DV		 1335out_unlock:
1336 mutex_unlock(&dev->struct_mutex);
a0e99e68 1337 drm_modeset_unlock_all(dev);
02e792fb
DV		 1338
1339 return ret;
1340}
1341
1342void intel_setup_overlay(struct drm_device *dev)
1343{
d5d45cc5 1344 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1345 struct intel_overlay *overlay;
05394f39 1346 struct drm_i915_gem_object *reg_bo;
75020bc1 1347 struct overlay_registers __iomem *regs;
02e792fb
DV		 1348 int ret;
1349
31578148 1350 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1351 return;
1352
b14c5679 1353 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
02e792fb
DV		 1354 if (!overlay)
1355 return;
79d24273
CW		 1356
1357 mutex_lock(&dev->struct_mutex);
1358 if (WARN_ON(dev_priv->overlay))
1359 goto out_free;
1360
02e792fb
DV		 1361 overlay->dev = dev;
1362
f63a484c
DV		 1363 reg_bo = NULL;
1364 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1365 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
80405138
CW		 1366 if (reg_bo == NULL)
1367 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1368 if (reg_bo == NULL)
02e792fb 1369 goto out_free;
05394f39 1370 overlay->reg_bo = reg_bo;
02e792fb 1371
31578148 1372 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
00731155 1373 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
0206e353
AJ		 1374 if (ret) {
1375 DRM_ERROR("failed to attach phys overlay regs\n");
1376 goto out_free_bo;
1377 }
00731155 1378 overlay->flip_addr = reg_bo->phys_handle->busaddr;
31578148 1379 } else {
1ec9e26d 1380 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
02e792fb 1381 if (ret) {
0206e353
AJ		 1382 DRM_ERROR("failed to pin overlay register bo\n");
1383 goto out_free_bo;
1384 }
f343c5f6 1385 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
0ddc1289
CW		 1386
1387 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1388 if (ret) {
0206e353
AJ		 1389 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1390 goto out_unpin_bo;
1391 }
02e792fb
DV		 1392 }
1393
1394 /* init all values */
1395 overlay->color_key = 0x0101fe;
1396 overlay->brightness = -19;
1397 overlay->contrast = 75;
1398 overlay->saturation = 146;
1399
8d74f656 1400 regs = intel_overlay_map_regs(overlay);
02e792fb 1401 if (!regs)
79d24273 1402 goto out_unpin_bo;
02e792fb 1403
75020bc1 1404 memset_io(regs, 0, sizeof(struct overlay_registers));
02e792fb 1405 update_polyphase_filter(regs);
02e792fb
DV		 1406 update_reg_attrs(overlay, regs);
1407
9bb2ff73 1408 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1409
1410 dev_priv->overlay = overlay;
79d24273 1411 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1412 DRM_INFO("initialized overlay support\n");
1413 return;
1414
0ddc1289 1415out_unpin_bo:
79d24273 1416 if (!OVERLAY_NEEDS_PHYSICAL(dev))
d7f46fc4 1417 i915_gem_object_ggtt_unpin(reg_bo);
02e792fb 1418out_free_bo:
05394f39 1419 drm_gem_object_unreference(&reg_bo->base);
02e792fb 1420out_free:
79d24273 1421 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1422 kfree(overlay);
1423 return;
1424}
1425
1426void intel_cleanup_overlay(struct drm_device *dev)
1427{
d5d45cc5 1428 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1429
62cf4e6f
CW		 1430 if (!dev_priv->overlay)
1431 return;
02e792fb 1432
62cf4e6f
CW		 1433 /* The bo's should be free'd by the generic code already.
1434 * Furthermore modesetting teardown happens beforehand so the
1435 * hardware should be off already */
1436 BUG_ON(dev_priv->overlay->active);
1437
1438 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1439 kfree(dev_priv->overlay);
02e792fb 1440}
6ef3d427
CW		 1441
1442struct intel_overlay_error_state {
1443 struct overlay_registers regs;
1444 unsigned long base;
1445 u32 dovsta;
1446 u32 isr;
1447};
1448
75020bc1 1449static struct overlay_registers __iomem *
c48c43e4 1450intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
3bd3c932 1451{
d5d45cc5 1452 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 1453 struct overlay_registers __iomem *regs;
3bd3c932
CW		 1454
1455 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
75020bc1
BW		 1456 /* Cast to make sparse happy, but it's wc memory anyway, so
1457 * equivalent to the wc io mapping on X86. */
1458 regs = (struct overlay_registers __iomem *)
00731155 1459 overlay->reg_bo->phys_handle->vaddr;
3bd3c932 1460 else
5d4545ae 1461 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
f343c5f6 1462 i915_gem_obj_ggtt_offset(overlay->reg_bo));
3bd3c932
CW		 1463
1464 return regs;
1465}
1466
1467static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
75020bc1 1468 struct overlay_registers __iomem *regs)
3bd3c932
CW		 1469{
1470 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
c48c43e4 1471 io_mapping_unmap_atomic(regs);
3bd3c932
CW		 1472}
1473
1474
6ef3d427
CW		 1475struct intel_overlay_error_state *
1476intel_overlay_capture_error_state(struct drm_device *dev)
1477{
d5d45cc5 1478 struct drm_i915_private *dev_priv = dev->dev_private;
6ef3d427
CW		 1479 struct intel_overlay *overlay = dev_priv->overlay;
1480 struct intel_overlay_error_state *error;
1481 struct overlay_registers __iomem *regs;
1482
1483 if (!overlay || !overlay->active)
1484 return NULL;
1485
1486 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1487 if (error == NULL)
1488 return NULL;
1489
1490 error->dovsta = I915_READ(DOVSTA);
1491 error->isr = I915_READ(ISR);
31578148 1492 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 1493 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
31578148 1494 else
f343c5f6 1495 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
6ef3d427
CW		 1496
1497 regs = intel_overlay_map_regs_atomic(overlay);
1498 if (!regs)
1499 goto err;
1500
1501 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
c48c43e4 1502 intel_overlay_unmap_regs_atomic(overlay, regs);
6ef3d427
CW		 1503
1504 return error;
1505
1506err:
1507 kfree(error);
1508 return NULL;
1509}
1510
1511void
edc3d884
MK		 1512intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1513 struct intel_overlay_error_state *error)
6ef3d427 1514{
edc3d884
MK		 1515 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1516 error->dovsta, error->isr);
1517 i915_error_printf(m, " Register file at 0x%08lx:\n",
1518 error->base);
6ef3d427 1519
edc3d884 1520#define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
6ef3d427
CW		 1521 P(OBUF_0Y);
1522 P(OBUF_1Y);
1523 P(OBUF_0U);
1524 P(OBUF_0V);
1525 P(OBUF_1U);
1526 P(OBUF_1V);
1527 P(OSTRIDE);
1528 P(YRGB_VPH);
1529 P(UV_VPH);
1530 P(HORZ_PH);
1531 P(INIT_PHS);
1532 P(DWINPOS);
1533 P(DWINSZ);
1534 P(SWIDTH);
1535 P(SWIDTHSW);
1536 P(SHEIGHT);
1537 P(YRGBSCALE);
1538 P(UVSCALE);
1539 P(OCLRC0);
1540 P(OCLRC1);
1541 P(DCLRKV);
1542 P(DCLRKM);
1543 P(SCLRKVH);
1544 P(SCLRKVL);
1545 P(SCLRKEN);
1546 P(OCONFIG);
1547 P(OCMD);
1548 P(OSTART_0Y);
1549 P(OSTART_1Y);
1550 P(OSTART_0U);
1551 P(OSTART_0V);
1552 P(OSTART_1U);
1553 P(OSTART_1V);
1554 P(OTILEOFF_0Y);
1555 P(OTILEOFF_1Y);
1556 P(OTILEOFF_0U);
1557 P(OTILEOFF_0V);
1558 P(OTILEOFF_1U);
1559 P(OTILEOFF_1V);
1560 P(FASTHSCALE);
1561 P(UVSCALEV);
1562#undef P
1563}
Linux kernel - Deliverables
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