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drm/i915: Convert 'trace_irq' to use requests rather than seqnos
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
02e792fb
DV		 30#include "i915_drv.h"
31#include "i915_reg.h"
32#include "intel_drv.h"
33
34/* Limits for overlay size. According to intel doc, the real limits are:
35 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
36 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
37 * the mininum of both. */
38#define IMAGE_MAX_WIDTH 2048
39#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
40/* on 830 and 845 these large limits result in the card hanging */
41#define IMAGE_MAX_WIDTH_LEGACY 1024
42#define IMAGE_MAX_HEIGHT_LEGACY 1088
43
44/* overlay register definitions */
45/* OCMD register */
46#define OCMD_TILED_SURFACE (0x1<<19)
47#define OCMD_MIRROR_MASK (0x3<<17)
48#define OCMD_MIRROR_MODE (0x3<<17)
49#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
50#define OCMD_MIRROR_VERTICAL (0x2<<17)
51#define OCMD_MIRROR_BOTH (0x3<<17)
52#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
53#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
54#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
55#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
56#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
57#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
58#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
59#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
60#define OCMD_YUV_422_PACKED (0x8<<10)
61#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
62#define OCMD_YUV_420_PLANAR (0xc<<10)
63#define OCMD_YUV_422_PLANAR (0xd<<10)
64#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
65#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
66#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 67#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 68#define OCMD_BUF_TYPE_FRAME (0x0<<5)
69#define OCMD_BUF_TYPE_FIELD (0x1<<5)
70#define OCMD_TEST_MODE (0x1<<4)
71#define OCMD_BUFFER_SELECT (0x3<<2)
72#define OCMD_BUFFER0 (0x0<<2)
73#define OCMD_BUFFER1 (0x1<<2)
74#define OCMD_FIELD_SELECT (0x1<<2)
75#define OCMD_FIELD0 (0x0<<1)
76#define OCMD_FIELD1 (0x1<<1)
77#define OCMD_ENABLE (0x1<<0)
78
79/* OCONFIG register */
80#define OCONF_PIPE_MASK (0x1<<18)
81#define OCONF_PIPE_A (0x0<<18)
82#define OCONF_PIPE_B (0x1<<18)
83#define OCONF_GAMMA2_ENABLE (0x1<<16)
84#define OCONF_CSC_MODE_BT601 (0x0<<5)
85#define OCONF_CSC_MODE_BT709 (0x1<<5)
86#define OCONF_CSC_BYPASS (0x1<<4)
87#define OCONF_CC_OUT_8BIT (0x1<<3)
88#define OCONF_TEST_MODE (0x1<<2)
89#define OCONF_THREE_LINE_BUFFER (0x1<<0)
90#define OCONF_TWO_LINE_BUFFER (0x0<<0)
91
92/* DCLRKM (dst-key) register */
93#define DST_KEY_ENABLE (0x1<<31)
94#define CLK_RGB24_MASK 0x0
95#define CLK_RGB16_MASK 0x070307
96#define CLK_RGB15_MASK 0x070707
97#define CLK_RGB8I_MASK 0xffffff
98
99#define RGB16_TO_COLORKEY(c) \
100 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
101#define RGB15_TO_COLORKEY(c) \
102 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
103
104/* overlay flip addr flag */
105#define OFC_UPDATE 0x1
106
107/* polyphase filter coefficients */
108#define N_HORIZ_Y_TAPS 5
109#define N_VERT_Y_TAPS 3
110#define N_HORIZ_UV_TAPS 3
111#define N_VERT_UV_TAPS 3
112#define N_PHASES 17
113#define MAX_TAPS 5
114
115/* memory bufferd overlay registers */
116struct overlay_registers {
0206e353
AJ		 117 u32 OBUF_0Y;
118 u32 OBUF_1Y;
119 u32 OBUF_0U;
120 u32 OBUF_0V;
121 u32 OBUF_1U;
122 u32 OBUF_1V;
123 u32 OSTRIDE;
124 u32 YRGB_VPH;
125 u32 UV_VPH;
126 u32 HORZ_PH;
127 u32 INIT_PHS;
128 u32 DWINPOS;
129 u32 DWINSZ;
130 u32 SWIDTH;
131 u32 SWIDTHSW;
132 u32 SHEIGHT;
133 u32 YRGBSCALE;
134 u32 UVSCALE;
135 u32 OCLRC0;
136 u32 OCLRC1;
137 u32 DCLRKV;
138 u32 DCLRKM;
139 u32 SCLRKVH;
140 u32 SCLRKVL;
141 u32 SCLRKEN;
142 u32 OCONFIG;
143 u32 OCMD;
144 u32 RESERVED1; /* 0x6C */
145 u32 OSTART_0Y;
146 u32 OSTART_1Y;
147 u32 OSTART_0U;
148 u32 OSTART_0V;
149 u32 OSTART_1U;
150 u32 OSTART_1V;
151 u32 OTILEOFF_0Y;
152 u32 OTILEOFF_1Y;
153 u32 OTILEOFF_0U;
154 u32 OTILEOFF_0V;
155 u32 OTILEOFF_1U;
156 u32 OTILEOFF_1V;
157 u32 FASTHSCALE; /* 0xA0 */
158 u32 UVSCALEV; /* 0xA4 */
159 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
160 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
161 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
162 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
163 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
164 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
165 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
166 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
167 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
02e792fb
DV		 168};
169
23f09ce3
CW		 170struct intel_overlay {
171 struct drm_device *dev;
172 struct intel_crtc *crtc;
173 struct drm_i915_gem_object *vid_bo;
174 struct drm_i915_gem_object *old_vid_bo;
175 int active;
176 int pfit_active;
177 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
178 u32 color_key;
179 u32 brightness, contrast, saturation;
180 u32 old_xscale, old_yscale;
181 /* register access */
182 u32 flip_addr;
183 struct drm_i915_gem_object *reg_bo;
184 /* flip handling */
9bfc01a2 185 struct drm_i915_gem_request *last_flip_req;
b303cf95 186 void (*flip_tail)(struct intel_overlay *);
23f09ce3 187};
02e792fb 188
75020bc1 189static struct overlay_registers __iomem *
8d74f656 190intel_overlay_map_regs(struct intel_overlay *overlay)
02e792fb 191{
d5d45cc5 192 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 193 struct overlay_registers __iomem *regs;
02e792fb 194
9bb2ff73 195 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 196 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
9bb2ff73 197 else
5d4545ae 198 regs = io_mapping_map_wc(dev_priv->gtt.mappable,
f343c5f6 199 i915_gem_obj_ggtt_offset(overlay->reg_bo));
02e792fb 200
9bb2ff73 201 return regs;
8d74f656 202}
02e792fb 203
9bb2ff73 204static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
75020bc1 205 struct overlay_registers __iomem *regs)
8d74f656
CW		 206{
207 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 208 io_mapping_unmap(regs);
02e792fb
DV		 209}
210
b6c028e0 211static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
b303cf95 212 void (*tail)(struct intel_overlay *))
02e792fb
DV		 213{
214 struct drm_device *dev = overlay->dev;
d5d45cc5 215 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 216 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
b6c028e0 217 int ret;
02e792fb 218
b303cf95 219 BUG_ON(overlay->last_flip_req);
9bfc01a2
JH		 220 i915_gem_request_assign(&overlay->last_flip_req,
221 ring->outstanding_lazy_request);
9400ae5c 222 ret = i915_add_request(ring);
acb868d3
CW		 223 if (ret)
224 return ret;
225
b303cf95 226 overlay->flip_tail = tail;
a4b3a571 227 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 228 if (ret)
03f77ea5 229 return ret;
b2da9fe5 230 i915_gem_retire_requests(dev);
02e792fb 231
9bfc01a2 232 i915_gem_request_assign(&overlay->last_flip_req, NULL);
02e792fb 233 return 0;
02e792fb
DV		 234}
235
02e792fb
DV		 236/* overlay needs to be disable in OCMD reg */
237static int intel_overlay_on(struct intel_overlay *overlay)
238{
239 struct drm_device *dev = overlay->dev;
e1f99ce6 240 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 241 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb 242 int ret;
02e792fb
DV		 243
244 BUG_ON(overlay->active);
03f77ea5 245 overlay->active = 1;
b6c028e0 246
6306cb4f 247 WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
106dadac 248
6d90c952 249 ret = intel_ring_begin(ring, 4);
acb868d3
CW		 250 if (ret)
251 return ret;
e1f99ce6 252
6d90c952
DV		 253 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
254 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
255 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
256 intel_ring_emit(ring, MI_NOOP);
257 intel_ring_advance(ring);
02e792fb 258
acb868d3 259 return intel_overlay_do_wait_request(overlay, NULL);
02e792fb
DV		 260}
261
262/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 263static int intel_overlay_continue(struct intel_overlay *overlay,
264 bool load_polyphase_filter)
02e792fb
DV		 265{
266 struct drm_device *dev = overlay->dev;
d5d45cc5 267 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 268 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb
DV		 269 u32 flip_addr = overlay->flip_addr;
270 u32 tmp;
e1f99ce6 271 int ret;
02e792fb
DV		 272
273 BUG_ON(!overlay->active);
274
275 if (load_polyphase_filter)
276 flip_addr |= OFC_UPDATE;
277
278 /* check for underruns */
279 tmp = I915_READ(DOVSTA);
280 if (tmp & (1 << 17))
281 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
282
6d90c952 283 ret = intel_ring_begin(ring, 2);
acb868d3 284 if (ret)
e1f99ce6 285 return ret;
acb868d3 286
6d90c952
DV		 287 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
288 intel_ring_emit(ring, flip_addr);
289 intel_ring_advance(ring);
5a5a0c64 290
9bfc01a2
JH		 291 WARN_ON(overlay->last_flip_req);
292 i915_gem_request_assign(&overlay->last_flip_req,
293 ring->outstanding_lazy_request);
9400ae5c 294 return i915_add_request(ring);
5a5a0c64
DV		 295}
296
b303cf95 297static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
5a5a0c64 298{
05394f39 299 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
5a5a0c64 300
d7f46fc4 301 i915_gem_object_ggtt_unpin(obj);
05394f39 302 drm_gem_object_unreference(&obj->base);
5a5a0c64 303
b303cf95
CW		 304 overlay->old_vid_bo = NULL;
305}
03f77ea5 306
b303cf95
CW		 307static void intel_overlay_off_tail(struct intel_overlay *overlay)
308{
05394f39 309 struct drm_i915_gem_object *obj = overlay->vid_bo;
02e792fb 310
b303cf95
CW		 311 /* never have the overlay hw on without showing a frame */
312 BUG_ON(!overlay->vid_bo);
02e792fb 313
d7f46fc4 314 i915_gem_object_ggtt_unpin(obj);
05394f39 315 drm_gem_object_unreference(&obj->base);
b303cf95 316 overlay->vid_bo = NULL;
03f77ea5 317
b303cf95
CW		 318 overlay->crtc->overlay = NULL;
319 overlay->crtc = NULL;
320 overlay->active = 0;
02e792fb
DV		 321}
322
323/* overlay needs to be disabled in OCMD reg */
ce453d81 324static int intel_overlay_off(struct intel_overlay *overlay)
02e792fb 325{
02e792fb 326 struct drm_device *dev = overlay->dev;
e1f99ce6 327 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 328 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
8dc5d147 329 u32 flip_addr = overlay->flip_addr;
e1f99ce6 330 int ret;
02e792fb
DV		 331
332 BUG_ON(!overlay->active);
333
334 /* According to intel docs the overlay hw may hang (when switching
335 * off) without loading the filter coeffs. It is however unclear whether
336 * this applies to the disabling of the overlay or to the switching off
337 * of the hw. Do it in both cases */
338 flip_addr |= OFC_UPDATE;
339
6d90c952 340 ret = intel_ring_begin(ring, 6);
acb868d3 341 if (ret)
e1f99ce6 342 return ret;
acb868d3 343
02e792fb 344 /* wait for overlay to go idle */
6d90c952
DV		 345 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
346 intel_ring_emit(ring, flip_addr);
347 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 348 /* turn overlay off */
a9193983
DV		 349 if (IS_I830(dev)) {
350 /* Workaround: Don't disable the overlay fully, since otherwise
351 * it dies on the next OVERLAY_ON cmd. */
352 intel_ring_emit(ring, MI_NOOP);
353 intel_ring_emit(ring, MI_NOOP);
354 intel_ring_emit(ring, MI_NOOP);
355 } else {
356 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
357 intel_ring_emit(ring, flip_addr);
358 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
359 }
6d90c952 360 intel_ring_advance(ring);
02e792fb 361
acb868d3 362 return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
12ca45fe
DV		 363}
364
03f77ea5
DV		 365/* recover from an interruption due to a signal
366 * We have to be careful not to repeat work forever an make forward progess. */
ce453d81 367static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
03f77ea5 368{
03f77ea5 369 int ret;
03f77ea5 370
9bfc01a2 371 if (overlay->last_flip_req == NULL)
b303cf95 372 return 0;
03f77ea5 373
a4b3a571 374 ret = i915_wait_request(overlay->last_flip_req);
b6c028e0 375 if (ret)
03f77ea5 376 return ret;
a4b3a571 377 i915_gem_retire_requests(overlay->dev);
03f77ea5 378
b303cf95
CW		 379 if (overlay->flip_tail)
380 overlay->flip_tail(overlay);
03f77ea5 381
9bfc01a2 382 i915_gem_request_assign(&overlay->last_flip_req, NULL);
03f77ea5
DV		 383 return 0;
384}
385
5a5a0c64
DV		 386/* Wait for pending overlay flip and release old frame.
387 * Needs to be called before the overlay register are changed
8d74f656
CW		 388 * via intel_overlay_(un)map_regs
389 */
02e792fb
DV		 390static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
391{
5cd68c98 392 struct drm_device *dev = overlay->dev;
d5d45cc5 393 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 394 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
02e792fb 395 int ret;
02e792fb 396
5cd68c98
CW		 397 /* Only wait if there is actually an old frame to release to
398 * guarantee forward progress.
399 */
03f77ea5
DV		 400 if (!overlay->old_vid_bo)
401 return 0;
402
5cd68c98
CW		 403 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
404 /* synchronous slowpath */
6d90c952 405 ret = intel_ring_begin(ring, 2);
acb868d3 406 if (ret)
e1f99ce6 407 return ret;
e1f99ce6 408
6d90c952
DV		 409 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
410 intel_ring_emit(ring, MI_NOOP);
411 intel_ring_advance(ring);
5cd68c98 412
acb868d3 413 ret = intel_overlay_do_wait_request(overlay,
b303cf95 414 intel_overlay_release_old_vid_tail);
5cd68c98
CW		 415 if (ret)
416 return ret;
417 }
02e792fb 418
5cd68c98 419 intel_overlay_release_old_vid_tail(overlay);
a071fa00
DV		 420
421
422 i915_gem_track_fb(overlay->old_vid_bo, NULL,
423 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
02e792fb
DV		 424 return 0;
425}
426
427struct put_image_params {
428 int format;
429 short dst_x;
430 short dst_y;
431 short dst_w;
432 short dst_h;
433 short src_w;
434 short src_scan_h;
435 short src_scan_w;
436 short src_h;
437 short stride_Y;
438 short stride_UV;
439 int offset_Y;
440 int offset_U;
441 int offset_V;
442};
443
444static int packed_depth_bytes(u32 format)
445{
446 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 447 case I915_OVERLAY_YUV422:
448 return 4;
449 case I915_OVERLAY_YUV411:
450 /* return 6; not implemented */
451 default:
452 return -EINVAL;
02e792fb
DV		 453 }
454}
455
456static int packed_width_bytes(u32 format, short width)
457{
458 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 459 case I915_OVERLAY_YUV422:
460 return width << 1;
461 default:
462 return -EINVAL;
02e792fb
DV		 463 }
464}
465
466static int uv_hsubsampling(u32 format)
467{
468 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 469 case I915_OVERLAY_YUV422:
470 case I915_OVERLAY_YUV420:
471 return 2;
472 case I915_OVERLAY_YUV411:
473 case I915_OVERLAY_YUV410:
474 return 4;
475 default:
476 return -EINVAL;
02e792fb
DV		 477 }
478}
479
480static int uv_vsubsampling(u32 format)
481{
482 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 483 case I915_OVERLAY_YUV420:
484 case I915_OVERLAY_YUV410:
485 return 2;
486 case I915_OVERLAY_YUV422:
487 case I915_OVERLAY_YUV411:
488 return 1;
489 default:
490 return -EINVAL;
02e792fb
DV		 491 }
492}
493
494static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
495{
496 u32 mask, shift, ret;
a6c45cf0 497 if (IS_GEN2(dev)) {
02e792fb
DV		 498 mask = 0x1f;
499 shift = 5;
a6c45cf0
CW		 500 } else {
501 mask = 0x3f;
502 shift = 6;
02e792fb
DV		 503 }
504 ret = ((offset + width + mask) >> shift) - (offset >> shift);
a6c45cf0 505 if (!IS_GEN2(dev))
02e792fb 506 ret <<= 1;
0206e353 507 ret -= 1;
02e792fb
DV		 508 return ret << 2;
509}
510
511static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
512 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
513 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
514 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
515 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
516 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
517 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
518 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
519 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
520 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
521 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
522 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
523 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
524 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
525 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
526 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
527 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 528 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
529};
530
02e792fb
DV		 531static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
532 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
533 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
534 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
535 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
536 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
537 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
538 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
539 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 540 0x3000, 0x0800, 0x3000
541};
02e792fb 542
75020bc1 543static void update_polyphase_filter(struct overlay_registers __iomem *regs)
02e792fb 544{
75020bc1
BW		 545 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
546 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
547 sizeof(uv_static_hcoeffs));
02e792fb
DV		 548}
549
550static bool update_scaling_factors(struct intel_overlay *overlay,
75020bc1 551 struct overlay_registers __iomem *regs,
02e792fb
DV		 552 struct put_image_params *params)
553{
554 /* fixed point with a 12 bit shift */
555 u32 xscale, yscale, xscale_UV, yscale_UV;
556#define FP_SHIFT 12
557#define FRACT_MASK 0xfff
558 bool scale_changed = false;
559 int uv_hscale = uv_hsubsampling(params->format);
560 int uv_vscale = uv_vsubsampling(params->format);
561
562 if (params->dst_w > 1)
563 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
564 /(params->dst_w);
565 else
566 xscale = 1 << FP_SHIFT;
567
568 if (params->dst_h > 1)
569 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
570 /(params->dst_h);
571 else
572 yscale = 1 << FP_SHIFT;
573
574 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 575 xscale_UV = xscale/uv_hscale;
576 yscale_UV = yscale/uv_vscale;
577 /* make the Y scale to UV scale ratio an exact multiply */
578 xscale = xscale_UV * uv_hscale;
579 yscale = yscale_UV * uv_vscale;
02e792fb 580 /*} else {
722506f0
CW		 581 xscale_UV = 0;
582 yscale_UV = 0;
583 }*/
02e792fb
DV		 584
585 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
586 scale_changed = true;
587 overlay->old_xscale = xscale;
588 overlay->old_yscale = yscale;
589
75020bc1
BW		 590 iowrite32(((yscale & FRACT_MASK) << 20) |
591 ((xscale >> FP_SHIFT) << 16) |
592 ((xscale & FRACT_MASK) << 3),
593 &regs->YRGBSCALE);
722506f0 594
75020bc1
BW		 595 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
596 ((xscale_UV >> FP_SHIFT) << 16) |
597 ((xscale_UV & FRACT_MASK) << 3),
598 &regs->UVSCALE);
722506f0 599
75020bc1
BW		 600 iowrite32((((yscale >> FP_SHIFT) << 16) |
601 ((yscale_UV >> FP_SHIFT) << 0)),
602 &regs->UVSCALEV);
02e792fb
DV		 603
604 if (scale_changed)
605 update_polyphase_filter(regs);
606
607 return scale_changed;
608}
609
610static void update_colorkey(struct intel_overlay *overlay,
75020bc1 611 struct overlay_registers __iomem *regs)
02e792fb
DV		 612{
613 u32 key = overlay->color_key;
6ba3ddd9 614
f4510a27 615 switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
722506f0 616 case 8:
75020bc1
BW		 617 iowrite32(0, &regs->DCLRKV);
618 iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
6ba3ddd9
CW		 619 break;
620
722506f0 621 case 16:
f4510a27 622 if (overlay->crtc->base.primary->fb->depth == 15) {
75020bc1
BW		 623 iowrite32(RGB15_TO_COLORKEY(key), &regs->DCLRKV);
624 iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE,
625 &regs->DCLRKM);
722506f0 626 } else {
75020bc1
BW		 627 iowrite32(RGB16_TO_COLORKEY(key), &regs->DCLRKV);
628 iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE,
629 &regs->DCLRKM);
722506f0 630 }
6ba3ddd9
CW		 631 break;
632
722506f0
CW		 633 case 24:
634 case 32:
75020bc1
BW		 635 iowrite32(key, &regs->DCLRKV);
636 iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, &regs->DCLRKM);
6ba3ddd9 637 break;
02e792fb
DV		 638 }
639}
640
641static u32 overlay_cmd_reg(struct put_image_params *params)
642{
643 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
644
645 if (params->format & I915_OVERLAY_YUV_PLANAR) {
646 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 647 case I915_OVERLAY_YUV422:
648 cmd |= OCMD_YUV_422_PLANAR;
649 break;
650 case I915_OVERLAY_YUV420:
651 cmd |= OCMD_YUV_420_PLANAR;
652 break;
653 case I915_OVERLAY_YUV411:
654 case I915_OVERLAY_YUV410:
655 cmd |= OCMD_YUV_410_PLANAR;
656 break;
02e792fb
DV		 657 }
658 } else { /* YUV packed */
659 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 660 case I915_OVERLAY_YUV422:
661 cmd |= OCMD_YUV_422_PACKED;
662 break;
663 case I915_OVERLAY_YUV411:
664 cmd |= OCMD_YUV_411_PACKED;
665 break;
02e792fb
DV		 666 }
667
668 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 669 case I915_OVERLAY_NO_SWAP:
670 break;
671 case I915_OVERLAY_UV_SWAP:
672 cmd |= OCMD_UV_SWAP;
673 break;
674 case I915_OVERLAY_Y_SWAP:
675 cmd |= OCMD_Y_SWAP;
676 break;
677 case I915_OVERLAY_Y_AND_UV_SWAP:
678 cmd |= OCMD_Y_AND_UV_SWAP;
679 break;
02e792fb
DV		 680 }
681 }
682
683 return cmd;
684}
685
5fe82c5e 686static int intel_overlay_do_put_image(struct intel_overlay *overlay,
05394f39 687 struct drm_i915_gem_object *new_bo,
5fe82c5e 688 struct put_image_params *params)
02e792fb
DV		 689{
690 int ret, tmp_width;
75020bc1 691 struct overlay_registers __iomem *regs;
02e792fb 692 bool scale_changed = false;
02e792fb 693 struct drm_device *dev = overlay->dev;
75020bc1 694 u32 swidth, swidthsw, sheight, ostride;
a071fa00 695 enum pipe pipe = overlay->crtc->pipe;
02e792fb
DV		 696
697 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
51fd371b 698 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb
DV		 699 BUG_ON(!overlay);
700
02e792fb
DV		 701 ret = intel_overlay_release_old_vid(overlay);
702 if (ret != 0)
703 return ret;
704
2da3b9b9 705 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
02e792fb
DV		 706 if (ret != 0)
707 return ret;
708
d9e86c0e
CW		 709 ret = i915_gem_object_put_fence(new_bo);
710 if (ret)
711 goto out_unpin;
712
02e792fb 713 if (!overlay->active) {
75020bc1 714 u32 oconfig;
8d74f656 715 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 716 if (!regs) {
717 ret = -ENOMEM;
718 goto out_unpin;
719 }
75020bc1 720 oconfig = OCONF_CC_OUT_8BIT;
a6c45cf0 721 if (IS_GEN4(overlay->dev))
75020bc1 722 oconfig |= OCONF_CSC_MODE_BT709;
a071fa00 723 oconfig |= pipe == 0 ?
02e792fb 724 OCONF_PIPE_A : OCONF_PIPE_B;
75020bc1 725 iowrite32(oconfig, &regs->OCONFIG);
9bb2ff73 726 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 727
728 ret = intel_overlay_on(overlay);
729 if (ret != 0)
730 goto out_unpin;
731 }
732
8d74f656 733 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 734 if (!regs) {
735 ret = -ENOMEM;
736 goto out_unpin;
737 }
738
75020bc1
BW		 739 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
740 iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
02e792fb
DV		 741
742 if (params->format & I915_OVERLAY_YUV_PACKED)
743 tmp_width = packed_width_bytes(params->format, params->src_w);
744 else
745 tmp_width = params->src_w;
746
75020bc1
BW		 747 swidth = params->src_w;
748 swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width);
749 sheight = params->src_h;
f343c5f6 750 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y);
75020bc1 751 ostride = params->stride_Y;
02e792fb
DV		 752
753 if (params->format & I915_OVERLAY_YUV_PLANAR) {
754 int uv_hscale = uv_hsubsampling(params->format);
755 int uv_vscale = uv_vsubsampling(params->format);
756 u32 tmp_U, tmp_V;
75020bc1 757 swidth |= (params->src_w/uv_hscale) << 16;
02e792fb 758 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 759 params->src_w/uv_hscale);
02e792fb 760 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 761 params->src_w/uv_hscale);
75020bc1
BW		 762 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
763 sheight |= (params->src_h/uv_vscale) << 16;
f343c5f6
BW		 764 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U);
765 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V);
75020bc1 766 ostride |= params->stride_UV << 16;
02e792fb
DV		 767 }
768
75020bc1
BW		 769 iowrite32(swidth, &regs->SWIDTH);
770 iowrite32(swidthsw, &regs->SWIDTHSW);
771 iowrite32(sheight, &regs->SHEIGHT);
772 iowrite32(ostride, &regs->OSTRIDE);
773
02e792fb
DV		 774 scale_changed = update_scaling_factors(overlay, regs, params);
775
776 update_colorkey(overlay, regs);
777
75020bc1 778 iowrite32(overlay_cmd_reg(params), &regs->OCMD);
02e792fb 779
9bb2ff73 780 intel_overlay_unmap_regs(overlay, regs);
02e792fb 781
8dc5d147
CW		 782 ret = intel_overlay_continue(overlay, scale_changed);
783 if (ret)
784 goto out_unpin;
02e792fb 785
a071fa00
DV		 786 i915_gem_track_fb(overlay->vid_bo, new_bo,
787 INTEL_FRONTBUFFER_OVERLAY(pipe));
788
02e792fb 789 overlay->old_vid_bo = overlay->vid_bo;
05394f39 790 overlay->vid_bo = new_bo;
02e792fb 791
f99d7069
DV		 792 intel_frontbuffer_flip(dev,
793 INTEL_FRONTBUFFER_OVERLAY(pipe));
794
02e792fb
DV		 795 return 0;
796
797out_unpin:
d7f46fc4 798 i915_gem_object_ggtt_unpin(new_bo);
02e792fb
DV		 799 return ret;
800}
801
ce453d81 802int intel_overlay_switch_off(struct intel_overlay *overlay)
02e792fb 803{
75020bc1 804 struct overlay_registers __iomem *regs;
02e792fb 805 struct drm_device *dev = overlay->dev;
5dcdbcb0 806 int ret;
02e792fb
DV		 807
808 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
51fd371b 809 BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
02e792fb 810
ce453d81 811 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 812 if (ret != 0)
813 return ret;
9bedb974 814
02e792fb
DV		 815 if (!overlay->active)
816 return 0;
817
02e792fb
DV		 818 ret = intel_overlay_release_old_vid(overlay);
819 if (ret != 0)
820 return ret;
821
8d74f656 822 regs = intel_overlay_map_regs(overlay);
75020bc1 823 iowrite32(0, &regs->OCMD);
9bb2ff73 824 intel_overlay_unmap_regs(overlay, regs);
02e792fb 825
ce453d81 826 ret = intel_overlay_off(overlay);
03f77ea5
DV		 827 if (ret != 0)
828 return ret;
829
12ca45fe 830 intel_overlay_off_tail(overlay);
02e792fb
DV		 831 return 0;
832}
833
834static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
835 struct intel_crtc *crtc)
836{
f7abfe8b 837 if (!crtc->active)
02e792fb
DV		 838 return -EINVAL;
839
02e792fb 840 /* can't use the overlay with double wide pipe */
4926cb76 841 if (crtc->config.double_wide)
02e792fb
DV		 842 return -EINVAL;
843
844 return 0;
845}
846
847static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
848{
849 struct drm_device *dev = overlay->dev;
d5d45cc5 850 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 851 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 852 u32 ratio;
02e792fb
DV		 853
854 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 855 * line with the intel documentation for the i965
856 */
a6c45cf0 857 if (INTEL_INFO(dev)->gen >= 4) {
0206e353 858 /* on i965 use the PGM reg to read out the autoscaler values */
a6c45cf0
CW		 859 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
860 } else {
446d2183
CW		 861 if (pfit_control & VERT_AUTO_SCALE)
862 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 863 else
446d2183
CW		 864 ratio = I915_READ(PFIT_PGM_RATIOS);
865 ratio >>= PFIT_VERT_SCALE_SHIFT;
02e792fb
DV		 866 }
867
868 overlay->pfit_vscale_ratio = ratio;
869}
870
871static int check_overlay_dst(struct intel_overlay *overlay,
872 struct drm_intel_overlay_put_image *rec)
873{
874 struct drm_display_mode *mode = &overlay->crtc->base.mode;
875
75c13993
DV		 876 if (rec->dst_x < mode->hdisplay &&
877 rec->dst_x + rec->dst_width <= mode->hdisplay &&
878 rec->dst_y < mode->vdisplay &&
879 rec->dst_y + rec->dst_height <= mode->vdisplay)
02e792fb
DV		 880 return 0;
881 else
882 return -EINVAL;
883}
884
885static int check_overlay_scaling(struct put_image_params *rec)
886{
887 u32 tmp;
888
889 /* downscaling limit is 8.0 */
890 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
891 if (tmp > 7)
892 return -EINVAL;
893 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
894 if (tmp > 7)
895 return -EINVAL;
896
897 return 0;
898}
899
900static int check_overlay_src(struct drm_device *dev,
901 struct drm_intel_overlay_put_image *rec,
05394f39 902 struct drm_i915_gem_object *new_bo)
02e792fb 903{
02e792fb
DV		 904 int uv_hscale = uv_hsubsampling(rec->flags);
905 int uv_vscale = uv_vsubsampling(rec->flags);
8f28f54a
DC		 906 u32 stride_mask;
907 int depth;
908 u32 tmp;
02e792fb
DV		 909
910 /* check src dimensions */
911 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 912 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 913 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 914 return -EINVAL;
915 } else {
722506f0 916 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 917 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 918 return -EINVAL;
919 }
9f7c3f44 920
02e792fb 921 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 922 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 923 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 924 return -EINVAL;
925
a1efd14a 926 /* check alignment constraints */
02e792fb 927 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 928 case I915_OVERLAY_RGB:
929 /* not implemented */
930 return -EINVAL;
9f7c3f44 931
722506f0 932 case I915_OVERLAY_YUV_PACKED:
722506f0 933 if (uv_vscale != 1)
02e792fb 934 return -EINVAL;
9f7c3f44
CW		 935
936 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 937 if (depth < 0)
938 return depth;
9f7c3f44 939
722506f0
CW		 940 /* ignore UV planes */
941 rec->stride_UV = 0;
942 rec->offset_U = 0;
943 rec->offset_V = 0;
944 /* check pixel alignment */
945 if (rec->offset_Y % depth)
946 return -EINVAL;
947 break;
9f7c3f44 948
722506f0
CW		 949 case I915_OVERLAY_YUV_PLANAR:
950 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 951 return -EINVAL;
722506f0
CW		 952 /* no offset restrictions for planar formats */
953 break;
9f7c3f44 954
722506f0
CW		 955 default:
956 return -EINVAL;
02e792fb
DV		 957 }
958
959 if (rec->src_width % uv_hscale)
960 return -EINVAL;
961
962 /* stride checking */
a1efd14a
CW		 963 if (IS_I830(dev) || IS_845G(dev))
964 stride_mask = 255;
965 else
966 stride_mask = 63;
02e792fb
DV		 967
968 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
969 return -EINVAL;
a6c45cf0 970 if (IS_GEN4(dev) && rec->stride_Y < 512)
02e792fb
DV		 971 return -EINVAL;
972
973 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 974 4096 : 8192;
975 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 976 return -EINVAL;
977
978 /* check buffer dimensions */
979 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 980 case I915_OVERLAY_RGB:
981 case I915_OVERLAY_YUV_PACKED:
982 /* always 4 Y values per depth pixels */
983 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
984 return -EINVAL;
985
986 tmp = rec->stride_Y*rec->src_height;
05394f39 987 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0
CW		 988 return -EINVAL;
989 break;
990
991 case I915_OVERLAY_YUV_PLANAR:
992 if (rec->src_width > rec->stride_Y)
993 return -EINVAL;
994 if (rec->src_width/uv_hscale > rec->stride_UV)
995 return -EINVAL;
996
9f7c3f44 997 tmp = rec->stride_Y * rec->src_height;
05394f39 998 if (rec->offset_Y + tmp > new_bo->base.size)
722506f0 999 return -EINVAL;
9f7c3f44
CW		 1000
1001 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
05394f39
CW		 1002 if (rec->offset_U + tmp > new_bo->base.size ||
1003 rec->offset_V + tmp > new_bo->base.size)
722506f0
CW		 1004 return -EINVAL;
1005 break;
02e792fb
DV		 1006 }
1007
1008 return 0;
1009}
1010
e9e331a8
CW		 1011/**
1012 * Return the pipe currently connected to the panel fitter,
1013 * or -1 if the panel fitter is not present or not in use
1014 */
1015static int intel_panel_fitter_pipe(struct drm_device *dev)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 pfit_control;
1019
1020 /* i830 doesn't have a panel fitter */
dc9e7dec 1021 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
e9e331a8
CW		 1022 return -1;
1023
1024 pfit_control = I915_READ(PFIT_CONTROL);
1025
1026 /* See if the panel fitter is in use */
1027 if ((pfit_control & PFIT_ENABLE) == 0)
1028 return -1;
1029
1030 /* 965 can place panel fitter on either pipe */
a6c45cf0 1031 if (IS_GEN4(dev))
e9e331a8
CW		 1032 return (pfit_control >> 29) & 0x3;
1033
1034 /* older chips can only use pipe 1 */
1035 return 1;
1036}
1037
02e792fb 1038int intel_overlay_put_image(struct drm_device *dev, void *data,
0206e353 1039 struct drm_file *file_priv)
02e792fb
DV		 1040{
1041 struct drm_intel_overlay_put_image *put_image_rec = data;
d5d45cc5 1042 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1043 struct intel_overlay *overlay;
7707e653 1044 struct drm_crtc *drmmode_crtc;
02e792fb 1045 struct intel_crtc *crtc;
05394f39 1046 struct drm_i915_gem_object *new_bo;
02e792fb
DV		 1047 struct put_image_params *params;
1048 int ret;
1049
1cff8f6b 1050 /* No need to check for DRIVER_MODESET - we don't set it up then. */
02e792fb
DV		 1051 overlay = dev_priv->overlay;
1052 if (!overlay) {
1053 DRM_DEBUG("userspace bug: no overlay\n");
1054 return -ENODEV;
1055 }
1056
1057 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
a0e99e68 1058 drm_modeset_lock_all(dev);
02e792fb
DV		 1059 mutex_lock(&dev->struct_mutex);
1060
ce453d81 1061 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1062
1063 mutex_unlock(&dev->struct_mutex);
a0e99e68 1064 drm_modeset_unlock_all(dev);
02e792fb
DV		 1065
1066 return ret;
1067 }
1068
b14c5679 1069 params = kmalloc(sizeof(*params), GFP_KERNEL);
02e792fb
DV		 1070 if (!params)
1071 return -ENOMEM;
1072
7707e653
RC		 1073 drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1074 if (!drmmode_crtc) {
915a428e
DC		 1075 ret = -ENOENT;
1076 goto out_free;
1077 }
7707e653 1078 crtc = to_intel_crtc(drmmode_crtc);
02e792fb 1079
05394f39
CW		 1080 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1081 put_image_rec->bo_handle));
c8725226 1082 if (&new_bo->base == NULL) {
915a428e
DC		 1083 ret = -ENOENT;
1084 goto out_free;
1085 }
02e792fb 1086
a0e99e68 1087 drm_modeset_lock_all(dev);
02e792fb
DV		 1088 mutex_lock(&dev->struct_mutex);
1089
d9e86c0e 1090 if (new_bo->tiling_mode) {
3b25b31f 1091 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
d9e86c0e
CW		 1092 ret = -EINVAL;
1093 goto out_unlock;
1094 }
1095
ce453d81 1096 ret = intel_overlay_recover_from_interrupt(overlay);
b303cf95
CW		 1097 if (ret != 0)
1098 goto out_unlock;
03f77ea5 1099
02e792fb
DV		 1100 if (overlay->crtc != crtc) {
1101 struct drm_display_mode *mode = &crtc->base.mode;
ce453d81 1102 ret = intel_overlay_switch_off(overlay);
02e792fb
DV		 1103 if (ret != 0)
1104 goto out_unlock;
1105
1106 ret = check_overlay_possible_on_crtc(overlay, crtc);
1107 if (ret != 0)
1108 goto out_unlock;
1109
1110 overlay->crtc = crtc;
1111 crtc->overlay = overlay;
1112
e9e331a8
CW		 1113 /* line too wide, i.e. one-line-mode */
1114 if (mode->hdisplay > 1024 &&
1115 intel_panel_fitter_pipe(dev) == crtc->pipe) {
02e792fb
DV		 1116 overlay->pfit_active = 1;
1117 update_pfit_vscale_ratio(overlay);
1118 } else
1119 overlay->pfit_active = 0;
1120 }
1121
1122 ret = check_overlay_dst(overlay, put_image_rec);
1123 if (ret != 0)
1124 goto out_unlock;
1125
1126 if (overlay->pfit_active) {
1127 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1128 overlay->pfit_vscale_ratio);
02e792fb
DV		 1129 /* shifting right rounds downwards, so add 1 */
1130 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1131 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1132 } else {
1133 params->dst_y = put_image_rec->dst_y;
1134 params->dst_h = put_image_rec->dst_height;
1135 }
1136 params->dst_x = put_image_rec->dst_x;
1137 params->dst_w = put_image_rec->dst_width;
1138
1139 params->src_w = put_image_rec->src_width;
1140 params->src_h = put_image_rec->src_height;
1141 params->src_scan_w = put_image_rec->src_scan_width;
1142 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1143 if (params->src_scan_h > params->src_h ||
1144 params->src_scan_w > params->src_w) {
02e792fb
DV		 1145 ret = -EINVAL;
1146 goto out_unlock;
1147 }
1148
1149 ret = check_overlay_src(dev, put_image_rec, new_bo);
1150 if (ret != 0)
1151 goto out_unlock;
1152 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1153 params->stride_Y = put_image_rec->stride_Y;
1154 params->stride_UV = put_image_rec->stride_UV;
1155 params->offset_Y = put_image_rec->offset_Y;
1156 params->offset_U = put_image_rec->offset_U;
1157 params->offset_V = put_image_rec->offset_V;
1158
1159 /* Check scaling after src size to prevent a divide-by-zero. */
1160 ret = check_overlay_scaling(params);
1161 if (ret != 0)
1162 goto out_unlock;
1163
1164 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1165 if (ret != 0)
1166 goto out_unlock;
1167
1168 mutex_unlock(&dev->struct_mutex);
a0e99e68 1169 drm_modeset_unlock_all(dev);
02e792fb
DV		 1170
1171 kfree(params);
1172
1173 return 0;
1174
1175out_unlock:
1176 mutex_unlock(&dev->struct_mutex);
a0e99e68 1177 drm_modeset_unlock_all(dev);
05394f39 1178 drm_gem_object_unreference_unlocked(&new_bo->base);
915a428e 1179out_free:
02e792fb
DV		 1180 kfree(params);
1181
1182 return ret;
1183}
1184
1185static void update_reg_attrs(struct intel_overlay *overlay,
75020bc1 1186 struct overlay_registers __iomem *regs)
02e792fb 1187{
75020bc1
BW		 1188 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1189 &regs->OCLRC0);
1190 iowrite32(overlay->saturation, &regs->OCLRC1);
02e792fb
DV		 1191}
1192
1193static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1194{
1195 int i;
1196
1197 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1198 return false;
1199
1200 for (i = 0; i < 3; i++) {
722506f0 1201 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1202 return false;
1203 }
1204
1205 return true;
1206}
1207
1208static bool check_gamma5_errata(u32 gamma5)
1209{
1210 int i;
1211
1212 for (i = 0; i < 3; i++) {
1213 if (((gamma5 >> i*8) & 0xff) == 0x80)
1214 return false;
1215 }
1216
1217 return true;
1218}
1219
1220static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1221{
722506f0
CW		 1222 if (!check_gamma_bounds(0, attrs->gamma0) ||
1223 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1224 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1225 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1226 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1227 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1228 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1229 return -EINVAL;
722506f0 1230
02e792fb
DV		 1231 if (!check_gamma5_errata(attrs->gamma5))
1232 return -EINVAL;
722506f0 1233
02e792fb
DV		 1234 return 0;
1235}
1236
1237int intel_overlay_attrs(struct drm_device *dev, void *data,
0206e353 1238 struct drm_file *file_priv)
02e792fb
DV		 1239{
1240 struct drm_intel_overlay_attrs *attrs = data;
d5d45cc5 1241 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1242 struct intel_overlay *overlay;
75020bc1 1243 struct overlay_registers __iomem *regs;
02e792fb
DV		 1244 int ret;
1245
1cff8f6b 1246 /* No need to check for DRIVER_MODESET - we don't set it up then. */
02e792fb
DV		 1247 overlay = dev_priv->overlay;
1248 if (!overlay) {
1249 DRM_DEBUG("userspace bug: no overlay\n");
1250 return -ENODEV;
1251 }
1252
a0e99e68 1253 drm_modeset_lock_all(dev);
02e792fb
DV		 1254 mutex_lock(&dev->struct_mutex);
1255
60fc332c 1256 ret = -EINVAL;
02e792fb 1257 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1258 attrs->color_key = overlay->color_key;
02e792fb 1259 attrs->brightness = overlay->brightness;
60fc332c 1260 attrs->contrast = overlay->contrast;
02e792fb
DV		 1261 attrs->saturation = overlay->saturation;
1262
a6c45cf0 1263 if (!IS_GEN2(dev)) {
02e792fb
DV		 1264 attrs->gamma0 = I915_READ(OGAMC0);
1265 attrs->gamma1 = I915_READ(OGAMC1);
1266 attrs->gamma2 = I915_READ(OGAMC2);
1267 attrs->gamma3 = I915_READ(OGAMC3);
1268 attrs->gamma4 = I915_READ(OGAMC4);
1269 attrs->gamma5 = I915_READ(OGAMC5);
1270 }
02e792fb 1271 } else {
60fc332c 1272 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1273 goto out_unlock;
60fc332c 1274 if (attrs->contrast > 255)
02e792fb 1275 goto out_unlock;
60fc332c 1276 if (attrs->saturation > 1023)
02e792fb 1277 goto out_unlock;
02e792fb 1278
60fc332c
CW		 1279 overlay->color_key = attrs->color_key;
1280 overlay->brightness = attrs->brightness;
1281 overlay->contrast = attrs->contrast;
1282 overlay->saturation = attrs->saturation;
02e792fb 1283
8d74f656 1284 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1285 if (!regs) {
1286 ret = -ENOMEM;
1287 goto out_unlock;
1288 }
1289
1290 update_reg_attrs(overlay, regs);
1291
9bb2ff73 1292 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1293
1294 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
a6c45cf0 1295 if (IS_GEN2(dev))
02e792fb 1296 goto out_unlock;
02e792fb
DV		 1297
1298 if (overlay->active) {
1299 ret = -EBUSY;
1300 goto out_unlock;
1301 }
1302
1303 ret = check_gamma(attrs);
60fc332c 1304 if (ret)
02e792fb
DV		 1305 goto out_unlock;
1306
1307 I915_WRITE(OGAMC0, attrs->gamma0);
1308 I915_WRITE(OGAMC1, attrs->gamma1);
1309 I915_WRITE(OGAMC2, attrs->gamma2);
1310 I915_WRITE(OGAMC3, attrs->gamma3);
1311 I915_WRITE(OGAMC4, attrs->gamma4);
1312 I915_WRITE(OGAMC5, attrs->gamma5);
1313 }
02e792fb
DV		 1314 }
1315
60fc332c 1316 ret = 0;
02e792fb
DV		 1317out_unlock:
1318 mutex_unlock(&dev->struct_mutex);
a0e99e68 1319 drm_modeset_unlock_all(dev);
02e792fb
DV		 1320
1321 return ret;
1322}
1323
1324void intel_setup_overlay(struct drm_device *dev)
1325{
d5d45cc5 1326 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1327 struct intel_overlay *overlay;
05394f39 1328 struct drm_i915_gem_object *reg_bo;
75020bc1 1329 struct overlay_registers __iomem *regs;
02e792fb
DV		 1330 int ret;
1331
31578148 1332 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1333 return;
1334
b14c5679 1335 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
02e792fb
DV		 1336 if (!overlay)
1337 return;
79d24273
CW		 1338
1339 mutex_lock(&dev->struct_mutex);
1340 if (WARN_ON(dev_priv->overlay))
1341 goto out_free;
1342
02e792fb
DV		 1343 overlay->dev = dev;
1344
f63a484c
DV		 1345 reg_bo = NULL;
1346 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1347 reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE);
80405138
CW		 1348 if (reg_bo == NULL)
1349 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1350 if (reg_bo == NULL)
02e792fb 1351 goto out_free;
05394f39 1352 overlay->reg_bo = reg_bo;
02e792fb 1353
31578148 1354 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
00731155 1355 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
0206e353
AJ		 1356 if (ret) {
1357 DRM_ERROR("failed to attach phys overlay regs\n");
1358 goto out_free_bo;
1359 }
00731155 1360 overlay->flip_addr = reg_bo->phys_handle->busaddr;
31578148 1361 } else {
1ec9e26d 1362 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
02e792fb 1363 if (ret) {
0206e353
AJ		 1364 DRM_ERROR("failed to pin overlay register bo\n");
1365 goto out_free_bo;
1366 }
f343c5f6 1367 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo);
0ddc1289
CW		 1368
1369 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1370 if (ret) {
0206e353
AJ		 1371 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1372 goto out_unpin_bo;
1373 }
02e792fb
DV		 1374 }
1375
1376 /* init all values */
1377 overlay->color_key = 0x0101fe;
1378 overlay->brightness = -19;
1379 overlay->contrast = 75;
1380 overlay->saturation = 146;
1381
8d74f656 1382 regs = intel_overlay_map_regs(overlay);
02e792fb 1383 if (!regs)
79d24273 1384 goto out_unpin_bo;
02e792fb 1385
75020bc1 1386 memset_io(regs, 0, sizeof(struct overlay_registers));
02e792fb 1387 update_polyphase_filter(regs);
02e792fb
DV		 1388 update_reg_attrs(overlay, regs);
1389
9bb2ff73 1390 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1391
1392 dev_priv->overlay = overlay;
79d24273 1393 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1394 DRM_INFO("initialized overlay support\n");
1395 return;
1396
0ddc1289 1397out_unpin_bo:
79d24273 1398 if (!OVERLAY_NEEDS_PHYSICAL(dev))
d7f46fc4 1399 i915_gem_object_ggtt_unpin(reg_bo);
02e792fb 1400out_free_bo:
05394f39 1401 drm_gem_object_unreference(&reg_bo->base);
02e792fb 1402out_free:
79d24273 1403 mutex_unlock(&dev->struct_mutex);
02e792fb
DV		 1404 kfree(overlay);
1405 return;
1406}
1407
1408void intel_cleanup_overlay(struct drm_device *dev)
1409{
d5d45cc5 1410 struct drm_i915_private *dev_priv = dev->dev_private;
02e792fb 1411
62cf4e6f
CW		 1412 if (!dev_priv->overlay)
1413 return;
02e792fb 1414
62cf4e6f
CW		 1415 /* The bo's should be free'd by the generic code already.
1416 * Furthermore modesetting teardown happens beforehand so the
1417 * hardware should be off already */
1418 BUG_ON(dev_priv->overlay->active);
1419
1420 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1421 kfree(dev_priv->overlay);
02e792fb 1422}
6ef3d427
CW		 1423
1424struct intel_overlay_error_state {
1425 struct overlay_registers regs;
1426 unsigned long base;
1427 u32 dovsta;
1428 u32 isr;
1429};
1430
75020bc1 1431static struct overlay_registers __iomem *
c48c43e4 1432intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
3bd3c932 1433{
d5d45cc5 1434 struct drm_i915_private *dev_priv = overlay->dev->dev_private;
75020bc1 1435 struct overlay_registers __iomem *regs;
3bd3c932
CW		 1436
1437 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
75020bc1
BW		 1438 /* Cast to make sparse happy, but it's wc memory anyway, so
1439 * equivalent to the wc io mapping on X86. */
1440 regs = (struct overlay_registers __iomem *)
00731155 1441 overlay->reg_bo->phys_handle->vaddr;
3bd3c932 1442 else
5d4545ae 1443 regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
f343c5f6 1444 i915_gem_obj_ggtt_offset(overlay->reg_bo));
3bd3c932
CW		 1445
1446 return regs;
1447}
1448
1449static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
75020bc1 1450 struct overlay_registers __iomem *regs)
3bd3c932
CW		 1451{
1452 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
c48c43e4 1453 io_mapping_unmap_atomic(regs);
3bd3c932
CW		 1454}
1455
1456
6ef3d427
CW		 1457struct intel_overlay_error_state *
1458intel_overlay_capture_error_state(struct drm_device *dev)
1459{
d5d45cc5 1460 struct drm_i915_private *dev_priv = dev->dev_private;
6ef3d427
CW		 1461 struct intel_overlay *overlay = dev_priv->overlay;
1462 struct intel_overlay_error_state *error;
1463 struct overlay_registers __iomem *regs;
1464
1465 if (!overlay || !overlay->active)
1466 return NULL;
1467
1468 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1469 if (error == NULL)
1470 return NULL;
1471
1472 error->dovsta = I915_READ(DOVSTA);
1473 error->isr = I915_READ(ISR);
31578148 1474 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
00731155 1475 error->base = (__force long)overlay->reg_bo->phys_handle->vaddr;
31578148 1476 else
f343c5f6 1477 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo);
6ef3d427
CW		 1478
1479 regs = intel_overlay_map_regs_atomic(overlay);
1480 if (!regs)
1481 goto err;
1482
1483 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
c48c43e4 1484 intel_overlay_unmap_regs_atomic(overlay, regs);
6ef3d427
CW		 1485
1486 return error;
1487
1488err:
1489 kfree(error);
1490 return NULL;
1491}
1492
1493void
edc3d884
MK		 1494intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1495 struct intel_overlay_error_state *error)
6ef3d427 1496{
edc3d884
MK		 1497 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1498 error->dovsta, error->isr);
1499 i915_error_printf(m, " Register file at 0x%08lx:\n",
1500 error->base);
6ef3d427 1501
edc3d884 1502#define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
6ef3d427
CW		 1503 P(OBUF_0Y);
1504 P(OBUF_1Y);
1505 P(OBUF_0U);
1506 P(OBUF_0V);
1507 P(OBUF_1U);
1508 P(OBUF_1V);
1509 P(OSTRIDE);
1510 P(YRGB_VPH);
1511 P(UV_VPH);
1512 P(HORZ_PH);
1513 P(INIT_PHS);
1514 P(DWINPOS);
1515 P(DWINSZ);
1516 P(SWIDTH);
1517 P(SWIDTHSW);
1518 P(SHEIGHT);
1519 P(YRGBSCALE);
1520 P(UVSCALE);
1521 P(OCLRC0);
1522 P(OCLRC1);
1523 P(DCLRKV);
1524 P(DCLRKM);
1525 P(SCLRKVH);
1526 P(SCLRKVL);
1527 P(SCLRKEN);
1528 P(OCONFIG);
1529 P(OCMD);
1530 P(OSTART_0Y);
1531 P(OSTART_1Y);
1532 P(OSTART_0U);
1533 P(OSTART_0V);
1534 P(OSTART_1U);
1535 P(OSTART_1V);
1536 P(OTILEOFF_0Y);
1537 P(OTILEOFF_1Y);
1538 P(OTILEOFF_0U);
1539 P(OTILEOFF_0V);
1540 P(OTILEOFF_1U);
1541 P(OTILEOFF_1V);
1542 P(FASTHSCALE);
1543 P(UVSCALEV);
1544#undef P
1545}
Linux kernel - Deliverables
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