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drm/i915/overlay: Combine SWITCH_OFF into a single step
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
8d74f656
CW		 173static struct overlay_registers *
174intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
175 int slot)
02e792fb
DV		 176{
177 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
178 struct overlay_registers *regs;
179
9bb2ff73 180 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
31578148 181 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 182 else
02e792fb 183 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
fca3ec01 184 overlay->reg_bo->gtt_offset,
8d74f656 185 slot);
02e792fb 186
9bb2ff73 187 return regs;
02e792fb
DV		 188}
189
8d74f656 190static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
9bb2ff73
CW		 191 int slot,
192 struct overlay_registers *regs)
02e792fb 193{
31578148 194 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 195 io_mapping_unmap_atomic(regs, slot);
8d74f656
CW		 196}
197
198static struct overlay_registers *
199intel_overlay_map_regs(struct intel_overlay *overlay)
200{
201 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
202 struct overlay_registers *regs;
203
9bb2ff73 204 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656 205 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 206 else
8d74f656
CW		 207 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
208 overlay->reg_bo->gtt_offset);
209
9bb2ff73 210 return regs;
8d74f656
CW		 211}
212
9bb2ff73
CW		 213static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
214 struct overlay_registers *regs)
8d74f656
CW		 215{
216 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 217 io_mapping_unmap(regs);
02e792fb
DV		 218}
219
b6c028e0
CW		 220static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
221 bool interruptible,
222 int stage)
02e792fb
DV		 223{
224 struct drm_device *dev = overlay->dev;
852835f3 225 drm_i915_private_t *dev_priv = dev->dev_private;
b6c028e0 226 int ret;
02e792fb 227
852835f3 228 overlay->last_flip_req =
8a1a49f9 229 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 230 if (overlay->last_flip_req == 0)
231 return -ENOMEM;
02e792fb 232
b6c028e0 233 overlay->hw_wedged = stage;
852835f3 234 ret = i915_do_wait_request(dev,
722506f0
CW		 235 overlay->last_flip_req, true,
236 &dev_priv->render_ring);
b6c028e0 237 if (ret)
03f77ea5 238 return ret;
02e792fb 239
03f77ea5
DV		 240 overlay->hw_wedged = 0;
241 overlay->last_flip_req = 0;
02e792fb
DV		 242 return 0;
243}
244
b6c028e0
CW		 245/* overlay needs to be disable in OCMD reg */
246static int intel_overlay_on(struct intel_overlay *overlay)
247{
248 struct drm_device *dev = overlay->dev;
249
250 BUG_ON(overlay->active);
251
252 overlay->active = 1;
253
254 BEGIN_LP_RING(4);
255 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
256 OUT_RING(overlay->flip_addr | OFC_UPDATE);
257 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
258 OUT_RING(MI_NOOP);
259 ADVANCE_LP_RING();
260
261 return intel_overlay_do_wait_request(overlay, true,
262 NEEDS_WAIT_FOR_FLIP);
263}
264
02e792fb
DV		 265/* overlay needs to be enabled in OCMD reg */
266static void intel_overlay_continue(struct intel_overlay *overlay,
722506f0 267 bool load_polyphase_filter)
02e792fb
DV		 268{
269 struct drm_device *dev = overlay->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
271 u32 flip_addr = overlay->flip_addr;
272 u32 tmp;
02e792fb
DV		 273
274 BUG_ON(!overlay->active);
275
276 if (load_polyphase_filter)
277 flip_addr |= OFC_UPDATE;
278
279 /* check for underruns */
280 tmp = I915_READ(DOVSTA);
281 if (tmp & (1 << 17))
282 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
283
4f8a567c 284 BEGIN_LP_RING(2);
02e792fb
DV		 285 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
286 OUT_RING(flip_addr);
5a5a0c64
DV		 287 ADVANCE_LP_RING();
288
852835f3 289 overlay->last_flip_req =
8a1a49f9 290 i915_add_request(dev, NULL, &dev_priv->render_ring);
5a5a0c64
DV		 291}
292
293static int intel_overlay_wait_flip(struct intel_overlay *overlay)
294{
295 struct drm_device *dev = overlay->dev;
722506f0 296 drm_i915_private_t *dev_priv = dev->dev_private;
5a5a0c64
DV		 297 int ret;
298 u32 tmp;
5a5a0c64
DV		 299
300 if (overlay->last_flip_req != 0) {
722506f0
CW		 301 ret = i915_do_wait_request(dev,
302 overlay->last_flip_req, true,
303 &dev_priv->render_ring);
5c5a4359
DV		 304 if (ret == 0) {
305 overlay->last_flip_req = 0;
5a5a0c64 306
5c5a4359 307 tmp = I915_READ(ISR);
5a5a0c64 308
5c5a4359
DV		 309 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
310 return 0;
311 }
5a5a0c64
DV		 312 }
313
314 /* synchronous slowpath */
315 BEGIN_LP_RING(2);
722506f0
CW		 316 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
317 OUT_RING(MI_NOOP);
318 ADVANCE_LP_RING();
02e792fb 319
b6c028e0 320 return intel_overlay_do_wait_request(overlay, true, RELEASE_OLD_VID);
02e792fb
DV		 321}
322
323/* overlay needs to be disabled in OCMD reg */
324static int intel_overlay_off(struct intel_overlay *overlay)
325{
326 u32 flip_addr = overlay->flip_addr;
327 struct drm_device *dev = overlay->dev;
02e792fb
DV		 328
329 BUG_ON(!overlay->active);
330
331 /* According to intel docs the overlay hw may hang (when switching
332 * off) without loading the filter coeffs. It is however unclear whether
333 * this applies to the disabling of the overlay or to the switching off
334 * of the hw. Do it in both cases */
335 flip_addr |= OFC_UPDATE;
336
8dfbc340 337 BEGIN_LP_RING(6);
02e792fb 338 /* wait for overlay to go idle */
02e792fb
DV		 339 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
340 OUT_RING(flip_addr);
722506f0 341 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 342 /* turn overlay off */
722506f0 343 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 344 OUT_RING(flip_addr);
722506f0 345 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb
DV		 346 ADVANCE_LP_RING();
347
8dfbc340 348 return intel_overlay_do_wait_request(overlay, true, SWITCH_OFF);
02e792fb
DV		 349}
350
12ca45fe
DV		 351static void intel_overlay_off_tail(struct intel_overlay *overlay)
352{
353 struct drm_gem_object *obj;
354
355 /* never have the overlay hw on without showing a frame */
356 BUG_ON(!overlay->vid_bo);
a8089e84 357 obj = &overlay->vid_bo->base;
12ca45fe
DV		 358
359 i915_gem_object_unpin(obj);
360 drm_gem_object_unreference(obj);
361 overlay->vid_bo = NULL;
362
363 overlay->crtc->overlay = NULL;
364 overlay->crtc = NULL;
365 overlay->active = 0;
366}
367
03f77ea5
DV		 368/* recover from an interruption due to a signal
369 * We have to be careful not to repeat work forever an make forward progess. */
370int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
722506f0 371 bool interruptible)
03f77ea5
DV		 372{
373 struct drm_device *dev = overlay->dev;
852835f3 374 drm_i915_private_t *dev_priv = dev->dev_private;
8dfbc340 375 struct drm_gem_object *obj;
03f77ea5 376 int ret;
03f77ea5
DV		 377
378 if (overlay->hw_wedged == HW_WEDGED)
379 return -EIO;
380
852835f3 381 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 382 interruptible, &dev_priv->render_ring);
b6c028e0 383 if (ret)
03f77ea5
DV		 384 return ret;
385
386 switch (overlay->hw_wedged) {
722506f0
CW		 387 case RELEASE_OLD_VID:
388 obj = &overlay->old_vid_bo->base;
389 i915_gem_object_unpin(obj);
390 drm_gem_object_unreference(obj);
391 overlay->old_vid_bo = NULL;
392 break;
b6c028e0 393
8dfbc340 394 case SWITCH_OFF:
722506f0
CW		 395 intel_overlay_off_tail(overlay);
396 break;
8dfbc340 397
722506f0
CW		 398 default:
399 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
03f77ea5
DV		 400 }
401
402 overlay->hw_wedged = 0;
403 overlay->last_flip_req = 0;
404 return 0;
405}
406
5a5a0c64
DV		 407/* Wait for pending overlay flip and release old frame.
408 * Needs to be called before the overlay register are changed
8d74f656
CW		 409 * via intel_overlay_(un)map_regs
410 */
02e792fb
DV		 411static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
412{
413 int ret;
414 struct drm_gem_object *obj;
415
03f77ea5
DV		 416 /* only wait if there is actually an old frame to release to
417 * guarantee forward progress */
418 if (!overlay->old_vid_bo)
419 return 0;
420
02e792fb
DV		 421 ret = intel_overlay_wait_flip(overlay);
422 if (ret != 0)
423 return ret;
424
a8089e84 425 obj = &overlay->old_vid_bo->base;
02e792fb
DV		 426 i915_gem_object_unpin(obj);
427 drm_gem_object_unreference(obj);
428 overlay->old_vid_bo = NULL;
429
430 return 0;
431}
432
433struct put_image_params {
434 int format;
435 short dst_x;
436 short dst_y;
437 short dst_w;
438 short dst_h;
439 short src_w;
440 short src_scan_h;
441 short src_scan_w;
442 short src_h;
443 short stride_Y;
444 short stride_UV;
445 int offset_Y;
446 int offset_U;
447 int offset_V;
448};
449
450static int packed_depth_bytes(u32 format)
451{
452 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 453 case I915_OVERLAY_YUV422:
454 return 4;
455 case I915_OVERLAY_YUV411:
456 /* return 6; not implemented */
457 default:
458 return -EINVAL;
02e792fb
DV		 459 }
460}
461
462static int packed_width_bytes(u32 format, short width)
463{
464 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 465 case I915_OVERLAY_YUV422:
466 return width << 1;
467 default:
468 return -EINVAL;
02e792fb
DV		 469 }
470}
471
472static int uv_hsubsampling(u32 format)
473{
474 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 475 case I915_OVERLAY_YUV422:
476 case I915_OVERLAY_YUV420:
477 return 2;
478 case I915_OVERLAY_YUV411:
479 case I915_OVERLAY_YUV410:
480 return 4;
481 default:
482 return -EINVAL;
02e792fb
DV		 483 }
484}
485
486static int uv_vsubsampling(u32 format)
487{
488 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 489 case I915_OVERLAY_YUV420:
490 case I915_OVERLAY_YUV410:
491 return 2;
492 case I915_OVERLAY_YUV422:
493 case I915_OVERLAY_YUV411:
494 return 1;
495 default:
496 return -EINVAL;
02e792fb
DV		 497 }
498}
499
500static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
501{
502 u32 mask, shift, ret;
503 if (IS_I9XX(dev)) {
504 mask = 0x3f;
505 shift = 6;
506 } else {
507 mask = 0x1f;
508 shift = 5;
509 }
510 ret = ((offset + width + mask) >> shift) - (offset >> shift);
511 if (IS_I9XX(dev))
512 ret <<= 1;
513 ret -=1;
514 return ret << 2;
515}
516
517static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
518 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
519 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
520 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
521 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
522 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
523 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
524 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
525 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
526 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
527 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
528 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
529 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
530 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
531 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
532 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
533 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 534 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
535};
536
02e792fb
DV		 537static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
538 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
539 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
540 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
541 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
542 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
543 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
544 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
545 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 546 0x3000, 0x0800, 0x3000
547};
02e792fb
DV		 548
549static void update_polyphase_filter(struct overlay_registers *regs)
550{
551 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
552 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
553}
554
555static bool update_scaling_factors(struct intel_overlay *overlay,
556 struct overlay_registers *regs,
557 struct put_image_params *params)
558{
559 /* fixed point with a 12 bit shift */
560 u32 xscale, yscale, xscale_UV, yscale_UV;
561#define FP_SHIFT 12
562#define FRACT_MASK 0xfff
563 bool scale_changed = false;
564 int uv_hscale = uv_hsubsampling(params->format);
565 int uv_vscale = uv_vsubsampling(params->format);
566
567 if (params->dst_w > 1)
568 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
569 /(params->dst_w);
570 else
571 xscale = 1 << FP_SHIFT;
572
573 if (params->dst_h > 1)
574 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
575 /(params->dst_h);
576 else
577 yscale = 1 << FP_SHIFT;
578
579 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 580 xscale_UV = xscale/uv_hscale;
581 yscale_UV = yscale/uv_vscale;
582 /* make the Y scale to UV scale ratio an exact multiply */
583 xscale = xscale_UV * uv_hscale;
584 yscale = yscale_UV * uv_vscale;
02e792fb 585 /*} else {
722506f0
CW		 586 xscale_UV = 0;
587 yscale_UV = 0;
588 }*/
02e792fb
DV		 589
590 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
591 scale_changed = true;
592 overlay->old_xscale = xscale;
593 overlay->old_yscale = yscale;
594
722506f0
CW		 595 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
596 ((xscale >> FP_SHIFT) << 16) |
597 ((xscale & FRACT_MASK) << 3));
598
599 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
600 ((xscale_UV >> FP_SHIFT) << 16) |
601 ((xscale_UV & FRACT_MASK) << 3));
602
603 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
604 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 605
606 if (scale_changed)
607 update_polyphase_filter(regs);
608
609 return scale_changed;
610}
611
612static void update_colorkey(struct intel_overlay *overlay,
613 struct overlay_registers *regs)
614{
615 u32 key = overlay->color_key;
6ba3ddd9 616
02e792fb 617 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 618 case 8:
619 regs->DCLRKV = 0;
620 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 621 break;
622
722506f0
CW		 623 case 16:
624 if (overlay->crtc->base.fb->depth == 15) {
625 regs->DCLRKV = RGB15_TO_COLORKEY(key);
626 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
627 } else {
628 regs->DCLRKV = RGB16_TO_COLORKEY(key);
629 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
630 }
6ba3ddd9
CW		 631 break;
632
722506f0
CW		 633 case 24:
634 case 32:
635 regs->DCLRKV = key;
636 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 637 break;
02e792fb
DV		 638 }
639}
640
641static u32 overlay_cmd_reg(struct put_image_params *params)
642{
643 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
644
645 if (params->format & I915_OVERLAY_YUV_PLANAR) {
646 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 647 case I915_OVERLAY_YUV422:
648 cmd |= OCMD_YUV_422_PLANAR;
649 break;
650 case I915_OVERLAY_YUV420:
651 cmd |= OCMD_YUV_420_PLANAR;
652 break;
653 case I915_OVERLAY_YUV411:
654 case I915_OVERLAY_YUV410:
655 cmd |= OCMD_YUV_410_PLANAR;
656 break;
02e792fb
DV		 657 }
658 } else { /* YUV packed */
659 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 660 case I915_OVERLAY_YUV422:
661 cmd |= OCMD_YUV_422_PACKED;
662 break;
663 case I915_OVERLAY_YUV411:
664 cmd |= OCMD_YUV_411_PACKED;
665 break;
02e792fb
DV		 666 }
667
668 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 669 case I915_OVERLAY_NO_SWAP:
670 break;
671 case I915_OVERLAY_UV_SWAP:
672 cmd |= OCMD_UV_SWAP;
673 break;
674 case I915_OVERLAY_Y_SWAP:
675 cmd |= OCMD_Y_SWAP;
676 break;
677 case I915_OVERLAY_Y_AND_UV_SWAP:
678 cmd |= OCMD_Y_AND_UV_SWAP;
679 break;
02e792fb
DV		 680 }
681 }
682
683 return cmd;
684}
685
686int intel_overlay_do_put_image(struct intel_overlay *overlay,
687 struct drm_gem_object *new_bo,
688 struct put_image_params *params)
689{
690 int ret, tmp_width;
691 struct overlay_registers *regs;
692 bool scale_changed = false;
23010e43 693 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 694 struct drm_device *dev = overlay->dev;
695
696 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
697 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
698 BUG_ON(!overlay);
699
02e792fb
DV		 700 ret = intel_overlay_release_old_vid(overlay);
701 if (ret != 0)
702 return ret;
703
704 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
705 if (ret != 0)
706 return ret;
707
708 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
709 if (ret != 0)
710 goto out_unpin;
711
712 if (!overlay->active) {
8d74f656 713 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 714 if (!regs) {
715 ret = -ENOMEM;
716 goto out_unpin;
717 }
718 regs->OCONFIG = OCONF_CC_OUT_8BIT;
719 if (IS_I965GM(overlay->dev))
720 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
721 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
722 OCONF_PIPE_A : OCONF_PIPE_B;
9bb2ff73 723 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 724
725 ret = intel_overlay_on(overlay);
726 if (ret != 0)
727 goto out_unpin;
728 }
729
8d74f656 730 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 731 if (!regs) {
732 ret = -ENOMEM;
733 goto out_unpin;
734 }
735
736 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
737 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
738
739 if (params->format & I915_OVERLAY_YUV_PACKED)
740 tmp_width = packed_width_bytes(params->format, params->src_w);
741 else
742 tmp_width = params->src_w;
743
744 regs->SWIDTH = params->src_w;
745 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 746 params->offset_Y, tmp_width);
02e792fb
DV		 747 regs->SHEIGHT = params->src_h;
748 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
749 regs->OSTRIDE = params->stride_Y;
750
751 if (params->format & I915_OVERLAY_YUV_PLANAR) {
752 int uv_hscale = uv_hsubsampling(params->format);
753 int uv_vscale = uv_vsubsampling(params->format);
754 u32 tmp_U, tmp_V;
755 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
756 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 757 params->src_w/uv_hscale);
02e792fb 758 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 759 params->src_w/uv_hscale);
02e792fb
DV		 760 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
761 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
762 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
763 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
764 regs->OSTRIDE |= params->stride_UV << 16;
765 }
766
767 scale_changed = update_scaling_factors(overlay, regs, params);
768
769 update_colorkey(overlay, regs);
770
771 regs->OCMD = overlay_cmd_reg(params);
772
9bb2ff73 773 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 774
775 intel_overlay_continue(overlay, scale_changed);
776
777 overlay->old_vid_bo = overlay->vid_bo;
23010e43 778 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 779
780 return 0;
781
782out_unpin:
783 i915_gem_object_unpin(new_bo);
784 return ret;
785}
786
787int intel_overlay_switch_off(struct intel_overlay *overlay)
788{
789 int ret;
790 struct overlay_registers *regs;
02e792fb
DV		 791 struct drm_device *dev = overlay->dev;
792
793 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
794 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
795
9bedb974
DV		 796 if (overlay->hw_wedged) {
797 ret = intel_overlay_recover_from_interrupt(overlay, 1);
798 if (ret != 0)
799 return ret;
800 }
801
02e792fb
DV		 802 if (!overlay->active)
803 return 0;
804
02e792fb
DV		 805 ret = intel_overlay_release_old_vid(overlay);
806 if (ret != 0)
807 return ret;
808
8d74f656 809 regs = intel_overlay_map_regs(overlay);
02e792fb 810 regs->OCMD = 0;
9bb2ff73 811 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 812
813 ret = intel_overlay_off(overlay);
03f77ea5
DV		 814 if (ret != 0)
815 return ret;
816
12ca45fe 817 intel_overlay_off_tail(overlay);
02e792fb
DV		 818
819 return 0;
820}
821
822static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
823 struct intel_crtc *crtc)
824{
722506f0 825 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb
DV		 826 u32 pipeconf;
827 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
828
829 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
830 return -EINVAL;
831
832 pipeconf = I915_READ(pipeconf_reg);
833
834 /* can't use the overlay with double wide pipe */
835 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
836 return -EINVAL;
837
838 return 0;
839}
840
841static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
842{
843 struct drm_device *dev = overlay->dev;
722506f0 844 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 845 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 846 u32 ratio;
02e792fb
DV		 847
848 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 849 * line with the intel documentation for the i965
850 */
851 if (!IS_I965G(dev)) {
852 if (pfit_control & VERT_AUTO_SCALE)
853 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 854 else
446d2183
CW		 855 ratio = I915_READ(PFIT_PGM_RATIOS);
856 ratio >>= PFIT_VERT_SCALE_SHIFT;
857 } else { /* on i965 use the PGM reg to read out the autoscaler values */
858 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
02e792fb
DV		 859 }
860
861 overlay->pfit_vscale_ratio = ratio;
862}
863
864static int check_overlay_dst(struct intel_overlay *overlay,
865 struct drm_intel_overlay_put_image *rec)
866{
867 struct drm_display_mode *mode = &overlay->crtc->base.mode;
868
722506f0
CW		 869 if (rec->dst_x < mode->crtc_hdisplay &&
870 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
871 rec->dst_y < mode->crtc_vdisplay &&
872 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 873 return 0;
874 else
875 return -EINVAL;
876}
877
878static int check_overlay_scaling(struct put_image_params *rec)
879{
880 u32 tmp;
881
882 /* downscaling limit is 8.0 */
883 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
884 if (tmp > 7)
885 return -EINVAL;
886 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
887 if (tmp > 7)
888 return -EINVAL;
889
890 return 0;
891}
892
893static int check_overlay_src(struct drm_device *dev,
894 struct drm_intel_overlay_put_image *rec,
895 struct drm_gem_object *new_bo)
896{
02e792fb
DV		 897 int uv_hscale = uv_hsubsampling(rec->flags);
898 int uv_vscale = uv_vsubsampling(rec->flags);
9f7c3f44 899 u32 stride_mask, depth, tmp;
02e792fb
DV		 900
901 /* check src dimensions */
902 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 903 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 904 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 905 return -EINVAL;
906 } else {
722506f0 907 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 908 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 909 return -EINVAL;
910 }
9f7c3f44 911
02e792fb 912 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 913 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 914 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 915 return -EINVAL;
916
a1efd14a 917 /* check alignment constraints */
02e792fb 918 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 919 case I915_OVERLAY_RGB:
920 /* not implemented */
921 return -EINVAL;
9f7c3f44 922
722506f0 923 case I915_OVERLAY_YUV_PACKED:
722506f0 924 if (uv_vscale != 1)
02e792fb 925 return -EINVAL;
9f7c3f44
CW		 926
927 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 928 if (depth < 0)
929 return depth;
9f7c3f44 930
722506f0
CW		 931 /* ignore UV planes */
932 rec->stride_UV = 0;
933 rec->offset_U = 0;
934 rec->offset_V = 0;
935 /* check pixel alignment */
936 if (rec->offset_Y % depth)
937 return -EINVAL;
938 break;
9f7c3f44 939
722506f0
CW		 940 case I915_OVERLAY_YUV_PLANAR:
941 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 942 return -EINVAL;
722506f0
CW		 943 /* no offset restrictions for planar formats */
944 break;
9f7c3f44 945
722506f0
CW		 946 default:
947 return -EINVAL;
02e792fb
DV		 948 }
949
950 if (rec->src_width % uv_hscale)
951 return -EINVAL;
952
953 /* stride checking */
a1efd14a
CW		 954 if (IS_I830(dev) || IS_845G(dev))
955 stride_mask = 255;
956 else
957 stride_mask = 63;
02e792fb
DV		 958
959 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
960 return -EINVAL;
961 if (IS_I965G(dev) && rec->stride_Y < 512)
962 return -EINVAL;
963
964 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 965 4096 : 8192;
966 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 967 return -EINVAL;
968
969 /* check buffer dimensions */
970 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 971 case I915_OVERLAY_RGB:
972 case I915_OVERLAY_YUV_PACKED:
973 /* always 4 Y values per depth pixels */
974 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
975 return -EINVAL;
976
977 tmp = rec->stride_Y*rec->src_height;
978 if (rec->offset_Y + tmp > new_bo->size)
979 return -EINVAL;
980 break;
981
982 case I915_OVERLAY_YUV_PLANAR:
983 if (rec->src_width > rec->stride_Y)
984 return -EINVAL;
985 if (rec->src_width/uv_hscale > rec->stride_UV)
986 return -EINVAL;
987
9f7c3f44 988 tmp = rec->stride_Y * rec->src_height;
722506f0
CW		 989 if (rec->offset_Y + tmp > new_bo->size)
990 return -EINVAL;
9f7c3f44
CW		 991
992 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
722506f0
CW		 993 if (rec->offset_U + tmp > new_bo->size ||
994 rec->offset_V + tmp > new_bo->size)
995 return -EINVAL;
996 break;
02e792fb
DV		 997 }
998
999 return 0;
1000}
1001
1002int intel_overlay_put_image(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv)
1004{
1005 struct drm_intel_overlay_put_image *put_image_rec = data;
1006 drm_i915_private_t *dev_priv = dev->dev_private;
1007 struct intel_overlay *overlay;
1008 struct drm_mode_object *drmmode_obj;
1009 struct intel_crtc *crtc;
1010 struct drm_gem_object *new_bo;
1011 struct put_image_params *params;
1012 int ret;
1013
1014 if (!dev_priv) {
1015 DRM_ERROR("called with no initialization\n");
1016 return -EINVAL;
1017 }
1018
1019 overlay = dev_priv->overlay;
1020 if (!overlay) {
1021 DRM_DEBUG("userspace bug: no overlay\n");
1022 return -ENODEV;
1023 }
1024
1025 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1026 mutex_lock(&dev->mode_config.mutex);
1027 mutex_lock(&dev->struct_mutex);
1028
1029 ret = intel_overlay_switch_off(overlay);
1030
1031 mutex_unlock(&dev->struct_mutex);
1032 mutex_unlock(&dev->mode_config.mutex);
1033
1034 return ret;
1035 }
1036
1037 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1038 if (!params)
1039 return -ENOMEM;
1040
1041 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1042 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1043 if (!drmmode_obj) {
1044 ret = -ENOENT;
1045 goto out_free;
1046 }
02e792fb
DV		 1047 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1048
1049 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1050 put_image_rec->bo_handle);
915a428e
DC		 1051 if (!new_bo) {
1052 ret = -ENOENT;
1053 goto out_free;
1054 }
02e792fb
DV		 1055
1056 mutex_lock(&dev->mode_config.mutex);
1057 mutex_lock(&dev->struct_mutex);
1058
03f77ea5
DV		 1059 if (overlay->hw_wedged) {
1060 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1061 if (ret != 0)
1062 goto out_unlock;
1063 }
1064
02e792fb
DV		 1065 if (overlay->crtc != crtc) {
1066 struct drm_display_mode *mode = &crtc->base.mode;
1067 ret = intel_overlay_switch_off(overlay);
1068 if (ret != 0)
1069 goto out_unlock;
1070
1071 ret = check_overlay_possible_on_crtc(overlay, crtc);
1072 if (ret != 0)
1073 goto out_unlock;
1074
1075 overlay->crtc = crtc;
1076 crtc->overlay = overlay;
1077
1078 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1079 /* and line to wide, i.e. one-line-mode */
1080 && mode->hdisplay > 1024) {
1081 overlay->pfit_active = 1;
1082 update_pfit_vscale_ratio(overlay);
1083 } else
1084 overlay->pfit_active = 0;
1085 }
1086
1087 ret = check_overlay_dst(overlay, put_image_rec);
1088 if (ret != 0)
1089 goto out_unlock;
1090
1091 if (overlay->pfit_active) {
1092 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1093 overlay->pfit_vscale_ratio);
02e792fb
DV		 1094 /* shifting right rounds downwards, so add 1 */
1095 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1096 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1097 } else {
1098 params->dst_y = put_image_rec->dst_y;
1099 params->dst_h = put_image_rec->dst_height;
1100 }
1101 params->dst_x = put_image_rec->dst_x;
1102 params->dst_w = put_image_rec->dst_width;
1103
1104 params->src_w = put_image_rec->src_width;
1105 params->src_h = put_image_rec->src_height;
1106 params->src_scan_w = put_image_rec->src_scan_width;
1107 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1108 if (params->src_scan_h > params->src_h ||
1109 params->src_scan_w > params->src_w) {
02e792fb
DV		 1110 ret = -EINVAL;
1111 goto out_unlock;
1112 }
1113
1114 ret = check_overlay_src(dev, put_image_rec, new_bo);
1115 if (ret != 0)
1116 goto out_unlock;
1117 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1118 params->stride_Y = put_image_rec->stride_Y;
1119 params->stride_UV = put_image_rec->stride_UV;
1120 params->offset_Y = put_image_rec->offset_Y;
1121 params->offset_U = put_image_rec->offset_U;
1122 params->offset_V = put_image_rec->offset_V;
1123
1124 /* Check scaling after src size to prevent a divide-by-zero. */
1125 ret = check_overlay_scaling(params);
1126 if (ret != 0)
1127 goto out_unlock;
1128
1129 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1130 if (ret != 0)
1131 goto out_unlock;
1132
1133 mutex_unlock(&dev->struct_mutex);
1134 mutex_unlock(&dev->mode_config.mutex);
1135
1136 kfree(params);
1137
1138 return 0;
1139
1140out_unlock:
1141 mutex_unlock(&dev->struct_mutex);
1142 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1143 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1144out_free:
02e792fb
DV		 1145 kfree(params);
1146
1147 return ret;
1148}
1149
1150static void update_reg_attrs(struct intel_overlay *overlay,
1151 struct overlay_registers *regs)
1152{
1153 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1154 regs->OCLRC1 = overlay->saturation;
1155}
1156
1157static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1158{
1159 int i;
1160
1161 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1162 return false;
1163
1164 for (i = 0; i < 3; i++) {
722506f0 1165 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1166 return false;
1167 }
1168
1169 return true;
1170}
1171
1172static bool check_gamma5_errata(u32 gamma5)
1173{
1174 int i;
1175
1176 for (i = 0; i < 3; i++) {
1177 if (((gamma5 >> i*8) & 0xff) == 0x80)
1178 return false;
1179 }
1180
1181 return true;
1182}
1183
1184static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1185{
722506f0
CW		 1186 if (!check_gamma_bounds(0, attrs->gamma0) ||
1187 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1188 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1189 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1190 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1191 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1192 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1193 return -EINVAL;
722506f0 1194
02e792fb
DV		 1195 if (!check_gamma5_errata(attrs->gamma5))
1196 return -EINVAL;
722506f0 1197
02e792fb
DV		 1198 return 0;
1199}
1200
1201int intel_overlay_attrs(struct drm_device *dev, void *data,
1202 struct drm_file *file_priv)
1203{
1204 struct drm_intel_overlay_attrs *attrs = data;
1205 drm_i915_private_t *dev_priv = dev->dev_private;
1206 struct intel_overlay *overlay;
1207 struct overlay_registers *regs;
1208 int ret;
1209
1210 if (!dev_priv) {
1211 DRM_ERROR("called with no initialization\n");
1212 return -EINVAL;
1213 }
1214
1215 overlay = dev_priv->overlay;
1216 if (!overlay) {
1217 DRM_DEBUG("userspace bug: no overlay\n");
1218 return -ENODEV;
1219 }
1220
1221 mutex_lock(&dev->mode_config.mutex);
1222 mutex_lock(&dev->struct_mutex);
1223
60fc332c 1224 ret = -EINVAL;
02e792fb 1225 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1226 attrs->color_key = overlay->color_key;
02e792fb 1227 attrs->brightness = overlay->brightness;
60fc332c 1228 attrs->contrast = overlay->contrast;
02e792fb
DV		 1229 attrs->saturation = overlay->saturation;
1230
1231 if (IS_I9XX(dev)) {
1232 attrs->gamma0 = I915_READ(OGAMC0);
1233 attrs->gamma1 = I915_READ(OGAMC1);
1234 attrs->gamma2 = I915_READ(OGAMC2);
1235 attrs->gamma3 = I915_READ(OGAMC3);
1236 attrs->gamma4 = I915_READ(OGAMC4);
1237 attrs->gamma5 = I915_READ(OGAMC5);
1238 }
02e792fb 1239 } else {
60fc332c 1240 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1241 goto out_unlock;
60fc332c 1242 if (attrs->contrast > 255)
02e792fb 1243 goto out_unlock;
60fc332c 1244 if (attrs->saturation > 1023)
02e792fb 1245 goto out_unlock;
60fc332c
CW		 1246
1247 overlay->color_key = attrs->color_key;
1248 overlay->brightness = attrs->brightness;
1249 overlay->contrast = attrs->contrast;
1250 overlay->saturation = attrs->saturation;
02e792fb 1251
8d74f656 1252 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1253 if (!regs) {
1254 ret = -ENOMEM;
1255 goto out_unlock;
1256 }
1257
1258 update_reg_attrs(overlay, regs);
1259
9bb2ff73 1260 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1261
1262 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
60fc332c 1263 if (!IS_I9XX(dev))
02e792fb 1264 goto out_unlock;
02e792fb
DV		 1265
1266 if (overlay->active) {
1267 ret = -EBUSY;
1268 goto out_unlock;
1269 }
1270
1271 ret = check_gamma(attrs);
60fc332c 1272 if (ret)
02e792fb
DV		 1273 goto out_unlock;
1274
1275 I915_WRITE(OGAMC0, attrs->gamma0);
1276 I915_WRITE(OGAMC1, attrs->gamma1);
1277 I915_WRITE(OGAMC2, attrs->gamma2);
1278 I915_WRITE(OGAMC3, attrs->gamma3);
1279 I915_WRITE(OGAMC4, attrs->gamma4);
1280 I915_WRITE(OGAMC5, attrs->gamma5);
1281 }
02e792fb
DV		 1282 }
1283
60fc332c 1284 ret = 0;
02e792fb
DV		 1285out_unlock:
1286 mutex_unlock(&dev->struct_mutex);
1287 mutex_unlock(&dev->mode_config.mutex);
1288
1289 return ret;
1290}
1291
1292void intel_setup_overlay(struct drm_device *dev)
1293{
1294 drm_i915_private_t *dev_priv = dev->dev_private;
1295 struct intel_overlay *overlay;
1296 struct drm_gem_object *reg_bo;
1297 struct overlay_registers *regs;
1298 int ret;
1299
31578148 1300 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1301 return;
1302
1303 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1304 if (!overlay)
1305 return;
1306 overlay->dev = dev;
1307
ac52bc56 1308 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1309 if (!reg_bo)
1310 goto out_free;
23010e43 1311 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1312
31578148
CW		 1313 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1314 ret = i915_gem_attach_phys_object(dev, reg_bo,
1315 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1316 PAGE_SIZE);
31578148
CW		 1317 if (ret) {
1318 DRM_ERROR("failed to attach phys overlay regs\n");
1319 goto out_free_bo;
1320 }
1321 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1322 } else {
02e792fb
DV		 1323 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1324 if (ret) {
1325 DRM_ERROR("failed to pin overlay register bo\n");
1326 goto out_free_bo;
1327 }
1328 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1329
1330 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1331 if (ret) {
1332 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1333 goto out_unpin_bo;
1334 }
02e792fb
DV		 1335 }
1336
1337 /* init all values */
1338 overlay->color_key = 0x0101fe;
1339 overlay->brightness = -19;
1340 overlay->contrast = 75;
1341 overlay->saturation = 146;
1342
8d74f656 1343 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1344 if (!regs)
1345 goto out_free_bo;
1346
1347 memset(regs, 0, sizeof(struct overlay_registers));
1348 update_polyphase_filter(regs);
02e792fb
DV		 1349 update_reg_attrs(overlay, regs);
1350
9bb2ff73 1351 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1352
1353 dev_priv->overlay = overlay;
1354 DRM_INFO("initialized overlay support\n");
1355 return;
1356
0ddc1289
CW		 1357out_unpin_bo:
1358 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1359out_free_bo:
1360 drm_gem_object_unreference(reg_bo);
1361out_free:
1362 kfree(overlay);
1363 return;
1364}
1365
1366void intel_cleanup_overlay(struct drm_device *dev)
1367{
722506f0 1368 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1369
62cf4e6f
CW		 1370 if (!dev_priv->overlay)
1371 return;
02e792fb 1372
62cf4e6f
CW		 1373 /* The bo's should be free'd by the generic code already.
1374 * Furthermore modesetting teardown happens beforehand so the
1375 * hardware should be off already */
1376 BUG_ON(dev_priv->overlay->active);
1377
1378 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1379 kfree(dev_priv->overlay);
02e792fb 1380}
6ef3d427
CW		 1381
1382struct intel_overlay_error_state {
1383 struct overlay_registers regs;
1384 unsigned long base;
1385 u32 dovsta;
1386 u32 isr;
1387};
1388
1389struct intel_overlay_error_state *
1390intel_overlay_capture_error_state(struct drm_device *dev)
1391{
1392 drm_i915_private_t *dev_priv = dev->dev_private;
1393 struct intel_overlay *overlay = dev_priv->overlay;
1394 struct intel_overlay_error_state *error;
1395 struct overlay_registers __iomem *regs;
1396
1397 if (!overlay || !overlay->active)
1398 return NULL;
1399
1400 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1401 if (error == NULL)
1402 return NULL;
1403
1404 error->dovsta = I915_READ(DOVSTA);
1405 error->isr = I915_READ(ISR);
31578148 1406 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1407 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1408 else
1409 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427 1410
8d74f656 1411 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1412 if (!regs)
1413 goto err;
1414
1415 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
9bb2ff73 1416 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0, regs);
6ef3d427
CW		 1417
1418 return error;
1419
1420err:
1421 kfree(error);
1422 return NULL;
1423}
1424
1425void
1426intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1427{
1428 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1429 error->dovsta, error->isr);
1430 seq_printf(m, " Register file at 0x%08lx:\n",
1431 error->base);
1432
1433#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1434 P(OBUF_0Y);
1435 P(OBUF_1Y);
1436 P(OBUF_0U);
1437 P(OBUF_0V);
1438 P(OBUF_1U);
1439 P(OBUF_1V);
1440 P(OSTRIDE);
1441 P(YRGB_VPH);
1442 P(UV_VPH);
1443 P(HORZ_PH);
1444 P(INIT_PHS);
1445 P(DWINPOS);
1446 P(DWINSZ);
1447 P(SWIDTH);
1448 P(SWIDTHSW);
1449 P(SHEIGHT);
1450 P(YRGBSCALE);
1451 P(UVSCALE);
1452 P(OCLRC0);
1453 P(OCLRC1);
1454 P(DCLRKV);
1455 P(DCLRKM);
1456 P(SCLRKVH);
1457 P(SCLRKVL);
1458 P(SCLRKEN);
1459 P(OCONFIG);
1460 P(OCMD);
1461 P(OSTART_0Y);
1462 P(OSTART_1Y);
1463 P(OSTART_0U);
1464 P(OSTART_0V);
1465 P(OSTART_1U);
1466 P(OSTART_1V);
1467 P(OTILEOFF_0Y);
1468 P(OTILEOFF_1Y);
1469 P(OTILEOFF_0U);
1470 P(OTILEOFF_0V);
1471 P(OTILEOFF_1U);
1472 P(OTILEOFF_1V);
1473 P(FASTHSCALE);
1474 P(UVSCALEV);
1475#undef P
1476}
Linux kernel - Deliverables
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