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drm/i915/overlay: Refactor do_wait_request()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
8d74f656
CW		 173static struct overlay_registers *
174intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
175 int slot)
02e792fb
DV		 176{
177 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
178 struct overlay_registers *regs;
179
180 /* no recursive mappings */
181 BUG_ON(overlay->virt_addr);
182
31578148
CW		 183 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
184 regs = overlay->reg_bo->phys_obj->handle->vaddr;
185 } else {
02e792fb 186 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
fca3ec01 187 overlay->reg_bo->gtt_offset,
8d74f656 188 slot);
02e792fb
DV		 189
190 if (!regs) {
191 DRM_ERROR("failed to map overlay regs in GTT\n");
192 return NULL;
193 }
31578148 194 }
02e792fb
DV		 195
196 return overlay->virt_addr = regs;
197}
198
8d74f656
CW		 199static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
200 int slot)
02e792fb 201{
31578148 202 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656
CW		 203 io_mapping_unmap_atomic(overlay->virt_addr, slot);
204
205 overlay->virt_addr = NULL;
206
207 return;
208}
209
210static struct overlay_registers *
211intel_overlay_map_regs(struct intel_overlay *overlay)
212{
213 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
214 struct overlay_registers *regs;
215
216 /* no recursive mappings */
217 BUG_ON(overlay->virt_addr);
218
219 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
220 regs = overlay->reg_bo->phys_obj->handle->vaddr;
221 } else {
222 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
223 overlay->reg_bo->gtt_offset);
224
225 if (!regs) {
226 DRM_ERROR("failed to map overlay regs in GTT\n");
227 return NULL;
228 }
229 }
230
231 return overlay->virt_addr = regs;
232}
233
234static void intel_overlay_unmap_regs(struct intel_overlay *overlay)
235{
236 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
237 io_mapping_unmap(overlay->virt_addr);
02e792fb
DV		 238
239 overlay->virt_addr = NULL;
240
02e792fb
DV		 241 return;
242}
243
b6c028e0
CW		 244static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
245 bool interruptible,
246 int stage)
02e792fb
DV		 247{
248 struct drm_device *dev = overlay->dev;
852835f3 249 drm_i915_private_t *dev_priv = dev->dev_private;
b6c028e0 250 int ret;
02e792fb 251
852835f3 252 overlay->last_flip_req =
8a1a49f9 253 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 254 if (overlay->last_flip_req == 0)
255 return -ENOMEM;
02e792fb 256
b6c028e0 257 overlay->hw_wedged = stage;
852835f3 258 ret = i915_do_wait_request(dev,
722506f0
CW		 259 overlay->last_flip_req, true,
260 &dev_priv->render_ring);
b6c028e0 261 if (ret)
03f77ea5 262 return ret;
02e792fb 263
03f77ea5
DV		 264 overlay->hw_wedged = 0;
265 overlay->last_flip_req = 0;
02e792fb
DV		 266 return 0;
267}
268
b6c028e0
CW		 269/* overlay needs to be disable in OCMD reg */
270static int intel_overlay_on(struct intel_overlay *overlay)
271{
272 struct drm_device *dev = overlay->dev;
273
274 BUG_ON(overlay->active);
275
276 overlay->active = 1;
277
278 BEGIN_LP_RING(4);
279 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
280 OUT_RING(overlay->flip_addr | OFC_UPDATE);
281 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
282 OUT_RING(MI_NOOP);
283 ADVANCE_LP_RING();
284
285 return intel_overlay_do_wait_request(overlay, true,
286 NEEDS_WAIT_FOR_FLIP);
287}
288
02e792fb
DV		 289/* overlay needs to be enabled in OCMD reg */
290static void intel_overlay_continue(struct intel_overlay *overlay,
722506f0 291 bool load_polyphase_filter)
02e792fb
DV		 292{
293 struct drm_device *dev = overlay->dev;
294 drm_i915_private_t *dev_priv = dev->dev_private;
295 u32 flip_addr = overlay->flip_addr;
296 u32 tmp;
02e792fb
DV		 297
298 BUG_ON(!overlay->active);
299
300 if (load_polyphase_filter)
301 flip_addr |= OFC_UPDATE;
302
303 /* check for underruns */
304 tmp = I915_READ(DOVSTA);
305 if (tmp & (1 << 17))
306 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
307
4f8a567c 308 BEGIN_LP_RING(2);
02e792fb
DV		 309 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
310 OUT_RING(flip_addr);
5a5a0c64
DV		 311 ADVANCE_LP_RING();
312
852835f3 313 overlay->last_flip_req =
8a1a49f9 314 i915_add_request(dev, NULL, &dev_priv->render_ring);
5a5a0c64
DV		 315}
316
317static int intel_overlay_wait_flip(struct intel_overlay *overlay)
318{
319 struct drm_device *dev = overlay->dev;
722506f0 320 drm_i915_private_t *dev_priv = dev->dev_private;
5a5a0c64
DV		 321 int ret;
322 u32 tmp;
5a5a0c64
DV		 323
324 if (overlay->last_flip_req != 0) {
722506f0
CW		 325 ret = i915_do_wait_request(dev,
326 overlay->last_flip_req, true,
327 &dev_priv->render_ring);
5c5a4359
DV		 328 if (ret == 0) {
329 overlay->last_flip_req = 0;
5a5a0c64 330
5c5a4359 331 tmp = I915_READ(ISR);
5a5a0c64 332
5c5a4359
DV		 333 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
334 return 0;
335 }
5a5a0c64
DV		 336 }
337
338 /* synchronous slowpath */
339 BEGIN_LP_RING(2);
722506f0
CW		 340 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
341 OUT_RING(MI_NOOP);
342 ADVANCE_LP_RING();
02e792fb 343
b6c028e0 344 return intel_overlay_do_wait_request(overlay, true, RELEASE_OLD_VID);
02e792fb
DV		 345}
346
347/* overlay needs to be disabled in OCMD reg */
348static int intel_overlay_off(struct intel_overlay *overlay)
349{
350 u32 flip_addr = overlay->flip_addr;
351 struct drm_device *dev = overlay->dev;
02e792fb 352 int ret;
02e792fb
DV		 353
354 BUG_ON(!overlay->active);
355
356 /* According to intel docs the overlay hw may hang (when switching
357 * off) without loading the filter coeffs. It is however unclear whether
358 * this applies to the disabling of the overlay or to the switching off
359 * of the hw. Do it in both cases */
360 flip_addr |= OFC_UPDATE;
361
362 /* wait for overlay to go idle */
4f8a567c 363 BEGIN_LP_RING(4);
02e792fb
DV		 364 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
365 OUT_RING(flip_addr);
722506f0
CW		 366 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
367 OUT_RING(MI_NOOP);
368 ADVANCE_LP_RING();
02e792fb 369
b6c028e0
CW		 370 ret = intel_overlay_do_wait_request(overlay, true,
371 SWITCH_OFF_STAGE_1);
372 if (ret)
02e792fb 373 return ret;
02e792fb
DV		 374
375 /* turn overlay off */
4f8a567c 376 BEGIN_LP_RING(4);
722506f0 377 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 378 OUT_RING(flip_addr);
722506f0
CW		 379 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
380 OUT_RING(MI_NOOP);
02e792fb
DV		 381 ADVANCE_LP_RING();
382
b6c028e0
CW		 383 return intel_overlay_do_wait_request(overlay, true,
384 SWITCH_OFF_STAGE_2);
02e792fb
DV		 385}
386
12ca45fe
DV		 387static void intel_overlay_off_tail(struct intel_overlay *overlay)
388{
389 struct drm_gem_object *obj;
390
391 /* never have the overlay hw on without showing a frame */
392 BUG_ON(!overlay->vid_bo);
a8089e84 393 obj = &overlay->vid_bo->base;
12ca45fe
DV		 394
395 i915_gem_object_unpin(obj);
396 drm_gem_object_unreference(obj);
397 overlay->vid_bo = NULL;
398
399 overlay->crtc->overlay = NULL;
400 overlay->crtc = NULL;
401 overlay->active = 0;
402}
403
03f77ea5
DV		 404/* recover from an interruption due to a signal
405 * We have to be careful not to repeat work forever an make forward progess. */
406int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
722506f0 407 bool interruptible)
03f77ea5
DV		 408{
409 struct drm_device *dev = overlay->dev;
03f77ea5 410 struct drm_gem_object *obj;
852835f3 411 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5
DV		 412 u32 flip_addr;
413 int ret;
03f77ea5
DV		 414
415 if (overlay->hw_wedged == HW_WEDGED)
416 return -EIO;
417
852835f3 418 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 419 interruptible, &dev_priv->render_ring);
b6c028e0 420 if (ret)
03f77ea5
DV		 421 return ret;
422
423 switch (overlay->hw_wedged) {
722506f0
CW		 424 case RELEASE_OLD_VID:
425 obj = &overlay->old_vid_bo->base;
426 i915_gem_object_unpin(obj);
427 drm_gem_object_unreference(obj);
428 overlay->old_vid_bo = NULL;
429 break;
b6c028e0 430
722506f0
CW		 431 case SWITCH_OFF_STAGE_1:
432 flip_addr = overlay->flip_addr;
433 flip_addr |= OFC_UPDATE;
03f77ea5 434
722506f0
CW		 435 BEGIN_LP_RING(4);
436 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
437 OUT_RING(flip_addr);
438 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
439 OUT_RING(MI_NOOP);
440 ADVANCE_LP_RING();
441
b6c028e0
CW		 442 ret = intel_overlay_do_wait_request(overlay, interruptible,
443 SWITCH_OFF_STAGE_2);
444 if (ret)
722506f0
CW		 445 return ret;
446
447 case SWITCH_OFF_STAGE_2:
448 intel_overlay_off_tail(overlay);
449 break;
450 default:
451 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
03f77ea5
DV		 452 }
453
454 overlay->hw_wedged = 0;
455 overlay->last_flip_req = 0;
456 return 0;
457}
458
5a5a0c64
DV		 459/* Wait for pending overlay flip and release old frame.
460 * Needs to be called before the overlay register are changed
8d74f656
CW		 461 * via intel_overlay_(un)map_regs
462 */
02e792fb
DV		 463static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
464{
465 int ret;
466 struct drm_gem_object *obj;
467
03f77ea5
DV		 468 /* only wait if there is actually an old frame to release to
469 * guarantee forward progress */
470 if (!overlay->old_vid_bo)
471 return 0;
472
02e792fb
DV		 473 ret = intel_overlay_wait_flip(overlay);
474 if (ret != 0)
475 return ret;
476
a8089e84 477 obj = &overlay->old_vid_bo->base;
02e792fb
DV		 478 i915_gem_object_unpin(obj);
479 drm_gem_object_unreference(obj);
480 overlay->old_vid_bo = NULL;
481
482 return 0;
483}
484
485struct put_image_params {
486 int format;
487 short dst_x;
488 short dst_y;
489 short dst_w;
490 short dst_h;
491 short src_w;
492 short src_scan_h;
493 short src_scan_w;
494 short src_h;
495 short stride_Y;
496 short stride_UV;
497 int offset_Y;
498 int offset_U;
499 int offset_V;
500};
501
502static int packed_depth_bytes(u32 format)
503{
504 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 505 case I915_OVERLAY_YUV422:
506 return 4;
507 case I915_OVERLAY_YUV411:
508 /* return 6; not implemented */
509 default:
510 return -EINVAL;
02e792fb
DV		 511 }
512}
513
514static int packed_width_bytes(u32 format, short width)
515{
516 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 517 case I915_OVERLAY_YUV422:
518 return width << 1;
519 default:
520 return -EINVAL;
02e792fb
DV		 521 }
522}
523
524static int uv_hsubsampling(u32 format)
525{
526 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 527 case I915_OVERLAY_YUV422:
528 case I915_OVERLAY_YUV420:
529 return 2;
530 case I915_OVERLAY_YUV411:
531 case I915_OVERLAY_YUV410:
532 return 4;
533 default:
534 return -EINVAL;
02e792fb
DV		 535 }
536}
537
538static int uv_vsubsampling(u32 format)
539{
540 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 541 case I915_OVERLAY_YUV420:
542 case I915_OVERLAY_YUV410:
543 return 2;
544 case I915_OVERLAY_YUV422:
545 case I915_OVERLAY_YUV411:
546 return 1;
547 default:
548 return -EINVAL;
02e792fb
DV		 549 }
550}
551
552static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
553{
554 u32 mask, shift, ret;
555 if (IS_I9XX(dev)) {
556 mask = 0x3f;
557 shift = 6;
558 } else {
559 mask = 0x1f;
560 shift = 5;
561 }
562 ret = ((offset + width + mask) >> shift) - (offset >> shift);
563 if (IS_I9XX(dev))
564 ret <<= 1;
565 ret -=1;
566 return ret << 2;
567}
568
569static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
570 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
571 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
572 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
573 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
574 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
575 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
576 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
577 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
578 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
579 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
580 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
581 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
582 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
583 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
584 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
585 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 586 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
587};
588
02e792fb
DV		 589static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
590 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
591 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
592 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
593 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
594 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
595 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
596 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
597 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 598 0x3000, 0x0800, 0x3000
599};
02e792fb
DV		 600
601static void update_polyphase_filter(struct overlay_registers *regs)
602{
603 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
604 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
605}
606
607static bool update_scaling_factors(struct intel_overlay *overlay,
608 struct overlay_registers *regs,
609 struct put_image_params *params)
610{
611 /* fixed point with a 12 bit shift */
612 u32 xscale, yscale, xscale_UV, yscale_UV;
613#define FP_SHIFT 12
614#define FRACT_MASK 0xfff
615 bool scale_changed = false;
616 int uv_hscale = uv_hsubsampling(params->format);
617 int uv_vscale = uv_vsubsampling(params->format);
618
619 if (params->dst_w > 1)
620 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
621 /(params->dst_w);
622 else
623 xscale = 1 << FP_SHIFT;
624
625 if (params->dst_h > 1)
626 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
627 /(params->dst_h);
628 else
629 yscale = 1 << FP_SHIFT;
630
631 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 632 xscale_UV = xscale/uv_hscale;
633 yscale_UV = yscale/uv_vscale;
634 /* make the Y scale to UV scale ratio an exact multiply */
635 xscale = xscale_UV * uv_hscale;
636 yscale = yscale_UV * uv_vscale;
02e792fb 637 /*} else {
722506f0
CW		 638 xscale_UV = 0;
639 yscale_UV = 0;
640 }*/
02e792fb
DV		 641
642 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
643 scale_changed = true;
644 overlay->old_xscale = xscale;
645 overlay->old_yscale = yscale;
646
722506f0
CW		 647 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
648 ((xscale >> FP_SHIFT) << 16) |
649 ((xscale & FRACT_MASK) << 3));
650
651 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
652 ((xscale_UV >> FP_SHIFT) << 16) |
653 ((xscale_UV & FRACT_MASK) << 3));
654
655 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
656 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 657
658 if (scale_changed)
659 update_polyphase_filter(regs);
660
661 return scale_changed;
662}
663
664static void update_colorkey(struct intel_overlay *overlay,
665 struct overlay_registers *regs)
666{
667 u32 key = overlay->color_key;
6ba3ddd9 668
02e792fb 669 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 670 case 8:
671 regs->DCLRKV = 0;
672 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 673 break;
674
722506f0
CW		 675 case 16:
676 if (overlay->crtc->base.fb->depth == 15) {
677 regs->DCLRKV = RGB15_TO_COLORKEY(key);
678 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
679 } else {
680 regs->DCLRKV = RGB16_TO_COLORKEY(key);
681 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
682 }
6ba3ddd9
CW		 683 break;
684
722506f0
CW		 685 case 24:
686 case 32:
687 regs->DCLRKV = key;
688 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 689 break;
02e792fb
DV		 690 }
691}
692
693static u32 overlay_cmd_reg(struct put_image_params *params)
694{
695 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
696
697 if (params->format & I915_OVERLAY_YUV_PLANAR) {
698 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 699 case I915_OVERLAY_YUV422:
700 cmd |= OCMD_YUV_422_PLANAR;
701 break;
702 case I915_OVERLAY_YUV420:
703 cmd |= OCMD_YUV_420_PLANAR;
704 break;
705 case I915_OVERLAY_YUV411:
706 case I915_OVERLAY_YUV410:
707 cmd |= OCMD_YUV_410_PLANAR;
708 break;
02e792fb
DV		 709 }
710 } else { /* YUV packed */
711 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 712 case I915_OVERLAY_YUV422:
713 cmd |= OCMD_YUV_422_PACKED;
714 break;
715 case I915_OVERLAY_YUV411:
716 cmd |= OCMD_YUV_411_PACKED;
717 break;
02e792fb
DV		 718 }
719
720 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 721 case I915_OVERLAY_NO_SWAP:
722 break;
723 case I915_OVERLAY_UV_SWAP:
724 cmd |= OCMD_UV_SWAP;
725 break;
726 case I915_OVERLAY_Y_SWAP:
727 cmd |= OCMD_Y_SWAP;
728 break;
729 case I915_OVERLAY_Y_AND_UV_SWAP:
730 cmd |= OCMD_Y_AND_UV_SWAP;
731 break;
02e792fb
DV		 732 }
733 }
734
735 return cmd;
736}
737
738int intel_overlay_do_put_image(struct intel_overlay *overlay,
739 struct drm_gem_object *new_bo,
740 struct put_image_params *params)
741{
742 int ret, tmp_width;
743 struct overlay_registers *regs;
744 bool scale_changed = false;
23010e43 745 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 746 struct drm_device *dev = overlay->dev;
747
748 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
749 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
750 BUG_ON(!overlay);
751
02e792fb
DV		 752 ret = intel_overlay_release_old_vid(overlay);
753 if (ret != 0)
754 return ret;
755
756 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
757 if (ret != 0)
758 return ret;
759
760 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
761 if (ret != 0)
762 goto out_unpin;
763
764 if (!overlay->active) {
8d74f656 765 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 766 if (!regs) {
767 ret = -ENOMEM;
768 goto out_unpin;
769 }
770 regs->OCONFIG = OCONF_CC_OUT_8BIT;
771 if (IS_I965GM(overlay->dev))
772 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
773 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
774 OCONF_PIPE_A : OCONF_PIPE_B;
8d74f656 775 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 776
777 ret = intel_overlay_on(overlay);
778 if (ret != 0)
779 goto out_unpin;
780 }
781
8d74f656 782 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 783 if (!regs) {
784 ret = -ENOMEM;
785 goto out_unpin;
786 }
787
788 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
789 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
790
791 if (params->format & I915_OVERLAY_YUV_PACKED)
792 tmp_width = packed_width_bytes(params->format, params->src_w);
793 else
794 tmp_width = params->src_w;
795
796 regs->SWIDTH = params->src_w;
797 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 798 params->offset_Y, tmp_width);
02e792fb
DV		 799 regs->SHEIGHT = params->src_h;
800 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
801 regs->OSTRIDE = params->stride_Y;
802
803 if (params->format & I915_OVERLAY_YUV_PLANAR) {
804 int uv_hscale = uv_hsubsampling(params->format);
805 int uv_vscale = uv_vsubsampling(params->format);
806 u32 tmp_U, tmp_V;
807 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
808 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 809 params->src_w/uv_hscale);
02e792fb 810 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 811 params->src_w/uv_hscale);
02e792fb
DV		 812 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
813 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
814 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
815 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
816 regs->OSTRIDE |= params->stride_UV << 16;
817 }
818
819 scale_changed = update_scaling_factors(overlay, regs, params);
820
821 update_colorkey(overlay, regs);
822
823 regs->OCMD = overlay_cmd_reg(params);
824
8d74f656 825 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 826
827 intel_overlay_continue(overlay, scale_changed);
828
829 overlay->old_vid_bo = overlay->vid_bo;
23010e43 830 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 831
832 return 0;
833
834out_unpin:
835 i915_gem_object_unpin(new_bo);
836 return ret;
837}
838
839int intel_overlay_switch_off(struct intel_overlay *overlay)
840{
841 int ret;
842 struct overlay_registers *regs;
02e792fb
DV		 843 struct drm_device *dev = overlay->dev;
844
845 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
846 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
847
9bedb974
DV		 848 if (overlay->hw_wedged) {
849 ret = intel_overlay_recover_from_interrupt(overlay, 1);
850 if (ret != 0)
851 return ret;
852 }
853
02e792fb
DV		 854 if (!overlay->active)
855 return 0;
856
02e792fb
DV		 857 ret = intel_overlay_release_old_vid(overlay);
858 if (ret != 0)
859 return ret;
860
8d74f656 861 regs = intel_overlay_map_regs(overlay);
02e792fb 862 regs->OCMD = 0;
8d74f656 863 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 864
865 ret = intel_overlay_off(overlay);
03f77ea5
DV		 866 if (ret != 0)
867 return ret;
868
12ca45fe 869 intel_overlay_off_tail(overlay);
02e792fb
DV		 870
871 return 0;
872}
873
874static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
875 struct intel_crtc *crtc)
876{
722506f0 877 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb
DV		 878 u32 pipeconf;
879 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
880
881 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
882 return -EINVAL;
883
884 pipeconf = I915_READ(pipeconf_reg);
885
886 /* can't use the overlay with double wide pipe */
887 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
888 return -EINVAL;
889
890 return 0;
891}
892
893static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
894{
895 struct drm_device *dev = overlay->dev;
722506f0 896 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 897 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 898 u32 ratio;
02e792fb
DV		 899
900 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 901 * line with the intel documentation for the i965
902 */
903 if (!IS_I965G(dev)) {
904 if (pfit_control & VERT_AUTO_SCALE)
905 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 906 else
446d2183
CW		 907 ratio = I915_READ(PFIT_PGM_RATIOS);
908 ratio >>= PFIT_VERT_SCALE_SHIFT;
909 } else { /* on i965 use the PGM reg to read out the autoscaler values */
910 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
02e792fb
DV		 911 }
912
913 overlay->pfit_vscale_ratio = ratio;
914}
915
916static int check_overlay_dst(struct intel_overlay *overlay,
917 struct drm_intel_overlay_put_image *rec)
918{
919 struct drm_display_mode *mode = &overlay->crtc->base.mode;
920
722506f0
CW		 921 if (rec->dst_x < mode->crtc_hdisplay &&
922 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
923 rec->dst_y < mode->crtc_vdisplay &&
924 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 925 return 0;
926 else
927 return -EINVAL;
928}
929
930static int check_overlay_scaling(struct put_image_params *rec)
931{
932 u32 tmp;
933
934 /* downscaling limit is 8.0 */
935 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
936 if (tmp > 7)
937 return -EINVAL;
938 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
939 if (tmp > 7)
940 return -EINVAL;
941
942 return 0;
943}
944
945static int check_overlay_src(struct drm_device *dev,
946 struct drm_intel_overlay_put_image *rec,
947 struct drm_gem_object *new_bo)
948{
02e792fb
DV		 949 int uv_hscale = uv_hsubsampling(rec->flags);
950 int uv_vscale = uv_vsubsampling(rec->flags);
9f7c3f44 951 u32 stride_mask, depth, tmp;
02e792fb
DV		 952
953 /* check src dimensions */
954 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 955 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 956 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 957 return -EINVAL;
958 } else {
722506f0 959 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 960 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 961 return -EINVAL;
962 }
9f7c3f44 963
02e792fb 964 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 965 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 966 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 967 return -EINVAL;
968
a1efd14a 969 /* check alignment constraints */
02e792fb 970 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 971 case I915_OVERLAY_RGB:
972 /* not implemented */
973 return -EINVAL;
9f7c3f44 974
722506f0 975 case I915_OVERLAY_YUV_PACKED:
722506f0 976 if (uv_vscale != 1)
02e792fb 977 return -EINVAL;
9f7c3f44
CW		 978
979 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 980 if (depth < 0)
981 return depth;
9f7c3f44 982
722506f0
CW		 983 /* ignore UV planes */
984 rec->stride_UV = 0;
985 rec->offset_U = 0;
986 rec->offset_V = 0;
987 /* check pixel alignment */
988 if (rec->offset_Y % depth)
989 return -EINVAL;
990 break;
9f7c3f44 991
722506f0
CW		 992 case I915_OVERLAY_YUV_PLANAR:
993 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 994 return -EINVAL;
722506f0
CW		 995 /* no offset restrictions for planar formats */
996 break;
9f7c3f44 997
722506f0
CW		 998 default:
999 return -EINVAL;
02e792fb
DV		 1000 }
1001
1002 if (rec->src_width % uv_hscale)
1003 return -EINVAL;
1004
1005 /* stride checking */
a1efd14a
CW		 1006 if (IS_I830(dev) || IS_845G(dev))
1007 stride_mask = 255;
1008 else
1009 stride_mask = 63;
02e792fb
DV		 1010
1011 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1012 return -EINVAL;
1013 if (IS_I965G(dev) && rec->stride_Y < 512)
1014 return -EINVAL;
1015
1016 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 1017 4096 : 8192;
1018 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 1019 return -EINVAL;
1020
1021 /* check buffer dimensions */
1022 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1023 case I915_OVERLAY_RGB:
1024 case I915_OVERLAY_YUV_PACKED:
1025 /* always 4 Y values per depth pixels */
1026 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1027 return -EINVAL;
1028
1029 tmp = rec->stride_Y*rec->src_height;
1030 if (rec->offset_Y + tmp > new_bo->size)
1031 return -EINVAL;
1032 break;
1033
1034 case I915_OVERLAY_YUV_PLANAR:
1035 if (rec->src_width > rec->stride_Y)
1036 return -EINVAL;
1037 if (rec->src_width/uv_hscale > rec->stride_UV)
1038 return -EINVAL;
1039
9f7c3f44 1040 tmp = rec->stride_Y * rec->src_height;
722506f0
CW		 1041 if (rec->offset_Y + tmp > new_bo->size)
1042 return -EINVAL;
9f7c3f44
CW		 1043
1044 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
722506f0
CW		 1045 if (rec->offset_U + tmp > new_bo->size ||
1046 rec->offset_V + tmp > new_bo->size)
1047 return -EINVAL;
1048 break;
02e792fb
DV		 1049 }
1050
1051 return 0;
1052}
1053
1054int intel_overlay_put_image(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv)
1056{
1057 struct drm_intel_overlay_put_image *put_image_rec = data;
1058 drm_i915_private_t *dev_priv = dev->dev_private;
1059 struct intel_overlay *overlay;
1060 struct drm_mode_object *drmmode_obj;
1061 struct intel_crtc *crtc;
1062 struct drm_gem_object *new_bo;
1063 struct put_image_params *params;
1064 int ret;
1065
1066 if (!dev_priv) {
1067 DRM_ERROR("called with no initialization\n");
1068 return -EINVAL;
1069 }
1070
1071 overlay = dev_priv->overlay;
1072 if (!overlay) {
1073 DRM_DEBUG("userspace bug: no overlay\n");
1074 return -ENODEV;
1075 }
1076
1077 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1078 mutex_lock(&dev->mode_config.mutex);
1079 mutex_lock(&dev->struct_mutex);
1080
1081 ret = intel_overlay_switch_off(overlay);
1082
1083 mutex_unlock(&dev->struct_mutex);
1084 mutex_unlock(&dev->mode_config.mutex);
1085
1086 return ret;
1087 }
1088
1089 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1090 if (!params)
1091 return -ENOMEM;
1092
1093 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1094 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1095 if (!drmmode_obj) {
1096 ret = -ENOENT;
1097 goto out_free;
1098 }
02e792fb
DV		 1099 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1100
1101 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1102 put_image_rec->bo_handle);
915a428e
DC		 1103 if (!new_bo) {
1104 ret = -ENOENT;
1105 goto out_free;
1106 }
02e792fb
DV		 1107
1108 mutex_lock(&dev->mode_config.mutex);
1109 mutex_lock(&dev->struct_mutex);
1110
03f77ea5
DV		 1111 if (overlay->hw_wedged) {
1112 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1113 if (ret != 0)
1114 goto out_unlock;
1115 }
1116
02e792fb
DV		 1117 if (overlay->crtc != crtc) {
1118 struct drm_display_mode *mode = &crtc->base.mode;
1119 ret = intel_overlay_switch_off(overlay);
1120 if (ret != 0)
1121 goto out_unlock;
1122
1123 ret = check_overlay_possible_on_crtc(overlay, crtc);
1124 if (ret != 0)
1125 goto out_unlock;
1126
1127 overlay->crtc = crtc;
1128 crtc->overlay = overlay;
1129
1130 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1131 /* and line to wide, i.e. one-line-mode */
1132 && mode->hdisplay > 1024) {
1133 overlay->pfit_active = 1;
1134 update_pfit_vscale_ratio(overlay);
1135 } else
1136 overlay->pfit_active = 0;
1137 }
1138
1139 ret = check_overlay_dst(overlay, put_image_rec);
1140 if (ret != 0)
1141 goto out_unlock;
1142
1143 if (overlay->pfit_active) {
1144 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1145 overlay->pfit_vscale_ratio);
02e792fb
DV		 1146 /* shifting right rounds downwards, so add 1 */
1147 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1148 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1149 } else {
1150 params->dst_y = put_image_rec->dst_y;
1151 params->dst_h = put_image_rec->dst_height;
1152 }
1153 params->dst_x = put_image_rec->dst_x;
1154 params->dst_w = put_image_rec->dst_width;
1155
1156 params->src_w = put_image_rec->src_width;
1157 params->src_h = put_image_rec->src_height;
1158 params->src_scan_w = put_image_rec->src_scan_width;
1159 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1160 if (params->src_scan_h > params->src_h ||
1161 params->src_scan_w > params->src_w) {
02e792fb
DV		 1162 ret = -EINVAL;
1163 goto out_unlock;
1164 }
1165
1166 ret = check_overlay_src(dev, put_image_rec, new_bo);
1167 if (ret != 0)
1168 goto out_unlock;
1169 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1170 params->stride_Y = put_image_rec->stride_Y;
1171 params->stride_UV = put_image_rec->stride_UV;
1172 params->offset_Y = put_image_rec->offset_Y;
1173 params->offset_U = put_image_rec->offset_U;
1174 params->offset_V = put_image_rec->offset_V;
1175
1176 /* Check scaling after src size to prevent a divide-by-zero. */
1177 ret = check_overlay_scaling(params);
1178 if (ret != 0)
1179 goto out_unlock;
1180
1181 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1182 if (ret != 0)
1183 goto out_unlock;
1184
1185 mutex_unlock(&dev->struct_mutex);
1186 mutex_unlock(&dev->mode_config.mutex);
1187
1188 kfree(params);
1189
1190 return 0;
1191
1192out_unlock:
1193 mutex_unlock(&dev->struct_mutex);
1194 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1195 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1196out_free:
02e792fb
DV		 1197 kfree(params);
1198
1199 return ret;
1200}
1201
1202static void update_reg_attrs(struct intel_overlay *overlay,
1203 struct overlay_registers *regs)
1204{
1205 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1206 regs->OCLRC1 = overlay->saturation;
1207}
1208
1209static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1210{
1211 int i;
1212
1213 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1214 return false;
1215
1216 for (i = 0; i < 3; i++) {
722506f0 1217 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1218 return false;
1219 }
1220
1221 return true;
1222}
1223
1224static bool check_gamma5_errata(u32 gamma5)
1225{
1226 int i;
1227
1228 for (i = 0; i < 3; i++) {
1229 if (((gamma5 >> i*8) & 0xff) == 0x80)
1230 return false;
1231 }
1232
1233 return true;
1234}
1235
1236static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1237{
722506f0
CW		 1238 if (!check_gamma_bounds(0, attrs->gamma0) ||
1239 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1240 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1241 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1242 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1243 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1244 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1245 return -EINVAL;
722506f0 1246
02e792fb
DV		 1247 if (!check_gamma5_errata(attrs->gamma5))
1248 return -EINVAL;
722506f0 1249
02e792fb
DV		 1250 return 0;
1251}
1252
1253int intel_overlay_attrs(struct drm_device *dev, void *data,
1254 struct drm_file *file_priv)
1255{
1256 struct drm_intel_overlay_attrs *attrs = data;
1257 drm_i915_private_t *dev_priv = dev->dev_private;
1258 struct intel_overlay *overlay;
1259 struct overlay_registers *regs;
1260 int ret;
1261
1262 if (!dev_priv) {
1263 DRM_ERROR("called with no initialization\n");
1264 return -EINVAL;
1265 }
1266
1267 overlay = dev_priv->overlay;
1268 if (!overlay) {
1269 DRM_DEBUG("userspace bug: no overlay\n");
1270 return -ENODEV;
1271 }
1272
1273 mutex_lock(&dev->mode_config.mutex);
1274 mutex_lock(&dev->struct_mutex);
1275
60fc332c 1276 ret = -EINVAL;
02e792fb 1277 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1278 attrs->color_key = overlay->color_key;
02e792fb 1279 attrs->brightness = overlay->brightness;
60fc332c 1280 attrs->contrast = overlay->contrast;
02e792fb
DV		 1281 attrs->saturation = overlay->saturation;
1282
1283 if (IS_I9XX(dev)) {
1284 attrs->gamma0 = I915_READ(OGAMC0);
1285 attrs->gamma1 = I915_READ(OGAMC1);
1286 attrs->gamma2 = I915_READ(OGAMC2);
1287 attrs->gamma3 = I915_READ(OGAMC3);
1288 attrs->gamma4 = I915_READ(OGAMC4);
1289 attrs->gamma5 = I915_READ(OGAMC5);
1290 }
02e792fb 1291 } else {
60fc332c 1292 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1293 goto out_unlock;
60fc332c 1294 if (attrs->contrast > 255)
02e792fb 1295 goto out_unlock;
60fc332c 1296 if (attrs->saturation > 1023)
02e792fb 1297 goto out_unlock;
60fc332c
CW		 1298
1299 overlay->color_key = attrs->color_key;
1300 overlay->brightness = attrs->brightness;
1301 overlay->contrast = attrs->contrast;
1302 overlay->saturation = attrs->saturation;
02e792fb 1303
8d74f656 1304 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1305 if (!regs) {
1306 ret = -ENOMEM;
1307 goto out_unlock;
1308 }
1309
1310 update_reg_attrs(overlay, regs);
1311
8d74f656 1312 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 1313
1314 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
60fc332c 1315 if (!IS_I9XX(dev))
02e792fb 1316 goto out_unlock;
02e792fb
DV		 1317
1318 if (overlay->active) {
1319 ret = -EBUSY;
1320 goto out_unlock;
1321 }
1322
1323 ret = check_gamma(attrs);
60fc332c 1324 if (ret)
02e792fb
DV		 1325 goto out_unlock;
1326
1327 I915_WRITE(OGAMC0, attrs->gamma0);
1328 I915_WRITE(OGAMC1, attrs->gamma1);
1329 I915_WRITE(OGAMC2, attrs->gamma2);
1330 I915_WRITE(OGAMC3, attrs->gamma3);
1331 I915_WRITE(OGAMC4, attrs->gamma4);
1332 I915_WRITE(OGAMC5, attrs->gamma5);
1333 }
02e792fb
DV		 1334 }
1335
60fc332c 1336 ret = 0;
02e792fb
DV		 1337out_unlock:
1338 mutex_unlock(&dev->struct_mutex);
1339 mutex_unlock(&dev->mode_config.mutex);
1340
1341 return ret;
1342}
1343
1344void intel_setup_overlay(struct drm_device *dev)
1345{
1346 drm_i915_private_t *dev_priv = dev->dev_private;
1347 struct intel_overlay *overlay;
1348 struct drm_gem_object *reg_bo;
1349 struct overlay_registers *regs;
1350 int ret;
1351
31578148 1352 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1353 return;
1354
1355 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1356 if (!overlay)
1357 return;
1358 overlay->dev = dev;
1359
ac52bc56 1360 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1361 if (!reg_bo)
1362 goto out_free;
23010e43 1363 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1364
31578148
CW		 1365 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1366 ret = i915_gem_attach_phys_object(dev, reg_bo,
1367 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1368 PAGE_SIZE);
31578148
CW		 1369 if (ret) {
1370 DRM_ERROR("failed to attach phys overlay regs\n");
1371 goto out_free_bo;
1372 }
1373 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1374 } else {
02e792fb
DV		 1375 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1376 if (ret) {
1377 DRM_ERROR("failed to pin overlay register bo\n");
1378 goto out_free_bo;
1379 }
1380 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1381
1382 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1383 if (ret) {
1384 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1385 goto out_unpin_bo;
1386 }
02e792fb
DV		 1387 }
1388
1389 /* init all values */
1390 overlay->color_key = 0x0101fe;
1391 overlay->brightness = -19;
1392 overlay->contrast = 75;
1393 overlay->saturation = 146;
1394
8d74f656 1395 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1396 if (!regs)
1397 goto out_free_bo;
1398
1399 memset(regs, 0, sizeof(struct overlay_registers));
1400 update_polyphase_filter(regs);
1401
1402 update_reg_attrs(overlay, regs);
1403
8d74f656 1404 intel_overlay_unmap_regs(overlay);
02e792fb
DV		 1405
1406 dev_priv->overlay = overlay;
1407 DRM_INFO("initialized overlay support\n");
1408 return;
1409
0ddc1289
CW		 1410out_unpin_bo:
1411 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1412out_free_bo:
1413 drm_gem_object_unreference(reg_bo);
1414out_free:
1415 kfree(overlay);
1416 return;
1417}
1418
1419void intel_cleanup_overlay(struct drm_device *dev)
1420{
722506f0 1421 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1422
62cf4e6f
CW		 1423 if (!dev_priv->overlay)
1424 return;
02e792fb 1425
62cf4e6f
CW		 1426 /* The bo's should be free'd by the generic code already.
1427 * Furthermore modesetting teardown happens beforehand so the
1428 * hardware should be off already */
1429 BUG_ON(dev_priv->overlay->active);
1430
1431 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1432 kfree(dev_priv->overlay);
02e792fb 1433}
6ef3d427
CW		 1434
1435struct intel_overlay_error_state {
1436 struct overlay_registers regs;
1437 unsigned long base;
1438 u32 dovsta;
1439 u32 isr;
1440};
1441
1442struct intel_overlay_error_state *
1443intel_overlay_capture_error_state(struct drm_device *dev)
1444{
1445 drm_i915_private_t *dev_priv = dev->dev_private;
1446 struct intel_overlay *overlay = dev_priv->overlay;
1447 struct intel_overlay_error_state *error;
1448 struct overlay_registers __iomem *regs;
1449
1450 if (!overlay || !overlay->active)
1451 return NULL;
1452
1453 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1454 if (error == NULL)
1455 return NULL;
1456
1457 error->dovsta = I915_READ(DOVSTA);
1458 error->isr = I915_READ(ISR);
31578148 1459 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1460 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1461 else
1462 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427 1463
8d74f656 1464 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1465 if (!regs)
1466 goto err;
1467
1468 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
8d74f656 1469 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1470
1471 return error;
1472
1473err:
1474 kfree(error);
1475 return NULL;
1476}
1477
1478void
1479intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1480{
1481 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1482 error->dovsta, error->isr);
1483 seq_printf(m, " Register file at 0x%08lx:\n",
1484 error->base);
1485
1486#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1487 P(OBUF_0Y);
1488 P(OBUF_1Y);
1489 P(OBUF_0U);
1490 P(OBUF_0V);
1491 P(OBUF_1U);
1492 P(OBUF_1V);
1493 P(OSTRIDE);
1494 P(YRGB_VPH);
1495 P(UV_VPH);
1496 P(HORZ_PH);
1497 P(INIT_PHS);
1498 P(DWINPOS);
1499 P(DWINSZ);
1500 P(SWIDTH);
1501 P(SWIDTHSW);
1502 P(SHEIGHT);
1503 P(YRGBSCALE);
1504 P(UVSCALE);
1505 P(OCLRC0);
1506 P(OCLRC1);
1507 P(DCLRKV);
1508 P(DCLRKM);
1509 P(SCLRKVH);
1510 P(SCLRKVL);
1511 P(SCLRKEN);
1512 P(OCONFIG);
1513 P(OCMD);
1514 P(OSTART_0Y);
1515 P(OSTART_1Y);
1516 P(OSTART_0U);
1517 P(OSTART_0V);
1518 P(OSTART_1U);
1519 P(OSTART_1V);
1520 P(OTILEOFF_0Y);
1521 P(OTILEOFF_1Y);
1522 P(OTILEOFF_0U);
1523 P(OTILEOFF_0V);
1524 P(OTILEOFF_1U);
1525 P(OTILEOFF_1V);
1526 P(FASTHSCALE);
1527 P(UVSCALEV);
1528#undef P
1529}
Linux kernel - Deliverables
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