Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW
1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
7bd90909 33#include <linux/moduleparam.h>
1d8e1c75
CW
34#include "intel_drv.h"
35
ba3820ad
TI
36#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
37
1d8e1c75 38void
4c6df4b4 39intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW
40 struct drm_display_mode *adjusted_mode)
41{
4c6df4b4 42 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID
43
44 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW
45}
46
47/* adjusted_mode has been preset to be the panel's fixed mode */
48void
b074cec8
JB
49intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
50 struct intel_crtc_config *pipe_config,
51 int fitting_mode)
1d8e1c75 52{
b074cec8 53 struct drm_display_mode *mode, *adjusted_mode;
1d8e1c75
CW
54 int x, y, width, height;
55
b074cec8
JB
56 mode = &pipe_config->requested_mode;
57 adjusted_mode = &pipe_config->adjusted_mode;
58
1d8e1c75
CW
59 x = y = width = height = 0;
60
61 /* Native modes don't need fitting */
62 if (adjusted_mode->hdisplay == mode->hdisplay &&
63 adjusted_mode->vdisplay == mode->vdisplay)
64 goto done;
65
66 switch (fitting_mode) {
67 case DRM_MODE_SCALE_CENTER:
68 width = mode->hdisplay;
69 height = mode->vdisplay;
70 x = (adjusted_mode->hdisplay - width + 1)/2;
71 y = (adjusted_mode->vdisplay - height + 1)/2;
72 break;
73
74 case DRM_MODE_SCALE_ASPECT:
75 /* Scale but preserve the aspect ratio */
76 {
77 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
78 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
79 if (scaled_width > scaled_height) { /* pillar */
80 width = scaled_height / mode->vdisplay;
302983e9 81 if (width & 1)
0206e353 82 width++;
1d8e1c75
CW
83 x = (adjusted_mode->hdisplay - width + 1) / 2;
84 y = 0;
85 height = adjusted_mode->vdisplay;
86 } else if (scaled_width < scaled_height) { /* letter */
87 height = scaled_width / mode->hdisplay;
302983e9
AJ
88 if (height & 1)
89 height++;
1d8e1c75
CW
90 y = (adjusted_mode->vdisplay - height + 1) / 2;
91 x = 0;
92 width = adjusted_mode->hdisplay;
93 } else {
94 x = y = 0;
95 width = adjusted_mode->hdisplay;
96 height = adjusted_mode->vdisplay;
97 }
98 }
99 break;
100
1d8e1c75
CW
101 case DRM_MODE_SCALE_FULLSCREEN:
102 x = y = 0;
103 width = adjusted_mode->hdisplay;
104 height = adjusted_mode->vdisplay;
105 break;
ab3e67f4
JB
106
107 default:
108 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
109 return;
1d8e1c75
CW
110 }
111
112done:
b074cec8
JB
113 pipe_config->pch_pfit.pos = (x << 16) | y;
114 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 115 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 116}
a9573556 117
2dd24552
JB
118static void
119centre_horizontally(struct drm_display_mode *mode,
120 int width)
121{
122 u32 border, sync_pos, blank_width, sync_width;
123
124 /* keep the hsync and hblank widths constant */
125 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
126 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
127 sync_pos = (blank_width - sync_width + 1) / 2;
128
129 border = (mode->hdisplay - width + 1) / 2;
130 border += border & 1; /* make the border even */
131
132 mode->crtc_hdisplay = width;
133 mode->crtc_hblank_start = width + border;
134 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
135
136 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
137 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
138}
139
140static void
141centre_vertically(struct drm_display_mode *mode,
142 int height)
143{
144 u32 border, sync_pos, blank_width, sync_width;
145
146 /* keep the vsync and vblank widths constant */
147 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
148 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
149 sync_pos = (blank_width - sync_width + 1) / 2;
150
151 border = (mode->vdisplay - height + 1) / 2;
152
153 mode->crtc_vdisplay = height;
154 mode->crtc_vblank_start = height + border;
155 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
156
157 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
158 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
159}
160
161static inline u32 panel_fitter_scaling(u32 source, u32 target)
162{
163 /*
164 * Floating point operation is not supported. So the FACTOR
165 * is defined, which can avoid the floating point computation
166 * when calculating the panel ratio.
167 */
168#define ACCURACY 12
169#define FACTOR (1 << ACCURACY)
170 u32 ratio = source * FACTOR / target;
171 return (FACTOR * ratio + FACTOR/2) / FACTOR;
172}
173
174void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
175 struct intel_crtc_config *pipe_config,
176 int fitting_mode)
177{
178 struct drm_device *dev = intel_crtc->base.dev;
2dd24552
JB
179 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
180 struct drm_display_mode *mode, *adjusted_mode;
181
182 mode = &pipe_config->requested_mode;
183 adjusted_mode = &pipe_config->adjusted_mode;
184
185 /* Native modes don't need fitting */
186 if (adjusted_mode->hdisplay == mode->hdisplay &&
187 adjusted_mode->vdisplay == mode->vdisplay)
188 goto out;
189
190 switch (fitting_mode) {
191 case DRM_MODE_SCALE_CENTER:
192 /*
193 * For centered modes, we have to calculate border widths &
194 * heights and modify the values programmed into the CRTC.
195 */
196 centre_horizontally(adjusted_mode, mode->hdisplay);
197 centre_vertically(adjusted_mode, mode->vdisplay);
198 border = LVDS_BORDER_ENABLE;
199 break;
200 case DRM_MODE_SCALE_ASPECT:
201 /* Scale but preserve the aspect ratio */
202 if (INTEL_INFO(dev)->gen >= 4) {
203 u32 scaled_width = adjusted_mode->hdisplay *
204 mode->vdisplay;
205 u32 scaled_height = mode->hdisplay *
206 adjusted_mode->vdisplay;
207
208 /* 965+ is easy, it does everything in hw */
209 if (scaled_width > scaled_height)
210 pfit_control |= PFIT_ENABLE |
211 PFIT_SCALING_PILLAR;
212 else if (scaled_width < scaled_height)
213 pfit_control |= PFIT_ENABLE |
214 PFIT_SCALING_LETTER;
215 else if (adjusted_mode->hdisplay != mode->hdisplay)
216 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
217 } else {
218 u32 scaled_width = adjusted_mode->hdisplay *
219 mode->vdisplay;
220 u32 scaled_height = mode->hdisplay *
221 adjusted_mode->vdisplay;
222 /*
223 * For earlier chips we have to calculate the scaling
224 * ratio by hand and program it into the
225 * PFIT_PGM_RATIO register
226 */
227 if (scaled_width > scaled_height) { /* pillar */
228 centre_horizontally(adjusted_mode,
229 scaled_height /
230 mode->vdisplay);
231
232 border = LVDS_BORDER_ENABLE;
233 if (mode->vdisplay != adjusted_mode->vdisplay) {
234 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
235 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
236 bits << PFIT_VERT_SCALE_SHIFT);
237 pfit_control |= (PFIT_ENABLE |
238 VERT_INTERP_BILINEAR |
239 HORIZ_INTERP_BILINEAR);
240 }
241 } else if (scaled_width < scaled_height) { /* letter */
242 centre_vertically(adjusted_mode,
243 scaled_width /
244 mode->hdisplay);
245
246 border = LVDS_BORDER_ENABLE;
247 if (mode->hdisplay != adjusted_mode->hdisplay) {
248 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
249 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
250 bits << PFIT_VERT_SCALE_SHIFT);
251 pfit_control |= (PFIT_ENABLE |
252 VERT_INTERP_BILINEAR |
253 HORIZ_INTERP_BILINEAR);
254 }
255 } else {
256 /* Aspects match, Let hw scale both directions */
257 pfit_control |= (PFIT_ENABLE |
258 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
259 VERT_INTERP_BILINEAR |
260 HORIZ_INTERP_BILINEAR);
261 }
262 }
263 break;
2dd24552
JB
264 case DRM_MODE_SCALE_FULLSCREEN:
265 /*
266 * Full scaling, even if it changes the aspect ratio.
267 * Fortunately this is all done for us in hw.
268 */
269 if (mode->vdisplay != adjusted_mode->vdisplay ||
270 mode->hdisplay != adjusted_mode->hdisplay) {
271 pfit_control |= PFIT_ENABLE;
272 if (INTEL_INFO(dev)->gen >= 4)
273 pfit_control |= PFIT_SCALING_AUTO;
274 else
275 pfit_control |= (VERT_AUTO_SCALE |
276 VERT_INTERP_BILINEAR |
277 HORIZ_AUTO_SCALE |
278 HORIZ_INTERP_BILINEAR);
279 }
280 break;
ab3e67f4
JB
281 default:
282 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
283 return;
2dd24552
JB
284 }
285
286 /* 965+ wants fuzzy fitting */
287 /* FIXME: handle multiple panels by failing gracefully */
288 if (INTEL_INFO(dev)->gen >= 4)
289 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
290 PFIT_FILTER_FUZZY);
291
292out:
293 if ((pfit_control & PFIT_ENABLE) == 0) {
294 pfit_control = 0;
295 pfit_pgm_ratios = 0;
296 }
297
298 /* Make sure pre-965 set dither correctly for 18bpp panels. */
299 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
300 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
301
2deefda5
DV
302 pipe_config->gmch_pfit.control = pfit_control;
303 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 304 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB
305}
306
ba3820ad
TI
307static int is_backlight_combination_mode(struct drm_device *dev)
308{
309 struct drm_i915_private *dev_priv = dev->dev_private;
310
311 if (INTEL_INFO(dev)->gen >= 4)
312 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
313
314 if (IS_GEN2(dev))
315 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
316
317 return 0;
318}
319
d6540632
JN
320/* XXX: query mode clock or hardware clock and program max PWM appropriately
321 * when it's 0.
322 */
bfd7590d 323static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
0b0b053a 324{
bfd7590d 325 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a
CW
326 u32 val;
327
df0a6797 328 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
8ba2d185 329
0b0b053a
CW
330 /* Restore the CTL value if it lost, e.g. GPU reset */
331
332 if (HAS_PCH_SPLIT(dev_priv->dev)) {
333 val = I915_READ(BLC_PWM_PCH_CTL2);
f4c956ad
DV
334 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
335 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
0b0b053a 336 } else if (val == 0) {
f4c956ad 337 val = dev_priv->regfile.saveBLC_PWM_CTL2;
bfd7590d 338 I915_WRITE(BLC_PWM_PCH_CTL2, val);
0b0b053a
CW
339 }
340 } else {
341 val = I915_READ(BLC_PWM_CTL);
f4c956ad
DV
342 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
343 dev_priv->regfile.saveBLC_PWM_CTL = val;
bfd7590d
JN
344 if (INTEL_INFO(dev)->gen >= 4)
345 dev_priv->regfile.saveBLC_PWM_CTL2 =
346 I915_READ(BLC_PWM_CTL2);
0b0b053a 347 } else if (val == 0) {
f4c956ad 348 val = dev_priv->regfile.saveBLC_PWM_CTL;
bfd7590d
JN
349 I915_WRITE(BLC_PWM_CTL, val);
350 if (INTEL_INFO(dev)->gen >= 4)
351 I915_WRITE(BLC_PWM_CTL2,
352 dev_priv->regfile.saveBLC_PWM_CTL2);
0b0b053a
CW
353 }
354 }
355
356 return val;
357}
358
d6540632 359static u32 intel_panel_get_max_backlight(struct drm_device *dev)
a9573556 360{
a9573556
CW
361 u32 max;
362
bfd7590d 363 max = i915_read_blc_pwm_ctl(dev);
0b0b053a 364
a9573556 365 if (HAS_PCH_SPLIT(dev)) {
0b0b053a 366 max >>= 16;
a9573556 367 } else {
ca88479c 368 if (INTEL_INFO(dev)->gen < 4)
a9573556 369 max >>= 17;
ca88479c 370 else
a9573556 371 max >>= 16;
ba3820ad
TI
372
373 if (is_backlight_combination_mode(dev))
374 max *= 0xff;
a9573556
CW
375 }
376
a9573556 377 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
d6540632 378
a9573556
CW
379 return max;
380}
381
4dca20ef
CE
382static int i915_panel_invert_brightness;
383MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
384 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
7bd90909
CE
385 "report PCI device ID, subsystem vendor and subsystem device ID "
386 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
387 "It will then be included in an upcoming module version.");
4dca20ef 388module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
7bd90909
CE
389static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
390{
4dca20ef
CE
391 struct drm_i915_private *dev_priv = dev->dev_private;
392
393 if (i915_panel_invert_brightness < 0)
394 return val;
395
396 if (i915_panel_invert_brightness > 0 ||
d6540632
JN
397 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
398 u32 max = intel_panel_get_max_backlight(dev);
399 if (max)
400 return max - val;
401 }
7bd90909
CE
402
403 return val;
404}
405
faea35dd 406static u32 intel_panel_get_backlight(struct drm_device *dev)
a9573556
CW
407{
408 struct drm_i915_private *dev_priv = dev->dev_private;
409 u32 val;
8ba2d185
JN
410 unsigned long flags;
411
412 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
a9573556
CW
413
414 if (HAS_PCH_SPLIT(dev)) {
415 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
416 } else {
417 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
ca88479c 418 if (INTEL_INFO(dev)->gen < 4)
a9573556 419 val >>= 1;
ba3820ad 420
0206e353 421 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI
422 u8 lbpc;
423
ba3820ad
TI
424 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
425 val *= lbpc;
426 }
a9573556
CW
427 }
428
7bd90909 429 val = intel_panel_compute_brightness(dev, val);
8ba2d185
JN
430
431 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
432
a9573556
CW
433 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
434 return val;
435}
436
437static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
438{
439 struct drm_i915_private *dev_priv = dev->dev_private;
440 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
441 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
442}
443
f52c619a 444static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
a9573556
CW
445{
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 u32 tmp;
448
449 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
7bd90909 450 level = intel_panel_compute_brightness(dev, level);
a9573556
CW
451
452 if (HAS_PCH_SPLIT(dev))
453 return intel_pch_panel_set_backlight(dev, level);
ba3820ad 454
0206e353 455 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI
456 u32 max = intel_panel_get_max_backlight(dev);
457 u8 lbpc;
458
d6540632
JN
459 /* we're screwed, but keep behaviour backwards compatible */
460 if (!max)
461 max = 1;
462
ba3820ad
TI
463 lbpc = level * 0xfe / max + 1;
464 level /= lbpc;
465 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
466 }
467
a9573556 468 tmp = I915_READ(BLC_PWM_CTL);
a726915c 469 if (INTEL_INFO(dev)->gen < 4)
a9573556 470 level <<= 1;
ca88479c 471 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
a9573556
CW
472 I915_WRITE(BLC_PWM_CTL, tmp | level);
473}
47356eb6 474
d6540632
JN
475/* set backlight brightness to level in range [0..max] */
476void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
47356eb6
CW
477{
478 struct drm_i915_private *dev_priv = dev->dev_private;
d6540632 479 u32 freq;
8ba2d185
JN
480 unsigned long flags;
481
482 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632
JN
483
484 freq = intel_panel_get_max_backlight(dev);
485 if (!freq) {
486 /* we are screwed, bail out */
8ba2d185 487 goto out;
d6540632
JN
488 }
489
22505b82
AL
490 /* scale to hardware, but be careful to not overflow */
491 if (freq < max)
492 level = level * freq / max;
493 else
494 level = freq / max * level;
47356eb6 495
31ad8ec6
JN
496 dev_priv->backlight.level = level;
497 if (dev_priv->backlight.device)
498 dev_priv->backlight.device->props.brightness = level;
b6b3ba5b 499
31ad8ec6 500 if (dev_priv->backlight.enabled)
f52c619a 501 intel_panel_actually_set_backlight(dev, level);
8ba2d185
JN
502out:
503 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
f52c619a
TI
504}
505
506void intel_panel_disable_backlight(struct drm_device *dev)
507{
508 struct drm_i915_private *dev_priv = dev->dev_private;
8ba2d185
JN
509 unsigned long flags;
510
3f577573
JN
511 /*
512 * Do not disable backlight on the vgaswitcheroo path. When switching
513 * away from i915, the other client may depend on i915 to handle the
514 * backlight. This will leave the backlight on unnecessarily when
515 * another client is not activated.
516 */
517 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
518 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
519 return;
520 }
521
8ba2d185 522 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 523
31ad8ec6 524 dev_priv->backlight.enabled = false;
f52c619a 525 intel_panel_actually_set_backlight(dev, 0);
24ded204
DV
526
527 if (INTEL_INFO(dev)->gen >= 4) {
a4f32fc3 528 uint32_t reg, tmp;
24ded204
DV
529
530 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
531
532 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
a4f32fc3
PZ
533
534 if (HAS_PCH_SPLIT(dev)) {
535 tmp = I915_READ(BLC_PWM_PCH_CTL1);
536 tmp &= ~BLM_PCH_PWM_ENABLE;
537 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
538 }
24ded204 539 }
8ba2d185
JN
540
541 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW
542}
543
24ded204
DV
544void intel_panel_enable_backlight(struct drm_device *dev,
545 enum pipe pipe)
47356eb6
CW
546{
547 struct drm_i915_private *dev_priv = dev->dev_private;
35ffda48
JN
548 enum transcoder cpu_transcoder =
549 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
8ba2d185
JN
550 unsigned long flags;
551
552 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 553
31ad8ec6
JN
554 if (dev_priv->backlight.level == 0) {
555 dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
556 if (dev_priv->backlight.device)
557 dev_priv->backlight.device->props.brightness =
558 dev_priv->backlight.level;
b6b3ba5b 559 }
47356eb6 560
24ded204
DV
561 if (INTEL_INFO(dev)->gen >= 4) {
562 uint32_t reg, tmp;
563
564 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
565
566
567 tmp = I915_READ(reg);
568
569 /* Note that this can also get called through dpms changes. And
570 * we don't track the backlight dpms state, hence check whether
571 * we have to do anything first. */
572 if (tmp & BLM_PWM_ENABLE)
770c1231 573 goto set_level;
24ded204 574
7eb552ae 575 if (INTEL_INFO(dev)->num_pipes == 3)
24ded204
DV
576 tmp &= ~BLM_PIPE_SELECT_IVB;
577 else
578 tmp &= ~BLM_PIPE_SELECT;
579
35ffda48
JN
580 if (cpu_transcoder == TRANSCODER_EDP)
581 tmp |= BLM_TRANSCODER_EDP;
582 else
583 tmp |= BLM_PIPE(cpu_transcoder);
24ded204
DV
584 tmp &= ~BLM_PWM_ENABLE;
585
586 I915_WRITE(reg, tmp);
587 POSTING_READ(reg);
588 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
a4f32fc3 589
e85843be
KM
590 if (HAS_PCH_SPLIT(dev) &&
591 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
a4f32fc3
PZ
592 tmp = I915_READ(BLC_PWM_PCH_CTL1);
593 tmp |= BLM_PCH_PWM_ENABLE;
594 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
595 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
596 }
24ded204 597 }
770c1231
TI
598
599set_level:
b1289371
DV
600 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
601 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
602 * registers are set.
770c1231 603 */
ecb135a1
DV
604 dev_priv->backlight.enabled = true;
605 intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
8ba2d185
JN
606
607 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW
608}
609
aaa6fd2a 610static void intel_panel_init_backlight(struct drm_device *dev)
47356eb6
CW
611{
612 struct drm_i915_private *dev_priv = dev->dev_private;
613
31ad8ec6
JN
614 dev_priv->backlight.level = intel_panel_get_backlight(dev);
615 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
47356eb6 616}
fe16d949
CW
617
618enum drm_connector_status
619intel_panel_detect(struct drm_device *dev)
620{
621 struct drm_i915_private *dev_priv = dev->dev_private;
622
623 /* Assume that the BIOS does not lie through the OpRegion... */
a726915c 624 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
fe16d949
CW
625 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
626 connector_status_connected :
627 connector_status_disconnected;
a726915c 628 }
fe16d949 629
a726915c
DV
630 switch (i915_panel_ignore_lid) {
631 case -2:
632 return connector_status_connected;
633 case -1:
634 return connector_status_disconnected;
635 default:
636 return connector_status_unknown;
637 }
fe16d949 638}
aaa6fd2a
MG
639
640#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
641static int intel_panel_update_status(struct backlight_device *bd)
642{
643 struct drm_device *dev = bl_get_data(bd);
d6540632
JN
644 intel_panel_set_backlight(dev, bd->props.brightness,
645 bd->props.max_brightness);
aaa6fd2a
MG
646 return 0;
647}
648
649static int intel_panel_get_brightness(struct backlight_device *bd)
650{
651 struct drm_device *dev = bl_get_data(bd);
7c23396b 652 return intel_panel_get_backlight(dev);
aaa6fd2a
MG
653}
654
655static const struct backlight_ops intel_panel_bl_ops = {
656 .update_status = intel_panel_update_status,
657 .get_brightness = intel_panel_get_brightness,
658};
659
0657b6b1 660int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 661{
0657b6b1 662 struct drm_device *dev = connector->dev;
aaa6fd2a
MG
663 struct drm_i915_private *dev_priv = dev->dev_private;
664 struct backlight_properties props;
8ba2d185 665 unsigned long flags;
aaa6fd2a
MG
666
667 intel_panel_init_backlight(dev);
668
dc652f90
JN
669 if (WARN_ON(dev_priv->backlight.device))
670 return -ENODEV;
671
af437cfd 672 memset(&props, 0, sizeof(props));
aaa6fd2a 673 props.type = BACKLIGHT_RAW;
31ad8ec6 674 props.brightness = dev_priv->backlight.level;
8ba2d185
JN
675
676 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632 677 props.max_brightness = intel_panel_get_max_backlight(dev);
8ba2d185
JN
678 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
679
28dcc2d6 680 if (props.max_brightness == 0) {
e86b6185 681 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
28dcc2d6
JN
682 return -ENODEV;
683 }
31ad8ec6 684 dev_priv->backlight.device =
aaa6fd2a
MG
685 backlight_device_register("intel_backlight",
686 &connector->kdev, dev,
687 &intel_panel_bl_ops, &props);
688
31ad8ec6 689 if (IS_ERR(dev_priv->backlight.device)) {
aaa6fd2a 690 DRM_ERROR("Failed to register backlight: %ld\n",
31ad8ec6
JN
691 PTR_ERR(dev_priv->backlight.device));
692 dev_priv->backlight.device = NULL;
aaa6fd2a
MG
693 return -ENODEV;
694 }
aaa6fd2a
MG
695 return 0;
696}
697
698void intel_panel_destroy_backlight(struct drm_device *dev)
699{
700 struct drm_i915_private *dev_priv = dev->dev_private;
dc652f90 701 if (dev_priv->backlight.device) {
31ad8ec6 702 backlight_device_unregister(dev_priv->backlight.device);
dc652f90
JN
703 dev_priv->backlight.device = NULL;
704 }
aaa6fd2a
MG
705}
706#else
0657b6b1 707int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 708{
0657b6b1 709 intel_panel_init_backlight(connector->dev);
aaa6fd2a
MG
710 return 0;
711}
712
713void intel_panel_destroy_backlight(struct drm_device *dev)
714{
715 return;
716}
717#endif
1d508706 718
dd06f90e
JN
719int intel_panel_init(struct intel_panel *panel,
720 struct drm_display_mode *fixed_mode)
1d508706 721{
dd06f90e
JN
722 panel->fixed_mode = fixed_mode;
723
1d508706
JN
724 return 0;
725}
726
727void intel_panel_fini(struct intel_panel *panel)
728{
dd06f90e
JN
729 struct intel_connector *intel_connector =
730 container_of(panel, struct intel_connector, panel);
731
732 if (panel->fixed_mode)
733 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
1d508706 734}
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