Commit | Line | Data |
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1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
7bd90909 | 33 | #include <linux/moduleparam.h> |
1d8e1c75 CW |
34 | #include "intel_drv.h" |
35 | ||
ba3820ad TI |
36 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
37 | ||
1d8e1c75 | 38 | void |
4c6df4b4 | 39 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 CW |
40 | struct drm_display_mode *adjusted_mode) |
41 | { | |
4c6df4b4 | 42 | drm_mode_copy(adjusted_mode, fixed_mode); |
a52690e4 ID |
43 | |
44 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1d8e1c75 CW |
45 | } |
46 | ||
47 | /* adjusted_mode has been preset to be the panel's fixed mode */ | |
48 | void | |
b074cec8 JB |
49 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
50 | struct intel_crtc_config *pipe_config, | |
51 | int fitting_mode) | |
1d8e1c75 | 52 | { |
b074cec8 | 53 | struct drm_display_mode *mode, *adjusted_mode; |
1d8e1c75 CW |
54 | int x, y, width, height; |
55 | ||
b074cec8 JB |
56 | mode = &pipe_config->requested_mode; |
57 | adjusted_mode = &pipe_config->adjusted_mode; | |
58 | ||
1d8e1c75 CW |
59 | x = y = width = height = 0; |
60 | ||
61 | /* Native modes don't need fitting */ | |
62 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
63 | adjusted_mode->vdisplay == mode->vdisplay) | |
64 | goto done; | |
65 | ||
66 | switch (fitting_mode) { | |
67 | case DRM_MODE_SCALE_CENTER: | |
68 | width = mode->hdisplay; | |
69 | height = mode->vdisplay; | |
70 | x = (adjusted_mode->hdisplay - width + 1)/2; | |
71 | y = (adjusted_mode->vdisplay - height + 1)/2; | |
72 | break; | |
73 | ||
74 | case DRM_MODE_SCALE_ASPECT: | |
75 | /* Scale but preserve the aspect ratio */ | |
76 | { | |
77 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; | |
78 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
79 | if (scaled_width > scaled_height) { /* pillar */ | |
80 | width = scaled_height / mode->vdisplay; | |
302983e9 | 81 | if (width & 1) |
0206e353 | 82 | width++; |
1d8e1c75 CW |
83 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
84 | y = 0; | |
85 | height = adjusted_mode->vdisplay; | |
86 | } else if (scaled_width < scaled_height) { /* letter */ | |
87 | height = scaled_width / mode->hdisplay; | |
302983e9 AJ |
88 | if (height & 1) |
89 | height++; | |
1d8e1c75 CW |
90 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
91 | x = 0; | |
92 | width = adjusted_mode->hdisplay; | |
93 | } else { | |
94 | x = y = 0; | |
95 | width = adjusted_mode->hdisplay; | |
96 | height = adjusted_mode->vdisplay; | |
97 | } | |
98 | } | |
99 | break; | |
100 | ||
1d8e1c75 CW |
101 | case DRM_MODE_SCALE_FULLSCREEN: |
102 | x = y = 0; | |
103 | width = adjusted_mode->hdisplay; | |
104 | height = adjusted_mode->vdisplay; | |
105 | break; | |
ab3e67f4 JB |
106 | |
107 | default: | |
108 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
109 | return; | |
1d8e1c75 CW |
110 | } |
111 | ||
112 | done: | |
b074cec8 JB |
113 | pipe_config->pch_pfit.pos = (x << 16) | y; |
114 | pipe_config->pch_pfit.size = (width << 16) | height; | |
1d8e1c75 | 115 | } |
a9573556 | 116 | |
2dd24552 JB |
117 | static void |
118 | centre_horizontally(struct drm_display_mode *mode, | |
119 | int width) | |
120 | { | |
121 | u32 border, sync_pos, blank_width, sync_width; | |
122 | ||
123 | /* keep the hsync and hblank widths constant */ | |
124 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
125 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
126 | sync_pos = (blank_width - sync_width + 1) / 2; | |
127 | ||
128 | border = (mode->hdisplay - width + 1) / 2; | |
129 | border += border & 1; /* make the border even */ | |
130 | ||
131 | mode->crtc_hdisplay = width; | |
132 | mode->crtc_hblank_start = width + border; | |
133 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
134 | ||
135 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
136 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
137 | } | |
138 | ||
139 | static void | |
140 | centre_vertically(struct drm_display_mode *mode, | |
141 | int height) | |
142 | { | |
143 | u32 border, sync_pos, blank_width, sync_width; | |
144 | ||
145 | /* keep the vsync and vblank widths constant */ | |
146 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
147 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
148 | sync_pos = (blank_width - sync_width + 1) / 2; | |
149 | ||
150 | border = (mode->vdisplay - height + 1) / 2; | |
151 | ||
152 | mode->crtc_vdisplay = height; | |
153 | mode->crtc_vblank_start = height + border; | |
154 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
155 | ||
156 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
157 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
158 | } | |
159 | ||
160 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
161 | { | |
162 | /* | |
163 | * Floating point operation is not supported. So the FACTOR | |
164 | * is defined, which can avoid the floating point computation | |
165 | * when calculating the panel ratio. | |
166 | */ | |
167 | #define ACCURACY 12 | |
168 | #define FACTOR (1 << ACCURACY) | |
169 | u32 ratio = source * FACTOR / target; | |
170 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
171 | } | |
172 | ||
173 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, | |
174 | struct intel_crtc_config *pipe_config, | |
175 | int fitting_mode) | |
176 | { | |
177 | struct drm_device *dev = intel_crtc->base.dev; | |
2dd24552 JB |
178 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
179 | struct drm_display_mode *mode, *adjusted_mode; | |
180 | ||
181 | mode = &pipe_config->requested_mode; | |
182 | adjusted_mode = &pipe_config->adjusted_mode; | |
183 | ||
184 | /* Native modes don't need fitting */ | |
185 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
186 | adjusted_mode->vdisplay == mode->vdisplay) | |
187 | goto out; | |
188 | ||
189 | switch (fitting_mode) { | |
190 | case DRM_MODE_SCALE_CENTER: | |
191 | /* | |
192 | * For centered modes, we have to calculate border widths & | |
193 | * heights and modify the values programmed into the CRTC. | |
194 | */ | |
195 | centre_horizontally(adjusted_mode, mode->hdisplay); | |
196 | centre_vertically(adjusted_mode, mode->vdisplay); | |
197 | border = LVDS_BORDER_ENABLE; | |
198 | break; | |
199 | case DRM_MODE_SCALE_ASPECT: | |
200 | /* Scale but preserve the aspect ratio */ | |
201 | if (INTEL_INFO(dev)->gen >= 4) { | |
202 | u32 scaled_width = adjusted_mode->hdisplay * | |
203 | mode->vdisplay; | |
204 | u32 scaled_height = mode->hdisplay * | |
205 | adjusted_mode->vdisplay; | |
206 | ||
207 | /* 965+ is easy, it does everything in hw */ | |
208 | if (scaled_width > scaled_height) | |
209 | pfit_control |= PFIT_ENABLE | | |
210 | PFIT_SCALING_PILLAR; | |
211 | else if (scaled_width < scaled_height) | |
212 | pfit_control |= PFIT_ENABLE | | |
213 | PFIT_SCALING_LETTER; | |
214 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
215 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
216 | } else { | |
217 | u32 scaled_width = adjusted_mode->hdisplay * | |
218 | mode->vdisplay; | |
219 | u32 scaled_height = mode->hdisplay * | |
220 | adjusted_mode->vdisplay; | |
221 | /* | |
222 | * For earlier chips we have to calculate the scaling | |
223 | * ratio by hand and program it into the | |
224 | * PFIT_PGM_RATIO register | |
225 | */ | |
226 | if (scaled_width > scaled_height) { /* pillar */ | |
227 | centre_horizontally(adjusted_mode, | |
228 | scaled_height / | |
229 | mode->vdisplay); | |
230 | ||
231 | border = LVDS_BORDER_ENABLE; | |
232 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
233 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
234 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
235 | bits << PFIT_VERT_SCALE_SHIFT); | |
236 | pfit_control |= (PFIT_ENABLE | | |
237 | VERT_INTERP_BILINEAR | | |
238 | HORIZ_INTERP_BILINEAR); | |
239 | } | |
240 | } else if (scaled_width < scaled_height) { /* letter */ | |
241 | centre_vertically(adjusted_mode, | |
242 | scaled_width / | |
243 | mode->hdisplay); | |
244 | ||
245 | border = LVDS_BORDER_ENABLE; | |
246 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
247 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
248 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
249 | bits << PFIT_VERT_SCALE_SHIFT); | |
250 | pfit_control |= (PFIT_ENABLE | | |
251 | VERT_INTERP_BILINEAR | | |
252 | HORIZ_INTERP_BILINEAR); | |
253 | } | |
254 | } else { | |
255 | /* Aspects match, Let hw scale both directions */ | |
256 | pfit_control |= (PFIT_ENABLE | | |
257 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
258 | VERT_INTERP_BILINEAR | | |
259 | HORIZ_INTERP_BILINEAR); | |
260 | } | |
261 | } | |
262 | break; | |
2dd24552 JB |
263 | case DRM_MODE_SCALE_FULLSCREEN: |
264 | /* | |
265 | * Full scaling, even if it changes the aspect ratio. | |
266 | * Fortunately this is all done for us in hw. | |
267 | */ | |
268 | if (mode->vdisplay != adjusted_mode->vdisplay || | |
269 | mode->hdisplay != adjusted_mode->hdisplay) { | |
270 | pfit_control |= PFIT_ENABLE; | |
271 | if (INTEL_INFO(dev)->gen >= 4) | |
272 | pfit_control |= PFIT_SCALING_AUTO; | |
273 | else | |
274 | pfit_control |= (VERT_AUTO_SCALE | | |
275 | VERT_INTERP_BILINEAR | | |
276 | HORIZ_AUTO_SCALE | | |
277 | HORIZ_INTERP_BILINEAR); | |
278 | } | |
279 | break; | |
ab3e67f4 JB |
280 | default: |
281 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
282 | return; | |
2dd24552 JB |
283 | } |
284 | ||
285 | /* 965+ wants fuzzy fitting */ | |
286 | /* FIXME: handle multiple panels by failing gracefully */ | |
287 | if (INTEL_INFO(dev)->gen >= 4) | |
288 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | | |
289 | PFIT_FILTER_FUZZY); | |
290 | ||
291 | out: | |
292 | if ((pfit_control & PFIT_ENABLE) == 0) { | |
293 | pfit_control = 0; | |
294 | pfit_pgm_ratios = 0; | |
295 | } | |
296 | ||
297 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ | |
298 | if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) | |
299 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
300 | ||
2deefda5 DV |
301 | pipe_config->gmch_pfit.control = pfit_control; |
302 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; | |
68fc8742 | 303 | pipe_config->gmch_pfit.lvds_border_bits = border; |
2dd24552 JB |
304 | } |
305 | ||
ba3820ad TI |
306 | static int is_backlight_combination_mode(struct drm_device *dev) |
307 | { | |
308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
309 | ||
310 | if (INTEL_INFO(dev)->gen >= 4) | |
311 | return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; | |
312 | ||
313 | if (IS_GEN2(dev)) | |
314 | return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
d6540632 JN |
319 | /* XXX: query mode clock or hardware clock and program max PWM appropriately |
320 | * when it's 0. | |
321 | */ | |
bfd7590d | 322 | static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) |
0b0b053a | 323 | { |
bfd7590d | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b0b053a CW |
325 | u32 val; |
326 | ||
df0a6797 | 327 | WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock)); |
8ba2d185 | 328 | |
0b0b053a CW |
329 | /* Restore the CTL value if it lost, e.g. GPU reset */ |
330 | ||
331 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
332 | val = I915_READ(BLC_PWM_PCH_CTL2); | |
f4c956ad DV |
333 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { |
334 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; | |
0b0b053a | 335 | } else if (val == 0) { |
f4c956ad | 336 | val = dev_priv->regfile.saveBLC_PWM_CTL2; |
bfd7590d | 337 | I915_WRITE(BLC_PWM_PCH_CTL2, val); |
0b0b053a CW |
338 | } |
339 | } else { | |
340 | val = I915_READ(BLC_PWM_CTL); | |
f4c956ad DV |
341 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
342 | dev_priv->regfile.saveBLC_PWM_CTL = val; | |
bfd7590d JN |
343 | if (INTEL_INFO(dev)->gen >= 4) |
344 | dev_priv->regfile.saveBLC_PWM_CTL2 = | |
345 | I915_READ(BLC_PWM_CTL2); | |
0b0b053a | 346 | } else if (val == 0) { |
f4c956ad | 347 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
bfd7590d JN |
348 | I915_WRITE(BLC_PWM_CTL, val); |
349 | if (INTEL_INFO(dev)->gen >= 4) | |
350 | I915_WRITE(BLC_PWM_CTL2, | |
351 | dev_priv->regfile.saveBLC_PWM_CTL2); | |
0b0b053a CW |
352 | } |
353 | } | |
354 | ||
355 | return val; | |
356 | } | |
357 | ||
d6540632 | 358 | static u32 intel_panel_get_max_backlight(struct drm_device *dev) |
a9573556 | 359 | { |
a9573556 CW |
360 | u32 max; |
361 | ||
bfd7590d | 362 | max = i915_read_blc_pwm_ctl(dev); |
0b0b053a | 363 | |
a9573556 | 364 | if (HAS_PCH_SPLIT(dev)) { |
0b0b053a | 365 | max >>= 16; |
a9573556 | 366 | } else { |
ca88479c | 367 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 368 | max >>= 17; |
ca88479c | 369 | else |
a9573556 | 370 | max >>= 16; |
ba3820ad TI |
371 | |
372 | if (is_backlight_combination_mode(dev)) | |
373 | max *= 0xff; | |
a9573556 CW |
374 | } |
375 | ||
a9573556 | 376 | DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
d6540632 | 377 | |
a9573556 CW |
378 | return max; |
379 | } | |
380 | ||
4dca20ef CE |
381 | static int i915_panel_invert_brightness; |
382 | MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness " | |
383 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " | |
7bd90909 CE |
384 | "report PCI device ID, subsystem vendor and subsystem device ID " |
385 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " | |
386 | "It will then be included in an upcoming module version."); | |
4dca20ef | 387 | module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600); |
7bd90909 CE |
388 | static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val) |
389 | { | |
4dca20ef CE |
390 | struct drm_i915_private *dev_priv = dev->dev_private; |
391 | ||
392 | if (i915_panel_invert_brightness < 0) | |
393 | return val; | |
394 | ||
395 | if (i915_panel_invert_brightness > 0 || | |
d6540632 JN |
396 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
397 | u32 max = intel_panel_get_max_backlight(dev); | |
398 | if (max) | |
399 | return max - val; | |
400 | } | |
7bd90909 CE |
401 | |
402 | return val; | |
403 | } | |
404 | ||
faea35dd | 405 | static u32 intel_panel_get_backlight(struct drm_device *dev) |
a9573556 CW |
406 | { |
407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
408 | u32 val; | |
8ba2d185 JN |
409 | unsigned long flags; |
410 | ||
411 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); | |
a9573556 CW |
412 | |
413 | if (HAS_PCH_SPLIT(dev)) { | |
414 | val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; | |
415 | } else { | |
416 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; | |
ca88479c | 417 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 418 | val >>= 1; |
ba3820ad | 419 | |
0206e353 | 420 | if (is_backlight_combination_mode(dev)) { |
ba3820ad TI |
421 | u8 lbpc; |
422 | ||
ba3820ad TI |
423 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
424 | val *= lbpc; | |
425 | } | |
a9573556 CW |
426 | } |
427 | ||
7bd90909 | 428 | val = intel_panel_compute_brightness(dev, val); |
8ba2d185 JN |
429 | |
430 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); | |
431 | ||
a9573556 CW |
432 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
433 | return val; | |
434 | } | |
435 | ||
436 | static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) | |
437 | { | |
438 | struct drm_i915_private *dev_priv = dev->dev_private; | |
439 | u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
440 | I915_WRITE(BLC_PWM_CPU_CTL, val | level); | |
441 | } | |
442 | ||
f52c619a | 443 | static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level) |
a9573556 CW |
444 | { |
445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
446 | u32 tmp; | |
447 | ||
448 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
7bd90909 | 449 | level = intel_panel_compute_brightness(dev, level); |
a9573556 CW |
450 | |
451 | if (HAS_PCH_SPLIT(dev)) | |
452 | return intel_pch_panel_set_backlight(dev, level); | |
ba3820ad | 453 | |
0206e353 | 454 | if (is_backlight_combination_mode(dev)) { |
ba3820ad TI |
455 | u32 max = intel_panel_get_max_backlight(dev); |
456 | u8 lbpc; | |
457 | ||
d6540632 JN |
458 | /* we're screwed, but keep behaviour backwards compatible */ |
459 | if (!max) | |
460 | max = 1; | |
461 | ||
ba3820ad TI |
462 | lbpc = level * 0xfe / max + 1; |
463 | level /= lbpc; | |
464 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); | |
465 | } | |
466 | ||
a9573556 | 467 | tmp = I915_READ(BLC_PWM_CTL); |
a726915c | 468 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 469 | level <<= 1; |
ca88479c | 470 | tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
a9573556 CW |
471 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
472 | } | |
47356eb6 | 473 | |
d6540632 JN |
474 | /* set backlight brightness to level in range [0..max] */ |
475 | void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max) | |
47356eb6 CW |
476 | { |
477 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6540632 | 478 | u32 freq; |
8ba2d185 JN |
479 | unsigned long flags; |
480 | ||
481 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); | |
d6540632 JN |
482 | |
483 | freq = intel_panel_get_max_backlight(dev); | |
484 | if (!freq) { | |
485 | /* we are screwed, bail out */ | |
8ba2d185 | 486 | goto out; |
d6540632 JN |
487 | } |
488 | ||
22505b82 AL |
489 | /* scale to hardware, but be careful to not overflow */ |
490 | if (freq < max) | |
491 | level = level * freq / max; | |
492 | else | |
493 | level = freq / max * level; | |
47356eb6 | 494 | |
31ad8ec6 JN |
495 | dev_priv->backlight.level = level; |
496 | if (dev_priv->backlight.device) | |
497 | dev_priv->backlight.device->props.brightness = level; | |
b6b3ba5b | 498 | |
31ad8ec6 | 499 | if (dev_priv->backlight.enabled) |
f52c619a | 500 | intel_panel_actually_set_backlight(dev, level); |
8ba2d185 JN |
501 | out: |
502 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); | |
f52c619a TI |
503 | } |
504 | ||
505 | void intel_panel_disable_backlight(struct drm_device *dev) | |
506 | { | |
507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8ba2d185 JN |
508 | unsigned long flags; |
509 | ||
3f577573 JN |
510 | /* |
511 | * Do not disable backlight on the vgaswitcheroo path. When switching | |
512 | * away from i915, the other client may depend on i915 to handle the | |
513 | * backlight. This will leave the backlight on unnecessarily when | |
514 | * another client is not activated. | |
515 | */ | |
516 | if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) { | |
517 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); | |
518 | return; | |
519 | } | |
520 | ||
8ba2d185 | 521 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); |
47356eb6 | 522 | |
31ad8ec6 | 523 | dev_priv->backlight.enabled = false; |
f52c619a | 524 | intel_panel_actually_set_backlight(dev, 0); |
24ded204 DV |
525 | |
526 | if (INTEL_INFO(dev)->gen >= 4) { | |
a4f32fc3 | 527 | uint32_t reg, tmp; |
24ded204 DV |
528 | |
529 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; | |
530 | ||
531 | I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); | |
a4f32fc3 PZ |
532 | |
533 | if (HAS_PCH_SPLIT(dev)) { | |
534 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
535 | tmp &= ~BLM_PCH_PWM_ENABLE; | |
536 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); | |
537 | } | |
24ded204 | 538 | } |
8ba2d185 JN |
539 | |
540 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); | |
47356eb6 CW |
541 | } |
542 | ||
24ded204 DV |
543 | void intel_panel_enable_backlight(struct drm_device *dev, |
544 | enum pipe pipe) | |
47356eb6 CW |
545 | { |
546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
35ffda48 JN |
547 | enum transcoder cpu_transcoder = |
548 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
8ba2d185 JN |
549 | unsigned long flags; |
550 | ||
551 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); | |
47356eb6 | 552 | |
31ad8ec6 JN |
553 | if (dev_priv->backlight.level == 0) { |
554 | dev_priv->backlight.level = intel_panel_get_max_backlight(dev); | |
555 | if (dev_priv->backlight.device) | |
556 | dev_priv->backlight.device->props.brightness = | |
557 | dev_priv->backlight.level; | |
b6b3ba5b | 558 | } |
47356eb6 | 559 | |
24ded204 DV |
560 | if (INTEL_INFO(dev)->gen >= 4) { |
561 | uint32_t reg, tmp; | |
562 | ||
563 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; | |
564 | ||
565 | ||
566 | tmp = I915_READ(reg); | |
567 | ||
568 | /* Note that this can also get called through dpms changes. And | |
569 | * we don't track the backlight dpms state, hence check whether | |
570 | * we have to do anything first. */ | |
571 | if (tmp & BLM_PWM_ENABLE) | |
770c1231 | 572 | goto set_level; |
24ded204 | 573 | |
7eb552ae | 574 | if (INTEL_INFO(dev)->num_pipes == 3) |
24ded204 DV |
575 | tmp &= ~BLM_PIPE_SELECT_IVB; |
576 | else | |
577 | tmp &= ~BLM_PIPE_SELECT; | |
578 | ||
35ffda48 JN |
579 | if (cpu_transcoder == TRANSCODER_EDP) |
580 | tmp |= BLM_TRANSCODER_EDP; | |
581 | else | |
582 | tmp |= BLM_PIPE(cpu_transcoder); | |
24ded204 DV |
583 | tmp &= ~BLM_PWM_ENABLE; |
584 | ||
585 | I915_WRITE(reg, tmp); | |
586 | POSTING_READ(reg); | |
587 | I915_WRITE(reg, tmp | BLM_PWM_ENABLE); | |
a4f32fc3 | 588 | |
e85843be KM |
589 | if (HAS_PCH_SPLIT(dev) && |
590 | !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) { | |
a4f32fc3 PZ |
591 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
592 | tmp |= BLM_PCH_PWM_ENABLE; | |
593 | tmp &= ~BLM_PCH_OVERRIDE_ENABLE; | |
594 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); | |
595 | } | |
24ded204 | 596 | } |
770c1231 TI |
597 | |
598 | set_level: | |
b1289371 DV |
599 | /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. |
600 | * BLC_PWM_CPU_CTL may be cleared to zero automatically when these | |
601 | * registers are set. | |
770c1231 | 602 | */ |
ecb135a1 DV |
603 | dev_priv->backlight.enabled = true; |
604 | intel_panel_actually_set_backlight(dev, dev_priv->backlight.level); | |
8ba2d185 JN |
605 | |
606 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); | |
47356eb6 CW |
607 | } |
608 | ||
aaa6fd2a | 609 | static void intel_panel_init_backlight(struct drm_device *dev) |
47356eb6 CW |
610 | { |
611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
612 | ||
31ad8ec6 JN |
613 | dev_priv->backlight.level = intel_panel_get_backlight(dev); |
614 | dev_priv->backlight.enabled = dev_priv->backlight.level != 0; | |
47356eb6 | 615 | } |
fe16d949 CW |
616 | |
617 | enum drm_connector_status | |
618 | intel_panel_detect(struct drm_device *dev) | |
619 | { | |
620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
621 | ||
622 | /* Assume that the BIOS does not lie through the OpRegion... */ | |
a726915c | 623 | if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) { |
fe16d949 CW |
624 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
625 | connector_status_connected : | |
626 | connector_status_disconnected; | |
a726915c | 627 | } |
fe16d949 | 628 | |
a726915c DV |
629 | switch (i915_panel_ignore_lid) { |
630 | case -2: | |
631 | return connector_status_connected; | |
632 | case -1: | |
633 | return connector_status_disconnected; | |
634 | default: | |
635 | return connector_status_unknown; | |
636 | } | |
fe16d949 | 637 | } |
aaa6fd2a MG |
638 | |
639 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE | |
640 | static int intel_panel_update_status(struct backlight_device *bd) | |
641 | { | |
642 | struct drm_device *dev = bl_get_data(bd); | |
d6540632 JN |
643 | intel_panel_set_backlight(dev, bd->props.brightness, |
644 | bd->props.max_brightness); | |
aaa6fd2a MG |
645 | return 0; |
646 | } | |
647 | ||
648 | static int intel_panel_get_brightness(struct backlight_device *bd) | |
649 | { | |
650 | struct drm_device *dev = bl_get_data(bd); | |
7c23396b | 651 | return intel_panel_get_backlight(dev); |
aaa6fd2a MG |
652 | } |
653 | ||
654 | static const struct backlight_ops intel_panel_bl_ops = { | |
655 | .update_status = intel_panel_update_status, | |
656 | .get_brightness = intel_panel_get_brightness, | |
657 | }; | |
658 | ||
0657b6b1 | 659 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 660 | { |
0657b6b1 | 661 | struct drm_device *dev = connector->dev; |
aaa6fd2a MG |
662 | struct drm_i915_private *dev_priv = dev->dev_private; |
663 | struct backlight_properties props; | |
8ba2d185 | 664 | unsigned long flags; |
aaa6fd2a MG |
665 | |
666 | intel_panel_init_backlight(dev); | |
667 | ||
dc652f90 JN |
668 | if (WARN_ON(dev_priv->backlight.device)) |
669 | return -ENODEV; | |
670 | ||
af437cfd | 671 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 672 | props.type = BACKLIGHT_RAW; |
31ad8ec6 | 673 | props.brightness = dev_priv->backlight.level; |
8ba2d185 JN |
674 | |
675 | spin_lock_irqsave(&dev_priv->backlight.lock, flags); | |
d6540632 | 676 | props.max_brightness = intel_panel_get_max_backlight(dev); |
8ba2d185 JN |
677 | spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); |
678 | ||
28dcc2d6 | 679 | if (props.max_brightness == 0) { |
e86b6185 | 680 | DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n"); |
28dcc2d6 JN |
681 | return -ENODEV; |
682 | } | |
31ad8ec6 | 683 | dev_priv->backlight.device = |
aaa6fd2a MG |
684 | backlight_device_register("intel_backlight", |
685 | &connector->kdev, dev, | |
686 | &intel_panel_bl_ops, &props); | |
687 | ||
31ad8ec6 | 688 | if (IS_ERR(dev_priv->backlight.device)) { |
aaa6fd2a | 689 | DRM_ERROR("Failed to register backlight: %ld\n", |
31ad8ec6 JN |
690 | PTR_ERR(dev_priv->backlight.device)); |
691 | dev_priv->backlight.device = NULL; | |
aaa6fd2a MG |
692 | return -ENODEV; |
693 | } | |
aaa6fd2a MG |
694 | return 0; |
695 | } | |
696 | ||
697 | void intel_panel_destroy_backlight(struct drm_device *dev) | |
698 | { | |
699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dc652f90 | 700 | if (dev_priv->backlight.device) { |
31ad8ec6 | 701 | backlight_device_unregister(dev_priv->backlight.device); |
dc652f90 JN |
702 | dev_priv->backlight.device = NULL; |
703 | } | |
aaa6fd2a MG |
704 | } |
705 | #else | |
0657b6b1 | 706 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 707 | { |
0657b6b1 | 708 | intel_panel_init_backlight(connector->dev); |
aaa6fd2a MG |
709 | return 0; |
710 | } | |
711 | ||
712 | void intel_panel_destroy_backlight(struct drm_device *dev) | |
713 | { | |
714 | return; | |
715 | } | |
716 | #endif | |
1d508706 | 717 | |
dd06f90e JN |
718 | int intel_panel_init(struct intel_panel *panel, |
719 | struct drm_display_mode *fixed_mode) | |
1d508706 | 720 | { |
dd06f90e JN |
721 | panel->fixed_mode = fixed_mode; |
722 | ||
1d508706 JN |
723 | return 0; |
724 | } | |
725 | ||
726 | void intel_panel_fini(struct intel_panel *panel) | |
727 | { | |
dd06f90e JN |
728 | struct intel_connector *intel_connector = |
729 | container_of(panel, struct intel_connector, panel); | |
730 | ||
731 | if (panel->fixed_mode) | |
732 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
1d508706 | 733 | } |