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drm/i915: factor out GMCH panel fitting code and use for eDP v3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW		 1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP		 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
7bd90909 33#include <linux/moduleparam.h>
1d8e1c75
CW		 34#include "intel_drv.h"
35
ba3820ad
TI		 36#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
37
1d8e1c75
CW		 38void
39intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
40 struct drm_display_mode *adjusted_mode)
41{
42 adjusted_mode->hdisplay = fixed_mode->hdisplay;
43 adjusted_mode->hsync_start = fixed_mode->hsync_start;
44 adjusted_mode->hsync_end = fixed_mode->hsync_end;
45 adjusted_mode->htotal = fixed_mode->htotal;
46
47 adjusted_mode->vdisplay = fixed_mode->vdisplay;
48 adjusted_mode->vsync_start = fixed_mode->vsync_start;
49 adjusted_mode->vsync_end = fixed_mode->vsync_end;
50 adjusted_mode->vtotal = fixed_mode->vtotal;
51
52 adjusted_mode->clock = fixed_mode->clock;
1d8e1c75
CW		 53}
54
55/* adjusted_mode has been preset to be the panel's fixed mode */
56void
57intel_pch_panel_fitting(struct drm_device *dev,
58 int fitting_mode,
cb1793ce 59 const struct drm_display_mode *mode,
1d8e1c75
CW		 60 struct drm_display_mode *adjusted_mode)
61{
62 struct drm_i915_private *dev_priv = dev->dev_private;
63 int x, y, width, height;
64
65 x = y = width = height = 0;
66
67 /* Native modes don't need fitting */
68 if (adjusted_mode->hdisplay == mode->hdisplay &&
69 adjusted_mode->vdisplay == mode->vdisplay)
70 goto done;
71
72 switch (fitting_mode) {
73 case DRM_MODE_SCALE_CENTER:
74 width = mode->hdisplay;
75 height = mode->vdisplay;
76 x = (adjusted_mode->hdisplay - width + 1)/2;
77 y = (adjusted_mode->vdisplay - height + 1)/2;
78 break;
79
80 case DRM_MODE_SCALE_ASPECT:
81 /* Scale but preserve the aspect ratio */
82 {
83 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
84 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
85 if (scaled_width > scaled_height) { /* pillar */
86 width = scaled_height / mode->vdisplay;
302983e9 87 if (width & 1)
0206e353 88 width++;
1d8e1c75
CW		 89 x = (adjusted_mode->hdisplay - width + 1) / 2;
90 y = 0;
91 height = adjusted_mode->vdisplay;
92 } else if (scaled_width < scaled_height) { /* letter */
93 height = scaled_width / mode->hdisplay;
302983e9
AJ		 94 if (height & 1)
95 height++;
1d8e1c75
CW		 96 y = (adjusted_mode->vdisplay - height + 1) / 2;
97 x = 0;
98 width = adjusted_mode->hdisplay;
99 } else {
100 x = y = 0;
101 width = adjusted_mode->hdisplay;
102 height = adjusted_mode->vdisplay;
103 }
104 }
105 break;
106
107 default:
108 case DRM_MODE_SCALE_FULLSCREEN:
109 x = y = 0;
110 width = adjusted_mode->hdisplay;
111 height = adjusted_mode->vdisplay;
112 break;
113 }
114
115done:
116 dev_priv->pch_pf_pos = (x << 16) | y;
117 dev_priv->pch_pf_size = (width << 16) | height;
118}
a9573556 119
2dd24552
JB		 120static void
121centre_horizontally(struct drm_display_mode *mode,
122 int width)
123{
124 u32 border, sync_pos, blank_width, sync_width;
125
126 /* keep the hsync and hblank widths constant */
127 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
128 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
129 sync_pos = (blank_width - sync_width + 1) / 2;
130
131 border = (mode->hdisplay - width + 1) / 2;
132 border += border & 1; /* make the border even */
133
134 mode->crtc_hdisplay = width;
135 mode->crtc_hblank_start = width + border;
136 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
137
138 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
139 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
140}
141
142static void
143centre_vertically(struct drm_display_mode *mode,
144 int height)
145{
146 u32 border, sync_pos, blank_width, sync_width;
147
148 /* keep the vsync and vblank widths constant */
149 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
150 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
151 sync_pos = (blank_width - sync_width + 1) / 2;
152
153 border = (mode->vdisplay - height + 1) / 2;
154
155 mode->crtc_vdisplay = height;
156 mode->crtc_vblank_start = height + border;
157 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
158
159 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
160 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
161}
162
163static inline u32 panel_fitter_scaling(u32 source, u32 target)
164{
165 /*
166 * Floating point operation is not supported. So the FACTOR
167 * is defined, which can avoid the floating point computation
168 * when calculating the panel ratio.
169 */
170#define ACCURACY 12
171#define FACTOR (1 << ACCURACY)
172 u32 ratio = source * FACTOR / target;
173 return (FACTOR * ratio + FACTOR/2) / FACTOR;
174}
175
176void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
177 struct intel_crtc_config *pipe_config,
178 int fitting_mode)
179{
180 struct drm_device *dev = intel_crtc->base.dev;
181 struct drm_i915_private *dev_priv = dev->dev_private;
182 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
183 struct drm_display_mode *mode, *adjusted_mode;
184
185 mode = &pipe_config->requested_mode;
186 adjusted_mode = &pipe_config->adjusted_mode;
187
188 /* Native modes don't need fitting */
189 if (adjusted_mode->hdisplay == mode->hdisplay &&
190 adjusted_mode->vdisplay == mode->vdisplay)
191 goto out;
192
193 switch (fitting_mode) {
194 case DRM_MODE_SCALE_CENTER:
195 /*
196 * For centered modes, we have to calculate border widths &
197 * heights and modify the values programmed into the CRTC.
198 */
199 centre_horizontally(adjusted_mode, mode->hdisplay);
200 centre_vertically(adjusted_mode, mode->vdisplay);
201 border = LVDS_BORDER_ENABLE;
202 break;
203 case DRM_MODE_SCALE_ASPECT:
204 /* Scale but preserve the aspect ratio */
205 if (INTEL_INFO(dev)->gen >= 4) {
206 u32 scaled_width = adjusted_mode->hdisplay *
207 mode->vdisplay;
208 u32 scaled_height = mode->hdisplay *
209 adjusted_mode->vdisplay;
210
211 /* 965+ is easy, it does everything in hw */
212 if (scaled_width > scaled_height)
213 pfit_control |= PFIT_ENABLE |
214 PFIT_SCALING_PILLAR;
215 else if (scaled_width < scaled_height)
216 pfit_control |= PFIT_ENABLE |
217 PFIT_SCALING_LETTER;
218 else if (adjusted_mode->hdisplay != mode->hdisplay)
219 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
220 } else {
221 u32 scaled_width = adjusted_mode->hdisplay *
222 mode->vdisplay;
223 u32 scaled_height = mode->hdisplay *
224 adjusted_mode->vdisplay;
225 /*
226 * For earlier chips we have to calculate the scaling
227 * ratio by hand and program it into the
228 * PFIT_PGM_RATIO register
229 */
230 if (scaled_width > scaled_height) { /* pillar */
231 centre_horizontally(adjusted_mode,
232 scaled_height /
233 mode->vdisplay);
234
235 border = LVDS_BORDER_ENABLE;
236 if (mode->vdisplay != adjusted_mode->vdisplay) {
237 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
238 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
239 bits << PFIT_VERT_SCALE_SHIFT);
240 pfit_control |= (PFIT_ENABLE |
241 VERT_INTERP_BILINEAR |
242 HORIZ_INTERP_BILINEAR);
243 }
244 } else if (scaled_width < scaled_height) { /* letter */
245 centre_vertically(adjusted_mode,
246 scaled_width /
247 mode->hdisplay);
248
249 border = LVDS_BORDER_ENABLE;
250 if (mode->hdisplay != adjusted_mode->hdisplay) {
251 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
252 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
253 bits << PFIT_VERT_SCALE_SHIFT);
254 pfit_control |= (PFIT_ENABLE |
255 VERT_INTERP_BILINEAR |
256 HORIZ_INTERP_BILINEAR);
257 }
258 } else {
259 /* Aspects match, Let hw scale both directions */
260 pfit_control |= (PFIT_ENABLE |
261 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
262 VERT_INTERP_BILINEAR |
263 HORIZ_INTERP_BILINEAR);
264 }
265 }
266 break;
267 default:
268 case DRM_MODE_SCALE_FULLSCREEN:
269 /*
270 * Full scaling, even if it changes the aspect ratio.
271 * Fortunately this is all done for us in hw.
272 */
273 if (mode->vdisplay != adjusted_mode->vdisplay ||
274 mode->hdisplay != adjusted_mode->hdisplay) {
275 pfit_control |= PFIT_ENABLE;
276 if (INTEL_INFO(dev)->gen >= 4)
277 pfit_control |= PFIT_SCALING_AUTO;
278 else
279 pfit_control |= (VERT_AUTO_SCALE |
280 VERT_INTERP_BILINEAR |
281 HORIZ_AUTO_SCALE |
282 HORIZ_INTERP_BILINEAR);
283 }
284 break;
285 }
286
287 /* 965+ wants fuzzy fitting */
288 /* FIXME: handle multiple panels by failing gracefully */
289 if (INTEL_INFO(dev)->gen >= 4)
290 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
291 PFIT_FILTER_FUZZY);
292
293out:
294 if ((pfit_control & PFIT_ENABLE) == 0) {
295 pfit_control = 0;
296 pfit_pgm_ratios = 0;
297 }
298
299 /* Make sure pre-965 set dither correctly for 18bpp panels. */
300 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
301 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
302
303 if (pfit_control != pipe_config->pfit_control ||
304 pfit_pgm_ratios != pipe_config->pfit_pgm_ratios) {
305 pipe_config->pfit_control = pfit_control;
306 pipe_config->pfit_pgm_ratios = pfit_pgm_ratios;
307 }
308 dev_priv->lvds_border_bits = border;
309}
310
ba3820ad
TI		 311static int is_backlight_combination_mode(struct drm_device *dev)
312{
313 struct drm_i915_private *dev_priv = dev->dev_private;
314
315 if (INTEL_INFO(dev)->gen >= 4)
316 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
317
318 if (IS_GEN2(dev))
319 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
320
321 return 0;
322}
323
d6540632
JN		 324/* XXX: query mode clock or hardware clock and program max PWM appropriately
325 * when it's 0.
326 */
bfd7590d 327static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
0b0b053a 328{
bfd7590d 329 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a
CW		 330 u32 val;
331
8ba2d185
JN		 332 WARN_ON(!spin_is_locked(&dev_priv->backlight.lock));
333
0b0b053a
CW		 334 /* Restore the CTL value if it lost, e.g. GPU reset */
335
336 if (HAS_PCH_SPLIT(dev_priv->dev)) {
337 val = I915_READ(BLC_PWM_PCH_CTL2);
f4c956ad
DV		 338 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
339 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
0b0b053a 340 } else if (val == 0) {
f4c956ad 341 val = dev_priv->regfile.saveBLC_PWM_CTL2;
bfd7590d 342 I915_WRITE(BLC_PWM_PCH_CTL2, val);
0b0b053a
CW		 343 }
344 } else {
345 val = I915_READ(BLC_PWM_CTL);
f4c956ad
DV		 346 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
347 dev_priv->regfile.saveBLC_PWM_CTL = val;
bfd7590d
JN		 348 if (INTEL_INFO(dev)->gen >= 4)
349 dev_priv->regfile.saveBLC_PWM_CTL2 =
350 I915_READ(BLC_PWM_CTL2);
0b0b053a 351 } else if (val == 0) {
f4c956ad 352 val = dev_priv->regfile.saveBLC_PWM_CTL;
bfd7590d
JN		 353 I915_WRITE(BLC_PWM_CTL, val);
354 if (INTEL_INFO(dev)->gen >= 4)
355 I915_WRITE(BLC_PWM_CTL2,
356 dev_priv->regfile.saveBLC_PWM_CTL2);
0b0b053a
CW		 357 }
358 }
359
360 return val;
361}
362
d6540632 363static u32 intel_panel_get_max_backlight(struct drm_device *dev)
a9573556 364{
a9573556
CW		 365 u32 max;
366
bfd7590d 367 max = i915_read_blc_pwm_ctl(dev);
0b0b053a 368
a9573556 369 if (HAS_PCH_SPLIT(dev)) {
0b0b053a 370 max >>= 16;
a9573556 371 } else {
ca88479c 372 if (INTEL_INFO(dev)->gen < 4)
a9573556 373 max >>= 17;
ca88479c 374 else
a9573556 375 max >>= 16;
ba3820ad
TI		 376
377 if (is_backlight_combination_mode(dev))
378 max *= 0xff;
a9573556
CW		 379 }
380
a9573556 381 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
d6540632 382
a9573556
CW		 383 return max;
384}
385
4dca20ef
CE		 386static int i915_panel_invert_brightness;
387MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
388 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
7bd90909
CE		 389 "report PCI device ID, subsystem vendor and subsystem device ID "
390 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
391 "It will then be included in an upcoming module version.");
4dca20ef 392module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
7bd90909
CE		 393static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
394{
4dca20ef
CE		 395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (i915_panel_invert_brightness < 0)
398 return val;
399
400 if (i915_panel_invert_brightness > 0 ||
d6540632
JN		 401 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
402 u32 max = intel_panel_get_max_backlight(dev);
403 if (max)
404 return max - val;
405 }
7bd90909
CE		 406
407 return val;
408}
409
faea35dd 410static u32 intel_panel_get_backlight(struct drm_device *dev)
a9573556
CW		 411{
412 struct drm_i915_private *dev_priv = dev->dev_private;
413 u32 val;
8ba2d185
JN		 414 unsigned long flags;
415
416 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
a9573556
CW		 417
418 if (HAS_PCH_SPLIT(dev)) {
419 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
420 } else {
421 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
ca88479c 422 if (INTEL_INFO(dev)->gen < 4)
a9573556 423 val >>= 1;
ba3820ad 424
0206e353 425 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI		 426 u8 lbpc;
427
ba3820ad
TI		 428 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
429 val *= lbpc;
430 }
a9573556
CW		 431 }
432
7bd90909 433 val = intel_panel_compute_brightness(dev, val);
8ba2d185
JN		 434
435 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
436
a9573556
CW		 437 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
438 return val;
439}
440
441static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
442{
443 struct drm_i915_private *dev_priv = dev->dev_private;
444 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
445 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
446}
447
f52c619a 448static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
a9573556
CW		 449{
450 struct drm_i915_private *dev_priv = dev->dev_private;
451 u32 tmp;
452
453 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
7bd90909 454 level = intel_panel_compute_brightness(dev, level);
a9573556
CW		 455
456 if (HAS_PCH_SPLIT(dev))
457 return intel_pch_panel_set_backlight(dev, level);
ba3820ad 458
0206e353 459 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI		 460 u32 max = intel_panel_get_max_backlight(dev);
461 u8 lbpc;
462
d6540632
JN		 463 /* we're screwed, but keep behaviour backwards compatible */
464 if (!max)
465 max = 1;
466
ba3820ad
TI		 467 lbpc = level * 0xfe / max + 1;
468 level /= lbpc;
469 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
470 }
471
a9573556 472 tmp = I915_READ(BLC_PWM_CTL);
a726915c 473 if (INTEL_INFO(dev)->gen < 4)
a9573556 474 level <<= 1;
ca88479c 475 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
a9573556
CW		 476 I915_WRITE(BLC_PWM_CTL, tmp | level);
477}
47356eb6 478
d6540632
JN		 479/* set backlight brightness to level in range [0..max] */
480void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
47356eb6
CW		 481{
482 struct drm_i915_private *dev_priv = dev->dev_private;
d6540632 483 u32 freq;
8ba2d185
JN		 484 unsigned long flags;
485
486 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632
JN		 487
488 freq = intel_panel_get_max_backlight(dev);
489 if (!freq) {
490 /* we are screwed, bail out */
8ba2d185 491 goto out;
d6540632
JN		 492 }
493
494 /* scale to hardware */
495 level = level * freq / max;
47356eb6 496
31ad8ec6
JN		 497 dev_priv->backlight.level = level;
498 if (dev_priv->backlight.device)
499 dev_priv->backlight.device->props.brightness = level;
b6b3ba5b 500
31ad8ec6 501 if (dev_priv->backlight.enabled)
f52c619a 502 intel_panel_actually_set_backlight(dev, level);
8ba2d185
JN		 503out:
504 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
f52c619a
TI		 505}
506
507void intel_panel_disable_backlight(struct drm_device *dev)
508{
509 struct drm_i915_private *dev_priv = dev->dev_private;
8ba2d185
JN		 510 unsigned long flags;
511
512 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 513
31ad8ec6 514 dev_priv->backlight.enabled = false;
f52c619a 515 intel_panel_actually_set_backlight(dev, 0);
24ded204
DV		 516
517 if (INTEL_INFO(dev)->gen >= 4) {
a4f32fc3 518 uint32_t reg, tmp;
24ded204
DV		 519
520 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
521
522 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
a4f32fc3
PZ		 523
524 if (HAS_PCH_SPLIT(dev)) {
525 tmp = I915_READ(BLC_PWM_PCH_CTL1);
526 tmp &= ~BLM_PCH_PWM_ENABLE;
527 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
528 }
24ded204 529 }
8ba2d185
JN		 530
531 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW		 532}
533
24ded204
DV		 534void intel_panel_enable_backlight(struct drm_device *dev,
535 enum pipe pipe)
47356eb6
CW		 536{
537 struct drm_i915_private *dev_priv = dev->dev_private;
35ffda48
JN		 538 enum transcoder cpu_transcoder =
539 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
8ba2d185
JN		 540 unsigned long flags;
541
542 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 543
31ad8ec6
JN		 544 if (dev_priv->backlight.level == 0) {
545 dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
546 if (dev_priv->backlight.device)
547 dev_priv->backlight.device->props.brightness =
548 dev_priv->backlight.level;
b6b3ba5b 549 }
47356eb6 550
24ded204
DV		 551 if (INTEL_INFO(dev)->gen >= 4) {
552 uint32_t reg, tmp;
553
554 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
555
556
557 tmp = I915_READ(reg);
558
559 /* Note that this can also get called through dpms changes. And
560 * we don't track the backlight dpms state, hence check whether
561 * we have to do anything first. */
562 if (tmp & BLM_PWM_ENABLE)
770c1231 563 goto set_level;
24ded204 564
7eb552ae 565 if (INTEL_INFO(dev)->num_pipes == 3)
24ded204
DV		 566 tmp &= ~BLM_PIPE_SELECT_IVB;
567 else
568 tmp &= ~BLM_PIPE_SELECT;
569
35ffda48
JN		 570 if (cpu_transcoder == TRANSCODER_EDP)
571 tmp |= BLM_TRANSCODER_EDP;
572 else
573 tmp |= BLM_PIPE(cpu_transcoder);
24ded204
DV		 574 tmp &= ~BLM_PWM_ENABLE;
575
576 I915_WRITE(reg, tmp);
577 POSTING_READ(reg);
578 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
a4f32fc3
PZ		 579
580 if (HAS_PCH_SPLIT(dev)) {
581 tmp = I915_READ(BLC_PWM_PCH_CTL1);
582 tmp |= BLM_PCH_PWM_ENABLE;
583 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
584 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
585 }
24ded204 586 }
770c1231
TI		 587
588set_level:
b1289371
DV		 589 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
590 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
591 * registers are set.
770c1231 592 */
ecb135a1
DV		 593 dev_priv->backlight.enabled = true;
594 intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
8ba2d185
JN		 595
596 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW		 597}
598
aaa6fd2a 599static void intel_panel_init_backlight(struct drm_device *dev)
47356eb6
CW		 600{
601 struct drm_i915_private *dev_priv = dev->dev_private;
602
31ad8ec6
JN		 603 dev_priv->backlight.level = intel_panel_get_backlight(dev);
604 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
47356eb6 605}
fe16d949
CW		 606
607enum drm_connector_status
608intel_panel_detect(struct drm_device *dev)
609{
610 struct drm_i915_private *dev_priv = dev->dev_private;
611
612 /* Assume that the BIOS does not lie through the OpRegion... */
a726915c 613 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
fe16d949
CW		 614 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
615 connector_status_connected :
616 connector_status_disconnected;
a726915c 617 }
fe16d949 618
a726915c
DV		 619 switch (i915_panel_ignore_lid) {
620 case -2:
621 return connector_status_connected;
622 case -1:
623 return connector_status_disconnected;
624 default:
625 return connector_status_unknown;
626 }
fe16d949 627}
aaa6fd2a
MG		 628
629#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
630static int intel_panel_update_status(struct backlight_device *bd)
631{
632 struct drm_device *dev = bl_get_data(bd);
d6540632
JN		 633 intel_panel_set_backlight(dev, bd->props.brightness,
634 bd->props.max_brightness);
aaa6fd2a
MG		 635 return 0;
636}
637
638static int intel_panel_get_brightness(struct backlight_device *bd)
639{
640 struct drm_device *dev = bl_get_data(bd);
7c23396b 641 return intel_panel_get_backlight(dev);
aaa6fd2a
MG		 642}
643
644static const struct backlight_ops intel_panel_bl_ops = {
645 .update_status = intel_panel_update_status,
646 .get_brightness = intel_panel_get_brightness,
647};
648
0657b6b1 649int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 650{
0657b6b1 651 struct drm_device *dev = connector->dev;
aaa6fd2a
MG		 652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct backlight_properties props;
8ba2d185 654 unsigned long flags;
aaa6fd2a
MG		 655
656 intel_panel_init_backlight(dev);
657
dc652f90
JN		 658 if (WARN_ON(dev_priv->backlight.device))
659 return -ENODEV;
660
af437cfd 661 memset(&props, 0, sizeof(props));
aaa6fd2a 662 props.type = BACKLIGHT_RAW;
31ad8ec6 663 props.brightness = dev_priv->backlight.level;
8ba2d185
JN		 664
665 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632 666 props.max_brightness = intel_panel_get_max_backlight(dev);
8ba2d185
JN		 667 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
668
28dcc2d6 669 if (props.max_brightness == 0) {
e86b6185 670 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
28dcc2d6
JN		 671 return -ENODEV;
672 }
31ad8ec6 673 dev_priv->backlight.device =
aaa6fd2a
MG		 674 backlight_device_register("intel_backlight",
675 &connector->kdev, dev,
676 &intel_panel_bl_ops, &props);
677
31ad8ec6 678 if (IS_ERR(dev_priv->backlight.device)) {
aaa6fd2a 679 DRM_ERROR("Failed to register backlight: %ld\n",
31ad8ec6
JN		 680 PTR_ERR(dev_priv->backlight.device));
681 dev_priv->backlight.device = NULL;
aaa6fd2a
MG		 682 return -ENODEV;
683 }
aaa6fd2a
MG		 684 return 0;
685}
686
687void intel_panel_destroy_backlight(struct drm_device *dev)
688{
689 struct drm_i915_private *dev_priv = dev->dev_private;
dc652f90 690 if (dev_priv->backlight.device) {
31ad8ec6 691 backlight_device_unregister(dev_priv->backlight.device);
dc652f90
JN		 692 dev_priv->backlight.device = NULL;
693 }
aaa6fd2a
MG		 694}
695#else
0657b6b1 696int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 697{
0657b6b1 698 intel_panel_init_backlight(connector->dev);
aaa6fd2a
MG		 699 return 0;
700}
701
702void intel_panel_destroy_backlight(struct drm_device *dev)
703{
704 return;
705}
706#endif
1d508706 707
dd06f90e
JN		 708int intel_panel_init(struct intel_panel *panel,
709 struct drm_display_mode *fixed_mode)
1d508706 710{
dd06f90e
JN		 711 panel->fixed_mode = fixed_mode;
712
1d508706
JN		 713 return 0;
714}
715
716void intel_panel_fini(struct intel_panel *panel)
717{
dd06f90e
JN		 718 struct intel_connector *intel_connector =
719 container_of(panel, struct intel_connector, panel);
720
721 if (panel->fixed_mode)
722 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
1d508706 723}
Linux kernel - Deliverables
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