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drm/i915/skl: Ensure pipes with changed wms get added to the state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
367294be 2129 /*
6f97235b
DL		 2130 * WaWmMemoryReadLatency:skl
2131 *
367294be
VK		 2132 * punit doesn't take into account the read latency so we need
2133 * to add 2us to the various latency levels we retrieve from
2134 * the punit.
2135 * - W0 is a bit special in that it's the only level that
2136 * can't be disabled if we want to have display working, so
2137 * we always add 2us there.
2138 * - For levels >=1, punit returns 0us latency when they are
2139 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2140 *
2141 * Additionally, if a level n (n > 1) has a 0us latency, all
2142 * levels m (m >= n) need to be disabled. We make sure to
2143 * sanitize the values out of the punit to satisfy this
2144 * requirement.
367294be
VK		 2145 */
2146 wm[0] += 2;
2147 for (level = 1; level <= max_level; level++)
2148 if (wm[level] != 0)
2149 wm[level] += 2;
4f947386
VK		 2150 else {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
367294be 2153
4f947386
VK		 2154 break;
2155 }
2af30a5c 2156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2157 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159 wm[0] = (sskpd >> 56) & 0xFF;
2160 if (wm[0] == 0)
2161 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2162 wm[1] = (sskpd >> 4) & 0xFF;
2163 wm[2] = (sskpd >> 12) & 0xFF;
2164 wm[3] = (sskpd >> 20) & 0x1FF;
2165 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2166 } else if (INTEL_INFO(dev)->gen >= 6) {
2167 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2173 } else if (INTEL_INFO(dev)->gen >= 5) {
2174 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176 /* ILK primary LP0 latency is 700 ns */
2177 wm[0] = 7;
2178 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2180 }
2181}
2182
53615a5e
VS		 2183static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184{
2185 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2186 if (IS_GEN5(dev))
53615a5e
VS		 2187 wm[0] = 13;
2188}
2189
2190static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191{
2192 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2193 if (IS_GEN5(dev))
53615a5e
VS		 2194 wm[0] = 13;
2195
2196 /* WaDoubleCursorLP3Latency:ivb */
2197 if (IS_IVYBRIDGE(dev))
2198 wm[3] *= 2;
2199}
2200
546c81fd 2201int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2202{
26ec971e 2203 /* how many WM levels are we expecting */
b6e742f6 2204 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2205 return 7;
2206 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2207 return 4;
26ec971e 2208 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2209 return 3;
26ec971e 2210 else
ad0d6dc4
VS		 2211 return 2;
2212}
7526ed79 2213
ad0d6dc4
VS		 2214static void intel_print_wm_latency(struct drm_device *dev,
2215 const char *name,
2af30a5c 2216 const uint16_t wm[8])
ad0d6dc4
VS		 2217{
2218 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2219
2220 for (level = 0; level <= max_level; level++) {
2221 unsigned int latency = wm[level];
2222
2223 if (latency == 0) {
2224 DRM_ERROR("%s WM%d latency not provided\n",
2225 name, level);
2226 continue;
2227 }
2228
2af30a5c
PB		 2229 /*
2230 * - latencies are in us on gen9.
2231 * - before then, WM1+ latency values are in 0.5us units
2232 */
2233 if (IS_GEN9(dev))
2234 latency *= 10;
2235 else if (level > 0)
26ec971e
VS		 2236 latency *= 5;
2237
2238 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239 name, level, wm[level],
2240 latency / 10, latency % 10);
2241 }
2242}
2243
e95a2f75
VS		 2244static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245 uint16_t wm[5], uint16_t min)
2246{
91c8a326 2247 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2248
2249 if (wm[0] >= min)
2250 return false;
2251
2252 wm[0] = max(wm[0], min);
2253 for (level = 1; level <= max_level; level++)
2254 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256 return true;
2257}
2258
2259static void snb_wm_latency_quirk(struct drm_device *dev)
2260{
fac5e23e 2261 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2262 bool changed;
2263
2264 /*
2265 * The BIOS provided WM memory latency values are often
2266 * inadequate for high resolution displays. Adjust them.
2267 */
2268 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272 if (!changed)
2273 return;
2274
2275 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279}
2280
fa50ad61 2281static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2282{
fac5e23e 2283 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2284
2285 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288 sizeof(dev_priv->wm.pri_latency));
2289 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291
2292 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2294
2295 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2298
2299 if (IS_GEN6(dev))
2300 snb_wm_latency_quirk(dev);
53615a5e
VS		 2301}
2302
2af30a5c
PB		 2303static void skl_setup_wm_latency(struct drm_device *dev)
2304{
fac5e23e 2305 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2306
2307 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309}
2310
ed4a6a7c
MR		 2311static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312 struct intel_pipe_wm *pipe_wm)
2313{
2314 /* LP0 watermark maximums depend on this pipe alone */
2315 const struct intel_wm_config config = {
2316 .num_pipes_active = 1,
2317 .sprites_enabled = pipe_wm->sprites_enabled,
2318 .sprites_scaled = pipe_wm->sprites_scaled,
2319 };
2320 struct ilk_wm_maximums max;
2321
2322 /* LP0 watermarks always use 1/2 DDB partitioning */
2323 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325 /* At least LP0 must be valid */
2326 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328 return false;
2329 }
2330
2331 return true;
2332}
2333
0b2ae6d7 2334/* Compute new watermarks for the pipe */
e3bddded 2335static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2336{
e3bddded
ML		 2337 struct drm_atomic_state *state = cstate->base.state;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2339 struct intel_pipe_wm *pipe_wm;
e3bddded 2340 struct drm_device *dev = state->dev;
fac5e23e 2341 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2342 struct intel_plane *intel_plane;
86c8bbbe 2343 struct intel_plane_state *pristate = NULL;
43d59eda 2344 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2345 struct intel_plane_state *curstate = NULL;
d81f04c5 2346 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2347 struct ilk_wm_maximums max;
0b2ae6d7 2348
e8f1f02e 2349 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2350
43d59eda 2351 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2352 struct intel_plane_state *ps;
2353
2354 ps = intel_atomic_get_existing_plane_state(state,
2355 intel_plane);
2356 if (!ps)
2357 continue;
86c8bbbe
MR		 2358
2359 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2360 pristate = ps;
86c8bbbe 2361 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2362 sprstate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2364 curstate = ps;
43d59eda
MR		 2365 }
2366
ed4a6a7c 2367 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2368 if (sprstate) {
936e71e3
VS		 2369 pipe_wm->sprites_enabled = sprstate->base.visible;
2370 pipe_wm->sprites_scaled = sprstate->base.visible &&
2371 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2372 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2373 }
2374
d81f04c5
ML		 2375 usable_level = max_level;
2376
7b39a0b7 2377 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2378 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2379 usable_level = 1;
7b39a0b7
VS		 2380
2381 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2382 if (pipe_wm->sprites_scaled)
d81f04c5 2383 usable_level = 0;
7b39a0b7 2384
86c8bbbe 2385 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2386 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2390
a42a5719 2391 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2392 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2393
ed4a6a7c 2394 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2395 return -EINVAL;
a3cb4048
VS		 2396
2397 ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399 for (level = 1; level <= max_level; level++) {
71f0a626 2400 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2401
86c8bbbe 2402 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2403 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2404
2405 /*
2406 * Disable any watermark level that exceeds the
2407 * register maximums since such watermarks are
2408 * always invalid.
2409 */
71f0a626
ML		 2410 if (level > usable_level)
2411 continue;
2412
2413 if (ilk_validate_wm_level(level, &max, wm))
2414 pipe_wm->wm[level] = *wm;
2415 else
d81f04c5 2416 usable_level = level;
a3cb4048
VS		 2417 }
2418
86c8bbbe 2419 return 0;
0b2ae6d7
VS		 2420}
2421
ed4a6a7c
MR		 2422/*
2423 * Build a set of 'intermediate' watermark values that satisfy both the old
2424 * state and the new state. These can be programmed to the hardware
2425 * immediately.
2426 */
2427static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428 struct intel_crtc *intel_crtc,
2429 struct intel_crtc_state *newstate)
2430{
e8f1f02e 2431 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2432 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433 int level, max_level = ilk_wm_max_level(dev);
2434
2435 /*
2436 * Start with the final, target watermarks, then combine with the
2437 * currently active watermarks to get values that are safe both before
2438 * and after the vblank.
2439 */
e8f1f02e 2440 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2441 a->pipe_enabled |= b->pipe_enabled;
2442 a->sprites_enabled |= b->sprites_enabled;
2443 a->sprites_scaled |= b->sprites_scaled;
2444
2445 for (level = 0; level <= max_level; level++) {
2446 struct intel_wm_level *a_wm = &a->wm[level];
2447 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449 a_wm->enable &= b_wm->enable;
2450 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454 }
2455
2456 /*
2457 * We need to make sure that these merged watermark values are
2458 * actually a valid configuration themselves. If they're not,
2459 * there's no safe way to transition from the old state to
2460 * the new state, so we need to fail the atomic transaction.
2461 */
2462 if (!ilk_validate_pipe_wm(dev, a))
2463 return -EINVAL;
2464
2465 /*
2466 * If our intermediate WM are identical to the final WM, then we can
2467 * omit the post-vblank programming; only update if it's different.
2468 */
e8f1f02e 2469 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2470 newstate->wm.need_postvbl_update = false;
2471
2472 return 0;
2473}
2474
0b2ae6d7
VS		 2475/*
2476 * Merge the watermarks from all active pipes for a specific level.
2477 */
2478static void ilk_merge_wm_level(struct drm_device *dev,
2479 int level,
2480 struct intel_wm_level *ret_wm)
2481{
2482 const struct intel_crtc *intel_crtc;
2483
d52fea5b
VS		 2484 ret_wm->enable = true;
2485
d3fcc808 2486 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2487 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2488 const struct intel_wm_level *wm = &active->wm[level];
2489
2490 if (!active->pipe_enabled)
2491 continue;
0b2ae6d7 2492
d52fea5b
VS		 2493 /*
2494 * The watermark values may have been used in the past,
2495 * so we must maintain them in the registers for some
2496 * time even if the level is now disabled.
2497 */
0b2ae6d7 2498 if (!wm->enable)
d52fea5b 2499 ret_wm->enable = false;
0b2ae6d7
VS		 2500
2501 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505 }
0b2ae6d7
VS		 2506}
2507
2508/*
2509 * Merge all low power watermarks for all active pipes.
2510 */
2511static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2512 const struct intel_wm_config *config,
820c1980 2513 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2514 struct intel_pipe_wm *merged)
2515{
fac5e23e 2516 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2517 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2518 int last_enabled_level = max_level;
0b2ae6d7 2519
0ba22e26
VS		 2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522 config->num_pipes_active > 1)
1204d5ba 2523 last_enabled_level = 0;
0ba22e26 2524
6c8b6c28
VS		 2525 /* ILK: FBC WM must be disabled always */
2526 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2527
2528 /* merge each WM1+ level */
2529 for (level = 1; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 ilk_merge_wm_level(dev, level, wm);
2533
d52fea5b
VS		 2534 if (level > last_enabled_level)
2535 wm->enable = false;
2536 else if (!ilk_validate_wm_level(level, max, wm))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level = level - 1;
0b2ae6d7
VS		 2539
2540 /*
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2543 */
2544 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2545 if (wm->enable)
2546 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2547 wm->fbc_val = 0;
2548 }
2549 }
6c8b6c28
VS		 2550
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552 /*
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2556 */
7733b49b 2557 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2558 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2559 for (level = 2; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 wm->enable = false;
2563 }
2564 }
0b2ae6d7
VS		 2565}
2566
b380ca3c
VS		 2567static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568{
2569 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571}
2572
a68d68ee
VS		 2573/* The value we need to program into the WM_LPx latency field */
2574static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575{
fac5e23e 2576 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2577
a42a5719 2578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2579 return 2 * level;
2580 else
2581 return dev_priv->wm.pri_latency[level];
2582}
2583
820c1980 2584static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2585 const struct intel_pipe_wm *merged,
609cedef 2586 enum intel_ddb_partitioning partitioning,
820c1980 2587 struct ilk_wm_values *results)
801bcfff 2588{
0b2ae6d7
VS		 2589 struct intel_crtc *intel_crtc;
2590 int level, wm_lp;
cca32e9a 2591
0362c781 2592 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2593 results->partitioning = partitioning;
cca32e9a 2594
0b2ae6d7 2595 /* LP1+ register values */
cca32e9a 2596 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2597 const struct intel_wm_level *r;
801bcfff 2598
b380ca3c 2599 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2600
0362c781 2601 r = &merged->wm[level];
cca32e9a 2602
d52fea5b
VS		 2603 /*
2604 * Maintain the watermark values even if the level is
2605 * disabled. Doing otherwise could cause underruns.
2606 */
2607 results->wm_lp[wm_lp - 1] =
a68d68ee 2608 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2609 (r->pri_val << WM1_LP_SR_SHIFT) |
2610 r->cur_val;
2611
d52fea5b
VS		 2612 if (r->enable)
2613 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
416f4727
VS		 2615 if (INTEL_INFO(dev)->gen >= 8)
2616 results->wm_lp[wm_lp - 1] |=
2617 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618 else
2619 results->wm_lp[wm_lp - 1] |=
2620 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
d52fea5b
VS		 2622 /*
2623 * Always set WM1S_LP_EN when spr_val != 0, even if the
2624 * level is disabled. Doing otherwise could cause underruns.
2625 */
6cef2b8a
VS		 2626 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627 WARN_ON(wm_lp != 1);
2628 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629 } else
2630 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2631 }
801bcfff 2632
0b2ae6d7 2633 /* LP0 register values */
d3fcc808 2634 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2635 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2636 const struct intel_wm_level *r =
2637 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2638
2639 if (WARN_ON(!r->enable))
2640 continue;
2641
ed4a6a7c 2642 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2643
0b2ae6d7
VS		 2644 results->wm_pipe[pipe] =
2645 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647 r->cur_val;
801bcfff
PZ		 2648 }
2649}
2650
861f3389
PZ		 2651/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2653static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2654 struct intel_pipe_wm *r1,
2655 struct intel_pipe_wm *r2)
861f3389 2656{
198a1e9b
VS		 2657 int level, max_level = ilk_wm_max_level(dev);
2658 int level1 = 0, level2 = 0;
861f3389 2659
198a1e9b
VS		 2660 for (level = 1; level <= max_level; level++) {
2661 if (r1->wm[level].enable)
2662 level1 = level;
2663 if (r2->wm[level].enable)
2664 level2 = level;
861f3389
PZ		 2665 }
2666
198a1e9b
VS		 2667 if (level1 == level2) {
2668 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2669 return r2;
2670 else
2671 return r1;
198a1e9b 2672 } else if (level1 > level2) {
861f3389
PZ		 2673 return r1;
2674 } else {
2675 return r2;
2676 }
2677}
2678
49a687c4
VS		 2679/* dirty bits used to track which watermarks need changes */
2680#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684#define WM_DIRTY_FBC (1 << 24)
2685#define WM_DIRTY_DDB (1 << 25)
2686
055e393f 2687static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2688 const struct ilk_wm_values *old,
2689 const struct ilk_wm_values *new)
49a687c4
VS		 2690{
2691 unsigned int dirty = 0;
2692 enum pipe pipe;
2693 int wm_lp;
2694
055e393f 2695 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2696 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697 dirty |= WM_DIRTY_LINETIME(pipe);
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2700 }
2701
2702 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703 dirty |= WM_DIRTY_PIPE(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707 }
2708
2709 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710 dirty |= WM_DIRTY_FBC;
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714
2715 if (old->partitioning != new->partitioning) {
2716 dirty |= WM_DIRTY_DDB;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 /* LP1+ watermarks already deemed dirty, no need to continue */
2722 if (dirty & WM_DIRTY_LP_ALL)
2723 return dirty;
2724
2725 /* Find the lowest numbered LP1+ watermark in need of an update... */
2726 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729 break;
2730 }
2731
2732 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733 for (; wm_lp <= 3; wm_lp++)
2734 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736 return dirty;
2737}
2738
8553c18e
VS		 2739static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740 unsigned int dirty)
801bcfff 2741{
820c1980 2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2743 bool changed = false;
801bcfff 2744
facd619b
VS		 2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2748 changed = true;
facd619b
VS		 2749 }
2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2753 changed = true;
facd619b
VS		 2754 }
2755 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2758 changed = true;
facd619b 2759 }
801bcfff 2760
facd619b
VS		 2761 /*
2762 * Don't touch WM1S_LP_EN here.
2763 * Doing so could cause underruns.
2764 */
6cef2b8a 2765
8553c18e
VS		 2766 return changed;
2767}
2768
2769/*
2770 * The spec says we shouldn't write when we don't need, because every write
2771 * causes WMs to be re-evaluated, expending some power.
2772 */
820c1980
ID		 2773static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774 struct ilk_wm_values *results)
8553c18e 2775{
91c8a326 2776 struct drm_device *dev = &dev_priv->drm;
820c1980 2777 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2778 unsigned int dirty;
2779 uint32_t val;
2780
055e393f 2781 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2782 if (!dirty)
2783 return;
2784
2785 _ilk_disable_lp_wm(dev_priv, dirty);
2786
49a687c4 2787 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2788 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2790 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2792 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
49a687c4 2794 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2795 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_DDB) {
a42a5719 2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2803 val = I915_READ(WM_MISC);
2804 if (results->partitioning == INTEL_DDB_PART_1_2)
2805 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806 else
2807 val |= WM_MISC_DATA_PARTITION_5_6;
2808 I915_WRITE(WM_MISC, val);
2809 } else {
2810 val = I915_READ(DISP_ARB_CTL2);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~DISP_DATA_PARTITION_5_6;
2813 else
2814 val |= DISP_DATA_PARTITION_5_6;
2815 I915_WRITE(DISP_ARB_CTL2, val);
2816 }
1011d8c4
PZ		 2817 }
2818
49a687c4 2819 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2820 val = I915_READ(DISP_ARB_CTL);
2821 if (results->enable_fbc_wm)
2822 val &= ~DISP_FBC_WM_DIS;
2823 else
2824 val |= DISP_FBC_WM_DIS;
2825 I915_WRITE(DISP_ARB_CTL, val);
2826 }
2827
954911eb
ID		 2828 if (dirty & WM_DIRTY_LP(1) &&
2829 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837 }
801bcfff 2838
facd619b 2839 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2840 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2841 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2842 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2843 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2844 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2845
2846 dev_priv->wm.hw = *results;
801bcfff
PZ		 2847}
2848
ed4a6a7c 2849bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2850{
fac5e23e 2851 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2852
2853 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854}
2855
b9cec075
DL		 2856/*
2857 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2858 * different active planes.
2859 */
2860
2861#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2862#define BXT_DDB_SIZE 512
656d1b89 2863#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2864
024c9045
MR		 2865/*
2866 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2867 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868 * other universal planes are in indices 1..n. Note that this may leave unused
2869 * indices between the top "sprite" plane and the cursor.
2870 */
2871static int
2872skl_wm_plane_id(const struct intel_plane *plane)
2873{
2874 switch (plane->base.type) {
2875 case DRM_PLANE_TYPE_PRIMARY:
2876 return 0;
2877 case DRM_PLANE_TYPE_CURSOR:
2878 return PLANE_CURSOR;
2879 case DRM_PLANE_TYPE_OVERLAY:
2880 return plane->plane + 1;
2881 default:
2882 MISSING_CASE(plane->base.type);
2883 return plane->plane;
2884 }
2885}
2886
656d1b89
L		 2887/*
2888 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2889 * depending on power and performance requirements. The display engine access
2890 * to system memory is blocked during the adjustment time. Because of the
2891 * blocking time, having this enabled can cause full system hangs and/or pipe
2892 * underruns if we don't meet all of the following requirements:
2893 *
2894 * - <= 1 pipe enabled
2895 * - All planes can enable watermarks for latencies >= SAGV engine block time
2896 * - We're not using an interlaced display configuration
2897 */
2898int
2899skl_enable_sagv(struct drm_i915_private *dev_priv)
2900{
2901 int ret;
2902
2903 if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2904 dev_priv->skl_sagv_status == I915_SKL_SAGV_ENABLED)
2905 return 0;
2906
2907 DRM_DEBUG_KMS("Enabling the SAGV\n");
2908 mutex_lock(&dev_priv->rps.hw_lock);
2909
2910 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2911 GEN9_SAGV_ENABLE);
2912
2913 /* We don't need to wait for the SAGV when enabling */
2914 mutex_unlock(&dev_priv->rps.hw_lock);
2915
2916 /*
2917 * Some skl systems, pre-release machines in particular,
2918 * don't actually have an SAGV.
2919 */
2920 if (ret == -ENXIO) {
2921 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2922 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2923 return 0;
2924 } else if (ret < 0) {
2925 DRM_ERROR("Failed to enable the SAGV\n");
2926 return ret;
2927 }
2928
2929 dev_priv->skl_sagv_status = I915_SKL_SAGV_ENABLED;
2930 return 0;
2931}
2932
2933static int
2934skl_do_sagv_disable(struct drm_i915_private *dev_priv)
2935{
2936 int ret;
2937 uint32_t temp = GEN9_SAGV_DISABLE;
2938
2939 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2940 &temp);
2941 if (ret)
2942 return ret;
2943 else
2944 return temp & GEN9_SAGV_IS_DISABLED;
2945}
2946
2947int
2948skl_disable_sagv(struct drm_i915_private *dev_priv)
2949{
2950 int ret, result;
2951
2952 if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2953 dev_priv->skl_sagv_status == I915_SKL_SAGV_DISABLED)
2954 return 0;
2955
2956 DRM_DEBUG_KMS("Disabling the SAGV\n");
2957 mutex_lock(&dev_priv->rps.hw_lock);
2958
2959 /* bspec says to keep retrying for at least 1 ms */
2960 ret = wait_for(result = skl_do_sagv_disable(dev_priv), 1);
2961 mutex_unlock(&dev_priv->rps.hw_lock);
2962
2963 if (ret == -ETIMEDOUT) {
2964 DRM_ERROR("Request to disable SAGV timed out\n");
2965 return -ETIMEDOUT;
2966 }
2967
2968 /*
2969 * Some skl systems, pre-release machines in particular,
2970 * don't actually have an SAGV.
2971 */
2972 if (result == -ENXIO) {
2973 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2974 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2975 return 0;
2976 } else if (result < 0) {
2977 DRM_ERROR("Failed to disable the SAGV\n");
2978 return result;
2979 }
2980
2981 dev_priv->skl_sagv_status = I915_SKL_SAGV_DISABLED;
2982 return 0;
2983}
2984
2985bool skl_can_enable_sagv(struct drm_atomic_state *state)
2986{
2987 struct drm_device *dev = state->dev;
2988 struct drm_i915_private *dev_priv = to_i915(dev);
2989 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2990 struct drm_crtc *crtc;
2991 enum pipe pipe;
2992 int level, plane;
2993
2994 /*
2995 * SKL workaround: bspec recommends we disable the SAGV when we have
2996 * more then one pipe enabled
2997 *
2998 * If there are no active CRTCs, no additional checks need be performed
2999 */
3000 if (hweight32(intel_state->active_crtcs) == 0)
3001 return true;
3002 else if (hweight32(intel_state->active_crtcs) > 1)
3003 return false;
3004
3005 /* Since we're now guaranteed to only have one active CRTC... */
3006 pipe = ffs(intel_state->active_crtcs) - 1;
3007 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3008
3009 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3010 return false;
3011
3012 for_each_plane(dev_priv, pipe, plane) {
3013 /* Skip this plane if it's not enabled */
3014 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3015 continue;
3016
3017 /* Find the highest enabled wm level for this plane */
3018 for (level = ilk_wm_max_level(dev);
3019 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3020 { }
3021
3022 /*
3023 * If any of the planes on this pipe don't enable wm levels
3024 * that incur memory latencies higher then 30µs we can't enable
3025 * the SAGV
3026 */
3027 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3028 return false;
3029 }
3030
3031 return true;
3032}
3033
b9cec075
DL		 3034static void
3035skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3036 const struct intel_crtc_state *cstate,
c107acfe
MR		 3037 struct skl_ddb_entry *alloc, /* out */
3038 int *num_active /* out */)
b9cec075 3039{
c107acfe
MR		 3040 struct drm_atomic_state *state = cstate->base.state;
3041 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3042 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3043 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3044 unsigned int pipe_size, ddb_size;
3045 int nth_active_pipe;
c107acfe
MR		 3046 int pipe = to_intel_crtc(for_crtc)->pipe;
3047
a6d3460e 3048 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3049 alloc->start = 0;
3050 alloc->end = 0;
a6d3460e 3051 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3052 return;
3053 }
3054
a6d3460e
MR		 3055 if (intel_state->active_pipe_changes)
3056 *num_active = hweight32(intel_state->active_crtcs);
3057 else
3058 *num_active = hweight32(dev_priv->active_crtcs);
3059
43d735a6
DL		 3060 if (IS_BROXTON(dev))
3061 ddb_size = BXT_DDB_SIZE;
3062 else
3063 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 3064
3065 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3066
c107acfe 3067 /*
a6d3460e
MR		 3068 * If the state doesn't change the active CRTC's, then there's
3069 * no need to recalculate; the existing pipe allocation limits
3070 * should remain unchanged. Note that we're safe from racing
3071 * commits since any racing commit that changes the active CRTC
3072 * list would need to grab _all_ crtc locks, including the one
3073 * we currently hold.
c107acfe 3074 */
a6d3460e
MR		 3075 if (!intel_state->active_pipe_changes) {
3076 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3077 return;
c107acfe 3078 }
a6d3460e
MR		 3079
3080 nth_active_pipe = hweight32(intel_state->active_crtcs &
3081 (drm_crtc_mask(for_crtc) - 1));
3082 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3083 alloc->start = nth_active_pipe * ddb_size / *num_active;
3084 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3085}
3086
c107acfe 3087static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3088{
c107acfe 3089 if (num_active == 1)
b9cec075
DL		 3090 return 32;
3091
3092 return 8;
3093}
3094
a269c583
DL		 3095static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3096{
3097 entry->start = reg & 0x3ff;
3098 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3099 if (entry->end)
3100 entry->end += 1;
a269c583
DL		 3101}
3102
08db6652
DL		 3103void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3104 struct skl_ddb_allocation *ddb /* out */)
a269c583 3105{
a269c583
DL		 3106 enum pipe pipe;
3107 int plane;
3108 u32 val;
3109
b10f1b20
ML		 3110 memset(ddb, 0, sizeof(*ddb));
3111
a269c583 3112 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3113 enum intel_display_power_domain power_domain;
3114
3115 power_domain = POWER_DOMAIN_PIPE(pipe);
3116 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3117 continue;
3118
dd740780 3119 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3120 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3121 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3122 val);
3123 }
3124
3125 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3126 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3127 val);
4d800030
ID		 3128
3129 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3130 }
3131}
3132
9c2f7a9d
KM		 3133/*
3134 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3135 * The bspec defines downscale amount as:
3136 *
3137 * """
3138 * Horizontal down scale amount = maximum[1, Horizontal source size /
3139 * Horizontal destination size]
3140 * Vertical down scale amount = maximum[1, Vertical source size /
3141 * Vertical destination size]
3142 * Total down scale amount = Horizontal down scale amount *
3143 * Vertical down scale amount
3144 * """
3145 *
3146 * Return value is provided in 16.16 fixed point form to retain fractional part.
3147 * Caller should take care of dividing & rounding off the value.
3148 */
3149static uint32_t
3150skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3151{
3152 uint32_t downscale_h, downscale_w;
3153 uint32_t src_w, src_h, dst_w, dst_h;
3154
936e71e3 3155 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3156 return DRM_PLANE_HELPER_NO_SCALING;
3157
3158 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3159 src_w = drm_rect_width(&pstate->base.src);
3160 src_h = drm_rect_height(&pstate->base.src);
3161 dst_w = drm_rect_width(&pstate->base.dst);
3162 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3163 if (intel_rotation_90_or_270(pstate->base.rotation))
3164 swap(dst_w, dst_h);
3165
3166 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3167 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3168
3169 /* Provide result in 16.16 fixed point */
3170 return (uint64_t)downscale_w * downscale_h >> 16;
3171}
3172
b9cec075 3173static unsigned int
024c9045
MR		 3174skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3175 const struct drm_plane_state *pstate,
3176 int y)
b9cec075 3177{
a280f7dd 3178 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3179 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3180 uint32_t down_scale_amount, data_rate;
a280f7dd 3181 uint32_t width = 0, height = 0;
a1de91e5
MR		 3182 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3183
936e71e3 3184 if (!intel_pstate->base.visible)
a1de91e5
MR		 3185 return 0;
3186 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3187 return 0;
3188 if (y && format != DRM_FORMAT_NV12)
3189 return 0;
a280f7dd 3190
936e71e3
VS		 3191 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3192 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3193
3194 if (intel_rotation_90_or_270(pstate->rotation))
3195 swap(width, height);
2cd601c6
CK		 3196
3197 /* for planar format */
a1de91e5 3198 if (format == DRM_FORMAT_NV12) {
2cd601c6 3199 if (y) /* y-plane data rate */
8d19d7d9 3200 data_rate = width * height *
a1de91e5 3201 drm_format_plane_cpp(format, 0);
2cd601c6 3202 else /* uv-plane data rate */
8d19d7d9 3203 data_rate = (width / 2) * (height / 2) *
a1de91e5 3204 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3205 } else {
3206 /* for packed formats */
3207 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3208 }
3209
8d19d7d9
KM		 3210 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3211
3212 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3213}
3214
3215/*
3216 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3217 * a 8192x4096@32bpp framebuffer:
3218 * 3 * 4096 * 8192 * 4 < 2^32
3219 */
3220static unsigned int
9c74d826 3221skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3222{
9c74d826
MR		 3223 struct drm_crtc_state *cstate = &intel_cstate->base;
3224 struct drm_atomic_state *state = cstate->state;
3225 struct drm_crtc *crtc = cstate->crtc;
3226 struct drm_device *dev = crtc->dev;
3227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3228 const struct drm_plane *plane;
024c9045 3229 const struct intel_plane *intel_plane;
a6d3460e 3230 struct drm_plane_state *pstate;
a1de91e5 3231 unsigned int rate, total_data_rate = 0;
9c74d826 3232 int id;
a6d3460e
MR		 3233 int i;
3234
3235 if (WARN_ON(!state))
3236 return 0;
b9cec075 3237
a1de91e5 3238 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3239 for_each_plane_in_state(state, plane, pstate, i) {
3240 id = skl_wm_plane_id(to_intel_plane(plane));
3241 intel_plane = to_intel_plane(plane);
3242
3243 if (intel_plane->pipe != intel_crtc->pipe)
3244 continue;
3245
3246 /* packed/uv */
3247 rate = skl_plane_relative_data_rate(intel_cstate,
3248 pstate, 0);
3249 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3250
3251 /* y-plane */
3252 rate = skl_plane_relative_data_rate(intel_cstate,
3253 pstate, 1);
3254 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3255 }
024c9045 3256
a1de91e5
MR		 3257 /* Calculate CRTC's total data rate from cached values */
3258 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3259 int id = skl_wm_plane_id(intel_plane);
024c9045 3260
a1de91e5 3261 /* packed/uv */
9c74d826
MR		 3262 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3263 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3264 }
3265
3266 return total_data_rate;
3267}
3268
cbcfd14b
KM		 3269static uint16_t
3270skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3271 const int y)
3272{
3273 struct drm_framebuffer *fb = pstate->fb;
3274 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3275 uint32_t src_w, src_h;
3276 uint32_t min_scanlines = 8;
3277 uint8_t plane_bpp;
3278
3279 if (WARN_ON(!fb))
3280 return 0;
3281
3282 /* For packed formats, no y-plane, return 0 */
3283 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3284 return 0;
3285
3286 /* For Non Y-tile return 8-blocks */
3287 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3288 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3289 return 8;
3290
936e71e3
VS		 3291 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3292 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3293
3294 if (intel_rotation_90_or_270(pstate->rotation))
3295 swap(src_w, src_h);
3296
3297 /* Halve UV plane width and height for NV12 */
3298 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3299 src_w /= 2;
3300 src_h /= 2;
3301 }
3302
3303 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3304 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3305 else
3306 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3307
3308 if (intel_rotation_90_or_270(pstate->rotation)) {
3309 switch (plane_bpp) {
3310 case 1:
3311 min_scanlines = 32;
3312 break;
3313 case 2:
3314 min_scanlines = 16;
3315 break;
3316 case 4:
3317 min_scanlines = 8;
3318 break;
3319 case 8:
3320 min_scanlines = 4;
3321 break;
3322 default:
3323 WARN(1, "Unsupported pixel depth %u for rotation",
3324 plane_bpp);
3325 min_scanlines = 32;
3326 }
3327 }
3328
3329 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3330}
3331
c107acfe 3332static int
024c9045 3333skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3334 struct skl_ddb_allocation *ddb /* out */)
3335{
c107acfe 3336 struct drm_atomic_state *state = cstate->base.state;
024c9045 3337 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3338 struct drm_device *dev = crtc->dev;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3340 struct intel_plane *intel_plane;
c107acfe
MR		 3341 struct drm_plane *plane;
3342 struct drm_plane_state *pstate;
b9cec075 3343 enum pipe pipe = intel_crtc->pipe;
34bb56af 3344 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3345 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3346 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3347 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3348 unsigned int total_data_rate;
c107acfe
MR		 3349 int num_active;
3350 int id, i;
b9cec075 3351
a6d3460e
MR		 3352 if (WARN_ON(!state))
3353 return 0;
3354
c107acfe
MR		 3355 if (!cstate->base.active) {
3356 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3357 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3358 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3359 return 0;
3360 }
3361
a6d3460e 3362 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3363 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3364 if (alloc_size == 0) {
3365 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3366 return 0;
b9cec075
DL		 3367 }
3368
c107acfe 3369 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3370 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3371 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3372
3373 alloc_size -= cursor_blocks;
b9cec075 3374
80958155 3375 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3376 for_each_plane_in_state(state, plane, pstate, i) {
3377 intel_plane = to_intel_plane(plane);
3378 id = skl_wm_plane_id(intel_plane);
c107acfe 3379
a6d3460e
MR		 3380 if (intel_plane->pipe != pipe)
3381 continue;
c107acfe 3382
936e71e3 3383 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3384 minimum[id] = 0;
3385 y_minimum[id] = 0;
3386 continue;
3387 }
3388 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3389 minimum[id] = 0;
3390 y_minimum[id] = 0;
3391 continue;
c107acfe 3392 }
a6d3460e 3393
cbcfd14b
KM		 3394 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3395 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3396 }
80958155 3397
c107acfe
MR		 3398 for (i = 0; i < PLANE_CURSOR; i++) {
3399 alloc_size -= minimum[i];
3400 alloc_size -= y_minimum[i];
80958155
DL		 3401 }
3402
b9cec075 3403 /*
80958155
DL		 3404 * 2. Distribute the remaining space in proportion to the amount of
3405 * data each plane needs to fetch from memory.
b9cec075
DL		 3406 *
3407 * FIXME: we may not allocate every single block here.
3408 */
024c9045 3409 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3410 if (total_data_rate == 0)
c107acfe 3411 return 0;
b9cec075 3412
34bb56af 3413 start = alloc->start;
024c9045 3414 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3415 unsigned int data_rate, y_data_rate;
3416 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3417 int id = skl_wm_plane_id(intel_plane);
b9cec075 3418
a1de91e5 3419 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3420
3421 /*
2cd601c6 3422 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3423 * promote the expression to 64 bits to avoid overflowing, the
3424 * result is < available as data_rate / total_data_rate < 1
3425 */
024c9045 3426 plane_blocks = minimum[id];
80958155
DL		 3427 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3428 total_data_rate);
b9cec075 3429
c107acfe
MR		 3430 /* Leave disabled planes at (0,0) */
3431 if (data_rate) {
3432 ddb->plane[pipe][id].start = start;
3433 ddb->plane[pipe][id].end = start + plane_blocks;
3434 }
b9cec075
DL		 3435
3436 start += plane_blocks;
2cd601c6
CK		 3437
3438 /*
3439 * allocation for y_plane part of planar format:
3440 */
a1de91e5
MR		 3441 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3442
3443 y_plane_blocks = y_minimum[id];
3444 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3445 total_data_rate);
2cd601c6 3446
c107acfe
MR		 3447 if (y_data_rate) {
3448 ddb->y_plane[pipe][id].start = start;
3449 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3450 }
a1de91e5
MR		 3451
3452 start += y_plane_blocks;
b9cec075
DL		 3453 }
3454
c107acfe 3455 return 0;
b9cec075
DL		 3456}
3457
5cec258b 3458static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3459{
3460 /* TODO: Take into account the scalers once we support them */
2d112de7 3461 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3462}
3463
3464/*
3465 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3466 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3467 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3468 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3469*/
ac484963 3470static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3471{
3472 uint32_t wm_intermediate_val, ret;
3473
3474 if (latency == 0)
3475 return UINT_MAX;
3476
ac484963 3477 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3478 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3479
3480 return ret;
3481}
3482
3483static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3484 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3485 uint64_t tiling, uint32_t latency)
2d41c0b5 3486{
d4c2aa60
TU		 3487 uint32_t ret;
3488 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3489 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3490
3491 if (latency == 0)
3492 return UINT_MAX;
3493
ac484963 3494 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3495
3496 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3497 tiling == I915_FORMAT_MOD_Yf_TILED) {
3498 plane_bytes_per_line *= 4;
3499 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3500 plane_blocks_per_line /= 4;
055c3ff6
MR		 3501 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3502 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3503 } else {
3504 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3505 }
3506
2d41c0b5
PB		 3507 wm_intermediate_val = latency * pixel_rate;
3508 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3509 plane_blocks_per_line;
2d41c0b5
PB		 3510
3511 return ret;
3512}
3513
9c2f7a9d
KM		 3514static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3515 struct intel_plane_state *pstate)
3516{
3517 uint64_t adjusted_pixel_rate;
3518 uint64_t downscale_amount;
3519 uint64_t pixel_rate;
3520
3521 /* Shouldn't reach here on disabled planes... */
936e71e3 3522 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3523 return 0;
3524
3525 /*
3526 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3527 * with additional adjustments for plane-specific scaling.
3528 */
3529 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3530 downscale_amount = skl_plane_downscale_amount(pstate);
3531
3532 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3533 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3534
3535 return pixel_rate;
3536}
3537
55994c2c
MR		 3538static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3539 struct intel_crtc_state *cstate,
3540 struct intel_plane_state *intel_pstate,
3541 uint16_t ddb_allocation,
3542 int level,
3543 uint16_t *out_blocks, /* out */
3544 uint8_t *out_lines, /* out */
3545 bool *enabled /* out */)
2d41c0b5 3546{
33815fa5
MR		 3547 struct drm_plane_state *pstate = &intel_pstate->base;
3548 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3549 uint32_t latency = dev_priv->wm.skl_latency[level];
3550 uint32_t method1, method2;
3551 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3552 uint32_t res_blocks, res_lines;
3553 uint32_t selected_result;
ac484963 3554 uint8_t cpp;
a280f7dd 3555 uint32_t width = 0, height = 0;
9c2f7a9d 3556 uint32_t plane_pixel_rate;
2d41c0b5 3557
936e71e3 3558 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3559 *enabled = false;
3560 return 0;
3561 }
2d41c0b5 3562
936e71e3
VS		 3563 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3564 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3565
33815fa5 3566 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3567 swap(width, height);
3568
ac484963 3569 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3570 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3571
3572 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3573 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3574 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3575 width,
3576 cpp,
3577 fb->modifier[0],
d4c2aa60 3578 latency);
2d41c0b5 3579
a280f7dd 3580 plane_bytes_per_line = width * cpp;
d4c2aa60 3581 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3582
024c9045
MR		 3583 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3584 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3585 uint32_t min_scanlines = 4;
3586 uint32_t y_tile_minimum;
33815fa5 3587 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3588 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3589 drm_format_plane_cpp(fb->pixel_format, 1) :
3590 drm_format_plane_cpp(fb->pixel_format, 0);
3591
ac484963 3592 switch (cpp) {
1fc0a8f7
TU		 3593 case 1:
3594 min_scanlines = 16;
3595 break;
3596 case 2:
3597 min_scanlines = 8;
3598 break;
3599 case 8:
3600 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3601 }
1fc0a8f7
TU		 3602 }
3603 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3604 selected_result = max(method2, y_tile_minimum);
3605 } else {
3606 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3607 selected_result = min(method1, method2);
3608 else
3609 selected_result = method1;
3610 }
2d41c0b5 3611
d4c2aa60
TU		 3612 res_blocks = selected_result + 1;
3613 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3614
0fda6568 3615 if (level >= 1 && level <= 7) {
024c9045
MR		 3616 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3617 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3618 res_lines += 4;
3619 else
3620 res_blocks++;
3621 }
e6d66171 3622
55994c2c
MR		 3623 if (res_blocks >= ddb_allocation || res_lines > 31) {
3624 *enabled = false;
6b6bada7
MR		 3625
3626 /*
3627 * If there are no valid level 0 watermarks, then we can't
3628 * support this display configuration.
3629 */
3630 if (level) {
3631 return 0;
3632 } else {
3633 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3634 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3635 to_intel_crtc(cstate->base.crtc)->pipe,
3636 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3637 res_blocks, ddb_allocation, res_lines);
3638
3639 return -EINVAL;
3640 }
55994c2c 3641 }
e6d66171
DL		 3642
3643 *out_blocks = res_blocks;
3644 *out_lines = res_lines;
55994c2c 3645 *enabled = true;
2d41c0b5 3646
55994c2c 3647 return 0;
2d41c0b5
PB		 3648}
3649
f4a96752
MR		 3650static int
3651skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3652 struct skl_ddb_allocation *ddb,
3653 struct intel_crtc_state *cstate,
3654 int level,
3655 struct skl_wm_level *result)
2d41c0b5 3656{
f4a96752 3657 struct drm_atomic_state *state = cstate->base.state;
024c9045 3658 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3659 struct drm_plane *plane;
024c9045 3660 struct intel_plane *intel_plane;
33815fa5 3661 struct intel_plane_state *intel_pstate;
2d41c0b5 3662 uint16_t ddb_blocks;
024c9045 3663 enum pipe pipe = intel_crtc->pipe;
55994c2c 3664 int ret;
024c9045 3665
f4a96752
MR		 3666 /*
3667 * We'll only calculate watermarks for planes that are actually
3668 * enabled, so make sure all other planes are set as disabled.
3669 */
3670 memset(result, 0, sizeof(*result));
3671
91c8a326
CW		 3672 for_each_intel_plane_mask(&dev_priv->drm,
3673 intel_plane,
3674 cstate->base.plane_mask) {
024c9045 3675 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3676
f4a96752
MR		 3677 plane = &intel_plane->base;
3678 intel_pstate = NULL;
3679 if (state)
3680 intel_pstate =
3681 intel_atomic_get_existing_plane_state(state,
3682 intel_plane);
3683
3684 /*
3685 * Note: If we start supporting multiple pending atomic commits
3686 * against the same planes/CRTC's in the future, plane->state
3687 * will no longer be the correct pre-state to use for the
3688 * calculations here and we'll need to change where we get the
3689 * 'unchanged' plane data from.
3690 *
3691 * For now this is fine because we only allow one queued commit
3692 * against a CRTC. Even if the plane isn't modified by this
3693 * transaction and we don't have a plane lock, we still have
3694 * the CRTC's lock, so we know that no other transactions are
3695 * racing with us to update it.
3696 */
3697 if (!intel_pstate)
3698 intel_pstate = to_intel_plane_state(plane->state);
3699
3700 WARN_ON(!intel_pstate->base.fb);
3701
2d41c0b5
PB		 3702 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3703
55994c2c
MR		 3704 ret = skl_compute_plane_wm(dev_priv,
3705 cstate,
3706 intel_pstate,
3707 ddb_blocks,
3708 level,
3709 &result->plane_res_b[i],
3710 &result->plane_res_l[i],
3711 &result->plane_en[i]);
3712 if (ret)
3713 return ret;
2d41c0b5 3714 }
f4a96752
MR		 3715
3716 return 0;
2d41c0b5
PB		 3717}
3718
407b50f3 3719static uint32_t
024c9045 3720skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3721{
024c9045 3722 if (!cstate->base.active)
407b50f3
DL		 3723 return 0;
3724
024c9045 3725 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3726 return 0;
407b50f3 3727
024c9045
MR		 3728 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3729 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3730}
3731
024c9045 3732static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3733 struct skl_wm_level *trans_wm /* out */)
407b50f3 3734{
024c9045 3735 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3737 struct intel_plane *intel_plane;
9414f563 3738
024c9045 3739 if (!cstate->base.active)
407b50f3 3740 return;
9414f563
DL		 3741
3742 /* Until we know more, just disable transition WMs */
024c9045
MR		 3743 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3744 int i = skl_wm_plane_id(intel_plane);
3745
9414f563 3746 trans_wm->plane_en[i] = false;
024c9045 3747 }
407b50f3
DL		 3748}
3749
55994c2c
MR		 3750static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3751 struct skl_ddb_allocation *ddb,
3752 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3753{
024c9045 3754 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3755 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3756 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3757 int ret;
2d41c0b5
PB		 3758
3759 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3760 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3761 level, &pipe_wm->wm[level]);
3762 if (ret)
3763 return ret;
2d41c0b5 3764 }
024c9045 3765 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3766
024c9045 3767 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3768
3769 return 0;
2d41c0b5
PB		 3770}
3771
3772static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3773 struct skl_pipe_wm *p_wm,
3774 struct skl_wm_values *r,
3775 struct intel_crtc *intel_crtc)
3776{
3777 int level, max_level = ilk_wm_max_level(dev);
3778 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3779 uint32_t temp;
3780 int i;
2d41c0b5
PB		 3781
3782 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3783 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3784 temp = 0;
2d41c0b5
PB		 3785
3786 temp |= p_wm->wm[level].plane_res_l[i] <<
3787 PLANE_WM_LINES_SHIFT;
3788 temp |= p_wm->wm[level].plane_res_b[i];
3789 if (p_wm->wm[level].plane_en[i])
3790 temp |= PLANE_WM_EN;
3791
3792 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3793 }
3794
3795 temp = 0;
2d41c0b5 3796
4969d33e
MR		 3797 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3798 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3799
4969d33e 3800 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3801 temp |= PLANE_WM_EN;
3802
4969d33e 3803 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3804
3805 }
3806
9414f563
DL		 3807 /* transition WMs */
3808 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3809 temp = 0;
3810 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3811 temp |= p_wm->trans_wm.plane_res_b[i];
3812 if (p_wm->trans_wm.plane_en[i])
3813 temp |= PLANE_WM_EN;
3814
3815 r->plane_trans[pipe][i] = temp;
3816 }
3817
3818 temp = 0;
4969d33e
MR		 3819 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3820 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3821 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3822 temp |= PLANE_WM_EN;
3823
4969d33e 3824 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3825
2d41c0b5
PB		 3826 r->wm_linetime[pipe] = p_wm->linetime;
3827}
3828
f0f59a00
VS		 3829static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3830 i915_reg_t reg,
16160e3d
DL		 3831 const struct skl_ddb_entry *entry)
3832{
3833 if (entry->end)
3834 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3835 else
3836 I915_WRITE(reg, 0);
3837}
3838
2d41c0b5
PB		 3839static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3840 const struct skl_wm_values *new)
3841{
91c8a326 3842 struct drm_device *dev = &dev_priv->drm;
2d41c0b5
PB		 3843 struct intel_crtc *crtc;
3844
19c8054c 3845 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3846 int i, level, max_level = ilk_wm_max_level(dev);
3847 enum pipe pipe = crtc->pipe;
3848
2b4b9f35 3849 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3850 continue;
734fa01f
MR		 3851 if (!crtc->active)
3852 continue;
8211bd5b 3853
5d374d96 3854 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3855
5d374d96
DL		 3856 for (level = 0; level <= max_level; level++) {
3857 for (i = 0; i < intel_num_planes(crtc); i++)
3858 I915_WRITE(PLANE_WM(pipe, i, level),
3859 new->plane[pipe][i][level]);
3860 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3861 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3862 }
5d374d96
DL		 3863 for (i = 0; i < intel_num_planes(crtc); i++)
3864 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3865 new->plane_trans[pipe][i]);
4969d33e
MR		 3866 I915_WRITE(CUR_WM_TRANS(pipe),
3867 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3868
2cd601c6 3869 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3870 skl_ddb_entry_write(dev_priv,
3871 PLANE_BUF_CFG(pipe, i),
3872 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3873 skl_ddb_entry_write(dev_priv,
3874 PLANE_NV12_BUF_CFG(pipe, i),
3875 &new->ddb.y_plane[pipe][i]);
3876 }
5d374d96
DL		 3877
3878 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3879 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3880 }
2d41c0b5
PB		 3881}
3882
0e8fb7ba
DL		 3883/*
3884 * When setting up a new DDB allocation arrangement, we need to correctly
3885 * sequence the times at which the new allocations for the pipes are taken into
3886 * account or we'll have pipes fetching from space previously allocated to
3887 * another pipe.
3888 *
3889 * Roughly the sequence looks like:
3890 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3891 * overlapping with a previous light-up pipe (another way to put it is:
3892 * pipes with their new allocation strickly included into their old ones).
3893 * 2. re-allocate the other pipes that get their allocation reduced
3894 * 3. allocate the pipes having their allocation increased
3895 *
3896 * Steps 1. and 2. are here to take care of the following case:
3897 * - Initially DDB looks like this:
3898 * | B | C |
3899 * - enable pipe A.
3900 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3901 * allocation
3902 * | A | B | C |
3903 *
3904 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3905 */
3906
d21b795c
DL		 3907static void
3908skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3909{
0e8fb7ba
DL		 3910 int plane;
3911
d21b795c
DL		 3912 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3913
dd740780 3914 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3915 I915_WRITE(PLANE_SURF(pipe, plane),
3916 I915_READ(PLANE_SURF(pipe, plane)));
3917 }
3918 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3919}
3920
3921static bool
3922skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3923 const struct skl_ddb_allocation *new,
3924 enum pipe pipe)
3925{
3926 uint16_t old_size, new_size;
3927
3928 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3929 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3930
3931 return old_size != new_size &&
3932 new->pipe[pipe].start >= old->pipe[pipe].start &&
3933 new->pipe[pipe].end <= old->pipe[pipe].end;
3934}
3935
3936static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3937 struct skl_wm_values *new_values)
3938{
91c8a326 3939 struct drm_device *dev = &dev_priv->drm;
0e8fb7ba 3940 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3941 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3942 struct intel_crtc *crtc;
3943 enum pipe pipe;
3944
3945 new_ddb = &new_values->ddb;
3946 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3947
3948 /*
3949 * First pass: flush the pipes with the new allocation contained into
3950 * the old space.
3951 *
3952 * We'll wait for the vblank on those pipes to ensure we can safely
3953 * re-allocate the freed space without this pipe fetching from it.
3954 */
3955 for_each_intel_crtc(dev, crtc) {
3956 if (!crtc->active)
3957 continue;
3958
3959 pipe = crtc->pipe;
3960
3961 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3962 continue;
3963
d21b795c 3964 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3965 intel_wait_for_vblank(dev, pipe);
3966
3967 reallocated[pipe] = true;
3968 }
3969
3970
3971 /*
3972 * Second pass: flush the pipes that are having their allocation
3973 * reduced, but overlapping with a previous allocation.
3974 *
3975 * Here as well we need to wait for the vblank to make sure the freed
3976 * space is not used anymore.
3977 */
3978 for_each_intel_crtc(dev, crtc) {
3979 if (!crtc->active)
3980 continue;
3981
3982 pipe = crtc->pipe;
3983
3984 if (reallocated[pipe])
3985 continue;
3986
3987 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3988 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3989 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3990 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3991 reallocated[pipe] = true;
0e8fb7ba 3992 }
0e8fb7ba
DL		 3993 }
3994
3995 /*
3996 * Third pass: flush the pipes that got more space allocated.
3997 *
3998 * We don't need to actively wait for the update here, next vblank
3999 * will just get more DDB space with the correct WM values.
4000 */
4001 for_each_intel_crtc(dev, crtc) {
4002 if (!crtc->active)
4003 continue;
4004
4005 pipe = crtc->pipe;
4006
4007 /*
4008 * At this point, only the pipes more space than before are
4009 * left to re-allocate.
4010 */
4011 if (reallocated[pipe])
4012 continue;
4013
d21b795c 4014 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 4015 }
4016}
4017
55994c2c
MR		 4018static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
4019 struct skl_ddb_allocation *ddb, /* out */
4020 struct skl_pipe_wm *pipe_wm, /* out */
4021 bool *changed /* out */)
2d41c0b5 4022{
f4a96752
MR		 4023 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
4024 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 4025 int ret;
2d41c0b5 4026
55994c2c
MR		 4027 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
4028 if (ret)
4029 return ret;
2d41c0b5 4030
4e0963c7 4031 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 4032 *changed = false;
4033 else
4034 *changed = true;
2d41c0b5 4035
55994c2c 4036 return 0;
2d41c0b5
PB		 4037}
4038
9b613022
MR		 4039static uint32_t
4040pipes_modified(struct drm_atomic_state *state)
4041{
4042 struct drm_crtc *crtc;
4043 struct drm_crtc_state *cstate;
4044 uint32_t i, ret = 0;
4045
4046 for_each_crtc_in_state(state, crtc, cstate, i)
4047 ret |= drm_crtc_mask(crtc);
4048
4049 return ret;
4050}
4051
98d39494
MR		 4052static int
4053skl_compute_ddb(struct drm_atomic_state *state)
4054{
4055 struct drm_device *dev = state->dev;
4056 struct drm_i915_private *dev_priv = to_i915(dev);
4057 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4058 struct intel_crtc *intel_crtc;
734fa01f 4059 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4060 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4061 int ret;
4062
4063 /*
4064 * If this is our first atomic update following hardware readout,
4065 * we can't trust the DDB that the BIOS programmed for us. Let's
4066 * pretend that all pipes switched active status so that we'll
4067 * ensure a full DDB recompute.
4068 */
1b54a880
MR		 4069 if (dev_priv->wm.distrust_bios_wm) {
4070 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4071 state->acquire_ctx);
4072 if (ret)
4073 return ret;
4074
98d39494
MR		 4075 intel_state->active_pipe_changes = ~0;
4076
1b54a880
MR		 4077 /*
4078 * We usually only initialize intel_state->active_crtcs if we
4079 * we're doing a modeset; make sure this field is always
4080 * initialized during the sanitization process that happens
4081 * on the first commit too.
4082 */
4083 if (!intel_state->modeset)
4084 intel_state->active_crtcs = dev_priv->active_crtcs;
4085 }
4086
98d39494
MR		 4087 /*
4088 * If the modeset changes which CRTC's are active, we need to
4089 * recompute the DDB allocation for *all* active pipes, even
4090 * those that weren't otherwise being modified in any way by this
4091 * atomic commit. Due to the shrinking of the per-pipe allocations
4092 * when new active CRTC's are added, it's possible for a pipe that
4093 * we were already using and aren't changing at all here to suddenly
4094 * become invalid if its DDB needs exceeds its new allocation.
4095 *
4096 * Note that if we wind up doing a full DDB recompute, we can't let
4097 * any other display updates race with this transaction, so we need
4098 * to grab the lock on *all* CRTC's.
4099 */
734fa01f 4100 if (intel_state->active_pipe_changes) {
98d39494 4101 realloc_pipes = ~0;
734fa01f
MR		 4102 intel_state->wm_results.dirty_pipes = ~0;
4103 }
98d39494
MR		 4104
4105 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4106 struct intel_crtc_state *cstate;
4107
4108 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4109 if (IS_ERR(cstate))
4110 return PTR_ERR(cstate);
4111
734fa01f 4112 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4113 if (ret)
4114 return ret;
05a76d3d
L		 4115
4116 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4117 if (ret)
4118 return ret;
98d39494
MR		 4119 }
4120
4121 return 0;
4122}
4123
2722efb9
MR		 4124static void
4125skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4126 struct skl_wm_values *src,
4127 enum pipe pipe)
4128{
4129 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4130 memcpy(dst->plane[pipe], src->plane[pipe],
4131 sizeof(dst->plane[pipe]));
4132 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4133 sizeof(dst->plane_trans[pipe]));
4134
4135 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4136 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4137 sizeof(dst->ddb.y_plane[pipe]));
4138 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4139 sizeof(dst->ddb.plane[pipe]));
4140}
4141
98d39494
MR		 4142static int
4143skl_compute_wm(struct drm_atomic_state *state)
4144{
4145 struct drm_crtc *crtc;
4146 struct drm_crtc_state *cstate;
734fa01f
MR		 4147 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4148 struct skl_wm_values *results = &intel_state->wm_results;
4149 struct skl_pipe_wm *pipe_wm;
98d39494 4150 bool changed = false;
734fa01f 4151 int ret, i;
98d39494
MR		 4152
4153 /*
4154 * If this transaction isn't actually touching any CRTC's, don't
4155 * bother with watermark calculation. Note that if we pass this
4156 * test, we're guaranteed to hold at least one CRTC state mutex,
4157 * which means we can safely use values like dev_priv->active_crtcs
4158 * since any racing commits that want to update them would need to
4159 * hold _all_ CRTC state mutexes.
4160 */
4161 for_each_crtc_in_state(state, crtc, cstate, i)
4162 changed = true;
4163 if (!changed)
4164 return 0;
4165
734fa01f
MR		 4166 /* Clear all dirty flags */
4167 results->dirty_pipes = 0;
4168
98d39494
MR		 4169 ret = skl_compute_ddb(state);
4170 if (ret)
4171 return ret;
4172
734fa01f
MR		 4173 /*
4174 * Calculate WM's for all pipes that are part of this transaction.
4175 * Note that the DDB allocation above may have added more CRTC's that
4176 * weren't otherwise being modified (and set bits in dirty_pipes) if
4177 * pipe allocations had to change.
4178 *
4179 * FIXME: Now that we're doing this in the atomic check phase, we
4180 * should allow skl_update_pipe_wm() to return failure in cases where
4181 * no suitable watermark values can be found.
4182 */
4183 for_each_crtc_in_state(state, crtc, cstate, i) {
4184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185 struct intel_crtc_state *intel_cstate =
4186 to_intel_crtc_state(cstate);
4187
4188 pipe_wm = &intel_cstate->wm.skl.optimal;
4189 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4190 &changed);
4191 if (ret)
4192 return ret;
4193
4194 if (changed)
4195 results->dirty_pipes |= drm_crtc_mask(crtc);
4196
4197 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4198 /* This pipe's WM's did not change */
4199 continue;
4200
4201 intel_cstate->update_wm_pre = true;
4202 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4203 }
4204
98d39494
MR		 4205 return 0;
4206}
4207
2d41c0b5
PB		 4208static void skl_update_wm(struct drm_crtc *crtc)
4209{
4210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4211 struct drm_device *dev = crtc->dev;
fac5e23e 4212 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4213 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4214 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4215 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4216 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
2722efb9 4217 int pipe;
adda50b8 4218
734fa01f 4219 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4220 return;
4221
734fa01f
MR		 4222 intel_crtc->wm.active.skl = *pipe_wm;
4223
4224 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4225
2d41c0b5 4226 skl_write_wm_values(dev_priv, results);
0e8fb7ba 4227 skl_flush_wm_values(dev_priv, results);
53b0deb4 4228
2722efb9
MR		 4229 /*
4230 * Store the new configuration (but only for the pipes that have
4231 * changed; the other values weren't recomputed).
4232 */
4233 for_each_pipe_masked(dev_priv, pipe, results->dirty_pipes)
4234 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4235
4236 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4237}
4238
d890565c
VS		 4239static void ilk_compute_wm_config(struct drm_device *dev,
4240 struct intel_wm_config *config)
4241{
4242 struct intel_crtc *crtc;
4243
4244 /* Compute the currently _active_ config */
4245 for_each_intel_crtc(dev, crtc) {
4246 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4247
4248 if (!wm->pipe_enabled)
4249 continue;
4250
4251 config->sprites_enabled |= wm->sprites_enabled;
4252 config->sprites_scaled |= wm->sprites_scaled;
4253 config->num_pipes_active++;
4254 }
4255}
4256
ed4a6a7c 4257static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4258{
91c8a326 4259 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4260 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4261 struct ilk_wm_maximums max;
d890565c 4262 struct intel_wm_config config = {};
820c1980 4263 struct ilk_wm_values results = {};
77c122bc 4264 enum intel_ddb_partitioning partitioning;
261a27d1 4265
d890565c
VS		 4266 ilk_compute_wm_config(dev, &config);
4267
4268 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4269 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4270
4271 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4272 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4273 config.num_pipes_active == 1 && config.sprites_enabled) {
4274 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4275 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4276
820c1980 4277 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4278 } else {
198a1e9b 4279 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4280 }
4281
198a1e9b 4282 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4283 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4284
820c1980 4285 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4286
820c1980 4287 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4288}
4289
ed4a6a7c 4290static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4291{
ed4a6a7c
MR		 4292 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4293 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4294
ed4a6a7c 4295 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4296 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4297 ilk_program_watermarks(dev_priv);
4298 mutex_unlock(&dev_priv->wm.wm_mutex);
4299}
bf220452 4300
ed4a6a7c
MR		 4301static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4302{
4303 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4304 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4305
ed4a6a7c
MR		 4306 mutex_lock(&dev_priv->wm.wm_mutex);
4307 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4308 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4309 ilk_program_watermarks(dev_priv);
4310 }
4311 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4312}
4313
3078999f
PB		 4314static void skl_pipe_wm_active_state(uint32_t val,
4315 struct skl_pipe_wm *active,
4316 bool is_transwm,
4317 bool is_cursor,
4318 int i,
4319 int level)
4320{
4321 bool is_enabled = (val & PLANE_WM_EN) != 0;
4322
4323 if (!is_transwm) {
4324 if (!is_cursor) {
4325 active->wm[level].plane_en[i] = is_enabled;
4326 active->wm[level].plane_res_b[i] =
4327 val & PLANE_WM_BLOCKS_MASK;
4328 active->wm[level].plane_res_l[i] =
4329 (val >> PLANE_WM_LINES_SHIFT) &
4330 PLANE_WM_LINES_MASK;
4331 } else {
4969d33e
MR		 4332 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4333 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4334 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4335 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4336 (val >> PLANE_WM_LINES_SHIFT) &
4337 PLANE_WM_LINES_MASK;
4338 }
4339 } else {
4340 if (!is_cursor) {
4341 active->trans_wm.plane_en[i] = is_enabled;
4342 active->trans_wm.plane_res_b[i] =
4343 val & PLANE_WM_BLOCKS_MASK;
4344 active->trans_wm.plane_res_l[i] =
4345 (val >> PLANE_WM_LINES_SHIFT) &
4346 PLANE_WM_LINES_MASK;
4347 } else {
4969d33e
MR		 4348 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4349 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4350 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4351 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4352 (val >> PLANE_WM_LINES_SHIFT) &
4353 PLANE_WM_LINES_MASK;
4354 }
4355 }
4356}
4357
4358static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4359{
4360 struct drm_device *dev = crtc->dev;
fac5e23e 4361 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4362 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4364 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4365 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4366 enum pipe pipe = intel_crtc->pipe;
4367 int level, i, max_level;
4368 uint32_t temp;
4369
4370 max_level = ilk_wm_max_level(dev);
4371
4372 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4373
4374 for (level = 0; level <= max_level; level++) {
4375 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4376 hw->plane[pipe][i][level] =
4377 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4378 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4379 }
4380
4381 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4382 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4383 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4384
3ef00284 4385 if (!intel_crtc->active)
3078999f
PB		 4386 return;
4387
2b4b9f35 4388 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4389
4390 active->linetime = hw->wm_linetime[pipe];
4391
4392 for (level = 0; level <= max_level; level++) {
4393 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4394 temp = hw->plane[pipe][i][level];
4395 skl_pipe_wm_active_state(temp, active, false,
4396 false, i, level);
4397 }
4969d33e 4398 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4399 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4400 }
4401
4402 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4403 temp = hw->plane_trans[pipe][i];
4404 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4405 }
4406
4969d33e 4407 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4408 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4409
4410 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4411}
4412
4413void skl_wm_get_hw_state(struct drm_device *dev)
4414{
fac5e23e 4415 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4416 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4417 struct drm_crtc *crtc;
4418
a269c583 4419 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4420 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4421 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4422
279e99d7
MR		 4423 if (dev_priv->active_crtcs) {
4424 /* Fully recompute DDB on first atomic commit */
4425 dev_priv->wm.distrust_bios_wm = true;
4426 } else {
4427 /* Easy/common case; just sanitize DDB now if everything off */
4428 memset(ddb, 0, sizeof(*ddb));
4429 }
3078999f
PB		 4430}
4431
243e6a44
VS		 4432static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4433{
4434 struct drm_device *dev = crtc->dev;
fac5e23e 4435 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4436 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4438 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4439 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4440 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4441 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4442 [PIPE_A] = WM0_PIPEA_ILK,
4443 [PIPE_B] = WM0_PIPEB_ILK,
4444 [PIPE_C] = WM0_PIPEC_IVB,
4445 };
4446
4447 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4448 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4449 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4450
15606534
VS		 4451 memset(active, 0, sizeof(*active));
4452
3ef00284 4453 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4454
4455 if (active->pipe_enabled) {
243e6a44
VS		 4456 u32 tmp = hw->wm_pipe[pipe];
4457
4458 /*
4459 * For active pipes LP0 watermark is marked as
4460 * enabled, and LP1+ watermaks as disabled since
4461 * we can't really reverse compute them in case
4462 * multiple pipes are active.
4463 */
4464 active->wm[0].enable = true;
4465 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4466 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4467 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4468 active->linetime = hw->wm_linetime[pipe];
4469 } else {
4470 int level, max_level = ilk_wm_max_level(dev);
4471
4472 /*
4473 * For inactive pipes, all watermark levels
4474 * should be marked as enabled but zeroed,
4475 * which is what we'd compute them to.
4476 */
4477 for (level = 0; level <= max_level; level++)
4478 active->wm[level].enable = true;
4479 }
4e0963c7
MR		 4480
4481 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4482}
4483
6eb1a681
VS		 4484#define _FW_WM(value, plane) \
4485 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4486#define _FW_WM_VLV(value, plane) \
4487 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4488
4489static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4490 struct vlv_wm_values *wm)
4491{
4492 enum pipe pipe;
4493 uint32_t tmp;
4494
4495 for_each_pipe(dev_priv, pipe) {
4496 tmp = I915_READ(VLV_DDL(pipe));
4497
4498 wm->ddl[pipe].primary =
4499 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4500 wm->ddl[pipe].cursor =
4501 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4502 wm->ddl[pipe].sprite[0] =
4503 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4504 wm->ddl[pipe].sprite[1] =
4505 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4506 }
4507
4508 tmp = I915_READ(DSPFW1);
4509 wm->sr.plane = _FW_WM(tmp, SR);
4510 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4511 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4512 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4513
4514 tmp = I915_READ(DSPFW2);
4515 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4516 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4517 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4518
4519 tmp = I915_READ(DSPFW3);
4520 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4521
4522 if (IS_CHERRYVIEW(dev_priv)) {
4523 tmp = I915_READ(DSPFW7_CHV);
4524 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4525 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4526
4527 tmp = I915_READ(DSPFW8_CHV);
4528 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4529 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4530
4531 tmp = I915_READ(DSPFW9_CHV);
4532 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4533 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4534
4535 tmp = I915_READ(DSPHOWM);
4536 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4537 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4538 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4539 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4540 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4541 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4542 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4543 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4544 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4545 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4546 } else {
4547 tmp = I915_READ(DSPFW7);
4548 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4549 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4550
4551 tmp = I915_READ(DSPHOWM);
4552 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4553 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4554 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4555 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4556 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4557 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4558 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4559 }
4560}
4561
4562#undef _FW_WM
4563#undef _FW_WM_VLV
4564
4565void vlv_wm_get_hw_state(struct drm_device *dev)
4566{
4567 struct drm_i915_private *dev_priv = to_i915(dev);
4568 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4569 struct intel_plane *plane;
4570 enum pipe pipe;
4571 u32 val;
4572
4573 vlv_read_wm_values(dev_priv, wm);
4574
4575 for_each_intel_plane(dev, plane) {
4576 switch (plane->base.type) {
4577 int sprite;
4578 case DRM_PLANE_TYPE_CURSOR:
4579 plane->wm.fifo_size = 63;
4580 break;
4581 case DRM_PLANE_TYPE_PRIMARY:
4582 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4583 break;
4584 case DRM_PLANE_TYPE_OVERLAY:
4585 sprite = plane->plane;
4586 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4587 break;
4588 }
4589 }
4590
4591 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4592 wm->level = VLV_WM_LEVEL_PM2;
4593
4594 if (IS_CHERRYVIEW(dev_priv)) {
4595 mutex_lock(&dev_priv->rps.hw_lock);
4596
4597 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4598 if (val & DSP_MAXFIFO_PM5_ENABLE)
4599 wm->level = VLV_WM_LEVEL_PM5;
4600
58590c14
VS		 4601 /*
4602 * If DDR DVFS is disabled in the BIOS, Punit
4603 * will never ack the request. So if that happens
4604 * assume we don't have to enable/disable DDR DVFS
4605 * dynamically. To test that just set the REQ_ACK
4606 * bit to poke the Punit, but don't change the
4607 * HIGH/LOW bits so that we don't actually change
4608 * the current state.
4609 */
6eb1a681 4610 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4611 val |= FORCE_DDR_FREQ_REQ_ACK;
4612 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4613
4614 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4615 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4616 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4617 "assuming DDR DVFS is disabled\n");
4618 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4619 } else {
4620 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4621 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4622 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4623 }
6eb1a681
VS		 4624
4625 mutex_unlock(&dev_priv->rps.hw_lock);
4626 }
4627
4628 for_each_pipe(dev_priv, pipe)
4629 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4630 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4631 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4632
4633 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4634 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4635}
4636
243e6a44
VS		 4637void ilk_wm_get_hw_state(struct drm_device *dev)
4638{
fac5e23e 4639 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4640 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4641 struct drm_crtc *crtc;
4642
70e1e0ec 4643 for_each_crtc(dev, crtc)
243e6a44
VS		 4644 ilk_pipe_wm_get_hw_state(crtc);
4645
4646 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4647 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4648 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4649
4650 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4651 if (INTEL_INFO(dev)->gen >= 7) {
4652 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4653 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4654 }
243e6a44 4655
a42a5719 4656 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4657 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4658 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4659 else if (IS_IVYBRIDGE(dev))
4660 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4661 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4662
4663 hw->enable_fbc_wm =
4664 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4665}
4666
b445e3b0
ED		 4667/**
4668 * intel_update_watermarks - update FIFO watermark values based on current modes
4669 *
4670 * Calculate watermark values for the various WM regs based on current mode
4671 * and plane configuration.
4672 *
4673 * There are several cases to deal with here:
4674 * - normal (i.e. non-self-refresh)
4675 * - self-refresh (SR) mode
4676 * - lines are large relative to FIFO size (buffer can hold up to 2)
4677 * - lines are small relative to FIFO size (buffer can hold more than 2
4678 * lines), so need to account for TLB latency
4679 *
4680 * The normal calculation is:
4681 * watermark = dotclock * bytes per pixel * latency
4682 * where latency is platform & configuration dependent (we assume pessimal
4683 * values here).
4684 *
4685 * The SR calculation is:
4686 * watermark = (trunc(latency/line time)+1) * surface width *
4687 * bytes per pixel
4688 * where
4689 * line time = htotal / dotclock
4690 * surface width = hdisplay for normal plane and 64 for cursor
4691 * and latency is assumed to be high, as above.
4692 *
4693 * The final value programmed to the register should always be rounded up,
4694 * and include an extra 2 entries to account for clock crossings.
4695 *
4696 * We don't use the sprite, so we can ignore that. And on Crestline we have
4697 * to set the non-SR watermarks to 8.
4698 */
46ba614c 4699void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4700{
fac5e23e 4701 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4702
4703 if (dev_priv->display.update_wm)
46ba614c 4704 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4705}
4706
e2828914 4707/*
9270388e 4708 * Lock protecting IPS related data structures
9270388e
DV		 4709 */
4710DEFINE_SPINLOCK(mchdev_lock);
4711
4712/* Global for IPS driver to get at the current i915 device. Protected by
4713 * mchdev_lock. */
4714static struct drm_i915_private *i915_mch_dev;
4715
91d14251 4716bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4717{
2b4e57bd
ED		 4718 u16 rgvswctl;
4719
9270388e
DV		 4720 assert_spin_locked(&mchdev_lock);
4721
2b4e57bd
ED		 4722 rgvswctl = I915_READ16(MEMSWCTL);
4723 if (rgvswctl & MEMCTL_CMD_STS) {
4724 DRM_DEBUG("gpu busy, RCS change rejected\n");
4725 return false; /* still busy with another command */
4726 }
4727
4728 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4729 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4730 I915_WRITE16(MEMSWCTL, rgvswctl);
4731 POSTING_READ16(MEMSWCTL);
4732
4733 rgvswctl |= MEMCTL_CMD_STS;
4734 I915_WRITE16(MEMSWCTL, rgvswctl);
4735
4736 return true;
4737}
4738
91d14251 4739static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4740{
84f1b20f 4741 u32 rgvmodectl;
2b4e57bd
ED		 4742 u8 fmax, fmin, fstart, vstart;
4743
9270388e
DV		 4744 spin_lock_irq(&mchdev_lock);
4745
84f1b20f
TU		 4746 rgvmodectl = I915_READ(MEMMODECTL);
4747
2b4e57bd
ED		 4748 /* Enable temp reporting */
4749 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4750 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4751
4752 /* 100ms RC evaluation intervals */
4753 I915_WRITE(RCUPEI, 100000);
4754 I915_WRITE(RCDNEI, 100000);
4755
4756 /* Set max/min thresholds to 90ms and 80ms respectively */
4757 I915_WRITE(RCBMAXAVG, 90000);
4758 I915_WRITE(RCBMINAVG, 80000);
4759
4760 I915_WRITE(MEMIHYST, 1);
4761
4762 /* Set up min, max, and cur for interrupt handling */
4763 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4764 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4765 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4766 MEMMODE_FSTART_SHIFT;
4767
616847e7 4768 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4769 PXVFREQ_PX_SHIFT;
4770
20e4d407
DV		 4771 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4772 dev_priv->ips.fstart = fstart;
2b4e57bd 4773
20e4d407
DV		 4774 dev_priv->ips.max_delay = fstart;
4775 dev_priv->ips.min_delay = fmin;
4776 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4777
4778 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4779 fmax, fmin, fstart);
4780
4781 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4782
4783 /*
4784 * Interrupts will be enabled in ironlake_irq_postinstall
4785 */
4786
4787 I915_WRITE(VIDSTART, vstart);
4788 POSTING_READ(VIDSTART);
4789
4790 rgvmodectl |= MEMMODE_SWMODE_EN;
4791 I915_WRITE(MEMMODECTL, rgvmodectl);
4792
9270388e 4793 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4794 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4795 mdelay(1);
2b4e57bd 4796
91d14251 4797 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4798
7d81c3e0
VS		 4799 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4800 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4801 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4802 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4803 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4804
4805 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4806}
4807
91d14251 4808static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4809{
9270388e
DV		 4810 u16 rgvswctl;
4811
4812 spin_lock_irq(&mchdev_lock);
4813
4814 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4815
4816 /* Ack interrupts, disable EFC interrupt */
4817 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4818 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4819 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4820 I915_WRITE(DEIIR, DE_PCU_EVENT);
4821 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4822
4823 /* Go back to the starting frequency */
91d14251 4824 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4825 mdelay(1);
2b4e57bd
ED		 4826 rgvswctl |= MEMCTL_CMD_STS;
4827 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4828 mdelay(1);
2b4e57bd 4829
9270388e 4830 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4831}
4832
acbe9475
DV		 4833/* There's a funny hw issue where the hw returns all 0 when reading from
4834 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4835 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4836 * all limits and the gpu stuck at whatever frequency it is at atm).
4837 */
74ef1173 4838static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4839{
7b9e0ae6 4840 u32 limits;
2b4e57bd 4841
20b46e59
DV		 4842 /* Only set the down limit when we've reached the lowest level to avoid
4843 * getting more interrupts, otherwise leave this clear. This prevents a
4844 * race in the hw when coming out of rc6: There's a tiny window where
4845 * the hw runs at the minimal clock before selecting the desired
4846 * frequency, if the down threshold expires in that window we will not
4847 * receive a down interrupt. */
2d1fe073 4848 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4849 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4850 if (val <= dev_priv->rps.min_freq_softlimit)
4851 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4852 } else {
4853 limits = dev_priv->rps.max_freq_softlimit << 24;
4854 if (val <= dev_priv->rps.min_freq_softlimit)
4855 limits |= dev_priv->rps.min_freq_softlimit << 16;
4856 }
20b46e59
DV		 4857
4858 return limits;
4859}
4860
dd75fdc8
CW		 4861static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4862{
4863 int new_power;
8a586437
AG		 4864 u32 threshold_up = 0, threshold_down = 0; /* in % */
4865 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4866
4867 new_power = dev_priv->rps.power;
4868 switch (dev_priv->rps.power) {
4869 case LOW_POWER:
a72b5623
CW		 4870 if (val > dev_priv->rps.efficient_freq + 1 &&
4871 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4872 new_power = BETWEEN;
4873 break;
4874
4875 case BETWEEN:
a72b5623
CW		 4876 if (val <= dev_priv->rps.efficient_freq &&
4877 val < dev_priv->rps.cur_freq)
dd75fdc8 4878 new_power = LOW_POWER;
a72b5623
CW		 4879 else if (val >= dev_priv->rps.rp0_freq &&
4880 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4881 new_power = HIGH_POWER;
4882 break;
4883
4884 case HIGH_POWER:
a72b5623
CW		 4885 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4886 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4887 new_power = BETWEEN;
4888 break;
4889 }
4890 /* Max/min bins are special */
aed242ff 4891 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4892 new_power = LOW_POWER;
aed242ff 4893 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4894 new_power = HIGH_POWER;
4895 if (new_power == dev_priv->rps.power)
4896 return;
4897
4898 /* Note the units here are not exactly 1us, but 1280ns. */
4899 switch (new_power) {
4900 case LOW_POWER:
4901 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4902 ei_up = 16000;
4903 threshold_up = 95;
dd75fdc8
CW		 4904
4905 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4906 ei_down = 32000;
4907 threshold_down = 85;
dd75fdc8
CW		 4908 break;
4909
4910 case BETWEEN:
4911 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4912 ei_up = 13000;
4913 threshold_up = 90;
dd75fdc8
CW		 4914
4915 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4916 ei_down = 32000;
4917 threshold_down = 75;
dd75fdc8
CW		 4918 break;
4919
4920 case HIGH_POWER:
4921 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4922 ei_up = 10000;
4923 threshold_up = 85;
dd75fdc8
CW		 4924
4925 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4926 ei_down = 32000;
4927 threshold_down = 60;
dd75fdc8
CW		 4928 break;
4929 }
4930
8a586437 4931 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4932 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4933 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4934 GT_INTERVAL_FROM_US(dev_priv,
4935 ei_up * threshold_up / 100));
8a586437
AG		 4936
4937 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4938 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4939 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4940 GT_INTERVAL_FROM_US(dev_priv,
4941 ei_down * threshold_down / 100));
4942
4943 I915_WRITE(GEN6_RP_CONTROL,
4944 GEN6_RP_MEDIA_TURBO |
4945 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4946 GEN6_RP_MEDIA_IS_GFX |
4947 GEN6_RP_ENABLE |
4948 GEN6_RP_UP_BUSY_AVG |
4949 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4950
dd75fdc8 4951 dev_priv->rps.power = new_power;
8fb55197
CW		 4952 dev_priv->rps.up_threshold = threshold_up;
4953 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4954 dev_priv->rps.last_adj = 0;
4955}
4956
2876ce73
CW		 4957static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4958{
4959 u32 mask = 0;
4960
4961 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4962 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4963 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4964 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4965
7b3c29f6
CW		 4966 mask &= dev_priv->pm_rps_events;
4967
59d02a1f 4968 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4969}
4970
b8a5ff8d
JM		 4971/* gen6_set_rps is called to update the frequency request, but should also be
4972 * called when the range (min_delay and max_delay) is modified so that we can
4973 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4974static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4975{
23eafea6 4976 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4977 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4978 return;
4979
4fc688ce 4980 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4981 WARN_ON(val > dev_priv->rps.max_freq);
4982 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4983
eb64cad1
CW		 4984 /* min/max delay may still have been modified so be sure to
4985 * write the limits value.
4986 */
4987 if (val != dev_priv->rps.cur_freq) {
4988 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4989
dc97997a 4990 if (IS_GEN9(dev_priv))
5704195c
AG		 4991 I915_WRITE(GEN6_RPNSWREQ,
4992 GEN9_FREQUENCY(val));
dc97997a 4993 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4994 I915_WRITE(GEN6_RPNSWREQ,
4995 HSW_FREQUENCY(val));
4996 else
4997 I915_WRITE(GEN6_RPNSWREQ,
4998 GEN6_FREQUENCY(val) |
4999 GEN6_OFFSET(0) |
5000 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 5001 }
7b9e0ae6 5002
7b9e0ae6
CW		 5003 /* Make sure we continue to get interrupts
5004 * until we hit the minimum or maximum frequencies.
5005 */
74ef1173 5006 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 5007 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 5008
d5570a72
BW		 5009 POSTING_READ(GEN6_RPNSWREQ);
5010
b39fb297 5011 dev_priv->rps.cur_freq = val;
0f94592e 5012 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 5013}
5014
dc97997a 5015static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 5016{
ffe02b40 5017 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 5018 WARN_ON(val > dev_priv->rps.max_freq);
5019 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 5020
dc97997a 5021 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 5022 "Odd GPU freq value\n"))
5023 val &= ~1;
5024
cd25dd5b
D		 5025 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5026
8fb55197 5027 if (val != dev_priv->rps.cur_freq) {
ffe02b40 5028 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 5029 if (!IS_CHERRYVIEW(dev_priv))
5030 gen6_set_rps_thresholds(dev_priv, val);
5031 }
ffe02b40 5032
ffe02b40
VS		 5033 dev_priv->rps.cur_freq = val;
5034 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5035}
5036
a7f6e231 5037/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5038 *
5039 * * If Gfx is Idle, then
a7f6e231
D		 5040 * 1. Forcewake Media well.
5041 * 2. Request idle freq.
5042 * 3. Release Forcewake of Media well.
76c3552f
D		 5043*/
5044static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5045{
aed242ff 5046 u32 val = dev_priv->rps.idle_freq;
5549d25f 5047
aed242ff 5048 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5049 return;
5050
a7f6e231
D		 5051 /* Wake up the media well, as that takes a lot less
5052 * power than the Render well. */
5053 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5054 valleyview_set_rps(dev_priv, val);
a7f6e231 5055 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5056}
5057
43cf3bf0
CW		 5058void gen6_rps_busy(struct drm_i915_private *dev_priv)
5059{
5060 mutex_lock(&dev_priv->rps.hw_lock);
5061 if (dev_priv->rps.enabled) {
5062 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5063 gen6_rps_reset_ei(dev_priv);
5064 I915_WRITE(GEN6_PMINTRMSK,
5065 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5066
c33d247d
CW		 5067 gen6_enable_rps_interrupts(dev_priv);
5068
2b83c4c4
MW		 5069 /* Ensure we start at the user's desired frequency */
5070 intel_set_rps(dev_priv,
5071 clamp(dev_priv->rps.cur_freq,
5072 dev_priv->rps.min_freq_softlimit,
5073 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5074 }
5075 mutex_unlock(&dev_priv->rps.hw_lock);
5076}
5077
b29c19b6
CW		 5078void gen6_rps_idle(struct drm_i915_private *dev_priv)
5079{
c33d247d
CW		 5080 /* Flush our bottom-half so that it does not race with us
5081 * setting the idle frequency and so that it is bounded by
5082 * our rpm wakeref. And then disable the interrupts to stop any
5083 * futher RPS reclocking whilst we are asleep.
5084 */
5085 gen6_disable_rps_interrupts(dev_priv);
5086
b29c19b6 5087 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5088 if (dev_priv->rps.enabled) {
dc97997a 5089 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5090 vlv_set_rps_idle(dev_priv);
7526ed79 5091 else
dc97997a 5092 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5093 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5094 I915_WRITE(GEN6_PMINTRMSK,
5095 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5096 }
8d3afd7d 5097 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5098
8d3afd7d 5099 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5100 while (!list_empty(&dev_priv->rps.clients))
5101 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5102 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5103}
5104
1854d5ca 5105void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5106 struct intel_rps_client *rps,
5107 unsigned long submitted)
b29c19b6 5108{
8d3afd7d
CW		 5109 /* This is intentionally racy! We peek at the state here, then
5110 * validate inside the RPS worker.
5111 */
67d97da3 5112 if (!(dev_priv->gt.awake &&
8d3afd7d 5113 dev_priv->rps.enabled &&
29ecd78d 5114 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5115 return;
43cf3bf0 5116
e61b9958
CW		 5117 /* Force a RPS boost (and don't count it against the client) if
5118 * the GPU is severely congested.
5119 */
d0bc54f2 5120 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5121 rps = NULL;
5122
8d3afd7d
CW		 5123 spin_lock(&dev_priv->rps.client_lock);
5124 if (rps == NULL || list_empty(&rps->link)) {
5125 spin_lock_irq(&dev_priv->irq_lock);
5126 if (dev_priv->rps.interrupts_enabled) {
5127 dev_priv->rps.client_boost = true;
c33d247d 5128 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5129 }
5130 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5131
2e1b8730
CW		 5132 if (rps != NULL) {
5133 list_add(&rps->link, &dev_priv->rps.clients);
5134 rps->boosts++;
1854d5ca
CW		 5135 } else
5136 dev_priv->rps.boosts++;
c0951f0c 5137 }
8d3afd7d 5138 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5139}
5140
dc97997a 5141void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5142{
dc97997a
CW		 5143 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5144 valleyview_set_rps(dev_priv, val);
ffe02b40 5145 else
dc97997a 5146 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5147}
5148
dc97997a 5149static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5150{
20e49366 5151 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5152 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5153}
5154
dc97997a 5155static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5156{
2030d684
AG		 5157 I915_WRITE(GEN6_RP_CONTROL, 0);
5158}
5159
dc97997a 5160static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5161{
d20d4f0c 5162 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5163 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5164 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5165}
5166
dc97997a 5167static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5168{
38807746
D		 5169 I915_WRITE(GEN6_RC_CONTROL, 0);
5170}
5171
dc97997a 5172static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5173{
98a2e5f9
D		 5174 /* we're doing forcewake before Disabling RC6,
5175 * This what the BIOS expects when going into suspend */
59bad947 5176 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5177
44fc7d5c 5178 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5179
59bad947 5180 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5181}
5182
dc97997a 5183static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5184{
dc97997a 5185 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5186 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5187 mode = GEN6_RC_CTL_RC6_ENABLE;
5188 else
5189 mode = 0;
5190 }
dc97997a 5191 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5192 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5193 "RC6 %s RC6p %s RC6pp %s\n",
5194 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5195 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5196 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5197
5198 else
b99d49cc
ID		 5199 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5200 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5201}
5202
dc97997a 5203static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5204{
72e96d64 5205 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5206 bool enable_rc6 = true;
5207 unsigned long rc6_ctx_base;
fc619841
ID		 5208 u32 rc_ctl;
5209 int rc_sw_target;
5210
5211 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5212 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5213 RC_SW_TARGET_STATE_SHIFT;
5214 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5215 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5216 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5217 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5218 rc_sw_target);
274008e8
SAK		 5219
5220 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5221 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5222 enable_rc6 = false;
5223 }
5224
5225 /*
5226 * The exact context size is not known for BXT, so assume a page size
5227 * for this check.
5228 */
5229 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5230 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5231 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5232 ggtt->stolen_reserved_size))) {
b99d49cc 5233 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5234 enable_rc6 = false;
5235 }
5236
5237 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5238 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5239 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5240 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5241 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5242 enable_rc6 = false;
5243 }
5244
fc619841
ID		 5245 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5246 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5247 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5248 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5249 enable_rc6 = false;
5250 }
5251
5252 if (!I915_READ(GEN6_GFXPAUSE)) {
5253 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5254 enable_rc6 = false;
5255 }
5256
5257 if (!I915_READ(GEN8_MISC_CTRL0)) {
5258 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5259 enable_rc6 = false;
5260 }
5261
5262 return enable_rc6;
5263}
5264
dc97997a 5265int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5266{
e7d66d89 5267 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5268 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5269 return 0;
5270
274008e8
SAK		 5271 if (!enable_rc6)
5272 return 0;
5273
dc97997a 5274 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5275 DRM_INFO("RC6 disabled by BIOS\n");
5276 return 0;
5277 }
5278
456470eb 5279 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5280 if (enable_rc6 >= 0) {
5281 int mask;
5282
dc97997a 5283 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5284 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5285 INTEL_RC6pp_ENABLE;
5286 else
5287 mask = INTEL_RC6_ENABLE;
5288
5289 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5290 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5291 "(requested %d, valid %d)\n",
5292 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5293
5294 return enable_rc6 & mask;
5295 }
2b4e57bd 5296
dc97997a 5297 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5298 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5299
5300 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5301}
5302
dc97997a 5303static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5304{
5305 /* All of these values are in units of 50MHz */
773ea9a8 5306
93ee2920 5307 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5308 if (IS_BROXTON(dev_priv)) {
773ea9a8 5309 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5310 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5311 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5312 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5313 } else {
773ea9a8 5314 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5315 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5316 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5317 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5318 }
3280e8b0 5319 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5320 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5321
93ee2920 5322 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5323 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5324 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5325 u32 ddcc_status = 0;
5326
5327 if (sandybridge_pcode_read(dev_priv,
5328 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5329 &ddcc_status) == 0)
93ee2920 5330 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5331 clamp_t(u8,
5332 ((ddcc_status >> 8) & 0xff),
5333 dev_priv->rps.min_freq,
5334 dev_priv->rps.max_freq);
93ee2920
TR		 5335 }
5336
dc97997a 5337 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5338 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5339 * the natural hardware unit for SKL
5340 */
c5e0688c
AG		 5341 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5342 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5343 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5344 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5345 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5346 }
3280e8b0
BW		 5347}
5348
3a45b05c
CW		 5349static void reset_rps(struct drm_i915_private *dev_priv,
5350 void (*set)(struct drm_i915_private *, u8))
5351{
5352 u8 freq = dev_priv->rps.cur_freq;
5353
5354 /* force a reset */
5355 dev_priv->rps.power = -1;
5356 dev_priv->rps.cur_freq = -1;
5357
5358 set(dev_priv, freq);
5359}
5360
b6fef0ef 5361/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5362static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5363{
b6fef0ef
JB		 5364 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5365
23eafea6 5366 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5367 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5368 /*
5369 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5370 * clear out the Control register just to avoid inconsitency
5371 * with debugfs interface, which will show Turbo as enabled
5372 * only and that is not expected by the User after adding the
5373 * WaGsvDisableTurbo. Apart from this there is no problem even
5374 * if the Turbo is left enabled in the Control register, as the
5375 * Up/Down interrupts would remain masked.
5376 */
dc97997a 5377 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5378 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5379 return;
5380 }
5381
0beb059a
AG		 5382 /* Program defaults and thresholds for RPS*/
5383 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5384 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5385
5386 /* 1 second timeout*/
5387 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5388 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5389
b6fef0ef 5390 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5391
0beb059a
AG		 5392 /* Leaning on the below call to gen6_set_rps to program/setup the
5393 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5394 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5395 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5396
5397 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5398}
5399
dc97997a 5400static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5401{
e2f80391 5402 struct intel_engine_cs *engine;
20e49366 5403 uint32_t rc6_mask = 0;
20e49366
ZW		 5404
5405 /* 1a: Software RC state - RC0 */
5406 I915_WRITE(GEN6_RC_STATE, 0);
5407
5408 /* 1b: Get forcewake during program sequence. Although the driver
5409 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5410 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5411
5412 /* 2a: Disable RC states. */
5413 I915_WRITE(GEN6_RC_CONTROL, 0);
5414
5415 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5416
5417 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5418 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5419 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5420 else
5421 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5422 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5423 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5424 for_each_engine(engine, dev_priv)
e2f80391 5425 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5426
1a3d1898 5427 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5428 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5429
20e49366 5430 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5431
38c23527
ZW		 5432 /* 2c: Program Coarse Power Gating Policies. */
5433 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5434 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5435
20e49366 5436 /* 3a: Enable RC6 */
dc97997a 5437 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5438 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5439 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5440 /* WaRsUseTimeoutMode */
dc97997a
CW		 5441 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5442 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5443 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5444 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5445 GEN7_RC_CTL_TO_MODE |
5446 rc6_mask);
3e7732a0
SAK		 5447 } else {
5448 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5449 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5450 GEN6_RC_CTL_EI_MODE(1) |
5451 rc6_mask);
3e7732a0 5452 }
20e49366 5453
cb07bae0
SK		 5454 /*
5455 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5456 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5457 */
dc97997a 5458 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5459 I915_WRITE(GEN9_PG_ENABLE, 0);
5460 else
5461 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5462 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5463
59bad947 5464 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5465}
5466
dc97997a 5467static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5468{
e2f80391 5469 struct intel_engine_cs *engine;
93ee2920 5470 uint32_t rc6_mask = 0;
6edee7f3
BW		 5471
5472 /* 1a: Software RC state - RC0 */
5473 I915_WRITE(GEN6_RC_STATE, 0);
5474
5475 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5476 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5477 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5478
5479 /* 2a: Disable RC states. */
5480 I915_WRITE(GEN6_RC_CONTROL, 0);
5481
6edee7f3
BW		 5482 /* 2b: Program RC6 thresholds.*/
5483 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5484 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5485 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5486 for_each_engine(engine, dev_priv)
e2f80391 5487 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5488 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5489 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5490 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5491 else
5492 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5493
5494 /* 3: Enable RC6 */
dc97997a 5495 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5496 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5497 intel_print_rc6_info(dev_priv, rc6_mask);
5498 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5499 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5500 GEN7_RC_CTL_TO_MODE |
5501 rc6_mask);
5502 else
5503 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5504 GEN6_RC_CTL_EI_MODE(1) |
5505 rc6_mask);
6edee7f3
BW		 5506
5507 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5508 I915_WRITE(GEN6_RPNSWREQ,
5509 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5510 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5511 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5512 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5513 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5514
5515 /* Docs recommend 900MHz, and 300 MHz respectively */
5516 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5517 dev_priv->rps.max_freq_softlimit << 24 |
5518 dev_priv->rps.min_freq_softlimit << 16);
5519
5520 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5521 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5522 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5523 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5524
5525 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5526
5527 /* 5: Enable RPS */
7526ed79
DV		 5528 I915_WRITE(GEN6_RP_CONTROL,
5529 GEN6_RP_MEDIA_TURBO |
5530 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5531 GEN6_RP_MEDIA_IS_GFX |
5532 GEN6_RP_ENABLE |
5533 GEN6_RP_UP_BUSY_AVG |
5534 GEN6_RP_DOWN_IDLE_AVG);
5535
5536 /* 6: Ring frequency + overclocking (our driver does this later */
5537
3a45b05c 5538 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5539
59bad947 5540 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5541}
5542
dc97997a 5543static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5544{
e2f80391 5545 struct intel_engine_cs *engine;
99ac9612 5546 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5547 u32 gtfifodbg;
2b4e57bd 5548 int rc6_mode;
b4ac5afc 5549 int ret;
2b4e57bd 5550
4fc688ce 5551 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5552
2b4e57bd
ED		 5553 /* Here begins a magic sequence of register writes to enable
5554 * auto-downclocking.
5555 *
5556 * Perhaps there might be some value in exposing these to
5557 * userspace...
5558 */
5559 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5560
5561 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5562 gtfifodbg = I915_READ(GTFIFODBG);
5563 if (gtfifodbg) {
2b4e57bd
ED		 5564 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5565 I915_WRITE(GTFIFODBG, gtfifodbg);
5566 }
5567
59bad947 5568 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5569
5570 /* disable the counters and set deterministic thresholds */
5571 I915_WRITE(GEN6_RC_CONTROL, 0);
5572
5573 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5574 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5575 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5576 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5577 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5578
b4ac5afc 5579 for_each_engine(engine, dev_priv)
e2f80391 5580 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5581
5582 I915_WRITE(GEN6_RC_SLEEP, 0);
5583 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5584 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5585 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5586 else
5587 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5588 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5589 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5590
5a7dc92a 5591 /* Check if we are enabling RC6 */
dc97997a 5592 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5593 if (rc6_mode & INTEL_RC6_ENABLE)
5594 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5595
5a7dc92a 5596 /* We don't use those on Haswell */
dc97997a 5597 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5598 if (rc6_mode & INTEL_RC6p_ENABLE)
5599 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5600
5a7dc92a
ED		 5601 if (rc6_mode & INTEL_RC6pp_ENABLE)
5602 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5603 }
2b4e57bd 5604
dc97997a 5605 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5606
5607 I915_WRITE(GEN6_RC_CONTROL,
5608 rc6_mask |
5609 GEN6_RC_CTL_EI_MODE(1) |
5610 GEN6_RC_CTL_HW_ENABLE);
5611
dd75fdc8
CW		 5612 /* Power down if completely idle for over 50ms */
5613 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5614 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5615
42c0526c 5616 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5617 if (ret)
42c0526c 5618 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5619
3a45b05c 5620 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5621
31643d54
BW		 5622 rc6vids = 0;
5623 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5624 if (IS_GEN6(dev_priv) && ret) {
31643d54 5625 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5626 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5627 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5628 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5629 rc6vids &= 0xffff00;
5630 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5631 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5632 if (ret)
5633 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5634 }
5635
59bad947 5636 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5637}
5638
fb7404e8 5639static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5640{
5641 int min_freq = 15;
3ebecd07
CW		 5642 unsigned int gpu_freq;
5643 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5644 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5645 int scaling_factor = 180;
eda79642 5646 struct cpufreq_policy *policy;
2b4e57bd 5647
4fc688ce 5648 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5649
eda79642
BW		 5650 policy = cpufreq_cpu_get(0);
5651 if (policy) {
5652 max_ia_freq = policy->cpuinfo.max_freq;
5653 cpufreq_cpu_put(policy);
5654 } else {
5655 /*
5656 * Default to measured freq if none found, PCU will ensure we
5657 * don't go over
5658 */
2b4e57bd 5659 max_ia_freq = tsc_khz;
eda79642 5660 }
2b4e57bd
ED		 5661
5662 /* Convert from kHz to MHz */
5663 max_ia_freq /= 1000;
5664
153b4b95 5665 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5666 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5667 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5668
dc97997a 5669 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5670 /* Convert GT frequency to 50 HZ units */
5671 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5672 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5673 } else {
5674 min_gpu_freq = dev_priv->rps.min_freq;
5675 max_gpu_freq = dev_priv->rps.max_freq;
5676 }
5677
2b4e57bd
ED		 5678 /*
5679 * For each potential GPU frequency, load a ring frequency we'd like
5680 * to use for memory access. We do this by specifying the IA frequency
5681 * the PCU should use as a reference to determine the ring frequency.
5682 */
4c8c7743
AG		 5683 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5684 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5685 unsigned int ia_freq = 0, ring_freq = 0;
5686
dc97997a 5687 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5688 /*
5689 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5690 * No floor required for ring frequency on SKL.
5691 */
5692 ring_freq = gpu_freq;
dc97997a 5693 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5694 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5695 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5696 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5697 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5698 ring_freq = max(min_ring_freq, ring_freq);
5699 /* leave ia_freq as the default, chosen by cpufreq */
5700 } else {
5701 /* On older processors, there is no separate ring
5702 * clock domain, so in order to boost the bandwidth
5703 * of the ring, we need to upclock the CPU (ia_freq).
5704 *
5705 * For GPU frequencies less than 750MHz,
5706 * just use the lowest ring freq.
5707 */
5708 if (gpu_freq < min_freq)
5709 ia_freq = 800;
5710 else
5711 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5712 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5713 }
2b4e57bd 5714
42c0526c
BW		 5715 sandybridge_pcode_write(dev_priv,
5716 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5717 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5718 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5719 gpu_freq);
2b4e57bd 5720 }
2b4e57bd
ED		 5721}
5722
03af2045 5723static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5724{
5725 u32 val, rp0;
5726
5b5929cb 5727 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5728
dc97997a 5729 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5730 case 8:
5731 /* (2 * 4) config */
5732 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5733 break;
5734 case 12:
5735 /* (2 * 6) config */
5736 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5737 break;
5738 case 16:
5739 /* (2 * 8) config */
5740 default:
5741 /* Setting (2 * 8) Min RP0 for any other combination */
5742 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5743 break;
095acd5f 5744 }
5b5929cb
JN		 5745
5746 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5747
2b6b3a09
D		 5748 return rp0;
5749}
5750
5751static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5752{
5753 u32 val, rpe;
5754
5755 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5756 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5757
5758 return rpe;
5759}
5760
7707df4a
D		 5761static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5762{
5763 u32 val, rp1;
5764
5b5929cb
JN		 5765 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5766 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5767
7707df4a
D		 5768 return rp1;
5769}
5770
f8f2b001
D		 5771static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5772{
5773 u32 val, rp1;
5774
5775 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5776
5777 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5778
5779 return rp1;
5780}
5781
03af2045 5782static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5783{
5784 u32 val, rp0;
5785
64936258 5786 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5787
5788 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5789 /* Clamp to max */
5790 rp0 = min_t(u32, rp0, 0xea);
5791
5792 return rp0;
5793}
5794
5795static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5796{
5797 u32 val, rpe;
5798
64936258 5799 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5800 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5801 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5802 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5803
5804 return rpe;
5805}
5806
03af2045 5807static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5808{
36146035
ID		 5809 u32 val;
5810
5811 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5812 /*
5813 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5814 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5815 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5816 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5817 * to make sure it matches what Punit accepts.
5818 */
5819 return max_t(u32, val, 0xc0);
0a073b84
JB		 5820}
5821
ae48434c
ID		 5822/* Check that the pctx buffer wasn't move under us. */
5823static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5824{
5825 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5826
5827 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5828 dev_priv->vlv_pctx->stolen->start);
5829}
5830
38807746
D		 5831
5832/* Check that the pcbr address is not empty. */
5833static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5834{
5835 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5836
5837 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5838}
5839
dc97997a 5840static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5841{
62106b4f 5842 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5843 unsigned long pctx_paddr, paddr;
38807746
D		 5844 u32 pcbr;
5845 int pctx_size = 32*1024;
5846
38807746
D		 5847 pcbr = I915_READ(VLV_PCBR);
5848 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5849 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5850 paddr = (dev_priv->mm.stolen_base +
62106b4f 5851 (ggtt->stolen_size - pctx_size));
38807746
D		 5852
5853 pctx_paddr = (paddr & (~4095));
5854 I915_WRITE(VLV_PCBR, pctx_paddr);
5855 }
ce611ef8
VS		 5856
5857 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5858}
5859
dc97997a 5860static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5861{
c9cddffc
JB		 5862 struct drm_i915_gem_object *pctx;
5863 unsigned long pctx_paddr;
5864 u32 pcbr;
5865 int pctx_size = 24*1024;
5866
5867 pcbr = I915_READ(VLV_PCBR);
5868 if (pcbr) {
5869 /* BIOS set it up already, grab the pre-alloc'd space */
5870 int pcbr_offset;
5871
5872 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5873 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5874 pcbr_offset,
190d6cd5 5875 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5876 pctx_size);
5877 goto out;
5878 }
5879
ce611ef8
VS		 5880 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5881
c9cddffc
JB		 5882 /*
5883 * From the Gunit register HAS:
5884 * The Gfx driver is expected to program this register and ensure
5885 * proper allocation within Gfx stolen memory. For example, this
5886 * register should be programmed such than the PCBR range does not
5887 * overlap with other ranges, such as the frame buffer, protected
5888 * memory, or any other relevant ranges.
5889 */
91c8a326 5890 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5891 if (!pctx) {
5892 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5893 goto out;
c9cddffc
JB		 5894 }
5895
5896 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5897 I915_WRITE(VLV_PCBR, pctx_paddr);
5898
5899out:
ce611ef8 5900 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5901 dev_priv->vlv_pctx = pctx;
5902}
5903
dc97997a 5904static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5905{
ae48434c
ID		 5906 if (WARN_ON(!dev_priv->vlv_pctx))
5907 return;
5908
34911fd3 5909 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5910 dev_priv->vlv_pctx = NULL;
5911}
5912
c30fec65
VS		 5913static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5914{
5915 dev_priv->rps.gpll_ref_freq =
5916 vlv_get_cck_clock(dev_priv, "GPLL ref",
5917 CCK_GPLL_CLOCK_CONTROL,
5918 dev_priv->czclk_freq);
5919
5920 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5921 dev_priv->rps.gpll_ref_freq);
5922}
5923
dc97997a 5924static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5925{
2bb25c17 5926 u32 val;
4e80519e 5927
dc97997a 5928 valleyview_setup_pctx(dev_priv);
4e80519e 5929
c30fec65
VS		 5930 vlv_init_gpll_ref_freq(dev_priv);
5931
2bb25c17
VS		 5932 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5933 switch ((val >> 6) & 3) {
5934 case 0:
5935 case 1:
5936 dev_priv->mem_freq = 800;
5937 break;
5938 case 2:
5939 dev_priv->mem_freq = 1066;
5940 break;
5941 case 3:
5942 dev_priv->mem_freq = 1333;
5943 break;
5944 }
80b83b62 5945 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5946
4e80519e
ID		 5947 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5948 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5949 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5950 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5951 dev_priv->rps.max_freq);
5952
5953 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5954 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5955 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5956 dev_priv->rps.efficient_freq);
5957
f8f2b001
D		 5958 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5959 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5960 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5961 dev_priv->rps.rp1_freq);
5962
4e80519e
ID		 5963 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5964 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5965 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5966 dev_priv->rps.min_freq);
4e80519e
ID		 5967}
5968
dc97997a 5969static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5970{
2bb25c17 5971 u32 val;
2b6b3a09 5972
dc97997a 5973 cherryview_setup_pctx(dev_priv);
2b6b3a09 5974
c30fec65
VS		 5975 vlv_init_gpll_ref_freq(dev_priv);
5976
a580516d 5977 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5978 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5979 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5980
2bb25c17 5981 switch ((val >> 2) & 0x7) {
2bb25c17 5982 case 3:
2bb25c17
VS		 5983 dev_priv->mem_freq = 2000;
5984 break;
bfa7df01 5985 default:
2bb25c17
VS		 5986 dev_priv->mem_freq = 1600;
5987 break;
5988 }
80b83b62 5989 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5990
2b6b3a09
D		 5991 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5992 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5993 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5994 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5995 dev_priv->rps.max_freq);
5996
5997 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5998 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5999 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 6000 dev_priv->rps.efficient_freq);
6001
7707df4a
D		 6002 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
6003 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 6004 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 6005 dev_priv->rps.rp1_freq);
6006
5b7c91b7
D		 6007 /* PUnit validated range is only [RPe, RP0] */
6008 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 6009 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 6010 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 6011 dev_priv->rps.min_freq);
6012
1c14762d
VS		 6013 WARN_ONCE((dev_priv->rps.max_freq |
6014 dev_priv->rps.efficient_freq |
6015 dev_priv->rps.rp1_freq |
6016 dev_priv->rps.min_freq) & 1,
6017 "Odd GPU freq values\n");
38807746
D		 6018}
6019
dc97997a 6020static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 6021{
dc97997a 6022 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 6023}
6024
dc97997a 6025static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 6026{
e2f80391 6027 struct intel_engine_cs *engine;
2b6b3a09 6028 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 6029
6030 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6031
297b32ec
VS		 6032 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6033 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6034 if (gtfifodbg) {
6035 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6036 gtfifodbg);
6037 I915_WRITE(GTFIFODBG, gtfifodbg);
6038 }
6039
6040 cherryview_check_pctx(dev_priv);
6041
6042 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6043 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6044 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6045
160614a2
VS		 6046 /* Disable RC states. */
6047 I915_WRITE(GEN6_RC_CONTROL, 0);
6048
38807746
D		 6049 /* 2a: Program RC6 thresholds.*/
6050 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6051 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6052 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6053
b4ac5afc 6054 for_each_engine(engine, dev_priv)
e2f80391 6055 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6056 I915_WRITE(GEN6_RC_SLEEP, 0);
6057
f4f71c7d
D		 6058 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6059 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6060
6061 /* allows RC6 residency counter to work */
6062 I915_WRITE(VLV_COUNTER_CONTROL,
6063 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6064 VLV_MEDIA_RC6_COUNT_EN |
6065 VLV_RENDER_RC6_COUNT_EN));
6066
6067 /* For now we assume BIOS is allocating and populating the PCBR */
6068 pcbr = I915_READ(VLV_PCBR);
6069
38807746 6070 /* 3: Enable RC6 */
dc97997a
CW		 6071 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6072 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6073 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6074
6075 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6076
2b6b3a09 6077 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6078 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6079 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6080 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6081 I915_WRITE(GEN6_RP_UP_EI, 66000);
6082 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6083
6084 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6085
6086 /* 5: Enable RPS */
6087 I915_WRITE(GEN6_RP_CONTROL,
6088 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6089 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6090 GEN6_RP_ENABLE |
6091 GEN6_RP_UP_BUSY_AVG |
6092 GEN6_RP_DOWN_IDLE_AVG);
6093
3ef62342
D		 6094 /* Setting Fixed Bias */
6095 val = VLV_OVERRIDE_EN |
6096 VLV_SOC_TDP_EN |
6097 CHV_BIAS_CPU_50_SOC_50;
6098 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6099
2b6b3a09
D		 6100 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6101
8d40c3ae
VS		 6102 /* RPS code assumes GPLL is used */
6103 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6104
742f491d 6105 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6106 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6107
3a45b05c 6108 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6109
59bad947 6110 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6111}
6112
dc97997a 6113static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6114{
e2f80391 6115 struct intel_engine_cs *engine;
2a5913a8 6116 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6117
6118 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6119
ae48434c
ID		 6120 valleyview_check_pctx(dev_priv);
6121
297b32ec
VS		 6122 gtfifodbg = I915_READ(GTFIFODBG);
6123 if (gtfifodbg) {
f7d85c1e
JB		 6124 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6125 gtfifodbg);
0a073b84
JB		 6126 I915_WRITE(GTFIFODBG, gtfifodbg);
6127 }
6128
c8d9a590 6129 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6130 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6131
160614a2
VS		 6132 /* Disable RC states. */
6133 I915_WRITE(GEN6_RC_CONTROL, 0);
6134
cad725fe 6135 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6136 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6137 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6138 I915_WRITE(GEN6_RP_UP_EI, 66000);
6139 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6140
6141 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6142
6143 I915_WRITE(GEN6_RP_CONTROL,
6144 GEN6_RP_MEDIA_TURBO |
6145 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6146 GEN6_RP_MEDIA_IS_GFX |
6147 GEN6_RP_ENABLE |
6148 GEN6_RP_UP_BUSY_AVG |
6149 GEN6_RP_DOWN_IDLE_CONT);
6150
6151 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6152 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6153 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6154
b4ac5afc 6155 for_each_engine(engine, dev_priv)
e2f80391 6156 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6157
2f0aa304 6158 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6159
6160 /* allows RC6 residency counter to work */
49798eb2 6161 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6162 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6163 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6164 VLV_MEDIA_RC6_COUNT_EN |
6165 VLV_RENDER_RC6_COUNT_EN));
31685c25 6166
dc97997a 6167 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6168 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6169
dc97997a 6170 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6171
a2b23fe0 6172 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6173
3ef62342
D		 6174 /* Setting Fixed Bias */
6175 val = VLV_OVERRIDE_EN |
6176 VLV_SOC_TDP_EN |
6177 VLV_BIAS_CPU_125_SOC_875;
6178 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6179
64936258 6180 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6181
8d40c3ae
VS		 6182 /* RPS code assumes GPLL is used */
6183 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6184
742f491d 6185 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6186 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6187
3a45b05c 6188 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6189
59bad947 6190 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6191}
6192
dde18883
ED		 6193static unsigned long intel_pxfreq(u32 vidfreq)
6194{
6195 unsigned long freq;
6196 int div = (vidfreq & 0x3f0000) >> 16;
6197 int post = (vidfreq & 0x3000) >> 12;
6198 int pre = (vidfreq & 0x7);
6199
6200 if (!pre)
6201 return 0;
6202
6203 freq = ((div * 133333) / ((1<<post) * pre));
6204
6205 return freq;
6206}
6207
eb48eb00
DV		 6208static const struct cparams {
6209 u16 i;
6210 u16 t;
6211 u16 m;
6212 u16 c;
6213} cparams[] = {
6214 { 1, 1333, 301, 28664 },
6215 { 1, 1066, 294, 24460 },
6216 { 1, 800, 294, 25192 },
6217 { 0, 1333, 276, 27605 },
6218 { 0, 1066, 276, 27605 },
6219 { 0, 800, 231, 23784 },
6220};
6221
f531dcb2 6222static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6223{
6224 u64 total_count, diff, ret;
6225 u32 count1, count2, count3, m = 0, c = 0;
6226 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6227 int i;
6228
02d71956
DV		 6229 assert_spin_locked(&mchdev_lock);
6230
20e4d407 6231 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6232
6233 /* Prevent division-by-zero if we are asking too fast.
6234 * Also, we don't get interesting results if we are polling
6235 * faster than once in 10ms, so just return the saved value
6236 * in such cases.
6237 */
6238 if (diff1 <= 10)
20e4d407 6239 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6240
6241 count1 = I915_READ(DMIEC);
6242 count2 = I915_READ(DDREC);
6243 count3 = I915_READ(CSIEC);
6244
6245 total_count = count1 + count2 + count3;
6246
6247 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6248 if (total_count < dev_priv->ips.last_count1) {
6249 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6250 diff += total_count;
6251 } else {
20e4d407 6252 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6253 }
6254
6255 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6256 if (cparams[i].i == dev_priv->ips.c_m &&
6257 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6258 m = cparams[i].m;
6259 c = cparams[i].c;
6260 break;
6261 }
6262 }
6263
6264 diff = div_u64(diff, diff1);
6265 ret = ((m * diff) + c);
6266 ret = div_u64(ret, 10);
6267
20e4d407
DV		 6268 dev_priv->ips.last_count1 = total_count;
6269 dev_priv->ips.last_time1 = now;
eb48eb00 6270
20e4d407 6271 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6272
6273 return ret;
6274}
6275
f531dcb2
CW		 6276unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6277{
6278 unsigned long val;
6279
dc97997a 6280 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6281 return 0;
6282
6283 spin_lock_irq(&mchdev_lock);
6284
6285 val = __i915_chipset_val(dev_priv);
6286
6287 spin_unlock_irq(&mchdev_lock);
6288
6289 return val;
6290}
6291
eb48eb00
DV		 6292unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6293{
6294 unsigned long m, x, b;
6295 u32 tsfs;
6296
6297 tsfs = I915_READ(TSFS);
6298
6299 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6300 x = I915_READ8(TR1);
6301
6302 b = tsfs & TSFS_INTR_MASK;
6303
6304 return ((m * x) / 127) - b;
6305}
6306
d972d6ee
MK		 6307static int _pxvid_to_vd(u8 pxvid)
6308{
6309 if (pxvid == 0)
6310 return 0;
6311
6312 if (pxvid >= 8 && pxvid < 31)
6313 pxvid = 31;
6314
6315 return (pxvid + 2) * 125;
6316}
6317
6318static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6319{
d972d6ee
MK		 6320 const int vd = _pxvid_to_vd(pxvid);
6321 const int vm = vd - 1125;
6322
dc97997a 6323 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6324 return vm > 0 ? vm : 0;
6325
6326 return vd;
eb48eb00
DV		 6327}
6328
02d71956 6329static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6330{
5ed0bdf2 6331 u64 now, diff, diffms;
eb48eb00
DV		 6332 u32 count;
6333
02d71956 6334 assert_spin_locked(&mchdev_lock);
eb48eb00 6335
5ed0bdf2
TG		 6336 now = ktime_get_raw_ns();
6337 diffms = now - dev_priv->ips.last_time2;
6338 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6339
6340 /* Don't divide by 0 */
eb48eb00
DV		 6341 if (!diffms)
6342 return;
6343
6344 count = I915_READ(GFXEC);
6345
20e4d407
DV		 6346 if (count < dev_priv->ips.last_count2) {
6347 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6348 diff += count;
6349 } else {
20e4d407 6350 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6351 }
6352
20e4d407
DV		 6353 dev_priv->ips.last_count2 = count;
6354 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6355
6356 /* More magic constants... */
6357 diff = diff * 1181;
6358 diff = div_u64(diff, diffms * 10);
20e4d407 6359 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6360}
6361
02d71956
DV		 6362void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6363{
dc97997a 6364 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6365 return;
6366
9270388e 6367 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6368
6369 __i915_update_gfx_val(dev_priv);
6370
9270388e 6371 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6372}
6373
f531dcb2 6374static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6375{
6376 unsigned long t, corr, state1, corr2, state2;
6377 u32 pxvid, ext_v;
6378
02d71956
DV		 6379 assert_spin_locked(&mchdev_lock);
6380
616847e7 6381 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6382 pxvid = (pxvid >> 24) & 0x7f;
6383 ext_v = pvid_to_extvid(dev_priv, pxvid);
6384
6385 state1 = ext_v;
6386
6387 t = i915_mch_val(dev_priv);
6388
6389 /* Revel in the empirically derived constants */
6390
6391 /* Correction factor in 1/100000 units */
6392 if (t > 80)
6393 corr = ((t * 2349) + 135940);
6394 else if (t >= 50)
6395 corr = ((t * 964) + 29317);
6396 else /* < 50 */
6397 corr = ((t * 301) + 1004);
6398
6399 corr = corr * ((150142 * state1) / 10000 - 78642);
6400 corr /= 100000;
20e4d407 6401 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6402
6403 state2 = (corr2 * state1) / 10000;
6404 state2 /= 100; /* convert to mW */
6405
02d71956 6406 __i915_update_gfx_val(dev_priv);
eb48eb00 6407
20e4d407 6408 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6409}
6410
f531dcb2
CW		 6411unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6412{
6413 unsigned long val;
6414
dc97997a 6415 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6416 return 0;
6417
6418 spin_lock_irq(&mchdev_lock);
6419
6420 val = __i915_gfx_val(dev_priv);
6421
6422 spin_unlock_irq(&mchdev_lock);
6423
6424 return val;
6425}
6426
eb48eb00
DV		 6427/**
6428 * i915_read_mch_val - return value for IPS use
6429 *
6430 * Calculate and return a value for the IPS driver to use when deciding whether
6431 * we have thermal and power headroom to increase CPU or GPU power budget.
6432 */
6433unsigned long i915_read_mch_val(void)
6434{
6435 struct drm_i915_private *dev_priv;
6436 unsigned long chipset_val, graphics_val, ret = 0;
6437
9270388e 6438 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6439 if (!i915_mch_dev)
6440 goto out_unlock;
6441 dev_priv = i915_mch_dev;
6442
f531dcb2
CW		 6443 chipset_val = __i915_chipset_val(dev_priv);
6444 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6445
6446 ret = chipset_val + graphics_val;
6447
6448out_unlock:
9270388e 6449 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6450
6451 return ret;
6452}
6453EXPORT_SYMBOL_GPL(i915_read_mch_val);
6454
6455/**
6456 * i915_gpu_raise - raise GPU frequency limit
6457 *
6458 * Raise the limit; IPS indicates we have thermal headroom.
6459 */
6460bool i915_gpu_raise(void)
6461{
6462 struct drm_i915_private *dev_priv;
6463 bool ret = true;
6464
9270388e 6465 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6466 if (!i915_mch_dev) {
6467 ret = false;
6468 goto out_unlock;
6469 }
6470 dev_priv = i915_mch_dev;
6471
20e4d407
DV		 6472 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6473 dev_priv->ips.max_delay--;
eb48eb00
DV		 6474
6475out_unlock:
9270388e 6476 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6477
6478 return ret;
6479}
6480EXPORT_SYMBOL_GPL(i915_gpu_raise);
6481
6482/**
6483 * i915_gpu_lower - lower GPU frequency limit
6484 *
6485 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6486 * frequency maximum.
6487 */
6488bool i915_gpu_lower(void)
6489{
6490 struct drm_i915_private *dev_priv;
6491 bool ret = true;
6492
9270388e 6493 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6494 if (!i915_mch_dev) {
6495 ret = false;
6496 goto out_unlock;
6497 }
6498 dev_priv = i915_mch_dev;
6499
20e4d407
DV		 6500 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6501 dev_priv->ips.max_delay++;
eb48eb00
DV		 6502
6503out_unlock:
9270388e 6504 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6505
6506 return ret;
6507}
6508EXPORT_SYMBOL_GPL(i915_gpu_lower);
6509
6510/**
6511 * i915_gpu_busy - indicate GPU business to IPS
6512 *
6513 * Tell the IPS driver whether or not the GPU is busy.
6514 */
6515bool i915_gpu_busy(void)
6516{
eb48eb00
DV		 6517 bool ret = false;
6518
9270388e 6519 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6520 if (i915_mch_dev)
6521 ret = i915_mch_dev->gt.awake;
9270388e 6522 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6523
6524 return ret;
6525}
6526EXPORT_SYMBOL_GPL(i915_gpu_busy);
6527
6528/**
6529 * i915_gpu_turbo_disable - disable graphics turbo
6530 *
6531 * Disable graphics turbo by resetting the max frequency and setting the
6532 * current frequency to the default.
6533 */
6534bool i915_gpu_turbo_disable(void)
6535{
6536 struct drm_i915_private *dev_priv;
6537 bool ret = true;
6538
9270388e 6539 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6540 if (!i915_mch_dev) {
6541 ret = false;
6542 goto out_unlock;
6543 }
6544 dev_priv = i915_mch_dev;
6545
20e4d407 6546 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6547
91d14251 6548 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6549 ret = false;
6550
6551out_unlock:
9270388e 6552 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6553
6554 return ret;
6555}
6556EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6557
6558/**
6559 * Tells the intel_ips driver that the i915 driver is now loaded, if
6560 * IPS got loaded first.
6561 *
6562 * This awkward dance is so that neither module has to depend on the
6563 * other in order for IPS to do the appropriate communication of
6564 * GPU turbo limits to i915.
6565 */
6566static void
6567ips_ping_for_i915_load(void)
6568{
6569 void (*link)(void);
6570
6571 link = symbol_get(ips_link_to_i915_driver);
6572 if (link) {
6573 link();
6574 symbol_put(ips_link_to_i915_driver);
6575 }
6576}
6577
6578void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6579{
02d71956
DV		 6580 /* We only register the i915 ips part with intel-ips once everything is
6581 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6582 spin_lock_irq(&mchdev_lock);
eb48eb00 6583 i915_mch_dev = dev_priv;
9270388e 6584 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6585
6586 ips_ping_for_i915_load();
6587}
6588
6589void intel_gpu_ips_teardown(void)
6590{
9270388e 6591 spin_lock_irq(&mchdev_lock);
eb48eb00 6592 i915_mch_dev = NULL;
9270388e 6593 spin_unlock_irq(&mchdev_lock);
eb48eb00 6594}
76c3552f 6595
dc97997a 6596static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6597{
dde18883
ED		 6598 u32 lcfuse;
6599 u8 pxw[16];
6600 int i;
6601
6602 /* Disable to program */
6603 I915_WRITE(ECR, 0);
6604 POSTING_READ(ECR);
6605
6606 /* Program energy weights for various events */
6607 I915_WRITE(SDEW, 0x15040d00);
6608 I915_WRITE(CSIEW0, 0x007f0000);
6609 I915_WRITE(CSIEW1, 0x1e220004);
6610 I915_WRITE(CSIEW2, 0x04000004);
6611
6612 for (i = 0; i < 5; i++)
616847e7 6613 I915_WRITE(PEW(i), 0);
dde18883 6614 for (i = 0; i < 3; i++)
616847e7 6615 I915_WRITE(DEW(i), 0);
dde18883
ED		 6616
6617 /* Program P-state weights to account for frequency power adjustment */
6618 for (i = 0; i < 16; i++) {
616847e7 6619 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6620 unsigned long freq = intel_pxfreq(pxvidfreq);
6621 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6622 PXVFREQ_PX_SHIFT;
6623 unsigned long val;
6624
6625 val = vid * vid;
6626 val *= (freq / 1000);
6627 val *= 255;
6628 val /= (127*127*900);
6629 if (val > 0xff)
6630 DRM_ERROR("bad pxval: %ld\n", val);
6631 pxw[i] = val;
6632 }
6633 /* Render standby states get 0 weight */
6634 pxw[14] = 0;
6635 pxw[15] = 0;
6636
6637 for (i = 0; i < 4; i++) {
6638 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6639 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6640 I915_WRITE(PXW(i), val);
dde18883
ED		 6641 }
6642
6643 /* Adjust magic regs to magic values (more experimental results) */
6644 I915_WRITE(OGW0, 0);
6645 I915_WRITE(OGW1, 0);
6646 I915_WRITE(EG0, 0x00007f00);
6647 I915_WRITE(EG1, 0x0000000e);
6648 I915_WRITE(EG2, 0x000e0000);
6649 I915_WRITE(EG3, 0x68000300);
6650 I915_WRITE(EG4, 0x42000000);
6651 I915_WRITE(EG5, 0x00140031);
6652 I915_WRITE(EG6, 0);
6653 I915_WRITE(EG7, 0);
6654
6655 for (i = 0; i < 8; i++)
616847e7 6656 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6657
6658 /* Enable PMON + select events */
6659 I915_WRITE(ECR, 0x80000019);
6660
6661 lcfuse = I915_READ(LCFUSE02);
6662
20e4d407 6663 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6664}
6665
dc97997a 6666void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6667{
b268c699
ID		 6668 /*
6669 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6670 * requirement.
6671 */
6672 if (!i915.enable_rc6) {
6673 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6674 intel_runtime_pm_get(dev_priv);
6675 }
e6069ca8 6676
b5163dbb 6677 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6678 mutex_lock(&dev_priv->rps.hw_lock);
6679
6680 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6681 if (IS_CHERRYVIEW(dev_priv))
6682 cherryview_init_gt_powersave(dev_priv);
6683 else if (IS_VALLEYVIEW(dev_priv))
6684 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6685 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6686 gen6_init_rps_frequencies(dev_priv);
6687
6688 /* Derive initial user preferences/limits from the hardware limits */
6689 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6690 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6691
6692 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6693 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6694
6695 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6696 dev_priv->rps.min_freq_softlimit =
6697 max_t(int,
6698 dev_priv->rps.efficient_freq,
6699 intel_freq_opcode(dev_priv, 450));
6700
99ac9612
CW		 6701 /* After setting max-softlimit, find the overclock max freq */
6702 if (IS_GEN6(dev_priv) ||
6703 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6704 u32 params = 0;
6705
6706 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6707 if (params & BIT(31)) { /* OC supported */
6708 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6709 (dev_priv->rps.max_freq & 0xff) * 50,
6710 (params & 0xff) * 50);
6711 dev_priv->rps.max_freq = params & 0xff;
6712 }
6713 }
6714
29ecd78d
CW		 6715 /* Finally allow us to boost to max by default */
6716 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6717
773ea9a8 6718 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6719 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6720
6721 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6722}
6723
dc97997a 6724void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6725{
8dac1e1f 6726 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6727 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6728
6729 if (!i915.enable_rc6)
6730 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6731}
6732
54b4f68f
CW		 6733/**
6734 * intel_suspend_gt_powersave - suspend PM work and helper threads
6735 * @dev_priv: i915 device
6736 *
6737 * We don't want to disable RC6 or other features here, we just want
6738 * to make sure any work we've queued has finished and won't bother
6739 * us while we're suspended.
6740 */
6741void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6742{
6743 if (INTEL_GEN(dev_priv) < 6)
6744 return;
6745
6746 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6747 intel_runtime_pm_put(dev_priv);
6748
6749 /* gen6_rps_idle() will be called later to disable interrupts */
6750}
6751
b7137e0c
CW		 6752void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6753{
6754 dev_priv->rps.enabled = true; /* force disabling */
6755 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6756
6757 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6758}
6759
dc97997a 6760void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6761{
b7137e0c
CW		 6762 if (!READ_ONCE(dev_priv->rps.enabled))
6763 return;
e494837a 6764
b7137e0c 6765 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6766
b7137e0c
CW		 6767 if (INTEL_GEN(dev_priv) >= 9) {
6768 gen9_disable_rc6(dev_priv);
6769 gen9_disable_rps(dev_priv);
6770 } else if (IS_CHERRYVIEW(dev_priv)) {
6771 cherryview_disable_rps(dev_priv);
6772 } else if (IS_VALLEYVIEW(dev_priv)) {
6773 valleyview_disable_rps(dev_priv);
6774 } else if (INTEL_GEN(dev_priv) >= 6) {
6775 gen6_disable_rps(dev_priv);
6776 } else if (IS_IRONLAKE_M(dev_priv)) {
6777 ironlake_disable_drps(dev_priv);
930ebb46 6778 }
b7137e0c
CW		 6779
6780 dev_priv->rps.enabled = false;
6781 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6782}
6783
b7137e0c 6784void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6785{
54b4f68f
CW		 6786 /* We shouldn't be disabling as we submit, so this should be less
6787 * racy than it appears!
6788 */
b7137e0c
CW		 6789 if (READ_ONCE(dev_priv->rps.enabled))
6790 return;
1a01ab3b 6791
b7137e0c
CW		 6792 /* Powersaving is controlled by the host when inside a VM */
6793 if (intel_vgpu_active(dev_priv))
6794 return;
0a073b84 6795
b7137e0c 6796 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6797
6798 if (IS_CHERRYVIEW(dev_priv)) {
6799 cherryview_enable_rps(dev_priv);
6800 } else if (IS_VALLEYVIEW(dev_priv)) {
6801 valleyview_enable_rps(dev_priv);
b7137e0c 6802 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6803 gen9_enable_rc6(dev_priv);
6804 gen9_enable_rps(dev_priv);
6805 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6806 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6807 } else if (IS_BROADWELL(dev_priv)) {
6808 gen8_enable_rps(dev_priv);
fb7404e8 6809 gen6_update_ring_freq(dev_priv);
b7137e0c 6810 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6811 gen6_enable_rps(dev_priv);
fb7404e8 6812 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6813 } else if (IS_IRONLAKE_M(dev_priv)) {
6814 ironlake_enable_drps(dev_priv);
6815 intel_init_emon(dev_priv);
0a073b84 6816 }
aed242ff
CW		 6817
6818 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6819 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6820
6821 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6822 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6823
54b4f68f 6824 dev_priv->rps.enabled = true;
b7137e0c
CW		 6825 mutex_unlock(&dev_priv->rps.hw_lock);
6826}
3cc134e3 6827
54b4f68f
CW		 6828static void __intel_autoenable_gt_powersave(struct work_struct *work)
6829{
6830 struct drm_i915_private *dev_priv =
6831 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6832 struct intel_engine_cs *rcs;
6833 struct drm_i915_gem_request *req;
6834
6835 if (READ_ONCE(dev_priv->rps.enabled))
6836 goto out;
6837
6838 rcs = &dev_priv->engine[RCS];
6839 if (rcs->last_context)
6840 goto out;
6841
6842 if (!rcs->init_context)
6843 goto out;
6844
6845 mutex_lock(&dev_priv->drm.struct_mutex);
6846
6847 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6848 if (IS_ERR(req))
6849 goto unlock;
6850
6851 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6852 rcs->init_context(req);
6853
6854 /* Mark the device busy, calling intel_enable_gt_powersave() */
6855 i915_add_request_no_flush(req);
6856
6857unlock:
6858 mutex_unlock(&dev_priv->drm.struct_mutex);
6859out:
6860 intel_runtime_pm_put(dev_priv);
6861}
6862
6863void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6864{
6865 if (READ_ONCE(dev_priv->rps.enabled))
6866 return;
6867
6868 if (IS_IRONLAKE_M(dev_priv)) {
6869 ironlake_enable_drps(dev_priv);
6870 mutex_lock(&dev_priv->drm.struct_mutex);
6871 intel_init_emon(dev_priv);
6872 mutex_unlock(&dev_priv->drm.struct_mutex);
6873 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6874 /*
6875 * PCU communication is slow and this doesn't need to be
6876 * done at any specific time, so do this out of our fast path
6877 * to make resume and init faster.
6878 *
6879 * We depend on the HW RC6 power context save/restore
6880 * mechanism when entering D3 through runtime PM suspend. So
6881 * disable RPM until RPS/RC6 is properly setup. We can only
6882 * get here via the driver load/system resume/runtime resume
6883 * paths, so the _noresume version is enough (and in case of
6884 * runtime resume it's necessary).
6885 */
6886 if (queue_delayed_work(dev_priv->wq,
6887 &dev_priv->rps.autoenable_work,
6888 round_jiffies_up_relative(HZ)))
6889 intel_runtime_pm_get_noresume(dev_priv);
6890 }
6891}
6892
3107bd48
DV		 6893static void ibx_init_clock_gating(struct drm_device *dev)
6894{
fac5e23e 6895 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6896
6897 /*
6898 * On Ibex Peak and Cougar Point, we need to disable clock
6899 * gating for the panel power sequencer or it will fail to
6900 * start up when no ports are active.
6901 */
6902 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6903}
6904
0e088b8f
VS		 6905static void g4x_disable_trickle_feed(struct drm_device *dev)
6906{
fac5e23e 6907 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6908 enum pipe pipe;
0e088b8f 6909
055e393f 6910 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6911 I915_WRITE(DSPCNTR(pipe),
6912 I915_READ(DSPCNTR(pipe)) |
6913 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6914
6915 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6916 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6917 }
6918}
6919
017636cc
VS		 6920static void ilk_init_lp_watermarks(struct drm_device *dev)
6921{
fac5e23e 6922 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6923
6924 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6925 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6926 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6927
6928 /*
6929 * Don't touch WM1S_LP_EN here.
6930 * Doing so could cause underruns.
6931 */
6932}
6933
1fa61106 6934static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6935{
fac5e23e 6936 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6937 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6938
f1e8fa56
DL		 6939 /*
6940 * Required for FBC
6941 * WaFbcDisableDpfcClockGating:ilk
6942 */
4d47e4f5
DL		 6943 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6944 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6945 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6946
6947 I915_WRITE(PCH_3DCGDIS0,
6948 MARIUNIT_CLOCK_GATE_DISABLE |
6949 SVSMUNIT_CLOCK_GATE_DISABLE);
6950 I915_WRITE(PCH_3DCGDIS1,
6951 VFMUNIT_CLOCK_GATE_DISABLE);
6952
6f1d69b0
ED		 6953 /*
6954 * According to the spec the following bits should be set in
6955 * order to enable memory self-refresh
6956 * The bit 22/21 of 0x42004
6957 * The bit 5 of 0x42020
6958 * The bit 15 of 0x45000
6959 */
6960 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6961 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6962 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6963 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6964 I915_WRITE(DISP_ARB_CTL,
6965 (I915_READ(DISP_ARB_CTL) |
6966 DISP_FBC_WM_DIS));
017636cc
VS		 6967
6968 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6969
6970 /*
6971 * Based on the document from hardware guys the following bits
6972 * should be set unconditionally in order to enable FBC.
6973 * The bit 22 of 0x42000
6974 * The bit 22 of 0x42004
6975 * The bit 7,8,9 of 0x42020.
6976 */
6977 if (IS_IRONLAKE_M(dev)) {
4bb35334 6978 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6979 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6980 I915_READ(ILK_DISPLAY_CHICKEN1) |
6981 ILK_FBCQ_DIS);
6982 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6983 I915_READ(ILK_DISPLAY_CHICKEN2) |
6984 ILK_DPARB_GATE);
6f1d69b0
ED		 6985 }
6986
4d47e4f5
DL		 6987 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6988
6f1d69b0
ED		 6989 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6990 I915_READ(ILK_DISPLAY_CHICKEN2) |
6991 ILK_ELPIN_409_SELECT);
6992 I915_WRITE(_3D_CHICKEN2,
6993 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6994 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6995
ecdb4eb7 6996 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6997 I915_WRITE(CACHE_MODE_0,
6998 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6999
4e04632e
AG		 7000 /* WaDisable_RenderCache_OperationalFlush:ilk */
7001 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7002
0e088b8f 7003 g4x_disable_trickle_feed(dev);
bdad2b2f 7004
3107bd48
DV		 7005 ibx_init_clock_gating(dev);
7006}
7007
7008static void cpt_init_clock_gating(struct drm_device *dev)
7009{
fac5e23e 7010 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 7011 int pipe;
3f704fa2 7012 uint32_t val;
3107bd48
DV		 7013
7014 /*
7015 * On Ibex Peak and Cougar Point, we need to disable clock
7016 * gating for the panel power sequencer or it will fail to
7017 * start up when no ports are active.
7018 */
cd664078
JB		 7019 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
7020 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
7021 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 7022 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7023 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 7024 /* The below fixes the weird display corruption, a few pixels shifted
7025 * downward, on (only) LVDS of some HP laptops with IVY.
7026 */
055e393f 7027 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 7028 val = I915_READ(TRANS_CHICKEN2(pipe));
7029 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7030 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 7031 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 7032 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7033 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7034 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7035 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7036 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7037 }
3107bd48 7038 /* WADP0ClockGatingDisable */
055e393f 7039 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7040 I915_WRITE(TRANS_CHICKEN1(pipe),
7041 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7042 }
6f1d69b0
ED		 7043}
7044
1d7aaa0c
DV		 7045static void gen6_check_mch_setup(struct drm_device *dev)
7046{
fac5e23e 7047 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7048 uint32_t tmp;
7049
7050 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7051 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7052 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7053 tmp);
1d7aaa0c
DV		 7054}
7055
1fa61106 7056static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7057{
fac5e23e 7058 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7059 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7060
231e54f6 7061 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7062
7063 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7064 I915_READ(ILK_DISPLAY_CHICKEN2) |
7065 ILK_ELPIN_409_SELECT);
7066
ecdb4eb7 7067 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7068 I915_WRITE(_3D_CHICKEN,
7069 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7070
4e04632e
AG		 7071 /* WaDisable_RenderCache_OperationalFlush:snb */
7072 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7073
8d85d272
VS		 7074 /*
7075 * BSpec recoomends 8x4 when MSAA is used,
7076 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7077 *
7078 * Note that PS/WM thread counts depend on the WIZ hashing
7079 * disable bit, which we don't touch here, but it's good
7080 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7081 */
7082 I915_WRITE(GEN6_GT_MODE,
98533251 7083 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7084
017636cc 7085 ilk_init_lp_watermarks(dev);
6f1d69b0 7086
6f1d69b0 7087 I915_WRITE(CACHE_MODE_0,
50743298 7088 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7089
7090 I915_WRITE(GEN6_UCGCTL1,
7091 I915_READ(GEN6_UCGCTL1) |
7092 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7093 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7094
7095 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7096 * gating disable must be set. Failure to set it results in
7097 * flickering pixels due to Z write ordering failures after
7098 * some amount of runtime in the Mesa "fire" demo, and Unigine
7099 * Sanctuary and Tropics, and apparently anything else with
7100 * alpha test or pixel discard.
7101 *
7102 * According to the spec, bit 11 (RCCUNIT) must also be set,
7103 * but we didn't debug actual testcases to find it out.
0f846f81 7104 *
ef59318c
VS		 7105 * WaDisableRCCUnitClockGating:snb
7106 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7107 */
7108 I915_WRITE(GEN6_UCGCTL2,
7109 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7110 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7111
5eb146dd 7112 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7113 I915_WRITE(_3D_CHICKEN3,
7114 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7115
e927ecde
VS		 7116 /*
7117 * Bspec says:
7118 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7119 * 3DSTATE_SF number of SF output attributes is more than 16."
7120 */
7121 I915_WRITE(_3D_CHICKEN3,
7122 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7123
6f1d69b0
ED		 7124 /*
7125 * According to the spec the following bits should be
7126 * set in order to enable memory self-refresh and fbc:
7127 * The bit21 and bit22 of 0x42000
7128 * The bit21 and bit22 of 0x42004
7129 * The bit5 and bit7 of 0x42020
7130 * The bit14 of 0x70180
7131 * The bit14 of 0x71180
4bb35334
DL		 7132 *
7133 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7134 */
7135 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7136 I915_READ(ILK_DISPLAY_CHICKEN1) |
7137 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7138 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7139 I915_READ(ILK_DISPLAY_CHICKEN2) |
7140 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7141 I915_WRITE(ILK_DSPCLK_GATE_D,
7142 I915_READ(ILK_DSPCLK_GATE_D) |
7143 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7144 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7145
0e088b8f 7146 g4x_disable_trickle_feed(dev);
f8f2ac9a 7147
3107bd48 7148 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7149
7150 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7151}
7152
7153static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7154{
7155 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7156
3aad9059 7157 /*
46680e0a 7158 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7159 *
7160 * This actually overrides the dispatch
7161 * mode for all thread types.
7162 */
6f1d69b0
ED		 7163 reg &= ~GEN7_FF_SCHED_MASK;
7164 reg |= GEN7_FF_TS_SCHED_HW;
7165 reg |= GEN7_FF_VS_SCHED_HW;
7166 reg |= GEN7_FF_DS_SCHED_HW;
7167
7168 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7169}
7170
17a303ec
PZ		 7171static void lpt_init_clock_gating(struct drm_device *dev)
7172{
fac5e23e 7173 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7174
7175 /*
7176 * TODO: this bit should only be enabled when really needed, then
7177 * disabled when not needed anymore in order to save power.
7178 */
c2699524 7179 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7180 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7181 I915_READ(SOUTH_DSPCLK_GATE_D) |
7182 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7183
7184 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7185 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7186 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7187 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7188}
7189
7d708ee4
ID		 7190static void lpt_suspend_hw(struct drm_device *dev)
7191{
fac5e23e 7192 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7193
c2699524 7194 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7195 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7196
7197 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7198 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7199 }
7200}
7201
450174fe
ID		 7202static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7203 int general_prio_credits,
7204 int high_prio_credits)
7205{
7206 u32 misccpctl;
7207
7208 /* WaTempDisableDOPClkGating:bdw */
7209 misccpctl = I915_READ(GEN7_MISCCPCTL);
7210 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7211
7212 I915_WRITE(GEN8_L3SQCREG1,
7213 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7214 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7215
7216 /*
7217 * Wait at least 100 clocks before re-enabling clock gating.
7218 * See the definition of L3SQCREG1 in BSpec.
7219 */
7220 POSTING_READ(GEN8_L3SQCREG1);
7221 udelay(1);
7222 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7223}
7224
9498dba7
MK		 7225static void kabylake_init_clock_gating(struct drm_device *dev)
7226{
9146f308 7227 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7228
b033bb6d 7229 gen9_init_clock_gating(dev);
9498dba7
MK		 7230
7231 /* WaDisableSDEUnitClockGating:kbl */
7232 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7233 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7234 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7235
7236 /* WaDisableGamClockGating:kbl */
7237 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7238 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7239 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7240
7241 /* WaFbcNukeOnHostModify:kbl */
7242 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7243 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7244}
7245
dc00b6a0
DV		 7246static void skylake_init_clock_gating(struct drm_device *dev)
7247{
c584e2d3 7248 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7249
b033bb6d 7250 gen9_init_clock_gating(dev);
44fff99f
MK		 7251
7252 /* WAC6entrylatency:skl */
7253 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7254 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7255
7256 /* WaFbcNukeOnHostModify:skl */
7257 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7258 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7259}
7260
47c2bd97 7261static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7262{
fac5e23e 7263 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7264 enum pipe pipe;
1020a5c2 7265
7ad0dbab 7266 ilk_init_lp_watermarks(dev);
50ed5fbd 7267
ab57fff1 7268 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7269 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7270
ab57fff1 7271 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7272 I915_WRITE(CHICKEN_PAR1_1,
7273 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7274
ab57fff1 7275 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7276 for_each_pipe(dev_priv, pipe) {
07d27e20 7277 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7278 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7279 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7280 }
63801f21 7281
ab57fff1
BW		 7282 /* WaVSRefCountFullforceMissDisable:bdw */
7283 /* WaDSRefCountFullforceMissDisable:bdw */
7284 I915_WRITE(GEN7_FF_THREAD_MODE,
7285 I915_READ(GEN7_FF_THREAD_MODE) &
7286 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7287
295e8bb7
VS		 7288 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7289 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7290
7291 /* WaDisableSDEUnitClockGating:bdw */
7292 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7293 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7294
450174fe
ID		 7295 /* WaProgramL3SqcReg1Default:bdw */
7296 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7297
6d50b065
VS		 7298 /*
7299 * WaGttCachingOffByDefault:bdw
7300 * GTT cache may not work with big pages, so if those
7301 * are ever enabled GTT cache may need to be disabled.
7302 */
7303 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7304
17e0adf0
MK		 7305 /* WaKVMNotificationOnConfigChange:bdw */
7306 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7307 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7308
89d6b2b8 7309 lpt_init_clock_gating(dev);
1020a5c2
BW		 7310}
7311
cad2a2d7
ED		 7312static void haswell_init_clock_gating(struct drm_device *dev)
7313{
fac5e23e 7314 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7315
017636cc 7316 ilk_init_lp_watermarks(dev);
cad2a2d7 7317
f3fc4884
FJ		 7318 /* L3 caching of data atomics doesn't work -- disable it. */
7319 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7320 I915_WRITE(HSW_ROW_CHICKEN3,
7321 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7322
ecdb4eb7 7323 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7324 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7325 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7326 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7327
e36ea7ff
VS		 7328 /* WaVSRefCountFullforceMissDisable:hsw */
7329 I915_WRITE(GEN7_FF_THREAD_MODE,
7330 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7331
4e04632e
AG		 7332 /* WaDisable_RenderCache_OperationalFlush:hsw */
7333 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7334
fe27c606
CW		 7335 /* enable HiZ Raw Stall Optimization */
7336 I915_WRITE(CACHE_MODE_0_GEN7,
7337 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7338
ecdb4eb7 7339 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7340 I915_WRITE(CACHE_MODE_1,
7341 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7342
a12c4967
VS		 7343 /*
7344 * BSpec recommends 8x4 when MSAA is used,
7345 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7346 *
7347 * Note that PS/WM thread counts depend on the WIZ hashing
7348 * disable bit, which we don't touch here, but it's good
7349 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7350 */
7351 I915_WRITE(GEN7_GT_MODE,
98533251 7352 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7353
94411593
KG		 7354 /* WaSampleCChickenBitEnable:hsw */
7355 I915_WRITE(HALF_SLICE_CHICKEN3,
7356 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7357
ecdb4eb7 7358 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7359 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7360
90a88643
PZ		 7361 /* WaRsPkgCStateDisplayPMReq:hsw */
7362 I915_WRITE(CHICKEN_PAR1_1,
7363 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7364
17a303ec 7365 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7366}
7367
1fa61106 7368static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7369{
fac5e23e 7370 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7371 uint32_t snpcr;
6f1d69b0 7372
017636cc 7373 ilk_init_lp_watermarks(dev);
6f1d69b0 7374
231e54f6 7375 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7376
ecdb4eb7 7377 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7378 I915_WRITE(_3D_CHICKEN3,
7379 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7380
ecdb4eb7 7381 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7382 I915_WRITE(IVB_CHICKEN3,
7383 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7384 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7385
ecdb4eb7 7386 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7387 if (IS_IVB_GT1(dev))
7388 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7389 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7390
4e04632e
AG		 7391 /* WaDisable_RenderCache_OperationalFlush:ivb */
7392 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7393
ecdb4eb7 7394 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7395 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7396 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7397
ecdb4eb7 7398 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7399 I915_WRITE(GEN7_L3CNTLREG1,
7400 GEN7_WA_FOR_GEN7_L3_CONTROL);
7401 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7402 GEN7_WA_L3_CHICKEN_MODE);
7403 if (IS_IVB_GT1(dev))
7404 I915_WRITE(GEN7_ROW_CHICKEN2,
7405 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7406 else {
7407 /* must write both registers */
7408 I915_WRITE(GEN7_ROW_CHICKEN2,
7409 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7410 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7411 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7412 }
6f1d69b0 7413
ecdb4eb7 7414 /* WaForceL3Serialization:ivb */
61939d97
JB		 7415 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7416 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7417
1b80a19a 7418 /*
0f846f81 7419 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7420 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7421 */
7422 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7423 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7424
ecdb4eb7 7425 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7426 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7427 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7428 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7429
0e088b8f 7430 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7431
7432 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7433
22721343
CW		 7434 if (0) { /* causes HiZ corruption on ivb:gt1 */
7435 /* enable HiZ Raw Stall Optimization */
7436 I915_WRITE(CACHE_MODE_0_GEN7,
7437 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7438 }
116f2b6d 7439
ecdb4eb7 7440 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7441 I915_WRITE(CACHE_MODE_1,
7442 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7443
a607c1a4
VS		 7444 /*
7445 * BSpec recommends 8x4 when MSAA is used,
7446 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7447 *
7448 * Note that PS/WM thread counts depend on the WIZ hashing
7449 * disable bit, which we don't touch here, but it's good
7450 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7451 */
7452 I915_WRITE(GEN7_GT_MODE,
98533251 7453 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7454
20848223
BW		 7455 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7456 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7457 snpcr |= GEN6_MBC_SNPCR_MED;
7458 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7459
ab5c608b
BW		 7460 if (!HAS_PCH_NOP(dev))
7461 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7462
7463 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7464}
7465
1fa61106 7466static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7467{
fac5e23e 7468 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7469
ecdb4eb7 7470 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7471 I915_WRITE(_3D_CHICKEN3,
7472 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7473
ecdb4eb7 7474 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7475 I915_WRITE(IVB_CHICKEN3,
7476 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7477 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7478
fad7d36e 7479 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7480 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7481 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7482 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7483 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7484
4e04632e
AG		 7485 /* WaDisable_RenderCache_OperationalFlush:vlv */
7486 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7487
ecdb4eb7 7488 /* WaForceL3Serialization:vlv */
61939d97
JB		 7489 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7490 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7491
ecdb4eb7 7492 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7493 I915_WRITE(GEN7_ROW_CHICKEN2,
7494 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7495
ecdb4eb7 7496 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7497 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7498 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7499 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7500
46680e0a
VS		 7501 gen7_setup_fixed_func_scheduler(dev_priv);
7502
3c0edaeb 7503 /*
0f846f81 7504 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7505 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7506 */
7507 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7508 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7509
c98f5062
AG		 7510 /* WaDisableL3Bank2xClockGate:vlv
7511 * Disabling L3 clock gating- MMIO 940c[25] = 1
7512 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7513 I915_WRITE(GEN7_UCGCTL4,
7514 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7515
afd58e79
VS		 7516 /*
7517 * BSpec says this must be set, even though
7518 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7519 */
6b26c86d
DV		 7520 I915_WRITE(CACHE_MODE_1,
7521 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7522
da2518f9
VS		 7523 /*
7524 * BSpec recommends 8x4 when MSAA is used,
7525 * however in practice 16x4 seems fastest.
7526 *
7527 * Note that PS/WM thread counts depend on the WIZ hashing
7528 * disable bit, which we don't touch here, but it's good
7529 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7530 */
7531 I915_WRITE(GEN7_GT_MODE,
7532 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7533
031994ee
VS		 7534 /*
7535 * WaIncreaseL3CreditsForVLVB0:vlv
7536 * This is the hardware default actually.
7537 */
7538 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7539
2d809570 7540 /*
ecdb4eb7 7541 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7542 * Disable clock gating on th GCFG unit to prevent a delay
7543 * in the reporting of vblank events.
7544 */
7a0d1eed 7545 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7546}
7547
a4565da8
VS		 7548static void cherryview_init_clock_gating(struct drm_device *dev)
7549{
fac5e23e 7550 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7551
232ce337
VS		 7552 /* WaVSRefCountFullforceMissDisable:chv */
7553 /* WaDSRefCountFullforceMissDisable:chv */
7554 I915_WRITE(GEN7_FF_THREAD_MODE,
7555 I915_READ(GEN7_FF_THREAD_MODE) &
7556 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7557
7558 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7559 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7560 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7561
7562 /* WaDisableCSUnitClockGating:chv */
7563 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7564 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7565
7566 /* WaDisableSDEUnitClockGating:chv */
7567 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7568 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7569
450174fe
ID		 7570 /*
7571 * WaProgramL3SqcReg1Default:chv
7572 * See gfxspecs/Related Documents/Performance Guide/
7573 * LSQC Setting Recommendations.
7574 */
7575 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7576
6d50b065
VS		 7577 /*
7578 * GTT cache may not work with big pages, so if those
7579 * are ever enabled GTT cache may need to be disabled.
7580 */
7581 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7582}
7583
1fa61106 7584static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7585{
fac5e23e 7586 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7587 uint32_t dspclk_gate;
7588
7589 I915_WRITE(RENCLK_GATE_D1, 0);
7590 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7591 GS_UNIT_CLOCK_GATE_DISABLE |
7592 CL_UNIT_CLOCK_GATE_DISABLE);
7593 I915_WRITE(RAMCLK_GATE_D, 0);
7594 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7595 OVRUNIT_CLOCK_GATE_DISABLE |
7596 OVCUNIT_CLOCK_GATE_DISABLE;
7597 if (IS_GM45(dev))
7598 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7599 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7600
7601 /* WaDisableRenderCachePipelinedFlush */
7602 I915_WRITE(CACHE_MODE_0,
7603 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7604
4e04632e
AG		 7605 /* WaDisable_RenderCache_OperationalFlush:g4x */
7606 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7607
0e088b8f 7608 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7609}
7610
1fa61106 7611static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7612{
fac5e23e 7613 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7614
7615 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7616 I915_WRITE(RENCLK_GATE_D2, 0);
7617 I915_WRITE(DSPCLK_GATE_D, 0);
7618 I915_WRITE(RAMCLK_GATE_D, 0);
7619 I915_WRITE16(DEUC, 0);
20f94967
VS		 7620 I915_WRITE(MI_ARB_STATE,
7621 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7622
7623 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7624 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7625}
7626
1fa61106 7627static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7628{
fac5e23e 7629 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7630
7631 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7632 I965_RCC_CLOCK_GATE_DISABLE |
7633 I965_RCPB_CLOCK_GATE_DISABLE |
7634 I965_ISC_CLOCK_GATE_DISABLE |
7635 I965_FBC_CLOCK_GATE_DISABLE);
7636 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7637 I915_WRITE(MI_ARB_STATE,
7638 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7639
7640 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7641 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7642}
7643
1fa61106 7644static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7645{
fac5e23e 7646 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7647 u32 dstate = I915_READ(D_STATE);
7648
7649 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7650 DSTATE_DOT_CLOCK_GATING;
7651 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7652
7653 if (IS_PINEVIEW(dev))
7654 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7655
7656 /* IIR "flip pending" means done if this bit is set */
7657 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7658
7659 /* interrupts should cause a wake up from C3 */
3299254f 7660 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7661
7662 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7663 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7664
7665 I915_WRITE(MI_ARB_STATE,
7666 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7667}
7668
1fa61106 7669static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7670{
fac5e23e 7671 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7672
7673 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7674
7675 /* interrupts should cause a wake up from C3 */
7676 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7677 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7678
7679 I915_WRITE(MEM_MODE,
7680 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7681}
7682
1fa61106 7683static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7684{
fac5e23e 7685 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7686
7687 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7688
7689 I915_WRITE(MEM_MODE,
7690 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7691 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7692}
7693
6f1d69b0
ED		 7694void intel_init_clock_gating(struct drm_device *dev)
7695{
fac5e23e 7696 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7697
bb400da9 7698 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7699}
7700
7d708ee4
ID		 7701void intel_suspend_hw(struct drm_device *dev)
7702{
7703 if (HAS_PCH_LPT(dev))
7704 lpt_suspend_hw(dev);
7705}
7706
bb400da9
ID		 7707static void nop_init_clock_gating(struct drm_device *dev)
7708{
7709 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7710}
7711
7712/**
7713 * intel_init_clock_gating_hooks - setup the clock gating hooks
7714 * @dev_priv: device private
7715 *
7716 * Setup the hooks that configure which clocks of a given platform can be
7717 * gated and also apply various GT and display specific workarounds for these
7718 * platforms. Note that some GT specific workarounds are applied separately
7719 * when GPU contexts or batchbuffers start their execution.
7720 */
7721void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7722{
7723 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7724 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7725 else if (IS_KABYLAKE(dev_priv))
9498dba7 7726 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7727 else if (IS_BROXTON(dev_priv))
7728 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7729 else if (IS_BROADWELL(dev_priv))
7730 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7731 else if (IS_CHERRYVIEW(dev_priv))
7732 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7733 else if (IS_HASWELL(dev_priv))
7734 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7735 else if (IS_IVYBRIDGE(dev_priv))
7736 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7737 else if (IS_VALLEYVIEW(dev_priv))
7738 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7739 else if (IS_GEN6(dev_priv))
7740 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7741 else if (IS_GEN5(dev_priv))
7742 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7743 else if (IS_G4X(dev_priv))
7744 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7745 else if (IS_CRESTLINE(dev_priv))
7746 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7747 else if (IS_BROADWATER(dev_priv))
7748 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7749 else if (IS_GEN3(dev_priv))
7750 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7751 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7752 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7753 else if (IS_GEN2(dev_priv))
7754 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7755 else {
7756 MISSING_CASE(INTEL_DEVID(dev_priv));
7757 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7758 }
7759}
7760
1fa61106
ED		 7761/* Set up chip specific power management-related functions */
7762void intel_init_pm(struct drm_device *dev)
7763{
fac5e23e 7764 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7765
7ff0ebcc 7766 intel_fbc_init(dev_priv);
1fa61106 7767
c921aba8
DV		 7768 /* For cxsr */
7769 if (IS_PINEVIEW(dev))
7770 i915_pineview_get_mem_freq(dev);
7771 else if (IS_GEN5(dev))
7772 i915_ironlake_get_mem_freq(dev);
7773
1fa61106 7774 /* For FIFO watermark updates */
f5ed50cb 7775 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7776 skl_setup_wm_latency(dev);
2d41c0b5 7777 dev_priv->display.update_wm = skl_update_wm;
98d39494 7778 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7779 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7780 ilk_setup_wm_latency(dev);
53615a5e 7781
bd602544
VS		 7782 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7783 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7784 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7785 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7786 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7787 dev_priv->display.compute_intermediate_wm =
7788 ilk_compute_intermediate_wm;
7789 dev_priv->display.initial_watermarks =
7790 ilk_initial_watermarks;
7791 dev_priv->display.optimize_watermarks =
7792 ilk_optimize_watermarks;
bd602544
VS		 7793 } else {
7794 DRM_DEBUG_KMS("Failed to read display plane latency. "
7795 "Disable CxSR\n");
7796 }
a4565da8 7797 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7798 vlv_setup_wm_latency(dev);
262cd2e1 7799 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7800 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7801 vlv_setup_wm_latency(dev);
26e1fe4f 7802 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7803 } else if (IS_PINEVIEW(dev)) {
7804 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7805 dev_priv->is_ddr3,
7806 dev_priv->fsb_freq,
7807 dev_priv->mem_freq)) {
7808 DRM_INFO("failed to find known CxSR latency "
7809 "(found ddr%s fsb freq %d, mem freq %d), "
7810 "disabling CxSR\n",
7811 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7812 dev_priv->fsb_freq, dev_priv->mem_freq);
7813 /* Disable CxSR and never update its watermark again */
5209b1f4 7814 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7815 dev_priv->display.update_wm = NULL;
7816 } else
7817 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7818 } else if (IS_G4X(dev)) {
7819 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7820 } else if (IS_GEN4(dev)) {
7821 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7822 } else if (IS_GEN3(dev)) {
7823 dev_priv->display.update_wm = i9xx_update_wm;
7824 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7825 } else if (IS_GEN2(dev)) {
7826 if (INTEL_INFO(dev)->num_pipes == 1) {
7827 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7828 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7829 } else {
7830 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7831 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7832 }
feb56b93
DV		 7833 } else {
7834 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7835 }
7836}
7837
87660502
L		 7838static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7839{
7840 uint32_t flags =
7841 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7842
7843 switch (flags) {
7844 case GEN6_PCODE_SUCCESS:
7845 return 0;
7846 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7847 case GEN6_PCODE_ILLEGAL_CMD:
7848 return -ENXIO;
7849 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850 return -EOVERFLOW;
7851 case GEN6_PCODE_TIMEOUT:
7852 return -ETIMEDOUT;
7853 default:
7854 MISSING_CASE(flags)
7855 return 0;
7856 }
7857}
7858
7859static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7860{
7861 uint32_t flags =
7862 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7863
7864 switch (flags) {
7865 case GEN6_PCODE_SUCCESS:
7866 return 0;
7867 case GEN6_PCODE_ILLEGAL_CMD:
7868 return -ENXIO;
7869 case GEN7_PCODE_TIMEOUT:
7870 return -ETIMEDOUT;
7871 case GEN7_PCODE_ILLEGAL_DATA:
7872 return -EINVAL;
7873 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7874 return -EOVERFLOW;
7875 default:
7876 MISSING_CASE(flags);
7877 return 0;
7878 }
7879}
7880
151a49d0 7881int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7882{
87660502
L		 7883 int status;
7884
4fc688ce 7885 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7886
3f5582dd
CW		 7887 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7888 * use te fw I915_READ variants to reduce the amount of work
7889 * required when reading/writing.
7890 */
7891
7892 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7893 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7894 return -EAGAIN;
7895 }
7896
3f5582dd
CW		 7897 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7898 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7899 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7900
3f5582dd
CW		 7901 if (intel_wait_for_register_fw(dev_priv,
7902 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7903 500)) {
42c0526c
BW		 7904 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7905 return -ETIMEDOUT;
7906 }
7907
3f5582dd
CW		 7908 *val = I915_READ_FW(GEN6_PCODE_DATA);
7909 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7910
87660502
L		 7911 if (INTEL_GEN(dev_priv) > 6)
7912 status = gen7_check_mailbox_status(dev_priv);
7913 else
7914 status = gen6_check_mailbox_status(dev_priv);
7915
7916 if (status) {
7917 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7918 status);
7919 return status;
7920 }
7921
42c0526c
BW		 7922 return 0;
7923}
7924
3f5582dd 7925int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7926 u32 mbox, u32 val)
42c0526c 7927{
87660502
L		 7928 int status;
7929
4fc688ce 7930 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7931
3f5582dd
CW		 7932 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7933 * use te fw I915_READ variants to reduce the amount of work
7934 * required when reading/writing.
7935 */
7936
7937 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7938 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7939 return -EAGAIN;
7940 }
7941
3f5582dd
CW		 7942 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7943 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7944
3f5582dd
CW		 7945 if (intel_wait_for_register_fw(dev_priv,
7946 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7947 500)) {
42c0526c
BW		 7948 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7949 return -ETIMEDOUT;
7950 }
7951
3f5582dd 7952 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7953
87660502
L		 7954 if (INTEL_GEN(dev_priv) > 6)
7955 status = gen7_check_mailbox_status(dev_priv);
7956 else
7957 status = gen6_check_mailbox_status(dev_priv);
7958
7959 if (status) {
7960 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7961 status);
7962 return status;
7963 }
7964
42c0526c
BW		 7965 return 0;
7966}
a0e4e199 7967
dd06f88c
VS		 7968static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7969{
c30fec65
VS		 7970 /*
7971 * N = val - 0xb7
7972 * Slow = Fast = GPLL ref * N
7973 */
7974 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7975}
7976
b55dd647 7977static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7978{
c30fec65 7979 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7980}
7981
b55dd647 7982static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7983{
c30fec65
VS		 7984 /*
7985 * N = val / 2
7986 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7987 */
7988 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7989}
7990
b55dd647 7991static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7992{
1c14762d 7993 /* CHV needs even values */
c30fec65 7994 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7995}
7996
616bc820 7997int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7998{
2d1fe073 7999 if (IS_GEN9(dev_priv))
500a3d2e
MK		 8000 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
8001 GEN9_FREQ_SCALER);
2d1fe073 8002 else if (IS_CHERRYVIEW(dev_priv))
616bc820 8003 return chv_gpu_freq(dev_priv, val);
2d1fe073 8004 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 8005 return byt_gpu_freq(dev_priv, val);
8006 else
8007 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 8008}
8009
616bc820
VS		 8010int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
8011{
2d1fe073 8012 if (IS_GEN9(dev_priv))
500a3d2e
MK		 8013 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
8014 GT_FREQUENCY_MULTIPLIER);
2d1fe073 8015 else if (IS_CHERRYVIEW(dev_priv))
616bc820 8016 return chv_freq_opcode(dev_priv, val);
2d1fe073 8017 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 8018 return byt_freq_opcode(dev_priv, val);
8019 else
500a3d2e 8020 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 8021}
22b1b2f8 8022
6ad790c0
CW		 8023struct request_boost {
8024 struct work_struct work;
eed29a5b 8025 struct drm_i915_gem_request *req;
6ad790c0
CW		 8026};
8027
8028static void __intel_rps_boost_work(struct work_struct *work)
8029{
8030 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8031 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8032
f69a02c9 8033 if (!i915_gem_request_completed(req))
c033666a 8034 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8035
e8a261ea 8036 i915_gem_request_put(req);
6ad790c0
CW		 8037 kfree(boost);
8038}
8039
91d14251 8040void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8041{
8042 struct request_boost *boost;
8043
91d14251 8044 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8045 return;
8046
f69a02c9 8047 if (i915_gem_request_completed(req))
e61b9958
CW		 8048 return;
8049
6ad790c0
CW		 8050 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8051 if (boost == NULL)
8052 return;
8053
e8a261ea 8054 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8055
8056 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8057 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8058}
8059
f742a552 8060void intel_pm_setup(struct drm_device *dev)
907b28c5 8061{
fac5e23e 8062 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8063
f742a552 8064 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8065 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8066
54b4f68f
CW		 8067 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8068 __intel_autoenable_gt_powersave);
1854d5ca 8069 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8070
33688d95 8071 dev_priv->pm.suspended = false;
1f814dac 8072 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 8073 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8074}
Linux kernel - Deliverables
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