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Merge branch 'jejb-fixes' into fixes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 489};
b445e3b0 490static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 510};
9d539105 511static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 517};
9d539105
VS		 518static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524};
feb56b93 525static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532
b445e3b0
ED		 533/**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
ac484963 537 * @cpp: bytes per pixel
b445e3b0
ED		 538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
ac484963 553 int fifo_size, int cpp,
b445e3b0
ED		 554 unsigned long latency_ns)
555{
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
ac484963 564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
d6feb196
VS		 579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
b445e3b0
ED		 590 return wm_size;
591}
592
593static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594{
595 struct drm_crtc *crtc, *enabled = NULL;
596
70e1e0ec 597 for_each_crtc(dev, crtc) {
3490ea5d 598 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606}
607
46ba614c 608static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 609{
46ba614c 610 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 621 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
7c5f93b0 627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 629 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
ac484963 634 cpp, latency->display_sr);
b445e3b0
ED		 635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
f4998963 637 reg |= FW_WM(wm, SR);
b445e3b0
ED		 638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
ac484963 644 cpp, latency->cursor_sr);
b445e3b0
ED		 645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 647 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
ac484963 653 cpp, latency->display_hpll_disable);
b445e3b0
ED		 654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 656 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
ac484963 662 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 665 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
5209b1f4 669 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 670 } else {
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 }
673}
674
675static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
ac484963 686 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 691 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
6e3c9717 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 698 clock = adjusted_mode->crtc_clock;
fec8cba3 699 htotal = adjusted_mode->crtc_htotal;
6e3c9717 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 702
703 /* Use the small buffer method to calculate plane watermark */
ac484963 704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
922044c9 714 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726}
727
728/*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739{
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761}
762
763static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769{
770 struct drm_crtc *crtc;
4fe8590a 771 const struct drm_display_mode *adjusted_mode;
ac484963 772 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 785 clock = adjusted_mode->crtc_clock;
fec8cba3 786 htotal = adjusted_mode->crtc_htotal;
6e3c9717 787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 789
922044c9 790 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 791 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 792 line_size = hdisplay * cpp;
b445e3b0
ED		 793
794 /* Use the minimum of the small and large buffer method for primary */
ac484963 795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
ac484963 802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809}
810
15665979
VS		 811#define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
0018fda1
VS		 814static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816{
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
ae80152d 826 I915_WRITE(DSPFW1,
15665979
VS		 827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 831 I915_WRITE(DSPFW2,
15665979
VS		 832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 835 I915_WRITE(DSPFW3,
15665979 836 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
15665979
VS		 840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 842 I915_WRITE(DSPFW8_CHV,
15665979
VS		 843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 845 I915_WRITE(DSPFW9_CHV,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 848 I915_WRITE(DSPHOWM,
15665979
VS		 849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 859 } else {
860 I915_WRITE(DSPFW7,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 863 I915_WRITE(DSPHOWM,
15665979
VS		 864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 871 }
872
2cb389b7
VS		 873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
ae80152d 879 POSTING_READ(DSPFW1);
0018fda1
VS		 880}
881
15665979
VS		 882#undef FW_WM_VLV
883
6eb1a681
VS		 884enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 888};
889
262cd2e1
VS		 890/* latency must be in 0.1us units. */
891static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
ac484963 894 unsigned int cpp,
262cd2e1
VS		 895 unsigned int latency)
896{
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 900 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904}
905
906static void vlv_setup_wm_latency(struct drm_device *dev)
907{
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
58590c14
VS		 913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
262cd2e1
VS		 915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 920 }
921}
922
923static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927{
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 929 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
ac484963 937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
ac484963 953 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958}
959
54f1b6e1
VS		 960static void vlv_compute_fifo(struct intel_crtc *crtc)
961{
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025}
1026
262cd2e1
VS		 1027static void vlv_invert_wms(struct intel_crtc *crtc)
1028{
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059}
1060
26e1fe4f 1061static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1062{
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
852eb00d 1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1073
1074 wm_state->num_active_planes = 0;
262cd2e1 1075
54f1b6e1 1076 vlv_compute_fifo(crtc);
262cd2e1
VS		 1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
5a37ed0a 1133 wm_state->wm[level].cursor;
262cd2e1
VS		 1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
58590c14 1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158}
1159
54f1b6e1
VS		 1160#define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164{
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246}
1247
1248#undef VLV_FIFO
1249
262cd2e1
VS		 1250static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252{
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
58590c14 1256 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
6f9c784b
VS		 1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
262cd2e1
VS		 1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294}
1295
1296static void vlv_update_wm(struct drm_crtc *crtc)
1297{
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
26e1fe4f 1304 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1305 vlv_merge_wm(dev, &wm);
1306
54f1b6e1
VS		 1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1310 return;
54f1b6e1 1311 }
262cd2e1
VS		 1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
852eb00d 1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1322 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1323
54f1b6e1
VS		 1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
262cd2e1
VS		 1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
852eb00d 1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1347}
1348
ae80152d
VS		 1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
46ba614c 1351static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1352{
46ba614c 1353 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
9858425c 1359 bool cxsr_enabled;
b445e3b0 1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
52bd02d8 1378 &plane_sr, &cursor_sr)) {
9858425c 1379 cxsr_enabled = true;
52bd02d8 1380 } else {
9858425c 1381 cxsr_enabled = false;
5209b1f4 1382 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0 1385
a5043453
VS		 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
f4998963
VS		 1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
b445e3b0 1397 I915_WRITE(DSPFW2,
8c919b28 1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1399 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
8c919b28 1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1403 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1407}
1408
46ba614c 1409static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1410{
46ba614c 1411 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
9858425c 1416 bool cxsr_enabled;
b445e3b0
ED		 1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
124abe07 1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1424 int clock = adjusted_mode->crtc_clock;
fec8cba3 1425 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1428 unsigned long line_time_us;
1429 int entries;
1430
922044c9 1431 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1435 cpp * hdisplay;
b445e3b0
ED		 1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1445 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
9858425c 1457 cxsr_enabled = true;
b445e3b0 1458 } else {
9858425c 1459 cxsr_enabled = false;
b445e3b0 1460 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
f4998963
VS		 1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
b445e3b0 1474 /* update cursor SR watermark */
f4998963 1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1479}
1480
f4998963
VS		 1481#undef FW_WM
1482
46ba614c 1483static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
9d539105 1500 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1504 if (intel_crtc_active(crtc)) {
241bfc38 1505 const struct drm_display_mode *adjusted_mode;
ac484963 1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
6e3c9717 1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1512 wm_info, fifo_size, cpp,
5aef6003 1513 pessimal_latency_ns);
b445e3b0 1514 enabled = crtc;
9d539105 1515 } else {
b445e3b0 1516 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
ac484963 1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
6e3c9717 1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
5aef6003 1535 pessimal_latency_ns);
b445e3b0
ED		 1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
9d539105 1540 } else {
b445e3b0 1541 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
b445e3b0
ED		 1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d 1548 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1549 struct drm_i915_gem_object *obj;
2ab1bc9d 1550
59bea882 1551 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1552
1553 /* self-refresh seems busted with untiled */
2ff8fde1 1554 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1564 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
124abe07 1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1571 int clock = adjusted_mode->crtc_clock;
fec8cba3 1572 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1575 unsigned long line_time_us;
1576 int entries;
1577
922044c9 1578 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1582 cpp * hdisplay;
b445e3b0
ED		 1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
5209b1f4
ID		 1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
6e3c9717 1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1630 4, pessimal_latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
8cfb3407 1639uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1640{
fd4daa9c 1641 uint32_t pixel_rate;
801bcfff 1642
8cfb3407 1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
8cfb3407 1648 if (pipe_config->pch_pfit.enabled) {
801bcfff 1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
801bcfff 1654
801bcfff
PZ		 1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
15126882
MR		 1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
801bcfff
PZ		 1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670}
1671
37126462 1672/* latency must be in 0.1us units. */
ac484963 1673static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1674{
1675 uint64_t ret;
1676
3312ba65
VS		 1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
ac484963 1680 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1688 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1689 uint32_t latency)
1690{
1691 uint32_t ret;
1692
3312ba65
VS		 1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
15126882
MR		 1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
3312ba65 1697
801bcfff 1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1699 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702}
1703
23297044 1704static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1705 uint8_t cpp)
cca32e9a 1706{
15126882
MR		 1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
ac484963 1713 if (WARN_ON(!cpp))
15126882
MR		 1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
ac484963 1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1719}
1720
820c1980 1721struct ilk_wm_maximums {
cca32e9a
PZ		 1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726};
1727
37126462
VS		 1728/*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
7221fc33 1732static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1733 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1734 uint32_t mem_value,
1735 bool is_lp)
801bcfff 1736{
ac484963
VS		 1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1739 uint32_t method1, method2;
1740
7221fc33 1741 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1742 return 0;
1743
ac484963 1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1745
1746 if (!is_lp)
1747 return method1;
1748
7221fc33
MR		 1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1751 drm_rect_width(&pstate->dst),
ac484963 1752 cpp, mem_value);
cca32e9a
PZ		 1753
1754 return min(method1, method2);
801bcfff
PZ		 1755}
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
801bcfff
PZ		 1763 uint32_t mem_value)
1764{
ac484963
VS		 1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1767 uint32_t method1, method2;
1768
7221fc33 1769 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1770 return 0;
1771
ac484963 1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1775 drm_rect_width(&pstate->dst),
ac484963 1776 cpp, mem_value);
801bcfff
PZ		 1777 return min(method1, method2);
1778}
1779
37126462
VS		 1780/*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
7221fc33 1784static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1785 const struct intel_plane_state *pstate,
801bcfff
PZ		 1786 uint32_t mem_value)
1787{
b2435692
MR		 1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1795
b2435692 1796 if (!cstate->base.active)
801bcfff
PZ		 1797 return 0;
1798
7221fc33
MR		 1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1801 width, cpp, mem_value);
801bcfff
PZ		 1802}
1803
cca32e9a 1804/* Only for WM_LP. */
7221fc33 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1806 const struct intel_plane_state *pstate,
1fda9882 1807 uint32_t pri_val)
cca32e9a 1808{
ac484963
VS		 1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1811
7221fc33 1812 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1813 return 0;
1814
ac484963 1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1816}
1817
158ae64f
VS		 1818static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819{
416f4727
VS		 1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1823 return 768;
1824 else
1825 return 512;
1826}
1827
4e975081
VS		 1828static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830{
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843}
1844
1845static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847{
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852}
1853
1854static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855{
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860}
1861
158ae64f
VS		 1862/* Calculate the maximum primary/sprite plane watermark */
1863static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
240264f4 1865 const struct intel_wm_config *config,
158ae64f
VS		 1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868{
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1870
1871 /* if sprites aren't enabled, sprites get nothing */
240264f4 1872 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1876 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
240264f4 1888 if (config->sprites_enabled) {
158ae64f
VS		 1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
4e975081 1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1901}
1902
1903/* Calculate the maximum cursor plane watermark */
1904static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1905 int level,
1906 const struct intel_wm_config *config)
158ae64f
VS		 1907{
1908 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1909 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
4e975081 1913 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1914}
1915
d34ff9c6 1916static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1920 struct ilk_wm_maximums *max)
158ae64f 1921{
240264f4
VS		 1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1925 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1926}
1927
a3cb4048
VS		 1928static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931{
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936}
1937
d9395655 1938static bool ilk_validate_wm_level(int level,
820c1980 1939 const struct ilk_wm_maximums *max,
d9395655 1940 struct intel_wm_level *result)
a9786a11
VS		 1941{
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
a9786a11
VS		 1976 return ret;
1977}
1978
d34ff9c6 1979static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1980 const struct intel_crtc *intel_crtc,
6f5ddd17 1981 int level,
7221fc33 1982 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1fd527cc 1986 struct intel_wm_level *result)
6f5ddd17
VS		 1987{
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
e3bddded
ML		 1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
6f5ddd17
VS		 2011 result->enable = true;
2012}
2013
801bcfff 2014static uint32_t
ee91a159
MR		 2015hsw_compute_linetime_wm(struct drm_device *dev,
2016 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2017{
2018 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
85a02deb 2021 u32 linetime, ips_linetime;
1f8eeabf 2022
ee91a159
MR		 2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
2027 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2028 return 0;
1011d8c4 2029
1f8eeabf
ED		 2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
124abe07
VS		 2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2036 dev_priv->cdclk_freq);
1f8eeabf 2037
801bcfff
PZ		 2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2040}
2041
2af30a5c 2042static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2af30a5c
PB		 2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
4f947386 2048 int ret, i;
367294be 2049 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
367294be 2092 /*
6f97235b
DL		 2093 * WaWmMemoryReadLatency:skl
2094 *
367294be
VK		 2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
367294be
VK		 2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
4f947386
VK		 2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
367294be 2116
4f947386
VK		 2117 break;
2118 }
2af30a5c 2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2143 }
2144}
2145
53615a5e
VS		 2146static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147{
2148 /* ILK sprite LP0 latency is 1300 ns */
2149 if (INTEL_INFO(dev)->gen == 5)
2150 wm[0] = 13;
2151}
2152
2153static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK cursor LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162}
2163
546c81fd 2164int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2165{
26ec971e 2166 /* how many WM levels are we expecting */
b6e742f6 2167 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2170 return 4;
26ec971e 2171 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2172 return 3;
26ec971e 2173 else
ad0d6dc4
VS		 2174 return 2;
2175}
7526ed79 2176
ad0d6dc4
VS		 2177static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2af30a5c 2179 const uint16_t wm[8])
ad0d6dc4
VS		 2180{
2181 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2af30a5c
PB		 2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
26ec971e
VS		 2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205}
2206
e95a2f75
VS		 2207static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209{
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220}
2221
2222static void snb_wm_latency_quirk(struct drm_device *dev)
2223{
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242}
2243
fa50ad61 2244static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
53615a5e
VS		 2264}
2265
2af30a5c
PB		 2266static void skl_setup_wm_latency(struct drm_device *dev)
2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272}
2273
ed4a6a7c
MR		 2274static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276{
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295}
2296
0b2ae6d7 2297/* Compute new watermarks for the pipe */
e3bddded 2298static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2299{
e3bddded
ML		 2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2302 struct intel_pipe_wm *pipe_wm;
e3bddded 2303 struct drm_device *dev = state->dev;
d34ff9c6 2304 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2305 struct intel_plane *intel_plane;
86c8bbbe 2306 struct intel_plane_state *pristate = NULL;
43d59eda 2307 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2308 struct intel_plane_state *curstate = NULL;
d81f04c5 2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2310 struct ilk_wm_maximums max;
0b2ae6d7 2311
86c8bbbe
MR		 2312 pipe_wm = &cstate->wm.optimal.ilk;
2313
43d59eda 2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
86c8bbbe
MR		 2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2323 pristate = ps;
86c8bbbe 2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2325 sprstate = ps;
86c8bbbe 2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2327 curstate = ps;
43d59eda
MR		 2328 }
2329
bf220452 2330 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
d81f04c5 2338 usable_level = max_level;
bf220452 2339
7b39a0b7 2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2341 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2342 usable_level = 1;
7b39a0b7
VS		 2343
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2345 if (pipe_wm->sprites_scaled)
d81f04c5 2346 usable_level = 0;
7b39a0b7 2347
86c8bbbe 2348 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2349 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2353
a42a5719 2354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2355 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2356
ed4a6a7c 2357 if (!ilk_validate_pipe_wm(dev, pipe_wm))
bf220452 2358 return -EINVAL;
a3cb4048
VS		 2359
2360 ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362 for (level = 1; level <= max_level; level++) {
71f0a626 2363 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2364
86c8bbbe 2365 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2366 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2367
2368 /*
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2371 * always invalid.
2372 */
71f0a626
ML		 2373 if (level > usable_level)
2374 continue;
a3cb4048 2375
71f0a626
ML		 2376 if (ilk_validate_wm_level(level, &max, wm))
2377 pipe_wm->wm[level] = *wm;
2378 else
d81f04c5 2379 usable_level = level;
a3cb4048
VS		 2380 }
2381
86c8bbbe 2382 return 0;
0b2ae6d7
VS		 2383}
2384
ed4a6a7c
MR		 2385/*
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2388 * immediately.
2389 */
2390static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391 struct intel_crtc *intel_crtc,
2392 struct intel_crtc_state *newstate)
2393{
2394 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2395 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396 int level, max_level = ilk_wm_max_level(dev);
2397
2398 /*
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2402 */
2403 *a = newstate->wm.optimal.ilk;
2404 a->pipe_enabled |= b->pipe_enabled;
2405 a->sprites_enabled |= b->sprites_enabled;
2406 a->sprites_scaled |= b->sprites_scaled;
2407
2408 for (level = 0; level <= max_level; level++) {
2409 struct intel_wm_level *a_wm = &a->wm[level];
2410 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412 a_wm->enable &= b_wm->enable;
2413 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417 }
2418
2419 /*
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2424 */
2425 if (!ilk_validate_pipe_wm(dev, a))
2426 return -EINVAL;
2427
2428 /*
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2431 */
2432 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2433 newstate->wm.need_postvbl_update = false;
2434
2435 return 0;
2436}
2437
0b2ae6d7
VS		 2438/*
2439 * Merge the watermarks from all active pipes for a specific level.
2440 */
2441static void ilk_merge_wm_level(struct drm_device *dev,
2442 int level,
2443 struct intel_wm_level *ret_wm)
2444{
2445 const struct intel_crtc *intel_crtc;
2446
d52fea5b
VS		 2447 ret_wm->enable = true;
2448
d3fcc808 2449 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2450 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2451 const struct intel_wm_level *wm = &active->wm[level];
2452
2453 if (!active->pipe_enabled)
2454 continue;
0b2ae6d7 2455
d52fea5b
VS		 2456 /*
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2460 */
0b2ae6d7 2461 if (!wm->enable)
d52fea5b 2462 ret_wm->enable = false;
0b2ae6d7
VS		 2463
2464 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468 }
0b2ae6d7
VS		 2469}
2470
2471/*
2472 * Merge all low power watermarks for all active pipes.
2473 */
2474static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2475 const struct intel_wm_config *config,
820c1980 2476 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2477 struct intel_pipe_wm *merged)
2478{
7733b49b 2479 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2480 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2481 int last_enabled_level = max_level;
0b2ae6d7 2482
0ba22e26
VS		 2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485 config->num_pipes_active > 1)
1204d5ba 2486 last_enabled_level = 0;
0ba22e26 2487
6c8b6c28
VS		 2488 /* ILK: FBC WM must be disabled always */
2489 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2490
2491 /* merge each WM1+ level */
2492 for (level = 1; level <= max_level; level++) {
2493 struct intel_wm_level *wm = &merged->wm[level];
2494
2495 ilk_merge_wm_level(dev, level, wm);
2496
d52fea5b
VS		 2497 if (level > last_enabled_level)
2498 wm->enable = false;
2499 else if (!ilk_validate_wm_level(level, max, wm))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level = level - 1;
0b2ae6d7
VS		 2502
2503 /*
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2506 */
2507 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2508 if (wm->enable)
2509 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2510 wm->fbc_val = 0;
2511 }
2512 }
6c8b6c28
VS		 2513
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515 /*
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2519 */
7733b49b 2520 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2521 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2522 for (level = 2; level <= max_level; level++) {
2523 struct intel_wm_level *wm = &merged->wm[level];
2524
2525 wm->enable = false;
2526 }
2527 }
0b2ae6d7
VS		 2528}
2529
b380ca3c
VS		 2530static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531{
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534}
2535
a68d68ee
VS		 2536/* The value we need to program into the WM_LPx latency field */
2537static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538{
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540
a42a5719 2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2542 return 2 * level;
2543 else
2544 return dev_priv->wm.pri_latency[level];
2545}
2546
820c1980 2547static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2548 const struct intel_pipe_wm *merged,
609cedef 2549 enum intel_ddb_partitioning partitioning,
820c1980 2550 struct ilk_wm_values *results)
801bcfff 2551{
0b2ae6d7
VS		 2552 struct intel_crtc *intel_crtc;
2553 int level, wm_lp;
cca32e9a 2554
0362c781 2555 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2556 results->partitioning = partitioning;
cca32e9a 2557
0b2ae6d7 2558 /* LP1+ register values */
cca32e9a 2559 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2560 const struct intel_wm_level *r;
801bcfff 2561
b380ca3c 2562 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2563
0362c781 2564 r = &merged->wm[level];
cca32e9a 2565
d52fea5b
VS		 2566 /*
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2569 */
2570 results->wm_lp[wm_lp - 1] =
a68d68ee 2571 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2572 (r->pri_val << WM1_LP_SR_SHIFT) |
2573 r->cur_val;
2574
d52fea5b
VS		 2575 if (r->enable)
2576 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
416f4727
VS		 2578 if (INTEL_INFO(dev)->gen >= 8)
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581 else
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
d52fea5b
VS		 2585 /*
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2588 */
6cef2b8a
VS		 2589 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590 WARN_ON(wm_lp != 1);
2591 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592 } else
2593 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2594 }
801bcfff 2595
0b2ae6d7 2596 /* LP0 register values */
d3fcc808 2597 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2598 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2599 const struct intel_wm_level *r =
2600 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2601
2602 if (WARN_ON(!r->enable))
2603 continue;
2604
ed4a6a7c 2605 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2606
0b2ae6d7
VS		 2607 results->wm_pipe[pipe] =
2608 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610 r->cur_val;
801bcfff
PZ		 2611 }
2612}
2613
861f3389
PZ		 2614/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2616static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2617 struct intel_pipe_wm *r1,
2618 struct intel_pipe_wm *r2)
861f3389 2619{
198a1e9b
VS		 2620 int level, max_level = ilk_wm_max_level(dev);
2621 int level1 = 0, level2 = 0;
861f3389 2622
198a1e9b
VS		 2623 for (level = 1; level <= max_level; level++) {
2624 if (r1->wm[level].enable)
2625 level1 = level;
2626 if (r2->wm[level].enable)
2627 level2 = level;
861f3389
PZ		 2628 }
2629
198a1e9b
VS		 2630 if (level1 == level2) {
2631 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2632 return r2;
2633 else
2634 return r1;
198a1e9b 2635 } else if (level1 > level2) {
861f3389
PZ		 2636 return r1;
2637 } else {
2638 return r2;
2639 }
2640}
2641
49a687c4
VS		 2642/* dirty bits used to track which watermarks need changes */
2643#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647#define WM_DIRTY_FBC (1 << 24)
2648#define WM_DIRTY_DDB (1 << 25)
2649
055e393f 2650static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2651 const struct ilk_wm_values *old,
2652 const struct ilk_wm_values *new)
49a687c4
VS		 2653{
2654 unsigned int dirty = 0;
2655 enum pipe pipe;
2656 int wm_lp;
2657
055e393f 2658 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2659 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660 dirty |= WM_DIRTY_LINETIME(pipe);
2661 /* Must disable LP1+ watermarks too */
2662 dirty |= WM_DIRTY_LP_ALL;
2663 }
2664
2665 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666 dirty |= WM_DIRTY_PIPE(pipe);
2667 /* Must disable LP1+ watermarks too */
2668 dirty |= WM_DIRTY_LP_ALL;
2669 }
2670 }
2671
2672 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673 dirty |= WM_DIRTY_FBC;
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677
2678 if (old->partitioning != new->partitioning) {
2679 dirty |= WM_DIRTY_DDB;
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty & WM_DIRTY_LP_ALL)
2686 return dirty;
2687
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692 break;
2693 }
2694
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp <= 3; wm_lp++)
2697 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699 return dirty;
2700}
2701
8553c18e
VS		 2702static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703 unsigned int dirty)
801bcfff 2704{
820c1980 2705 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2706 bool changed = false;
801bcfff 2707
facd619b
VS		 2708 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2711 changed = true;
facd619b
VS		 2712 }
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2716 changed = true;
facd619b
VS		 2717 }
2718 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2721 changed = true;
facd619b 2722 }
801bcfff 2723
facd619b
VS		 2724 /*
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2727 */
6cef2b8a 2728
8553c18e
VS		 2729 return changed;
2730}
2731
2732/*
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2735 */
820c1980
ID		 2736static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737 struct ilk_wm_values *results)
8553c18e
VS		 2738{
2739 struct drm_device *dev = dev_priv->dev;
820c1980 2740 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2741 unsigned int dirty;
2742 uint32_t val;
2743
055e393f 2744 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2745 if (!dirty)
2746 return;
2747
2748 _ilk_disable_lp_wm(dev_priv, dirty);
2749
49a687c4 2750 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2751 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2752 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2753 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2754 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2755 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
49a687c4 2757 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2759 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2761 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
49a687c4 2764 if (dirty & WM_DIRTY_DDB) {
a42a5719 2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2766 val = I915_READ(WM_MISC);
2767 if (results->partitioning == INTEL_DDB_PART_1_2)
2768 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769 else
2770 val |= WM_MISC_DATA_PARTITION_5_6;
2771 I915_WRITE(WM_MISC, val);
2772 } else {
2773 val = I915_READ(DISP_ARB_CTL2);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~DISP_DATA_PARTITION_5_6;
2776 else
2777 val |= DISP_DATA_PARTITION_5_6;
2778 I915_WRITE(DISP_ARB_CTL2, val);
2779 }
1011d8c4
PZ		 2780 }
2781
49a687c4 2782 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2783 val = I915_READ(DISP_ARB_CTL);
2784 if (results->enable_fbc_wm)
2785 val &= ~DISP_FBC_WM_DIS;
2786 else
2787 val |= DISP_FBC_WM_DIS;
2788 I915_WRITE(DISP_ARB_CTL, val);
2789 }
2790
954911eb
ID		 2791 if (dirty & WM_DIRTY_LP(1) &&
2792 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2796 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800 }
801bcfff 2801
facd619b 2802 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2803 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2804 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2805 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2806 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2807 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2808
2809 dev_priv->wm.hw = *results;
801bcfff
PZ		 2810}
2811
ed4a6a7c 2812bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2813{
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817}
2818
b9cec075
DL		 2819/*
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2822 */
2823
2824#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2825#define BXT_DDB_SIZE 512
b9cec075 2826
024c9045
MR		 2827/*
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2832 */
2833static int
2834skl_wm_plane_id(const struct intel_plane *plane)
2835{
2836 switch (plane->base.type) {
2837 case DRM_PLANE_TYPE_PRIMARY:
2838 return 0;
2839 case DRM_PLANE_TYPE_CURSOR:
2840 return PLANE_CURSOR;
2841 case DRM_PLANE_TYPE_OVERLAY:
2842 return plane->plane + 1;
2843 default:
2844 MISSING_CASE(plane->base.type);
2845 return plane->plane;
2846 }
2847}
2848
b9cec075
DL		 2849static void
2850skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2851 const struct intel_crtc_state *cstate,
b9cec075 2852 const struct intel_wm_config *config,
b9cec075
DL		 2853 struct skl_ddb_entry *alloc /* out */)
2854{
024c9045 2855 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2856 struct drm_crtc *crtc;
2857 unsigned int pipe_size, ddb_size;
2858 int nth_active_pipe;
2859
024c9045 2860 if (!cstate->base.active) {
b9cec075
DL		 2861 alloc->start = 0;
2862 alloc->end = 0;
2863 return;
2864 }
2865
43d735a6
DL		 2866 if (IS_BROXTON(dev))
2867 ddb_size = BXT_DDB_SIZE;
2868 else
2869 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2870
2871 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2872
2873 nth_active_pipe = 0;
2874 for_each_crtc(dev, crtc) {
3ef00284 2875 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2876 continue;
2877
2878 if (crtc == for_crtc)
2879 break;
2880
2881 nth_active_pipe++;
2882 }
2883
2884 pipe_size = ddb_size / config->num_pipes_active;
2885 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2886 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2887}
2888
2889static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2890{
2891 if (config->num_pipes_active == 1)
2892 return 32;
2893
2894 return 8;
2895}
2896
a269c583
DL		 2897static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2898{
2899 entry->start = reg & 0x3ff;
2900 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2901 if (entry->end)
2902 entry->end += 1;
a269c583
DL		 2903}
2904
08db6652
DL		 2905void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2906 struct skl_ddb_allocation *ddb /* out */)
a269c583 2907{
a269c583
DL		 2908 enum pipe pipe;
2909 int plane;
2910 u32 val;
2911
b10f1b20
ML		 2912 memset(ddb, 0, sizeof(*ddb));
2913
a269c583 2914 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2915 enum intel_display_power_domain power_domain;
2916
2917 power_domain = POWER_DOMAIN_PIPE(pipe);
2918 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2919 continue;
2920
dd740780 2921 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2922 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2923 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2924 val);
2925 }
2926
2927 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2928 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2929 val);
4d800030
ID		 2930
2931 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2932 }
2933}
2934
b9cec075 2935static unsigned int
024c9045
MR		 2936skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2937 const struct drm_plane_state *pstate,
2938 int y)
b9cec075 2939{
9aec6a08 2940 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 2941 struct drm_framebuffer *fb = pstate->fb;
9aec6a08
KM		 2942 uint32_t width = 0, height = 0;
2943
2944 width = drm_rect_width(&intel_pstate->src) >> 16;
2945 height = drm_rect_height(&intel_pstate->src) >> 16;
2946
2947 if (intel_rotation_90_or_270(pstate->rotation))
2948 swap(width, height);
2cd601c6
CK		 2949
2950 /* for planar format */
024c9045 2951 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2952 if (y) /* y-plane data rate */
9aec6a08 2953 return width * height *
024c9045 2954 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2955 else /* uv-plane data rate */
9aec6a08 2956 return (width / 2) * (height / 2) *
024c9045 2957 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2958 }
2959
2960 /* for packed formats */
9aec6a08 2961 return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2962}
2963
2964/*
2965 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2966 * a 8192x4096@32bpp framebuffer:
2967 * 3 * 4096 * 8192 * 4 < 2^32
2968 */
2969static unsigned int
024c9045 2970skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2971{
024c9045
MR		 2972 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2973 struct drm_device *dev = intel_crtc->base.dev;
2974 const struct intel_plane *intel_plane;
b9cec075 2975 unsigned int total_data_rate = 0;
b9cec075 2976
024c9045
MR		 2977 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2978 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2979
024c9045 2980 if (pstate->fb == NULL)
b9cec075
DL		 2981 continue;
2982
024c9045
MR		 2983 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2984 continue;
2985
2986 /* packed/uv */
2987 total_data_rate += skl_plane_relative_data_rate(cstate,
2988 pstate,
2989 0);
2990
2991 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2992 /* y-plane */
2993 total_data_rate += skl_plane_relative_data_rate(cstate,
2994 pstate,
2995 1);
b9cec075
DL		 2996 }
2997
2998 return total_data_rate;
2999}
3000
3001static void
024c9045 3002skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3003 struct skl_ddb_allocation *ddb /* out */)
3004{
024c9045 3005 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 3006 struct drm_device *dev = crtc->dev;
aa363136
MR		 3007 struct drm_i915_private *dev_priv = to_i915(dev);
3008 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3010 struct intel_plane *intel_plane;
b9cec075 3011 enum pipe pipe = intel_crtc->pipe;
34bb56af 3012 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3013 uint16_t alloc_size, start, cursor_blocks;
80958155 3014 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 3015 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 3016 unsigned int total_data_rate;
b9cec075 3017
024c9045 3018 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 3019 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3020 if (alloc_size == 0) {
3021 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 3022 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3023 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 3024 return;
3025 }
3026
3027 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 3028 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3029 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3030
3031 alloc_size -= cursor_blocks;
34bb56af 3032 alloc->end -= cursor_blocks;
b9cec075 3033
80958155 3034 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 3035 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3036 struct drm_plane *plane = &intel_plane->base;
3037 struct drm_framebuffer *fb = plane->state->fb;
3038 int id = skl_wm_plane_id(intel_plane);
80958155 3039
9aec6a08 3040 if (!to_intel_plane_state(plane->state)->visible)
024c9045 3041 continue;
9aec6a08 3042
024c9045 3043 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 3044 continue;
3045
024c9045
MR		 3046 minimum[id] = 8;
3047 alloc_size -= minimum[id];
3048 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3049 alloc_size -= y_minimum[id];
80958155
DL		 3050 }
3051
b9cec075 3052 /*
80958155
DL		 3053 * 2. Distribute the remaining space in proportion to the amount of
3054 * data each plane needs to fetch from memory.
b9cec075
DL		 3055 *
3056 * FIXME: we may not allocate every single block here.
3057 */
024c9045 3058 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3059
34bb56af 3060 start = alloc->start;
024c9045
MR		 3061 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3062 struct drm_plane *plane = &intel_plane->base;
3063 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3064 unsigned int data_rate, y_data_rate;
3065 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3066 int id = skl_wm_plane_id(intel_plane);
b9cec075 3067
9aec6a08 3068 if (!to_intel_plane_state(pstate)->visible)
024c9045
MR		 3069 continue;
3070 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3071 continue;
3072
024c9045 3073 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3074
3075 /*
2cd601c6 3076 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3077 * promote the expression to 64 bits to avoid overflowing, the
3078 * result is < available as data_rate / total_data_rate < 1
3079 */
024c9045 3080 plane_blocks = minimum[id];
80958155
DL		 3081 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3082 total_data_rate);
b9cec075 3083
024c9045
MR		 3084 ddb->plane[pipe][id].start = start;
3085 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3086
3087 start += plane_blocks;
2cd601c6
CK		 3088
3089 /*
3090 * allocation for y_plane part of planar format:
3091 */
024c9045
MR		 3092 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3093 y_data_rate = skl_plane_relative_data_rate(cstate,
3094 pstate,
3095 1);
3096 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3097 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3098 total_data_rate);
3099
024c9045
MR		 3100 ddb->y_plane[pipe][id].start = start;
3101 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3102
3103 start += y_plane_blocks;
3104 }
3105
b9cec075
DL		 3106 }
3107
3108}
3109
5cec258b 3110static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3111{
3112 /* TODO: Take into account the scalers once we support them */
2d112de7 3113 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3114}
3115
3116/*
3117 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3118 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3119 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3120 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3121*/
ac484963 3122static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3123{
3124 uint32_t wm_intermediate_val, ret;
3125
3126 if (latency == 0)
3127 return UINT_MAX;
3128
ac484963 3129 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3130 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3131
3132 return ret;
3133}
3134
3135static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3136 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3137 uint64_t tiling, uint32_t latency)
2d41c0b5 3138{
d4c2aa60
TU		 3139 uint32_t ret;
3140 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3141 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3142
3143 if (latency == 0)
3144 return UINT_MAX;
3145
ac484963 3146 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3147
3148 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3149 tiling == I915_FORMAT_MOD_Yf_TILED) {
3150 plane_bytes_per_line *= 4;
3151 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3152 plane_blocks_per_line /= 4;
3153 } else {
3154 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3155 }
3156
2d41c0b5
PB		 3157 wm_intermediate_val = latency * pixel_rate;
3158 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3159 plane_blocks_per_line;
2d41c0b5
PB		 3160
3161 return ret;
3162}
3163
2d41c0b5
PB		 3164static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3165 const struct intel_crtc *intel_crtc)
3166{
3167 struct drm_device *dev = intel_crtc->base.dev;
3168 struct drm_i915_private *dev_priv = dev->dev_private;
3169 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3170
e6d90023
KM		 3171 /*
3172 * If ddb allocation of pipes changed, it may require recalculation of
3173 * watermarks
3174 */
3175 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3176 return true;
3177
3178 return false;
3179}
3180
d4c2aa60 3181static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3182 struct intel_crtc_state *cstate,
3183 struct intel_plane *intel_plane,
afb024aa 3184 uint16_t ddb_allocation,
d4c2aa60 3185 int level,
afb024aa
DL		 3186 uint16_t *out_blocks, /* out */
3187 uint8_t *out_lines /* out */)
2d41c0b5 3188{
024c9045
MR		 3189 struct drm_plane *plane = &intel_plane->base;
3190 struct drm_framebuffer *fb = plane->state->fb;
9aec6a08
KM		 3191 struct intel_plane_state *intel_pstate =
3192 to_intel_plane_state(plane->state);
d4c2aa60
TU		 3193 uint32_t latency = dev_priv->wm.skl_latency[level];
3194 uint32_t method1, method2;
3195 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3196 uint32_t res_blocks, res_lines;
3197 uint32_t selected_result;
ac484963 3198 uint8_t cpp;
9aec6a08 3199 uint32_t width = 0, height = 0;
2d41c0b5 3200
9aec6a08 3201 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
2d41c0b5
PB		 3202 return false;
3203
9aec6a08
KM		 3204 width = drm_rect_width(&intel_pstate->src) >> 16;
3205 height = drm_rect_height(&intel_pstate->src) >> 16;
3206
3207 if (intel_rotation_90_or_270(plane->state->rotation))
3208 swap(width, height);
3209
ac484963 3210 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3211 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3212 cpp, latency);
024c9045
MR		 3213 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3214 cstate->base.adjusted_mode.crtc_htotal,
9aec6a08
KM		 3215 width,
3216 cpp,
3217 fb->modifier[0],
d4c2aa60 3218 latency);
2d41c0b5 3219
9aec6a08 3220 plane_bytes_per_line = width * cpp;
d4c2aa60 3221 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3222
024c9045
MR		 3223 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3224 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3225 uint32_t min_scanlines = 4;
3226 uint32_t y_tile_minimum;
024c9045 3227 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3228 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3229 drm_format_plane_cpp(fb->pixel_format, 1) :
3230 drm_format_plane_cpp(fb->pixel_format, 0);
3231
ac484963 3232 switch (cpp) {
1fc0a8f7
TU		 3233 case 1:
3234 min_scanlines = 16;
3235 break;
3236 case 2:
3237 min_scanlines = 8;
3238 break;
3239 case 8:
3240 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3241 }
1fc0a8f7
TU		 3242 }
3243 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3244 selected_result = max(method2, y_tile_minimum);
3245 } else {
3246 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3247 selected_result = min(method1, method2);
3248 else
3249 selected_result = method1;
3250 }
2d41c0b5 3251
d4c2aa60
TU		 3252 res_blocks = selected_result + 1;
3253 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3254
0fda6568 3255 if (level >= 1 && level <= 7) {
024c9045
MR		 3256 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3257 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3258 res_lines += 4;
3259 else
3260 res_blocks++;
3261 }
e6d66171 3262
d4c2aa60 3263 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3264 return false;
3265
3266 *out_blocks = res_blocks;
3267 *out_lines = res_lines;
2d41c0b5
PB		 3268
3269 return true;
3270}
3271
3272static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3273 struct skl_ddb_allocation *ddb,
024c9045 3274 struct intel_crtc_state *cstate,
2d41c0b5 3275 int level,
2d41c0b5
PB		 3276 struct skl_wm_level *result)
3277{
024c9045
MR		 3278 struct drm_device *dev = dev_priv->dev;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3280 struct intel_plane *intel_plane;
2d41c0b5 3281 uint16_t ddb_blocks;
024c9045
MR		 3282 enum pipe pipe = intel_crtc->pipe;
3283
3284 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3285 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3286
2d41c0b5
PB		 3287 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3288
d4c2aa60 3289 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3290 cstate,
3291 intel_plane,
2d41c0b5 3292 ddb_blocks,
d4c2aa60 3293 level,
2d41c0b5
PB		 3294 &result->plane_res_b[i],
3295 &result->plane_res_l[i]);
3296 }
2d41c0b5
PB		 3297}
3298
407b50f3 3299static uint32_t
024c9045 3300skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3301{
024c9045 3302 if (!cstate->base.active)
407b50f3
DL		 3303 return 0;
3304
024c9045 3305 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3306 return 0;
407b50f3 3307
024c9045
MR		 3308 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3309 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3310}
3311
024c9045 3312static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3313 struct skl_wm_level *trans_wm /* out */)
407b50f3 3314{
024c9045 3315 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3317 struct intel_plane *intel_plane;
9414f563 3318
024c9045 3319 if (!cstate->base.active)
407b50f3 3320 return;
9414f563
DL		 3321
3322 /* Until we know more, just disable transition WMs */
024c9045
MR		 3323 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3324 int i = skl_wm_plane_id(intel_plane);
3325
9414f563 3326 trans_wm->plane_en[i] = false;
024c9045 3327 }
407b50f3
DL		 3328}
3329
024c9045 3330static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3331 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3332 struct skl_pipe_wm *pipe_wm)
3333{
024c9045 3334 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3335 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3336 int level, max_level = ilk_wm_max_level(dev);
3337
3338 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3339 skl_compute_wm_level(dev_priv, ddb, cstate,
3340 level, &pipe_wm->wm[level]);
2d41c0b5 3341 }
024c9045 3342 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3343
024c9045 3344 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3345}
3346
3347static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3348 struct skl_pipe_wm *p_wm,
3349 struct skl_wm_values *r,
3350 struct intel_crtc *intel_crtc)
3351{
3352 int level, max_level = ilk_wm_max_level(dev);
3353 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3354 uint32_t temp;
3355 int i;
2d41c0b5
PB		 3356
3357 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3358 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3359 temp = 0;
2d41c0b5
PB		 3360
3361 temp |= p_wm->wm[level].plane_res_l[i] <<
3362 PLANE_WM_LINES_SHIFT;
3363 temp |= p_wm->wm[level].plane_res_b[i];
3364 if (p_wm->wm[level].plane_en[i])
3365 temp |= PLANE_WM_EN;
3366
3367 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3368 }
3369
3370 temp = 0;
2d41c0b5 3371
4969d33e
MR		 3372 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3373 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3374
4969d33e 3375 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3376 temp |= PLANE_WM_EN;
3377
4969d33e 3378 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3379
3380 }
3381
9414f563
DL		 3382 /* transition WMs */
3383 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3384 temp = 0;
3385 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3386 temp |= p_wm->trans_wm.plane_res_b[i];
3387 if (p_wm->trans_wm.plane_en[i])
3388 temp |= PLANE_WM_EN;
3389
3390 r->plane_trans[pipe][i] = temp;
3391 }
3392
3393 temp = 0;
4969d33e
MR		 3394 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3395 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3396 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3397 temp |= PLANE_WM_EN;
3398
4969d33e 3399 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3400
2d41c0b5
PB		 3401 r->wm_linetime[pipe] = p_wm->linetime;
3402}
3403
f0f59a00
VS		 3404static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3405 i915_reg_t reg,
16160e3d
DL		 3406 const struct skl_ddb_entry *entry)
3407{
3408 if (entry->end)
3409 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3410 else
3411 I915_WRITE(reg, 0);
3412}
3413
2d41c0b5
PB		 3414static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3415 const struct skl_wm_values *new)
3416{
3417 struct drm_device *dev = dev_priv->dev;
3418 struct intel_crtc *crtc;
3419
19c8054c 3420 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3421 int i, level, max_level = ilk_wm_max_level(dev);
3422 enum pipe pipe = crtc->pipe;
3423
5d374d96
DL		 3424 if (!new->dirty[pipe])
3425 continue;
8211bd5b 3426
5d374d96 3427 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3428
5d374d96
DL		 3429 for (level = 0; level <= max_level; level++) {
3430 for (i = 0; i < intel_num_planes(crtc); i++)
3431 I915_WRITE(PLANE_WM(pipe, i, level),
3432 new->plane[pipe][i][level]);
3433 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3434 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3435 }
5d374d96
DL		 3436 for (i = 0; i < intel_num_planes(crtc); i++)
3437 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3438 new->plane_trans[pipe][i]);
4969d33e
MR		 3439 I915_WRITE(CUR_WM_TRANS(pipe),
3440 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3441
2cd601c6 3442 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3443 skl_ddb_entry_write(dev_priv,
3444 PLANE_BUF_CFG(pipe, i),
3445 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3446 skl_ddb_entry_write(dev_priv,
3447 PLANE_NV12_BUF_CFG(pipe, i),
3448 &new->ddb.y_plane[pipe][i]);
3449 }
5d374d96
DL		 3450
3451 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3452 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3453 }
2d41c0b5
PB		 3454}
3455
0e8fb7ba
DL		 3456/*
3457 * When setting up a new DDB allocation arrangement, we need to correctly
3458 * sequence the times at which the new allocations for the pipes are taken into
3459 * account or we'll have pipes fetching from space previously allocated to
3460 * another pipe.
3461 *
3462 * Roughly the sequence looks like:
3463 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3464 * overlapping with a previous light-up pipe (another way to put it is:
3465 * pipes with their new allocation strickly included into their old ones).
3466 * 2. re-allocate the other pipes that get their allocation reduced
3467 * 3. allocate the pipes having their allocation increased
3468 *
3469 * Steps 1. and 2. are here to take care of the following case:
3470 * - Initially DDB looks like this:
3471 * | B | C |
3472 * - enable pipe A.
3473 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3474 * allocation
3475 * | A | B | C |
3476 *
3477 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3478 */
3479
d21b795c
DL		 3480static void
3481skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3482{
0e8fb7ba
DL		 3483 int plane;
3484
d21b795c
DL		 3485 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3486
dd740780 3487 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3488 I915_WRITE(PLANE_SURF(pipe, plane),
3489 I915_READ(PLANE_SURF(pipe, plane)));
3490 }
3491 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3492}
3493
3494static bool
3495skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3496 const struct skl_ddb_allocation *new,
3497 enum pipe pipe)
3498{
3499 uint16_t old_size, new_size;
3500
3501 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3502 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3503
3504 return old_size != new_size &&
3505 new->pipe[pipe].start >= old->pipe[pipe].start &&
3506 new->pipe[pipe].end <= old->pipe[pipe].end;
3507}
3508
3509static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3510 struct skl_wm_values *new_values)
3511{
3512 struct drm_device *dev = dev_priv->dev;
3513 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3514 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3515 struct intel_crtc *crtc;
3516 enum pipe pipe;
3517
3518 new_ddb = &new_values->ddb;
3519 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3520
3521 /*
3522 * First pass: flush the pipes with the new allocation contained into
3523 * the old space.
3524 *
3525 * We'll wait for the vblank on those pipes to ensure we can safely
3526 * re-allocate the freed space without this pipe fetching from it.
3527 */
3528 for_each_intel_crtc(dev, crtc) {
3529 if (!crtc->active)
3530 continue;
3531
3532 pipe = crtc->pipe;
3533
3534 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3535 continue;
3536
d21b795c 3537 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3538 intel_wait_for_vblank(dev, pipe);
3539
3540 reallocated[pipe] = true;
3541 }
3542
3543
3544 /*
3545 * Second pass: flush the pipes that are having their allocation
3546 * reduced, but overlapping with a previous allocation.
3547 *
3548 * Here as well we need to wait for the vblank to make sure the freed
3549 * space is not used anymore.
3550 */
3551 for_each_intel_crtc(dev, crtc) {
3552 if (!crtc->active)
3553 continue;
3554
3555 pipe = crtc->pipe;
3556
3557 if (reallocated[pipe])
3558 continue;
3559
3560 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3561 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3562 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3563 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3564 reallocated[pipe] = true;
0e8fb7ba 3565 }
0e8fb7ba
DL		 3566 }
3567
3568 /*
3569 * Third pass: flush the pipes that got more space allocated.
3570 *
3571 * We don't need to actively wait for the update here, next vblank
3572 * will just get more DDB space with the correct WM values.
3573 */
3574 for_each_intel_crtc(dev, crtc) {
3575 if (!crtc->active)
3576 continue;
3577
3578 pipe = crtc->pipe;
3579
3580 /*
3581 * At this point, only the pipes more space than before are
3582 * left to re-allocate.
3583 */
3584 if (reallocated[pipe])
3585 continue;
3586
d21b795c 3587 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3588 }
3589}
3590
2d41c0b5 3591static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3592 struct skl_ddb_allocation *ddb, /* out */
3593 struct skl_pipe_wm *pipe_wm /* out */)
3594{
3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3596 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3597
aa363136 3598 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3599 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3600
4e0963c7 3601 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3602 return false;
3603
4e0963c7 3604 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3605
2d41c0b5
PB		 3606 return true;
3607}
3608
3609static void skl_update_other_pipe_wm(struct drm_device *dev,
3610 struct drm_crtc *crtc,
2d41c0b5
PB		 3611 struct skl_wm_values *r)
3612{
3613 struct intel_crtc *intel_crtc;
3614 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3615
3616 /*
3617 * If the WM update hasn't changed the allocation for this_crtc (the
3618 * crtc we are currently computing the new WM values for), other
3619 * enabled crtcs will keep the same allocation and we don't need to
3620 * recompute anything for them.
3621 */
3622 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3623 return;
3624
3625 /*
3626 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3627 * other active pipes need new DDB allocation and WM values.
3628 */
19c8054c 3629 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3630 struct skl_pipe_wm pipe_wm = {};
3631 bool wm_changed;
3632
3633 if (this_crtc->pipe == intel_crtc->pipe)
3634 continue;
3635
3636 if (!intel_crtc->active)
3637 continue;
3638
aa363136 3639 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3640 &r->ddb, &pipe_wm);
3641
3642 /*
3643 * If we end up re-computing the other pipe WM values, it's
3644 * because it was really needed, so we expect the WM values to
3645 * be different.
3646 */
3647 WARN_ON(!wm_changed);
3648
024c9045 3649 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3650 r->dirty[intel_crtc->pipe] = true;
3651 }
3652}
3653
adda50b8
BP		 3654static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3655{
3656 watermarks->wm_linetime[pipe] = 0;
3657 memset(watermarks->plane[pipe], 0,
3658 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3659 memset(watermarks->plane_trans[pipe],
3660 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3661 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3662
3663 /* Clear ddb entries for pipe */
3664 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3665 memset(&watermarks->ddb.plane[pipe], 0,
3666 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3667 memset(&watermarks->ddb.y_plane[pipe], 0,
3668 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3669 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3670 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3671
3672}
3673
2d41c0b5
PB		 3674static void skl_update_wm(struct drm_crtc *crtc)
3675{
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct drm_device *dev = crtc->dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3679 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3680 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3681 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3682
adda50b8
BP		 3683
3684 /* Clear all dirty flags */
3685 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3686
3687 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3688
aa363136 3689 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3690 return;
3691
4e0963c7 3692 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3693 results->dirty[intel_crtc->pipe] = true;
3694
aa363136 3695 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3696 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3697 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3698
3699 /* store the new configuration */
3700 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3701}
3702
d890565c
VS		 3703static void ilk_compute_wm_config(struct drm_device *dev,
3704 struct intel_wm_config *config)
3705{
3706 struct intel_crtc *crtc;
3707
3708 /* Compute the currently _active_ config */
3709 for_each_intel_crtc(dev, crtc) {
3710 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3711
3712 if (!wm->pipe_enabled)
3713 continue;
3714
3715 config->sprites_enabled |= wm->sprites_enabled;
3716 config->sprites_scaled |= wm->sprites_scaled;
3717 config->num_pipes_active++;
3718 }
3719}
3720
ed4a6a7c 3721static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3722{
ed4a6a7c 3723 struct drm_device *dev = dev_priv->dev;
b9d5c839 3724 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3725 struct ilk_wm_maximums max;
d890565c 3726 struct intel_wm_config config = {};
820c1980 3727 struct ilk_wm_values results = {};
77c122bc 3728 enum intel_ddb_partitioning partitioning;
261a27d1 3729
d890565c
VS		 3730 ilk_compute_wm_config(dev, &config);
3731
3732 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3733 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3734
3735 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3736 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3737 config.num_pipes_active == 1 && config.sprites_enabled) {
3738 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3739 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3740
820c1980 3741 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3742 } else {
198a1e9b 3743 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3744 }
3745
198a1e9b 3746 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3747 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3748
820c1980 3749 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3750
820c1980 3751 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3752}
3753
ed4a6a7c 3754static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3755{
ed4a6a7c
MR		 3756 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3757 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3758
ed4a6a7c
MR		 3759 mutex_lock(&dev_priv->wm.wm_mutex);
3760 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3761 ilk_program_watermarks(dev_priv);
3762 mutex_unlock(&dev_priv->wm.wm_mutex);
3763}
bf220452 3764
ed4a6a7c
MR		 3765static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3766{
3767 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3768 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3769
ed4a6a7c
MR		 3770 mutex_lock(&dev_priv->wm.wm_mutex);
3771 if (cstate->wm.need_postvbl_update) {
3772 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3773 ilk_program_watermarks(dev_priv);
3774 }
3775 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3776}
3777
3078999f
PB		 3778static void skl_pipe_wm_active_state(uint32_t val,
3779 struct skl_pipe_wm *active,
3780 bool is_transwm,
3781 bool is_cursor,
3782 int i,
3783 int level)
3784{
3785 bool is_enabled = (val & PLANE_WM_EN) != 0;
3786
3787 if (!is_transwm) {
3788 if (!is_cursor) {
3789 active->wm[level].plane_en[i] = is_enabled;
3790 active->wm[level].plane_res_b[i] =
3791 val & PLANE_WM_BLOCKS_MASK;
3792 active->wm[level].plane_res_l[i] =
3793 (val >> PLANE_WM_LINES_SHIFT) &
3794 PLANE_WM_LINES_MASK;
3795 } else {
4969d33e
MR		 3796 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3797 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3798 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3799 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3800 (val >> PLANE_WM_LINES_SHIFT) &
3801 PLANE_WM_LINES_MASK;
3802 }
3803 } else {
3804 if (!is_cursor) {
3805 active->trans_wm.plane_en[i] = is_enabled;
3806 active->trans_wm.plane_res_b[i] =
3807 val & PLANE_WM_BLOCKS_MASK;
3808 active->trans_wm.plane_res_l[i] =
3809 (val >> PLANE_WM_LINES_SHIFT) &
3810 PLANE_WM_LINES_MASK;
3811 } else {
4969d33e
MR		 3812 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3813 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3814 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3815 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3816 (val >> PLANE_WM_LINES_SHIFT) &
3817 PLANE_WM_LINES_MASK;
3818 }
3819 }
3820}
3821
3822static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3823{
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3828 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3829 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3830 enum pipe pipe = intel_crtc->pipe;
3831 int level, i, max_level;
3832 uint32_t temp;
3833
3834 max_level = ilk_wm_max_level(dev);
3835
3836 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3837
3838 for (level = 0; level <= max_level; level++) {
3839 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3840 hw->plane[pipe][i][level] =
3841 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3842 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3843 }
3844
3845 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3846 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3847 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3848
3ef00284 3849 if (!intel_crtc->active)
3078999f
PB		 3850 return;
3851
3852 hw->dirty[pipe] = true;
3853
3854 active->linetime = hw->wm_linetime[pipe];
3855
3856 for (level = 0; level <= max_level; level++) {
3857 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3858 temp = hw->plane[pipe][i][level];
3859 skl_pipe_wm_active_state(temp, active, false,
3860 false, i, level);
3861 }
4969d33e 3862 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3863 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3864 }
3865
3866 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3867 temp = hw->plane_trans[pipe][i];
3868 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3869 }
3870
4969d33e 3871 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3872 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3873
3874 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3875}
3876
3877void skl_wm_get_hw_state(struct drm_device *dev)
3878{
a269c583
DL		 3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3881 struct drm_crtc *crtc;
3882
a269c583 3883 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3885 skl_pipe_wm_get_hw_state(crtc);
3886}
3887
243e6a44
VS		 3888static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3889{
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3892 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3894 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3895 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3896 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3897 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3898 [PIPE_A] = WM0_PIPEA_ILK,
3899 [PIPE_B] = WM0_PIPEB_ILK,
3900 [PIPE_C] = WM0_PIPEC_IVB,
3901 };
3902
3903 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3904 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3905 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3906
7045c368
VS		 3907 memset(active, 0, sizeof(*active));
3908
3ef00284 3909 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3910
3911 if (active->pipe_enabled) {
243e6a44
VS		 3912 u32 tmp = hw->wm_pipe[pipe];
3913
3914 /*
3915 * For active pipes LP0 watermark is marked as
3916 * enabled, and LP1+ watermaks as disabled since
3917 * we can't really reverse compute them in case
3918 * multiple pipes are active.
3919 */
3920 active->wm[0].enable = true;
3921 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3922 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3923 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3924 active->linetime = hw->wm_linetime[pipe];
3925 } else {
3926 int level, max_level = ilk_wm_max_level(dev);
3927
3928 /*
3929 * For inactive pipes, all watermark levels
3930 * should be marked as enabled but zeroed,
3931 * which is what we'd compute them to.
3932 */
3933 for (level = 0; level <= max_level; level++)
3934 active->wm[level].enable = true;
3935 }
4e0963c7
MR		 3936
3937 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3938}
3939
6eb1a681
VS		 3940#define _FW_WM(value, plane) \
3941 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3942#define _FW_WM_VLV(value, plane) \
3943 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3944
3945static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3946 struct vlv_wm_values *wm)
3947{
3948 enum pipe pipe;
3949 uint32_t tmp;
3950
3951 for_each_pipe(dev_priv, pipe) {
3952 tmp = I915_READ(VLV_DDL(pipe));
3953
3954 wm->ddl[pipe].primary =
3955 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3956 wm->ddl[pipe].cursor =
3957 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3958 wm->ddl[pipe].sprite[0] =
3959 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3960 wm->ddl[pipe].sprite[1] =
3961 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3962 }
3963
3964 tmp = I915_READ(DSPFW1);
3965 wm->sr.plane = _FW_WM(tmp, SR);
3966 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3967 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3968 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3969
3970 tmp = I915_READ(DSPFW2);
3971 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3972 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3973 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3974
3975 tmp = I915_READ(DSPFW3);
3976 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3977
3978 if (IS_CHERRYVIEW(dev_priv)) {
3979 tmp = I915_READ(DSPFW7_CHV);
3980 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3981 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3982
3983 tmp = I915_READ(DSPFW8_CHV);
3984 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3985 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3986
3987 tmp = I915_READ(DSPFW9_CHV);
3988 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3989 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3990
3991 tmp = I915_READ(DSPHOWM);
3992 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3993 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3994 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3995 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3996 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3997 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3998 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3999 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4000 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4001 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4002 } else {
4003 tmp = I915_READ(DSPFW7);
4004 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4005 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4006
4007 tmp = I915_READ(DSPHOWM);
4008 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4009 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4010 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4011 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4012 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4013 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4014 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4015 }
4016}
4017
4018#undef _FW_WM
4019#undef _FW_WM_VLV
4020
4021void vlv_wm_get_hw_state(struct drm_device *dev)
4022{
4023 struct drm_i915_private *dev_priv = to_i915(dev);
4024 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4025 struct intel_plane *plane;
4026 enum pipe pipe;
4027 u32 val;
4028
4029 vlv_read_wm_values(dev_priv, wm);
4030
4031 for_each_intel_plane(dev, plane) {
4032 switch (plane->base.type) {
4033 int sprite;
4034 case DRM_PLANE_TYPE_CURSOR:
4035 plane->wm.fifo_size = 63;
4036 break;
4037 case DRM_PLANE_TYPE_PRIMARY:
4038 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4039 break;
4040 case DRM_PLANE_TYPE_OVERLAY:
4041 sprite = plane->plane;
4042 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4043 break;
4044 }
4045 }
4046
4047 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4048 wm->level = VLV_WM_LEVEL_PM2;
4049
4050 if (IS_CHERRYVIEW(dev_priv)) {
4051 mutex_lock(&dev_priv->rps.hw_lock);
4052
4053 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4054 if (val & DSP_MAXFIFO_PM5_ENABLE)
4055 wm->level = VLV_WM_LEVEL_PM5;
4056
58590c14
VS		 4057 /*
4058 * If DDR DVFS is disabled in the BIOS, Punit
4059 * will never ack the request. So if that happens
4060 * assume we don't have to enable/disable DDR DVFS
4061 * dynamically. To test that just set the REQ_ACK
4062 * bit to poke the Punit, but don't change the
4063 * HIGH/LOW bits so that we don't actually change
4064 * the current state.
4065 */
6eb1a681 4066 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4067 val |= FORCE_DDR_FREQ_REQ_ACK;
4068 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4069
4070 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4071 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4072 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4073 "assuming DDR DVFS is disabled\n");
4074 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4075 } else {
4076 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4077 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4078 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4079 }
6eb1a681
VS		 4080
4081 mutex_unlock(&dev_priv->rps.hw_lock);
4082 }
4083
4084 for_each_pipe(dev_priv, pipe)
4085 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4086 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4087 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4088
4089 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4090 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4091}
4092
243e6a44
VS		 4093void ilk_wm_get_hw_state(struct drm_device *dev)
4094{
4095 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4096 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4097 struct drm_crtc *crtc;
4098
70e1e0ec 4099 for_each_crtc(dev, crtc)
243e6a44
VS		 4100 ilk_pipe_wm_get_hw_state(crtc);
4101
4102 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4103 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4104 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4105
4106 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4107 if (INTEL_INFO(dev)->gen >= 7) {
4108 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4109 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4110 }
243e6a44 4111
a42a5719 4112 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4113 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4114 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4115 else if (IS_IVYBRIDGE(dev))
4116 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4117 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4118
4119 hw->enable_fbc_wm =
4120 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4121}
4122
b445e3b0
ED		 4123/**
4124 * intel_update_watermarks - update FIFO watermark values based on current modes
4125 *
4126 * Calculate watermark values for the various WM regs based on current mode
4127 * and plane configuration.
4128 *
4129 * There are several cases to deal with here:
4130 * - normal (i.e. non-self-refresh)
4131 * - self-refresh (SR) mode
4132 * - lines are large relative to FIFO size (buffer can hold up to 2)
4133 * - lines are small relative to FIFO size (buffer can hold more than 2
4134 * lines), so need to account for TLB latency
4135 *
4136 * The normal calculation is:
4137 * watermark = dotclock * bytes per pixel * latency
4138 * where latency is platform & configuration dependent (we assume pessimal
4139 * values here).
4140 *
4141 * The SR calculation is:
4142 * watermark = (trunc(latency/line time)+1) * surface width *
4143 * bytes per pixel
4144 * where
4145 * line time = htotal / dotclock
4146 * surface width = hdisplay for normal plane and 64 for cursor
4147 * and latency is assumed to be high, as above.
4148 *
4149 * The final value programmed to the register should always be rounded up,
4150 * and include an extra 2 entries to account for clock crossings.
4151 *
4152 * We don't use the sprite, so we can ignore that. And on Crestline we have
4153 * to set the non-SR watermarks to 8.
4154 */
46ba614c 4155void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4156{
46ba614c 4157 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4158
4159 if (dev_priv->display.update_wm)
46ba614c 4160 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4161}
4162
e2828914 4163/*
9270388e 4164 * Lock protecting IPS related data structures
9270388e
DV		 4165 */
4166DEFINE_SPINLOCK(mchdev_lock);
4167
4168/* Global for IPS driver to get at the current i915 device. Protected by
4169 * mchdev_lock. */
4170static struct drm_i915_private *i915_mch_dev;
4171
2b4e57bd
ED		 4172bool ironlake_set_drps(struct drm_device *dev, u8 val)
4173{
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 u16 rgvswctl;
4176
9270388e
DV		 4177 assert_spin_locked(&mchdev_lock);
4178
2b4e57bd
ED		 4179 rgvswctl = I915_READ16(MEMSWCTL);
4180 if (rgvswctl & MEMCTL_CMD_STS) {
4181 DRM_DEBUG("gpu busy, RCS change rejected\n");
4182 return false; /* still busy with another command */
4183 }
4184
4185 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4186 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4187 I915_WRITE16(MEMSWCTL, rgvswctl);
4188 POSTING_READ16(MEMSWCTL);
4189
4190 rgvswctl |= MEMCTL_CMD_STS;
4191 I915_WRITE16(MEMSWCTL, rgvswctl);
4192
4193 return true;
4194}
4195
8090c6b9 4196static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4197{
4198 struct drm_i915_private *dev_priv = dev->dev_private;
84f1b20f 4199 u32 rgvmodectl;
2b4e57bd
ED		 4200 u8 fmax, fmin, fstart, vstart;
4201
9270388e
DV		 4202 spin_lock_irq(&mchdev_lock);
4203
84f1b20f
TU		 4204 rgvmodectl = I915_READ(MEMMODECTL);
4205
2b4e57bd
ED		 4206 /* Enable temp reporting */
4207 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4208 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4209
4210 /* 100ms RC evaluation intervals */
4211 I915_WRITE(RCUPEI, 100000);
4212 I915_WRITE(RCDNEI, 100000);
4213
4214 /* Set max/min thresholds to 90ms and 80ms respectively */
4215 I915_WRITE(RCBMAXAVG, 90000);
4216 I915_WRITE(RCBMINAVG, 80000);
4217
4218 I915_WRITE(MEMIHYST, 1);
4219
4220 /* Set up min, max, and cur for interrupt handling */
4221 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4222 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4223 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4224 MEMMODE_FSTART_SHIFT;
4225
616847e7 4226 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4227 PXVFREQ_PX_SHIFT;
4228
20e4d407
DV		 4229 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4230 dev_priv->ips.fstart = fstart;
2b4e57bd 4231
20e4d407
DV		 4232 dev_priv->ips.max_delay = fstart;
4233 dev_priv->ips.min_delay = fmin;
4234 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4235
4236 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4237 fmax, fmin, fstart);
4238
4239 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4240
4241 /*
4242 * Interrupts will be enabled in ironlake_irq_postinstall
4243 */
4244
4245 I915_WRITE(VIDSTART, vstart);
4246 POSTING_READ(VIDSTART);
4247
4248 rgvmodectl |= MEMMODE_SWMODE_EN;
4249 I915_WRITE(MEMMODECTL, rgvmodectl);
4250
9270388e 4251 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4252 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4253 mdelay(1);
2b4e57bd
ED		 4254
4255 ironlake_set_drps(dev, fstart);
4256
7d81c3e0
VS		 4257 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4258 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4259 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4260 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4261 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4262
4263 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4264}
4265
8090c6b9 4266static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4267{
4268 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4269 u16 rgvswctl;
4270
4271 spin_lock_irq(&mchdev_lock);
4272
4273 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4274
4275 /* Ack interrupts, disable EFC interrupt */
4276 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4277 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4278 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4279 I915_WRITE(DEIIR, DE_PCU_EVENT);
4280 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4281
4282 /* Go back to the starting frequency */
20e4d407 4283 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4284 mdelay(1);
2b4e57bd
ED		 4285 rgvswctl |= MEMCTL_CMD_STS;
4286 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4287 mdelay(1);
2b4e57bd 4288
9270388e 4289 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4290}
4291
acbe9475
DV		 4292/* There's a funny hw issue where the hw returns all 0 when reading from
4293 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4294 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4295 * all limits and the gpu stuck at whatever frequency it is at atm).
4296 */
74ef1173 4297static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4298{
7b9e0ae6 4299 u32 limits;
2b4e57bd 4300
20b46e59
DV		 4301 /* Only set the down limit when we've reached the lowest level to avoid
4302 * getting more interrupts, otherwise leave this clear. This prevents a
4303 * race in the hw when coming out of rc6: There's a tiny window where
4304 * the hw runs at the minimal clock before selecting the desired
4305 * frequency, if the down threshold expires in that window we will not
4306 * receive a down interrupt. */
2d1fe073 4307 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4308 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4309 if (val <= dev_priv->rps.min_freq_softlimit)
4310 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4311 } else {
4312 limits = dev_priv->rps.max_freq_softlimit << 24;
4313 if (val <= dev_priv->rps.min_freq_softlimit)
4314 limits |= dev_priv->rps.min_freq_softlimit << 16;
4315 }
20b46e59
DV		 4316
4317 return limits;
4318}
4319
dd75fdc8
CW		 4320static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4321{
4322 int new_power;
8a586437
AG		 4323 u32 threshold_up = 0, threshold_down = 0; /* in % */
4324 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4325
4326 new_power = dev_priv->rps.power;
4327 switch (dev_priv->rps.power) {
4328 case LOW_POWER:
b39fb297 4329 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4330 new_power = BETWEEN;
4331 break;
4332
4333 case BETWEEN:
b39fb297 4334 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4335 new_power = LOW_POWER;
b39fb297 4336 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4337 new_power = HIGH_POWER;
4338 break;
4339
4340 case HIGH_POWER:
b39fb297 4341 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4342 new_power = BETWEEN;
4343 break;
4344 }
4345 /* Max/min bins are special */
aed242ff 4346 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4347 new_power = LOW_POWER;
aed242ff 4348 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4349 new_power = HIGH_POWER;
4350 if (new_power == dev_priv->rps.power)
4351 return;
4352
4353 /* Note the units here are not exactly 1us, but 1280ns. */
4354 switch (new_power) {
4355 case LOW_POWER:
4356 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4357 ei_up = 16000;
4358 threshold_up = 95;
dd75fdc8
CW		 4359
4360 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4361 ei_down = 32000;
4362 threshold_down = 85;
dd75fdc8
CW		 4363 break;
4364
4365 case BETWEEN:
4366 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4367 ei_up = 13000;
4368 threshold_up = 90;
dd75fdc8
CW		 4369
4370 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4371 ei_down = 32000;
4372 threshold_down = 75;
dd75fdc8
CW		 4373 break;
4374
4375 case HIGH_POWER:
4376 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4377 ei_up = 10000;
4378 threshold_up = 85;
dd75fdc8
CW		 4379
4380 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4381 ei_down = 32000;
4382 threshold_down = 60;
dd75fdc8
CW		 4383 break;
4384 }
4385
8a586437
AG		 4386 I915_WRITE(GEN6_RP_UP_EI,
4387 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4388 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4389 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4390
4391 I915_WRITE(GEN6_RP_DOWN_EI,
4392 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4393 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4394 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4395
4396 I915_WRITE(GEN6_RP_CONTROL,
4397 GEN6_RP_MEDIA_TURBO |
4398 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4399 GEN6_RP_MEDIA_IS_GFX |
4400 GEN6_RP_ENABLE |
4401 GEN6_RP_UP_BUSY_AVG |
4402 GEN6_RP_DOWN_IDLE_AVG);
4403
dd75fdc8 4404 dev_priv->rps.power = new_power;
8fb55197
CW		 4405 dev_priv->rps.up_threshold = threshold_up;
4406 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4407 dev_priv->rps.last_adj = 0;
4408}
4409
2876ce73
CW		 4410static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4411{
4412 u32 mask = 0;
4413
4414 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4415 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4416 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4417 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4418
7b3c29f6
CW		 4419 mask &= dev_priv->pm_rps_events;
4420
59d02a1f 4421 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4422}
4423
b8a5ff8d
JM		 4424/* gen6_set_rps is called to update the frequency request, but should also be
4425 * called when the range (min_delay and max_delay) is modified so that we can
4426 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4427static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4428{
4429 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4430
23eafea6 4431 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4432 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4433 return;
4434
4fc688ce 4435 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4436 WARN_ON(val > dev_priv->rps.max_freq);
4437 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4438
eb64cad1
CW		 4439 /* min/max delay may still have been modified so be sure to
4440 * write the limits value.
4441 */
4442 if (val != dev_priv->rps.cur_freq) {
4443 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4444
5704195c
AG		 4445 if (IS_GEN9(dev))
4446 I915_WRITE(GEN6_RPNSWREQ,
4447 GEN9_FREQUENCY(val));
4448 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4449 I915_WRITE(GEN6_RPNSWREQ,
4450 HSW_FREQUENCY(val));
4451 else
4452 I915_WRITE(GEN6_RPNSWREQ,
4453 GEN6_FREQUENCY(val) |
4454 GEN6_OFFSET(0) |
4455 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4456 }
7b9e0ae6 4457
7b9e0ae6
CW		 4458 /* Make sure we continue to get interrupts
4459 * until we hit the minimum or maximum frequencies.
4460 */
74ef1173 4461 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4462 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4463
d5570a72
BW		 4464 POSTING_READ(GEN6_RPNSWREQ);
4465
b39fb297 4466 dev_priv->rps.cur_freq = val;
0f94592e 4467 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4468}
4469
ffe02b40
VS		 4470static void valleyview_set_rps(struct drm_device *dev, u8 val)
4471{
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473
4474 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4475 WARN_ON(val > dev_priv->rps.max_freq);
4476 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4477
4478 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4479 "Odd GPU freq value\n"))
4480 val &= ~1;
4481
cd25dd5b
D		 4482 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4483
8fb55197 4484 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4485 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4486 if (!IS_CHERRYVIEW(dev_priv))
4487 gen6_set_rps_thresholds(dev_priv, val);
4488 }
ffe02b40 4489
ffe02b40
VS		 4490 dev_priv->rps.cur_freq = val;
4491 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4492}
4493
a7f6e231 4494/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4495 *
4496 * * If Gfx is Idle, then
a7f6e231
D		 4497 * 1. Forcewake Media well.
4498 * 2. Request idle freq.
4499 * 3. Release Forcewake of Media well.
76c3552f
D		 4500*/
4501static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4502{
aed242ff 4503 u32 val = dev_priv->rps.idle_freq;
5549d25f 4504
aed242ff 4505 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4506 return;
4507
a7f6e231
D		 4508 /* Wake up the media well, as that takes a lot less
4509 * power than the Render well. */
4510 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4511 valleyview_set_rps(dev_priv->dev, val);
4512 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4513}
4514
43cf3bf0
CW		 4515void gen6_rps_busy(struct drm_i915_private *dev_priv)
4516{
4517 mutex_lock(&dev_priv->rps.hw_lock);
4518 if (dev_priv->rps.enabled) {
4519 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4520 gen6_rps_reset_ei(dev_priv);
4521 I915_WRITE(GEN6_PMINTRMSK,
4522 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4523 }
4524 mutex_unlock(&dev_priv->rps.hw_lock);
4525}
4526
b29c19b6
CW		 4527void gen6_rps_idle(struct drm_i915_private *dev_priv)
4528{
691bb717
DL		 4529 struct drm_device *dev = dev_priv->dev;
4530
b29c19b6 4531 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4532 if (dev_priv->rps.enabled) {
666a4537 4533 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4534 vlv_set_rps_idle(dev_priv);
7526ed79 4535 else
aed242ff 4536 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4537 dev_priv->rps.last_adj = 0;
43cf3bf0 4538 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4539 }
8d3afd7d 4540 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4541
8d3afd7d 4542 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4543 while (!list_empty(&dev_priv->rps.clients))
4544 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4545 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4546}
4547
1854d5ca 4548void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4549 struct intel_rps_client *rps,
4550 unsigned long submitted)
b29c19b6 4551{
8d3afd7d
CW		 4552 /* This is intentionally racy! We peek at the state here, then
4553 * validate inside the RPS worker.
4554 */
4555 if (!(dev_priv->mm.busy &&
4556 dev_priv->rps.enabled &&
4557 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4558 return;
43cf3bf0 4559
e61b9958
CW		 4560 /* Force a RPS boost (and don't count it against the client) if
4561 * the GPU is severely congested.
4562 */
d0bc54f2 4563 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4564 rps = NULL;
4565
8d3afd7d
CW		 4566 spin_lock(&dev_priv->rps.client_lock);
4567 if (rps == NULL || list_empty(&rps->link)) {
4568 spin_lock_irq(&dev_priv->irq_lock);
4569 if (dev_priv->rps.interrupts_enabled) {
4570 dev_priv->rps.client_boost = true;
4571 queue_work(dev_priv->wq, &dev_priv->rps.work);
4572 }
4573 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4574
2e1b8730
CW		 4575 if (rps != NULL) {
4576 list_add(&rps->link, &dev_priv->rps.clients);
4577 rps->boosts++;
1854d5ca
CW		 4578 } else
4579 dev_priv->rps.boosts++;
c0951f0c 4580 }
8d3afd7d 4581 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4582}
4583
ffe02b40 4584void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4585{
666a4537 4586 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4587 valleyview_set_rps(dev, val);
4588 else
4589 gen6_set_rps(dev, val);
0a073b84
JB		 4590}
4591
2030d684 4592static void gen9_disable_rc6(struct drm_device *dev)
20e49366
ZW		 4593{
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4597 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4598}
4599
2030d684
AG		 4600static void gen9_disable_rps(struct drm_device *dev)
4601{
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603
4604 I915_WRITE(GEN6_RP_CONTROL, 0);
4605}
4606
44fc7d5c 4607static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4608{
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610
4611 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4612 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4613 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4614}
4615
38807746
D		 4616static void cherryview_disable_rps(struct drm_device *dev)
4617{
4618 struct drm_i915_private *dev_priv = dev->dev_private;
4619
4620 I915_WRITE(GEN6_RC_CONTROL, 0);
4621}
4622
44fc7d5c
DV		 4623static void valleyview_disable_rps(struct drm_device *dev)
4624{
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626
98a2e5f9
D		 4627 /* we're doing forcewake before Disabling RC6,
4628 * This what the BIOS expects when going into suspend */
59bad947 4629 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4630
44fc7d5c 4631 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4632
59bad947 4633 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4634}
4635
dc39fff7
BW		 4636static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4637{
666a4537 4638 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4639 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4640 mode = GEN6_RC_CTL_RC6_ENABLE;
4641 else
4642 mode = 0;
4643 }
58abf1da
RV		 4644 if (HAS_RC6p(dev))
4645 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4646 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4647 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4648 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4649
4650 else
4651 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4652 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4653}
4654
274008e8
SAK		 4655static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4656{
72e96d64
JL		 4657 struct drm_i915_private *dev_priv = to_i915(dev);
4658 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4659 bool enable_rc6 = true;
4660 unsigned long rc6_ctx_base;
4661
4662 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4663 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4664 enable_rc6 = false;
4665 }
4666
4667 /*
4668 * The exact context size is not known for BXT, so assume a page size
4669 * for this check.
4670 */
4671 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4672 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4673 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4674 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4675 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4676 enable_rc6 = false;
4677 }
4678
4679 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4680 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4681 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4682 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4683 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4684 enable_rc6 = false;
4685 }
4686
4687 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4688 GEN6_RC_CTL_HW_ENABLE)) &&
4689 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4690 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4691 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4692 enable_rc6 = false;
4693 }
4694
4695 return enable_rc6;
4696}
4697
4698int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4699{
e7d66d89
DV		 4700 /* No RC6 before Ironlake and code is gone for ilk. */
4701 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4702 return 0;
4703
274008e8
SAK		 4704 if (!enable_rc6)
4705 return 0;
4706
4707 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4708 DRM_INFO("RC6 disabled by BIOS\n");
4709 return 0;
4710 }
4711
456470eb 4712 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4713 if (enable_rc6 >= 0) {
4714 int mask;
4715
58abf1da 4716 if (HAS_RC6p(dev))
e6069ca8
ID		 4717 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4718 INTEL_RC6pp_ENABLE;
4719 else
4720 mask = INTEL_RC6_ENABLE;
4721
4722 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4723 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4724 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4725
4726 return enable_rc6 & mask;
4727 }
2b4e57bd 4728
8bade1ad 4729 if (IS_IVYBRIDGE(dev))
cca84a1f 4730 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4731
4732 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4733}
4734
e6069ca8
ID		 4735int intel_enable_rc6(const struct drm_device *dev)
4736{
4737 return i915.enable_rc6;
4738}
4739
93ee2920 4740static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4741{
93ee2920
TR		 4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 uint32_t rp_state_cap;
4744 u32 ddcc_status = 0;
4745 int ret;
4746
3280e8b0
BW		 4747 /* All of these values are in units of 50MHz */
4748 dev_priv->rps.cur_freq = 0;
93ee2920 4749 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4750 if (IS_BROXTON(dev)) {
4751 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4752 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4753 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4754 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4755 } else {
4756 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4757 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4758 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4759 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4760 }
4761
3280e8b0
BW		 4762 /* hw_max = RP0 until we check for overclocking */
4763 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4764
93ee2920 4765 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4766 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4767 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4768 ret = sandybridge_pcode_read(dev_priv,
4769 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4770 &ddcc_status);
4771 if (0 == ret)
4772 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4773 clamp_t(u8,
4774 ((ddcc_status >> 8) & 0xff),
4775 dev_priv->rps.min_freq,
4776 dev_priv->rps.max_freq);
93ee2920
TR		 4777 }
4778
ef11bdb3 4779 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4780 /* Store the frequency values in 16.66 MHZ units, which is
4781 the natural hardware unit for SKL */
4782 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4783 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4784 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4785 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4786 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4787 }
4788
aed242ff
CW		 4789 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4790
3280e8b0
BW		 4791 /* Preserve min/max settings in case of re-init */
4792 if (dev_priv->rps.max_freq_softlimit == 0)
4793 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4794
93ee2920
TR		 4795 if (dev_priv->rps.min_freq_softlimit == 0) {
4796 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4797 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4798 max_t(int, dev_priv->rps.efficient_freq,
4799 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4800 else
4801 dev_priv->rps.min_freq_softlimit =
4802 dev_priv->rps.min_freq;
4803 }
3280e8b0
BW		 4804}
4805
b6fef0ef 4806/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4807static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4808{
4809 struct drm_i915_private *dev_priv = dev->dev_private;
4810
4811 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4812
ba1c554c
DL		 4813 gen6_init_rps_frequencies(dev);
4814
23eafea6 4815 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4816 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2030d684
AG		 4817 /*
4818 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4819 * clear out the Control register just to avoid inconsitency
4820 * with debugfs interface, which will show Turbo as enabled
4821 * only and that is not expected by the User after adding the
4822 * WaGsvDisableTurbo. Apart from this there is no problem even
4823 * if the Turbo is left enabled in the Control register, as the
4824 * Up/Down interrupts would remain masked.
4825 */
4826 gen9_disable_rps(dev);
23eafea6
SAK		 4827 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4828 return;
4829 }
4830
0beb059a
AG		 4831 /* Program defaults and thresholds for RPS*/
4832 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4833 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4834
4835 /* 1 second timeout*/
4836 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4837 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4838
b6fef0ef 4839 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4840
0beb059a
AG		 4841 /* Leaning on the below call to gen6_set_rps to program/setup the
4842 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4843 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4844 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5fd9f523 4845 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
b6fef0ef
JB		 4846
4847 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4848}
4849
4850static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4851{
4852 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 4853 struct intel_engine_cs *engine;
20e49366 4854 uint32_t rc6_mask = 0;
20e49366
ZW		 4855
4856 /* 1a: Software RC state - RC0 */
4857 I915_WRITE(GEN6_RC_STATE, 0);
4858
4859 /* 1b: Get forcewake during program sequence. Although the driver
4860 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4861 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4862
4863 /* 2a: Disable RC states. */
4864 I915_WRITE(GEN6_RC_CONTROL, 0);
4865
4866 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4867
4868 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4869 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4870 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4871 else
4872 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4873 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4874 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 4875 for_each_engine(engine, dev_priv)
e2f80391 4876 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7
SAK		 4877
4878 if (HAS_GUC_UCODE(dev))
4879 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4880
20e49366 4881 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4882
38c23527
ZW		 4883 /* 2c: Program Coarse Power Gating Policies. */
4884 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4885 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4886
20e49366
ZW		 4887 /* 3a: Enable RC6 */
4888 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4889 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4890 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4891 /* WaRsUseTimeoutMode */
e87a005d 4892 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4893 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4894 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4895 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4896 GEN7_RC_CTL_TO_MODE |
4897 rc6_mask);
3e7732a0
SAK		 4898 } else {
4899 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4900 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4901 GEN6_RC_CTL_EI_MODE(1) |
4902 rc6_mask);
3e7732a0 4903 }
20e49366 4904
cb07bae0
SK		 4905 /*
4906 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4907 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4908 */
06e668ac 4909 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4910 I915_WRITE(GEN9_PG_ENABLE, 0);
4911 else
4912 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4913 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4914
59bad947 4915 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4916
4917}
4918
6edee7f3
BW		 4919static void gen8_enable_rps(struct drm_device *dev)
4920{
4921 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 4922 struct intel_engine_cs *engine;
93ee2920 4923 uint32_t rc6_mask = 0;
6edee7f3
BW		 4924
4925 /* 1a: Software RC state - RC0 */
4926 I915_WRITE(GEN6_RC_STATE, 0);
4927
4928 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4929 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4930 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4931
4932 /* 2a: Disable RC states. */
4933 I915_WRITE(GEN6_RC_CONTROL, 0);
4934
93ee2920
TR		 4935 /* Initialize rps frequencies */
4936 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4937
4938 /* 2b: Program RC6 thresholds.*/
4939 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4940 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4941 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 4942 for_each_engine(engine, dev_priv)
e2f80391 4943 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 4944 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4945 if (IS_BROADWELL(dev))
4946 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4947 else
4948 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4949
4950 /* 3: Enable RC6 */
4951 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4952 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4953 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4954 if (IS_BROADWELL(dev))
4955 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4956 GEN7_RC_CTL_TO_MODE |
4957 rc6_mask);
4958 else
4959 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4960 GEN6_RC_CTL_EI_MODE(1) |
4961 rc6_mask);
6edee7f3
BW		 4962
4963 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4964 I915_WRITE(GEN6_RPNSWREQ,
4965 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4966 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4967 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4968 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4969 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4970
4971 /* Docs recommend 900MHz, and 300 MHz respectively */
4972 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4973 dev_priv->rps.max_freq_softlimit << 24 |
4974 dev_priv->rps.min_freq_softlimit << 16);
4975
4976 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4977 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4978 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4979 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4980
4981 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4982
4983 /* 5: Enable RPS */
7526ed79
DV		 4984 I915_WRITE(GEN6_RP_CONTROL,
4985 GEN6_RP_MEDIA_TURBO |
4986 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4987 GEN6_RP_MEDIA_IS_GFX |
4988 GEN6_RP_ENABLE |
4989 GEN6_RP_UP_BUSY_AVG |
4990 GEN6_RP_DOWN_IDLE_AVG);
4991
4992 /* 6: Ring frequency + overclocking (our driver does this later */
4993
c7f3153a 4994 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4995 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4996
59bad947 4997 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4998}
4999
79f5b2c7 5000static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 5001{
79f5b2c7 5002 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5003 struct intel_engine_cs *engine;
d060c169 5004 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5005 u32 gtfifodbg;
2b4e57bd 5006 int rc6_mode;
b4ac5afc 5007 int ret;
2b4e57bd 5008
4fc688ce 5009 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5010
2b4e57bd
ED		 5011 /* Here begins a magic sequence of register writes to enable
5012 * auto-downclocking.
5013 *
5014 * Perhaps there might be some value in exposing these to
5015 * userspace...
5016 */
5017 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5018
5019 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5020 gtfifodbg = I915_READ(GTFIFODBG);
5021 if (gtfifodbg) {
2b4e57bd
ED		 5022 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5023 I915_WRITE(GTFIFODBG, gtfifodbg);
5024 }
5025
59bad947 5026 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5027
93ee2920
TR		 5028 /* Initialize rps frequencies */
5029 gen6_init_rps_frequencies(dev);
dd0a1aa1 5030
2b4e57bd
ED		 5031 /* disable the counters and set deterministic thresholds */
5032 I915_WRITE(GEN6_RC_CONTROL, 0);
5033
5034 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5035 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5036 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5037 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5038 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5039
b4ac5afc 5040 for_each_engine(engine, dev_priv)
e2f80391 5041 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5042
5043 I915_WRITE(GEN6_RC_SLEEP, 0);
5044 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5045 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5046 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5047 else
5048 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5049 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5050 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5051
5a7dc92a 5052 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5053 rc6_mode = intel_enable_rc6(dev_priv->dev);
5054 if (rc6_mode & INTEL_RC6_ENABLE)
5055 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5056
5a7dc92a
ED		 5057 /* We don't use those on Haswell */
5058 if (!IS_HASWELL(dev)) {
5059 if (rc6_mode & INTEL_RC6p_ENABLE)
5060 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5061
5a7dc92a
ED		 5062 if (rc6_mode & INTEL_RC6pp_ENABLE)
5063 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5064 }
2b4e57bd 5065
dc39fff7 5066 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5067
5068 I915_WRITE(GEN6_RC_CONTROL,
5069 rc6_mask |
5070 GEN6_RC_CTL_EI_MODE(1) |
5071 GEN6_RC_CTL_HW_ENABLE);
5072
dd75fdc8
CW		 5073 /* Power down if completely idle for over 50ms */
5074 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5075 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5076
42c0526c 5077 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5078 if (ret)
42c0526c 5079 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5080
5081 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5082 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5083 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5084 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5085 (pcu_mbox & 0xff) * 50);
b39fb297 5086 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5087 }
5088
dd75fdc8 5089 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5090 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5091
31643d54
BW		 5092 rc6vids = 0;
5093 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5094 if (IS_GEN6(dev) && ret) {
5095 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5096 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5097 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5098 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5099 rc6vids &= 0xffff00;
5100 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5101 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5102 if (ret)
5103 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5104 }
5105
59bad947 5106 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5107}
5108
c2bc2fc5 5109static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5110{
79f5b2c7 5111 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5112 int min_freq = 15;
3ebecd07
CW		 5113 unsigned int gpu_freq;
5114 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5115 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5116 int scaling_factor = 180;
eda79642 5117 struct cpufreq_policy *policy;
2b4e57bd 5118
4fc688ce 5119 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5120
eda79642
BW		 5121 policy = cpufreq_cpu_get(0);
5122 if (policy) {
5123 max_ia_freq = policy->cpuinfo.max_freq;
5124 cpufreq_cpu_put(policy);
5125 } else {
5126 /*
5127 * Default to measured freq if none found, PCU will ensure we
5128 * don't go over
5129 */
2b4e57bd 5130 max_ia_freq = tsc_khz;
eda79642 5131 }
2b4e57bd
ED		 5132
5133 /* Convert from kHz to MHz */
5134 max_ia_freq /= 1000;
5135
153b4b95 5136 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5137 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5138 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5139
ef11bdb3 5140 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5141 /* Convert GT frequency to 50 HZ units */
5142 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5143 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5144 } else {
5145 min_gpu_freq = dev_priv->rps.min_freq;
5146 max_gpu_freq = dev_priv->rps.max_freq;
5147 }
5148
2b4e57bd
ED		 5149 /*
5150 * For each potential GPU frequency, load a ring frequency we'd like
5151 * to use for memory access. We do this by specifying the IA frequency
5152 * the PCU should use as a reference to determine the ring frequency.
5153 */
4c8c7743
AG		 5154 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5155 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5156 unsigned int ia_freq = 0, ring_freq = 0;
5157
ef11bdb3 5158 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5159 /*
5160 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5161 * No floor required for ring frequency on SKL.
5162 */
5163 ring_freq = gpu_freq;
5164 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5165 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5166 ring_freq = max(min_ring_freq, gpu_freq);
5167 } else if (IS_HASWELL(dev)) {
f6aca45c 5168 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5169 ring_freq = max(min_ring_freq, ring_freq);
5170 /* leave ia_freq as the default, chosen by cpufreq */
5171 } else {
5172 /* On older processors, there is no separate ring
5173 * clock domain, so in order to boost the bandwidth
5174 * of the ring, we need to upclock the CPU (ia_freq).
5175 *
5176 * For GPU frequencies less than 750MHz,
5177 * just use the lowest ring freq.
5178 */
5179 if (gpu_freq < min_freq)
5180 ia_freq = 800;
5181 else
5182 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5183 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5184 }
2b4e57bd 5185
42c0526c
BW		 5186 sandybridge_pcode_write(dev_priv,
5187 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5188 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5189 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5190 gpu_freq);
2b4e57bd 5191 }
2b4e57bd
ED		 5192}
5193
c2bc2fc5
ID		 5194void gen6_update_ring_freq(struct drm_device *dev)
5195{
5196 struct drm_i915_private *dev_priv = dev->dev_private;
5197
97d3308a 5198 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5199 return;
5200
5201 mutex_lock(&dev_priv->rps.hw_lock);
5202 __gen6_update_ring_freq(dev);
5203 mutex_unlock(&dev_priv->rps.hw_lock);
5204}
5205
03af2045 5206static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5207{
095acd5f 5208 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5209 u32 val, rp0;
5210
5b5929cb 5211 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5212
5b5929cb
JN		 5213 switch (INTEL_INFO(dev)->eu_total) {
5214 case 8:
5215 /* (2 * 4) config */
5216 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5217 break;
5218 case 12:
5219 /* (2 * 6) config */
5220 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5221 break;
5222 case 16:
5223 /* (2 * 8) config */
5224 default:
5225 /* Setting (2 * 8) Min RP0 for any other combination */
5226 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5227 break;
095acd5f 5228 }
5b5929cb
JN		 5229
5230 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5231
2b6b3a09
D		 5232 return rp0;
5233}
5234
5235static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5236{
5237 u32 val, rpe;
5238
5239 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5240 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5241
5242 return rpe;
5243}
5244
7707df4a
D		 5245static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5246{
5247 u32 val, rp1;
5248
5b5929cb
JN		 5249 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5250 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5251
7707df4a
D		 5252 return rp1;
5253}
5254
f8f2b001
D		 5255static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5256{
5257 u32 val, rp1;
5258
5259 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5260
5261 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5262
5263 return rp1;
5264}
5265
03af2045 5266static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5267{
5268 u32 val, rp0;
5269
64936258 5270 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5271
5272 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5273 /* Clamp to max */
5274 rp0 = min_t(u32, rp0, 0xea);
5275
5276 return rp0;
5277}
5278
5279static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5280{
5281 u32 val, rpe;
5282
64936258 5283 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5284 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5285 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5286 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5287
5288 return rpe;
5289}
5290
03af2045 5291static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5292{
36146035
ID		 5293 u32 val;
5294
5295 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5296 /*
5297 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5298 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5299 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5300 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5301 * to make sure it matches what Punit accepts.
5302 */
5303 return max_t(u32, val, 0xc0);
0a073b84
JB		 5304}
5305
ae48434c
ID		 5306/* Check that the pctx buffer wasn't move under us. */
5307static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5308{
5309 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5310
5311 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5312 dev_priv->vlv_pctx->stolen->start);
5313}
5314
38807746
D		 5315
5316/* Check that the pcbr address is not empty. */
5317static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5318{
5319 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5320
5321 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5322}
5323
5324static void cherryview_setup_pctx(struct drm_device *dev)
5325{
72e96d64 5326 struct drm_i915_private *dev_priv = to_i915(dev);
62106b4f 5327 struct i915_ggtt *ggtt = &dev_priv->ggtt;
38807746 5328 unsigned long pctx_paddr, paddr;
38807746
D		 5329 u32 pcbr;
5330 int pctx_size = 32*1024;
5331
38807746
D		 5332 pcbr = I915_READ(VLV_PCBR);
5333 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5334 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5335 paddr = (dev_priv->mm.stolen_base +
62106b4f 5336 (ggtt->stolen_size - pctx_size));
38807746
D		 5337
5338 pctx_paddr = (paddr & (~4095));
5339 I915_WRITE(VLV_PCBR, pctx_paddr);
5340 }
ce611ef8
VS		 5341
5342 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5343}
5344
c9cddffc
JB		 5345static void valleyview_setup_pctx(struct drm_device *dev)
5346{
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348 struct drm_i915_gem_object *pctx;
5349 unsigned long pctx_paddr;
5350 u32 pcbr;
5351 int pctx_size = 24*1024;
5352
ee504898 5353 mutex_lock(&dev->struct_mutex);
17b0c1f7 5354
c9cddffc
JB		 5355 pcbr = I915_READ(VLV_PCBR);
5356 if (pcbr) {
5357 /* BIOS set it up already, grab the pre-alloc'd space */
5358 int pcbr_offset;
5359
5360 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5361 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5362 pcbr_offset,
190d6cd5 5363 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5364 pctx_size);
5365 goto out;
5366 }
5367
ce611ef8
VS		 5368 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5369
c9cddffc
JB		 5370 /*
5371 * From the Gunit register HAS:
5372 * The Gfx driver is expected to program this register and ensure
5373 * proper allocation within Gfx stolen memory. For example, this
5374 * register should be programmed such than the PCBR range does not
5375 * overlap with other ranges, such as the frame buffer, protected
5376 * memory, or any other relevant ranges.
5377 */
5378 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5379 if (!pctx) {
5380 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5381 goto out;
c9cddffc
JB		 5382 }
5383
5384 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5385 I915_WRITE(VLV_PCBR, pctx_paddr);
5386
5387out:
ce611ef8 5388 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5389 dev_priv->vlv_pctx = pctx;
ee504898 5390 mutex_unlock(&dev->struct_mutex);
c9cddffc
JB		 5391}
5392
ae48434c
ID		 5393static void valleyview_cleanup_pctx(struct drm_device *dev)
5394{
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396
5397 if (WARN_ON(!dev_priv->vlv_pctx))
5398 return;
5399
ee504898 5400 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5401 dev_priv->vlv_pctx = NULL;
5402}
5403
c30fec65
VS		 5404static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5405{
5406 dev_priv->rps.gpll_ref_freq =
5407 vlv_get_cck_clock(dev_priv, "GPLL ref",
5408 CCK_GPLL_CLOCK_CONTROL,
5409 dev_priv->czclk_freq);
5410
5411 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5412 dev_priv->rps.gpll_ref_freq);
5413}
5414
4e80519e
ID		 5415static void valleyview_init_gt_powersave(struct drm_device *dev)
5416{
5417 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5418 u32 val;
4e80519e
ID		 5419
5420 valleyview_setup_pctx(dev);
5421
c30fec65
VS		 5422 vlv_init_gpll_ref_freq(dev_priv);
5423
4e80519e
ID		 5424 mutex_lock(&dev_priv->rps.hw_lock);
5425
2bb25c17
VS		 5426 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5427 switch ((val >> 6) & 3) {
5428 case 0:
5429 case 1:
5430 dev_priv->mem_freq = 800;
5431 break;
5432 case 2:
5433 dev_priv->mem_freq = 1066;
5434 break;
5435 case 3:
5436 dev_priv->mem_freq = 1333;
5437 break;
5438 }
80b83b62 5439 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5440
4e80519e
ID		 5441 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5442 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5443 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5444 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5445 dev_priv->rps.max_freq);
5446
5447 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5448 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5449 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5450 dev_priv->rps.efficient_freq);
5451
f8f2b001
D		 5452 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5453 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5454 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5455 dev_priv->rps.rp1_freq);
5456
4e80519e
ID		 5457 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5458 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5459 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5460 dev_priv->rps.min_freq);
5461
aed242ff
CW		 5462 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5463
4e80519e
ID		 5464 /* Preserve min/max settings in case of re-init */
5465 if (dev_priv->rps.max_freq_softlimit == 0)
5466 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5467
5468 if (dev_priv->rps.min_freq_softlimit == 0)
5469 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5470
5471 mutex_unlock(&dev_priv->rps.hw_lock);
5472}
5473
38807746
D		 5474static void cherryview_init_gt_powersave(struct drm_device *dev)
5475{
2b6b3a09 5476 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5477 u32 val;
2b6b3a09 5478
38807746 5479 cherryview_setup_pctx(dev);
2b6b3a09 5480
c30fec65
VS		 5481 vlv_init_gpll_ref_freq(dev_priv);
5482
2b6b3a09
D		 5483 mutex_lock(&dev_priv->rps.hw_lock);
5484
a580516d 5485 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5486 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5487 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5488
2bb25c17 5489 switch ((val >> 2) & 0x7) {
2bb25c17 5490 case 3:
2bb25c17
VS		 5491 dev_priv->mem_freq = 2000;
5492 break;
bfa7df01 5493 default:
2bb25c17
VS		 5494 dev_priv->mem_freq = 1600;
5495 break;
5496 }
80b83b62 5497 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5498
2b6b3a09
D		 5499 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5500 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5501 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5502 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5503 dev_priv->rps.max_freq);
5504
5505 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5506 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5507 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5508 dev_priv->rps.efficient_freq);
5509
7707df4a
D		 5510 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5511 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5512 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5513 dev_priv->rps.rp1_freq);
5514
5b7c91b7
D		 5515 /* PUnit validated range is only [RPe, RP0] */
5516 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5517 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5518 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5519 dev_priv->rps.min_freq);
5520
1c14762d
VS		 5521 WARN_ONCE((dev_priv->rps.max_freq |
5522 dev_priv->rps.efficient_freq |
5523 dev_priv->rps.rp1_freq |
5524 dev_priv->rps.min_freq) & 1,
5525 "Odd GPU freq values\n");
5526
aed242ff
CW		 5527 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5528
2b6b3a09
D		 5529 /* Preserve min/max settings in case of re-init */
5530 if (dev_priv->rps.max_freq_softlimit == 0)
5531 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5532
5533 if (dev_priv->rps.min_freq_softlimit == 0)
5534 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5535
5536 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5537}
5538
4e80519e
ID		 5539static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5540{
5541 valleyview_cleanup_pctx(dev);
5542}
5543
38807746
D		 5544static void cherryview_enable_rps(struct drm_device *dev)
5545{
5546 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5547 struct intel_engine_cs *engine;
2b6b3a09 5548 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5549
5550 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5551
297b32ec
VS		 5552 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5553 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5554 if (gtfifodbg) {
5555 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5556 gtfifodbg);
5557 I915_WRITE(GTFIFODBG, gtfifodbg);
5558 }
5559
5560 cherryview_check_pctx(dev_priv);
5561
5562 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5563 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5564 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5565
160614a2
VS		 5566 /* Disable RC states. */
5567 I915_WRITE(GEN6_RC_CONTROL, 0);
5568
38807746
D		 5569 /* 2a: Program RC6 thresholds.*/
5570 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5571 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5572 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5573
b4ac5afc 5574 for_each_engine(engine, dev_priv)
e2f80391 5575 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5576 I915_WRITE(GEN6_RC_SLEEP, 0);
5577
f4f71c7d
D		 5578 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5579 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5580
5581 /* allows RC6 residency counter to work */
5582 I915_WRITE(VLV_COUNTER_CONTROL,
5583 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5584 VLV_MEDIA_RC6_COUNT_EN |
5585 VLV_RENDER_RC6_COUNT_EN));
5586
5587 /* For now we assume BIOS is allocating and populating the PCBR */
5588 pcbr = I915_READ(VLV_PCBR);
5589
38807746
D		 5590 /* 3: Enable RC6 */
5591 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5592 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5593 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5594
5595 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5596
2b6b3a09 5597 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5598 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5599 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5600 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5601 I915_WRITE(GEN6_RP_UP_EI, 66000);
5602 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5603
5604 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5605
5606 /* 5: Enable RPS */
5607 I915_WRITE(GEN6_RP_CONTROL,
5608 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5609 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5610 GEN6_RP_ENABLE |
5611 GEN6_RP_UP_BUSY_AVG |
5612 GEN6_RP_DOWN_IDLE_AVG);
5613
3ef62342
D		 5614 /* Setting Fixed Bias */
5615 val = VLV_OVERRIDE_EN |
5616 VLV_SOC_TDP_EN |
5617 CHV_BIAS_CPU_50_SOC_50;
5618 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5619
2b6b3a09
D		 5620 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5621
8d40c3ae
VS		 5622 /* RPS code assumes GPLL is used */
5623 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5624
742f491d 5625 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5626 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5627
5628 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5629 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5630 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5631 dev_priv->rps.cur_freq);
5632
5633 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5634 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5635 dev_priv->rps.idle_freq);
2b6b3a09 5636
5fd9f523 5637 valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b6b3a09 5638
59bad947 5639 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5640}
5641
0a073b84
JB		 5642static void valleyview_enable_rps(struct drm_device *dev)
5643{
5644 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5645 struct intel_engine_cs *engine;
2a5913a8 5646 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5647
5648 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5649
ae48434c
ID		 5650 valleyview_check_pctx(dev_priv);
5651
297b32ec
VS		 5652 gtfifodbg = I915_READ(GTFIFODBG);
5653 if (gtfifodbg) {
f7d85c1e
JB		 5654 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5655 gtfifodbg);
0a073b84
JB		 5656 I915_WRITE(GTFIFODBG, gtfifodbg);
5657 }
5658
c8d9a590 5659 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5660 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5661
160614a2
VS		 5662 /* Disable RC states. */
5663 I915_WRITE(GEN6_RC_CONTROL, 0);
5664
cad725fe 5665 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5666 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5667 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5668 I915_WRITE(GEN6_RP_UP_EI, 66000);
5669 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5670
5671 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5672
5673 I915_WRITE(GEN6_RP_CONTROL,
5674 GEN6_RP_MEDIA_TURBO |
5675 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5676 GEN6_RP_MEDIA_IS_GFX |
5677 GEN6_RP_ENABLE |
5678 GEN6_RP_UP_BUSY_AVG |
5679 GEN6_RP_DOWN_IDLE_CONT);
5680
5681 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5682 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5683 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5684
b4ac5afc 5685 for_each_engine(engine, dev_priv)
e2f80391 5686 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5687
2f0aa304 5688 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5689
5690 /* allows RC6 residency counter to work */
49798eb2 5691 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5692 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5693 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5694 VLV_MEDIA_RC6_COUNT_EN |
5695 VLV_RENDER_RC6_COUNT_EN));
31685c25 5696
a2b23fe0 5697 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5698 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5699
5700 intel_print_rc6_info(dev, rc6_mode);
5701
a2b23fe0 5702 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5703
3ef62342
D		 5704 /* Setting Fixed Bias */
5705 val = VLV_OVERRIDE_EN |
5706 VLV_SOC_TDP_EN |
5707 VLV_BIAS_CPU_125_SOC_875;
5708 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5709
64936258 5710 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5711
8d40c3ae
VS		 5712 /* RPS code assumes GPLL is used */
5713 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5714
742f491d 5715 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5716 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5717
b39fb297 5718 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5719 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5720 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5721 dev_priv->rps.cur_freq);
0a073b84 5722
73008b98 5723 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5724 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5725 dev_priv->rps.idle_freq);
0a073b84 5726
5fd9f523 5727 valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
0a073b84 5728
59bad947 5729 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5730}
5731
dde18883
ED		 5732static unsigned long intel_pxfreq(u32 vidfreq)
5733{
5734 unsigned long freq;
5735 int div = (vidfreq & 0x3f0000) >> 16;
5736 int post = (vidfreq & 0x3000) >> 12;
5737 int pre = (vidfreq & 0x7);
5738
5739 if (!pre)
5740 return 0;
5741
5742 freq = ((div * 133333) / ((1<<post) * pre));
5743
5744 return freq;
5745}
5746
eb48eb00
DV		 5747static const struct cparams {
5748 u16 i;
5749 u16 t;
5750 u16 m;
5751 u16 c;
5752} cparams[] = {
5753 { 1, 1333, 301, 28664 },
5754 { 1, 1066, 294, 24460 },
5755 { 1, 800, 294, 25192 },
5756 { 0, 1333, 276, 27605 },
5757 { 0, 1066, 276, 27605 },
5758 { 0, 800, 231, 23784 },
5759};
5760
f531dcb2 5761static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5762{
5763 u64 total_count, diff, ret;
5764 u32 count1, count2, count3, m = 0, c = 0;
5765 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5766 int i;
5767
02d71956
DV		 5768 assert_spin_locked(&mchdev_lock);
5769
20e4d407 5770 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5771
5772 /* Prevent division-by-zero if we are asking too fast.
5773 * Also, we don't get interesting results if we are polling
5774 * faster than once in 10ms, so just return the saved value
5775 * in such cases.
5776 */
5777 if (diff1 <= 10)
20e4d407 5778 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5779
5780 count1 = I915_READ(DMIEC);
5781 count2 = I915_READ(DDREC);
5782 count3 = I915_READ(CSIEC);
5783
5784 total_count = count1 + count2 + count3;
5785
5786 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5787 if (total_count < dev_priv->ips.last_count1) {
5788 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5789 diff += total_count;
5790 } else {
20e4d407 5791 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5792 }
5793
5794 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5795 if (cparams[i].i == dev_priv->ips.c_m &&
5796 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5797 m = cparams[i].m;
5798 c = cparams[i].c;
5799 break;
5800 }
5801 }
5802
5803 diff = div_u64(diff, diff1);
5804 ret = ((m * diff) + c);
5805 ret = div_u64(ret, 10);
5806
20e4d407
DV		 5807 dev_priv->ips.last_count1 = total_count;
5808 dev_priv->ips.last_time1 = now;
eb48eb00 5809
20e4d407 5810 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5811
5812 return ret;
5813}
5814
f531dcb2
CW		 5815unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5816{
3d13ef2e 5817 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5818 unsigned long val;
5819
3d13ef2e 5820 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5821 return 0;
5822
5823 spin_lock_irq(&mchdev_lock);
5824
5825 val = __i915_chipset_val(dev_priv);
5826
5827 spin_unlock_irq(&mchdev_lock);
5828
5829 return val;
5830}
5831
eb48eb00
DV		 5832unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5833{
5834 unsigned long m, x, b;
5835 u32 tsfs;
5836
5837 tsfs = I915_READ(TSFS);
5838
5839 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5840 x = I915_READ8(TR1);
5841
5842 b = tsfs & TSFS_INTR_MASK;
5843
5844 return ((m * x) / 127) - b;
5845}
5846
d972d6ee
MK		 5847static int _pxvid_to_vd(u8 pxvid)
5848{
5849 if (pxvid == 0)
5850 return 0;
5851
5852 if (pxvid >= 8 && pxvid < 31)
5853 pxvid = 31;
5854
5855 return (pxvid + 2) * 125;
5856}
5857
5858static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5859{
3d13ef2e 5860 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5861 const int vd = _pxvid_to_vd(pxvid);
5862 const int vm = vd - 1125;
5863
3d13ef2e 5864 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5865 return vm > 0 ? vm : 0;
5866
5867 return vd;
eb48eb00
DV		 5868}
5869
02d71956 5870static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5871{
5ed0bdf2 5872 u64 now, diff, diffms;
eb48eb00
DV		 5873 u32 count;
5874
02d71956 5875 assert_spin_locked(&mchdev_lock);
eb48eb00 5876
5ed0bdf2
TG		 5877 now = ktime_get_raw_ns();
5878 diffms = now - dev_priv->ips.last_time2;
5879 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5880
5881 /* Don't divide by 0 */
eb48eb00
DV		 5882 if (!diffms)
5883 return;
5884
5885 count = I915_READ(GFXEC);
5886
20e4d407
DV		 5887 if (count < dev_priv->ips.last_count2) {
5888 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5889 diff += count;
5890 } else {
20e4d407 5891 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5892 }
5893
20e4d407
DV		 5894 dev_priv->ips.last_count2 = count;
5895 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5896
5897 /* More magic constants... */
5898 diff = diff * 1181;
5899 diff = div_u64(diff, diffms * 10);
20e4d407 5900 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5901}
5902
02d71956
DV		 5903void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5904{
3d13ef2e
DL		 5905 struct drm_device *dev = dev_priv->dev;
5906
5907 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5908 return;
5909
9270388e 5910 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5911
5912 __i915_update_gfx_val(dev_priv);
5913
9270388e 5914 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5915}
5916
f531dcb2 5917static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5918{
5919 unsigned long t, corr, state1, corr2, state2;
5920 u32 pxvid, ext_v;
5921
02d71956
DV		 5922 assert_spin_locked(&mchdev_lock);
5923
616847e7 5924 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5925 pxvid = (pxvid >> 24) & 0x7f;
5926 ext_v = pvid_to_extvid(dev_priv, pxvid);
5927
5928 state1 = ext_v;
5929
5930 t = i915_mch_val(dev_priv);
5931
5932 /* Revel in the empirically derived constants */
5933
5934 /* Correction factor in 1/100000 units */
5935 if (t > 80)
5936 corr = ((t * 2349) + 135940);
5937 else if (t >= 50)
5938 corr = ((t * 964) + 29317);
5939 else /* < 50 */
5940 corr = ((t * 301) + 1004);
5941
5942 corr = corr * ((150142 * state1) / 10000 - 78642);
5943 corr /= 100000;
20e4d407 5944 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5945
5946 state2 = (corr2 * state1) / 10000;
5947 state2 /= 100; /* convert to mW */
5948
02d71956 5949 __i915_update_gfx_val(dev_priv);
eb48eb00 5950
20e4d407 5951 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5952}
5953
f531dcb2
CW		 5954unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5955{
3d13ef2e 5956 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5957 unsigned long val;
5958
3d13ef2e 5959 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5960 return 0;
5961
5962 spin_lock_irq(&mchdev_lock);
5963
5964 val = __i915_gfx_val(dev_priv);
5965
5966 spin_unlock_irq(&mchdev_lock);
5967
5968 return val;
5969}
5970
eb48eb00
DV		 5971/**
5972 * i915_read_mch_val - return value for IPS use
5973 *
5974 * Calculate and return a value for the IPS driver to use when deciding whether
5975 * we have thermal and power headroom to increase CPU or GPU power budget.
5976 */
5977unsigned long i915_read_mch_val(void)
5978{
5979 struct drm_i915_private *dev_priv;
5980 unsigned long chipset_val, graphics_val, ret = 0;
5981
9270388e 5982 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5983 if (!i915_mch_dev)
5984 goto out_unlock;
5985 dev_priv = i915_mch_dev;
5986
f531dcb2
CW		 5987 chipset_val = __i915_chipset_val(dev_priv);
5988 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5989
5990 ret = chipset_val + graphics_val;
5991
5992out_unlock:
9270388e 5993 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5994
5995 return ret;
5996}
5997EXPORT_SYMBOL_GPL(i915_read_mch_val);
5998
5999/**
6000 * i915_gpu_raise - raise GPU frequency limit
6001 *
6002 * Raise the limit; IPS indicates we have thermal headroom.
6003 */
6004bool i915_gpu_raise(void)
6005{
6006 struct drm_i915_private *dev_priv;
6007 bool ret = true;
6008
9270388e 6009 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6010 if (!i915_mch_dev) {
6011 ret = false;
6012 goto out_unlock;
6013 }
6014 dev_priv = i915_mch_dev;
6015
20e4d407
DV		 6016 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6017 dev_priv->ips.max_delay--;
eb48eb00
DV		 6018
6019out_unlock:
9270388e 6020 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6021
6022 return ret;
6023}
6024EXPORT_SYMBOL_GPL(i915_gpu_raise);
6025
6026/**
6027 * i915_gpu_lower - lower GPU frequency limit
6028 *
6029 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6030 * frequency maximum.
6031 */
6032bool i915_gpu_lower(void)
6033{
6034 struct drm_i915_private *dev_priv;
6035 bool ret = true;
6036
9270388e 6037 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6038 if (!i915_mch_dev) {
6039 ret = false;
6040 goto out_unlock;
6041 }
6042 dev_priv = i915_mch_dev;
6043
20e4d407
DV		 6044 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6045 dev_priv->ips.max_delay++;
eb48eb00
DV		 6046
6047out_unlock:
9270388e 6048 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6049
6050 return ret;
6051}
6052EXPORT_SYMBOL_GPL(i915_gpu_lower);
6053
6054/**
6055 * i915_gpu_busy - indicate GPU business to IPS
6056 *
6057 * Tell the IPS driver whether or not the GPU is busy.
6058 */
6059bool i915_gpu_busy(void)
6060{
6061 struct drm_i915_private *dev_priv;
e2f80391 6062 struct intel_engine_cs *engine;
eb48eb00
DV		 6063 bool ret = false;
6064
9270388e 6065 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6066 if (!i915_mch_dev)
6067 goto out_unlock;
6068 dev_priv = i915_mch_dev;
6069
b4ac5afc 6070 for_each_engine(engine, dev_priv)
e2f80391 6071 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6072
6073out_unlock:
9270388e 6074 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6075
6076 return ret;
6077}
6078EXPORT_SYMBOL_GPL(i915_gpu_busy);
6079
6080/**
6081 * i915_gpu_turbo_disable - disable graphics turbo
6082 *
6083 * Disable graphics turbo by resetting the max frequency and setting the
6084 * current frequency to the default.
6085 */
6086bool i915_gpu_turbo_disable(void)
6087{
6088 struct drm_i915_private *dev_priv;
6089 bool ret = true;
6090
9270388e 6091 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6092 if (!i915_mch_dev) {
6093 ret = false;
6094 goto out_unlock;
6095 }
6096 dev_priv = i915_mch_dev;
6097
20e4d407 6098 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6099
20e4d407 6100 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6101 ret = false;
6102
6103out_unlock:
9270388e 6104 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6105
6106 return ret;
6107}
6108EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6109
6110/**
6111 * Tells the intel_ips driver that the i915 driver is now loaded, if
6112 * IPS got loaded first.
6113 *
6114 * This awkward dance is so that neither module has to depend on the
6115 * other in order for IPS to do the appropriate communication of
6116 * GPU turbo limits to i915.
6117 */
6118static void
6119ips_ping_for_i915_load(void)
6120{
6121 void (*link)(void);
6122
6123 link = symbol_get(ips_link_to_i915_driver);
6124 if (link) {
6125 link();
6126 symbol_put(ips_link_to_i915_driver);
6127 }
6128}
6129
6130void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6131{
02d71956
DV		 6132 /* We only register the i915 ips part with intel-ips once everything is
6133 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6134 spin_lock_irq(&mchdev_lock);
eb48eb00 6135 i915_mch_dev = dev_priv;
9270388e 6136 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6137
6138 ips_ping_for_i915_load();
6139}
6140
6141void intel_gpu_ips_teardown(void)
6142{
9270388e 6143 spin_lock_irq(&mchdev_lock);
eb48eb00 6144 i915_mch_dev = NULL;
9270388e 6145 spin_unlock_irq(&mchdev_lock);
eb48eb00 6146}
76c3552f 6147
8090c6b9 6148static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6149{
6150 struct drm_i915_private *dev_priv = dev->dev_private;
6151 u32 lcfuse;
6152 u8 pxw[16];
6153 int i;
6154
6155 /* Disable to program */
6156 I915_WRITE(ECR, 0);
6157 POSTING_READ(ECR);
6158
6159 /* Program energy weights for various events */
6160 I915_WRITE(SDEW, 0x15040d00);
6161 I915_WRITE(CSIEW0, 0x007f0000);
6162 I915_WRITE(CSIEW1, 0x1e220004);
6163 I915_WRITE(CSIEW2, 0x04000004);
6164
6165 for (i = 0; i < 5; i++)
616847e7 6166 I915_WRITE(PEW(i), 0);
dde18883 6167 for (i = 0; i < 3; i++)
616847e7 6168 I915_WRITE(DEW(i), 0);
dde18883
ED		 6169
6170 /* Program P-state weights to account for frequency power adjustment */
6171 for (i = 0; i < 16; i++) {
616847e7 6172 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6173 unsigned long freq = intel_pxfreq(pxvidfreq);
6174 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6175 PXVFREQ_PX_SHIFT;
6176 unsigned long val;
6177
6178 val = vid * vid;
6179 val *= (freq / 1000);
6180 val *= 255;
6181 val /= (127*127*900);
6182 if (val > 0xff)
6183 DRM_ERROR("bad pxval: %ld\n", val);
6184 pxw[i] = val;
6185 }
6186 /* Render standby states get 0 weight */
6187 pxw[14] = 0;
6188 pxw[15] = 0;
6189
6190 for (i = 0; i < 4; i++) {
6191 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6192 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6193 I915_WRITE(PXW(i), val);
dde18883
ED		 6194 }
6195
6196 /* Adjust magic regs to magic values (more experimental results) */
6197 I915_WRITE(OGW0, 0);
6198 I915_WRITE(OGW1, 0);
6199 I915_WRITE(EG0, 0x00007f00);
6200 I915_WRITE(EG1, 0x0000000e);
6201 I915_WRITE(EG2, 0x000e0000);
6202 I915_WRITE(EG3, 0x68000300);
6203 I915_WRITE(EG4, 0x42000000);
6204 I915_WRITE(EG5, 0x00140031);
6205 I915_WRITE(EG6, 0);
6206 I915_WRITE(EG7, 0);
6207
6208 for (i = 0; i < 8; i++)
616847e7 6209 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6210
6211 /* Enable PMON + select events */
6212 I915_WRITE(ECR, 0x80000019);
6213
6214 lcfuse = I915_READ(LCFUSE02);
6215
20e4d407 6216 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6217}
6218
ae48434c
ID		 6219void intel_init_gt_powersave(struct drm_device *dev)
6220{
b268c699
ID		 6221 struct drm_i915_private *dev_priv = dev->dev_private;
6222
b268c699
ID		 6223 /*
6224 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6225 * requirement.
6226 */
6227 if (!i915.enable_rc6) {
6228 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6229 intel_runtime_pm_get(dev_priv);
6230 }
e6069ca8 6231
38807746
D		 6232 if (IS_CHERRYVIEW(dev))
6233 cherryview_init_gt_powersave(dev);
6234 else if (IS_VALLEYVIEW(dev))
4e80519e 6235 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6236}
6237
6238void intel_cleanup_gt_powersave(struct drm_device *dev)
6239{
b268c699
ID		 6240 struct drm_i915_private *dev_priv = dev->dev_private;
6241
38807746
D		 6242 if (IS_CHERRYVIEW(dev))
6243 return;
6244 else if (IS_VALLEYVIEW(dev))
4e80519e 6245 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6246
6247 if (!i915.enable_rc6)
6248 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6249}
6250
dbea3cea
ID		 6251static void gen6_suspend_rps(struct drm_device *dev)
6252{
6253 struct drm_i915_private *dev_priv = dev->dev_private;
6254
6255 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6256
4c2a8897 6257 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6258}
6259
156c7ca0
JB		 6260/**
6261 * intel_suspend_gt_powersave - suspend PM work and helper threads
6262 * @dev: drm device
6263 *
6264 * We don't want to disable RC6 or other features here, we just want
6265 * to make sure any work we've queued has finished and won't bother
6266 * us while we're suspended.
6267 */
6268void intel_suspend_gt_powersave(struct drm_device *dev)
6269{
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271
d4d70aa5
ID		 6272 if (INTEL_INFO(dev)->gen < 6)
6273 return;
6274
dbea3cea 6275 gen6_suspend_rps(dev);
b47adc17
D		 6276
6277 /* Force GPU to min freq during suspend */
6278 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6279}
6280
8090c6b9
DV		 6281void intel_disable_gt_powersave(struct drm_device *dev)
6282{
1a01ab3b
JB		 6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284
930ebb46 6285 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6286 ironlake_disable_drps(dev);
38807746 6287 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6288 intel_suspend_gt_powersave(dev);
e494837a 6289
4fc688ce 6290 mutex_lock(&dev_priv->rps.hw_lock);
2030d684
AG		 6291 if (INTEL_INFO(dev)->gen >= 9) {
6292 gen9_disable_rc6(dev);
20e49366 6293 gen9_disable_rps(dev);
2030d684 6294 } else if (IS_CHERRYVIEW(dev))
38807746
D		 6295 cherryview_disable_rps(dev);
6296 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6297 valleyview_disable_rps(dev);
6298 else
6299 gen6_disable_rps(dev);
e534770a 6300
c0951f0c 6301 dev_priv->rps.enabled = false;
4fc688ce 6302 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6303 }
8090c6b9
DV		 6304}
6305
1a01ab3b
JB		 6306static void intel_gen6_powersave_work(struct work_struct *work)
6307{
6308 struct drm_i915_private *dev_priv =
6309 container_of(work, struct drm_i915_private,
6310 rps.delayed_resume_work.work);
6311 struct drm_device *dev = dev_priv->dev;
6312
4fc688ce 6313 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6314
4c2a8897 6315 gen6_reset_rps_interrupts(dev);
3cc134e3 6316
38807746
D		 6317 if (IS_CHERRYVIEW(dev)) {
6318 cherryview_enable_rps(dev);
6319 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6320 valleyview_enable_rps(dev);
20e49366 6321 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6322 gen9_enable_rc6(dev);
20e49366 6323 gen9_enable_rps(dev);
ef11bdb3 6324 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6325 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6326 } else if (IS_BROADWELL(dev)) {
6327 gen8_enable_rps(dev);
c2bc2fc5 6328 __gen6_update_ring_freq(dev);
0a073b84
JB		 6329 } else {
6330 gen6_enable_rps(dev);
c2bc2fc5 6331 __gen6_update_ring_freq(dev);
0a073b84 6332 }
aed242ff
CW		 6333
6334 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6335 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6336
6337 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6338 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6339
c0951f0c 6340 dev_priv->rps.enabled = true;
3cc134e3 6341
4c2a8897 6342 gen6_enable_rps_interrupts(dev);
3cc134e3 6343
4fc688ce 6344 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6345
6346 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6347}
6348
8090c6b9
DV		 6349void intel_enable_gt_powersave(struct drm_device *dev)
6350{
1a01ab3b
JB		 6351 struct drm_i915_private *dev_priv = dev->dev_private;
6352
f61018b1
YZ		 6353 /* Powersaving is controlled by the host when inside a VM */
6354 if (intel_vgpu_active(dev))
6355 return;
6356
8090c6b9
DV		 6357 if (IS_IRONLAKE_M(dev)) {
6358 ironlake_enable_drps(dev);
84f1b20f 6359 mutex_lock(&dev->struct_mutex);
8090c6b9 6360 intel_init_emon(dev);
dc1d0136 6361 mutex_unlock(&dev->struct_mutex);
38807746 6362 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6363 /*
6364 * PCU communication is slow and this doesn't need to be
6365 * done at any specific time, so do this out of our fast path
6366 * to make resume and init faster.
c6df39b5
ID		 6367 *
6368 * We depend on the HW RC6 power context save/restore
6369 * mechanism when entering D3 through runtime PM suspend. So
6370 * disable RPM until RPS/RC6 is properly setup. We can only
6371 * get here via the driver load/system resume/runtime resume
6372 * paths, so the _noresume version is enough (and in case of
6373 * runtime resume it's necessary).
1a01ab3b 6374 */
c6df39b5
ID		 6375 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6376 round_jiffies_up_relative(HZ)))
6377 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6378 }
6379}
6380
c6df39b5
ID		 6381void intel_reset_gt_powersave(struct drm_device *dev)
6382{
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6384
dbea3cea
ID		 6385 if (INTEL_INFO(dev)->gen < 6)
6386 return;
6387
6388 gen6_suspend_rps(dev);
c6df39b5 6389 dev_priv->rps.enabled = false;
c6df39b5
ID		 6390}
6391
3107bd48
DV		 6392static void ibx_init_clock_gating(struct drm_device *dev)
6393{
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395
6396 /*
6397 * On Ibex Peak and Cougar Point, we need to disable clock
6398 * gating for the panel power sequencer or it will fail to
6399 * start up when no ports are active.
6400 */
6401 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6402}
6403
0e088b8f
VS		 6404static void g4x_disable_trickle_feed(struct drm_device *dev)
6405{
6406 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6407 enum pipe pipe;
0e088b8f 6408
055e393f 6409 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6410 I915_WRITE(DSPCNTR(pipe),
6411 I915_READ(DSPCNTR(pipe)) |
6412 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6413
6414 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6415 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6416 }
6417}
6418
017636cc
VS		 6419static void ilk_init_lp_watermarks(struct drm_device *dev)
6420{
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422
6423 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6424 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6425 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6426
6427 /*
6428 * Don't touch WM1S_LP_EN here.
6429 * Doing so could cause underruns.
6430 */
6431}
6432
1fa61106 6433static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6434{
6435 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6436 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6437
f1e8fa56
DL		 6438 /*
6439 * Required for FBC
6440 * WaFbcDisableDpfcClockGating:ilk
6441 */
4d47e4f5
DL		 6442 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6443 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6444 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6445
6446 I915_WRITE(PCH_3DCGDIS0,
6447 MARIUNIT_CLOCK_GATE_DISABLE |
6448 SVSMUNIT_CLOCK_GATE_DISABLE);
6449 I915_WRITE(PCH_3DCGDIS1,
6450 VFMUNIT_CLOCK_GATE_DISABLE);
6451
6f1d69b0
ED		 6452 /*
6453 * According to the spec the following bits should be set in
6454 * order to enable memory self-refresh
6455 * The bit 22/21 of 0x42004
6456 * The bit 5 of 0x42020
6457 * The bit 15 of 0x45000
6458 */
6459 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6460 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6461 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6462 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6463 I915_WRITE(DISP_ARB_CTL,
6464 (I915_READ(DISP_ARB_CTL) |
6465 DISP_FBC_WM_DIS));
017636cc
VS		 6466
6467 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6468
6469 /*
6470 * Based on the document from hardware guys the following bits
6471 * should be set unconditionally in order to enable FBC.
6472 * The bit 22 of 0x42000
6473 * The bit 22 of 0x42004
6474 * The bit 7,8,9 of 0x42020.
6475 */
6476 if (IS_IRONLAKE_M(dev)) {
4bb35334 6477 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6478 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6479 I915_READ(ILK_DISPLAY_CHICKEN1) |
6480 ILK_FBCQ_DIS);
6481 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6482 I915_READ(ILK_DISPLAY_CHICKEN2) |
6483 ILK_DPARB_GATE);
6f1d69b0
ED		 6484 }
6485
4d47e4f5
DL		 6486 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6487
6f1d69b0
ED		 6488 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6489 I915_READ(ILK_DISPLAY_CHICKEN2) |
6490 ILK_ELPIN_409_SELECT);
6491 I915_WRITE(_3D_CHICKEN2,
6492 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6493 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6494
ecdb4eb7 6495 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6496 I915_WRITE(CACHE_MODE_0,
6497 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6498
4e04632e
AG		 6499 /* WaDisable_RenderCache_OperationalFlush:ilk */
6500 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6501
0e088b8f 6502 g4x_disable_trickle_feed(dev);
bdad2b2f 6503
3107bd48
DV		 6504 ibx_init_clock_gating(dev);
6505}
6506
6507static void cpt_init_clock_gating(struct drm_device *dev)
6508{
6509 struct drm_i915_private *dev_priv = dev->dev_private;
6510 int pipe;
3f704fa2 6511 uint32_t val;
3107bd48
DV		 6512
6513 /*
6514 * On Ibex Peak and Cougar Point, we need to disable clock
6515 * gating for the panel power sequencer or it will fail to
6516 * start up when no ports are active.
6517 */
cd664078
JB		 6518 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6519 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6520 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6521 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6522 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6523 /* The below fixes the weird display corruption, a few pixels shifted
6524 * downward, on (only) LVDS of some HP laptops with IVY.
6525 */
055e393f 6526 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6527 val = I915_READ(TRANS_CHICKEN2(pipe));
6528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6529 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6530 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6531 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6532 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6533 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6534 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6535 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6536 }
3107bd48 6537 /* WADP0ClockGatingDisable */
055e393f 6538 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6539 I915_WRITE(TRANS_CHICKEN1(pipe),
6540 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6541 }
6f1d69b0
ED		 6542}
6543
1d7aaa0c
DV		 6544static void gen6_check_mch_setup(struct drm_device *dev)
6545{
6546 struct drm_i915_private *dev_priv = dev->dev_private;
6547 uint32_t tmp;
6548
6549 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6550 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6551 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6552 tmp);
1d7aaa0c
DV		 6553}
6554
1fa61106 6555static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6556{
6557 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6558 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6559
231e54f6 6560 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6561
6562 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6563 I915_READ(ILK_DISPLAY_CHICKEN2) |
6564 ILK_ELPIN_409_SELECT);
6565
ecdb4eb7 6566 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6567 I915_WRITE(_3D_CHICKEN,
6568 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6569
4e04632e
AG		 6570 /* WaDisable_RenderCache_OperationalFlush:snb */
6571 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6572
8d85d272
VS		 6573 /*
6574 * BSpec recoomends 8x4 when MSAA is used,
6575 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6576 *
6577 * Note that PS/WM thread counts depend on the WIZ hashing
6578 * disable bit, which we don't touch here, but it's good
6579 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6580 */
6581 I915_WRITE(GEN6_GT_MODE,
98533251 6582 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6583
017636cc 6584 ilk_init_lp_watermarks(dev);
6f1d69b0 6585
6f1d69b0 6586 I915_WRITE(CACHE_MODE_0,
50743298 6587 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6588
6589 I915_WRITE(GEN6_UCGCTL1,
6590 I915_READ(GEN6_UCGCTL1) |
6591 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6592 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6593
6594 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6595 * gating disable must be set. Failure to set it results in
6596 * flickering pixels due to Z write ordering failures after
6597 * some amount of runtime in the Mesa "fire" demo, and Unigine
6598 * Sanctuary and Tropics, and apparently anything else with
6599 * alpha test or pixel discard.
6600 *
6601 * According to the spec, bit 11 (RCCUNIT) must also be set,
6602 * but we didn't debug actual testcases to find it out.
0f846f81 6603 *
ef59318c
VS		 6604 * WaDisableRCCUnitClockGating:snb
6605 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6606 */
6607 I915_WRITE(GEN6_UCGCTL2,
6608 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6609 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6610
5eb146dd 6611 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6612 I915_WRITE(_3D_CHICKEN3,
6613 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6614
e927ecde
VS		 6615 /*
6616 * Bspec says:
6617 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6618 * 3DSTATE_SF number of SF output attributes is more than 16."
6619 */
6620 I915_WRITE(_3D_CHICKEN3,
6621 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6622
6f1d69b0
ED		 6623 /*
6624 * According to the spec the following bits should be
6625 * set in order to enable memory self-refresh and fbc:
6626 * The bit21 and bit22 of 0x42000
6627 * The bit21 and bit22 of 0x42004
6628 * The bit5 and bit7 of 0x42020
6629 * The bit14 of 0x70180
6630 * The bit14 of 0x71180
4bb35334
DL		 6631 *
6632 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6633 */
6634 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6635 I915_READ(ILK_DISPLAY_CHICKEN1) |
6636 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6637 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6638 I915_READ(ILK_DISPLAY_CHICKEN2) |
6639 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6640 I915_WRITE(ILK_DSPCLK_GATE_D,
6641 I915_READ(ILK_DSPCLK_GATE_D) |
6642 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6643 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6644
0e088b8f 6645 g4x_disable_trickle_feed(dev);
f8f2ac9a 6646
3107bd48 6647 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6648
6649 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6650}
6651
6652static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6653{
6654 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6655
3aad9059 6656 /*
46680e0a 6657 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6658 *
6659 * This actually overrides the dispatch
6660 * mode for all thread types.
6661 */
6f1d69b0
ED		 6662 reg &= ~GEN7_FF_SCHED_MASK;
6663 reg |= GEN7_FF_TS_SCHED_HW;
6664 reg |= GEN7_FF_VS_SCHED_HW;
6665 reg |= GEN7_FF_DS_SCHED_HW;
6666
6667 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6668}
6669
17a303ec
PZ		 6670static void lpt_init_clock_gating(struct drm_device *dev)
6671{
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673
6674 /*
6675 * TODO: this bit should only be enabled when really needed, then
6676 * disabled when not needed anymore in order to save power.
6677 */
c2699524 6678 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6679 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6680 I915_READ(SOUTH_DSPCLK_GATE_D) |
6681 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6682
6683 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6684 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6685 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6686 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6687}
6688
7d708ee4
ID		 6689static void lpt_suspend_hw(struct drm_device *dev)
6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
6692
c2699524 6693 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6694 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6695
6696 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6697 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6698 }
6699}
6700
47c2bd97 6701static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6702{
6703 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6704 enum pipe pipe;
4d487cff 6705 uint32_t misccpctl;
1020a5c2 6706
7ad0dbab 6707 ilk_init_lp_watermarks(dev);
50ed5fbd 6708
ab57fff1 6709 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6710 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6711
ab57fff1 6712 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6713 I915_WRITE(CHICKEN_PAR1_1,
6714 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6715
ab57fff1 6716 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6717 for_each_pipe(dev_priv, pipe) {
07d27e20 6718 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6719 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6720 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6721 }
63801f21 6722
ab57fff1
BW		 6723 /* WaVSRefCountFullforceMissDisable:bdw */
6724 /* WaDSRefCountFullforceMissDisable:bdw */
6725 I915_WRITE(GEN7_FF_THREAD_MODE,
6726 I915_READ(GEN7_FF_THREAD_MODE) &
6727 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6728
295e8bb7
VS		 6729 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6730 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6731
6732 /* WaDisableSDEUnitClockGating:bdw */
6733 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6734 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6735
4d487cff
VS		 6736 /*
6737 * WaProgramL3SqcReg1Default:bdw
6738 * WaTempDisableDOPClkGating:bdw
6739 */
6740 misccpctl = I915_READ(GEN7_MISCCPCTL);
6741 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6742 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
d6a862fe
ID		 6743 /*
6744 * Wait at least 100 clocks before re-enabling clock gating. See
6745 * the definition of L3SQCREG1 in BSpec.
6746 */
6747 POSTING_READ(GEN8_L3SQCREG1);
6748 udelay(1);
4d487cff
VS		 6749 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6750
6d50b065
VS		 6751 /*
6752 * WaGttCachingOffByDefault:bdw
6753 * GTT cache may not work with big pages, so if those
6754 * are ever enabled GTT cache may need to be disabled.
6755 */
6756 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6757
89d6b2b8 6758 lpt_init_clock_gating(dev);
1020a5c2
BW		 6759}
6760
cad2a2d7
ED		 6761static void haswell_init_clock_gating(struct drm_device *dev)
6762{
6763 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6764
017636cc 6765 ilk_init_lp_watermarks(dev);
cad2a2d7 6766
f3fc4884
FJ		 6767 /* L3 caching of data atomics doesn't work -- disable it. */
6768 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6769 I915_WRITE(HSW_ROW_CHICKEN3,
6770 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6771
ecdb4eb7 6772 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6773 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6774 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6775 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6776
e36ea7ff
VS		 6777 /* WaVSRefCountFullforceMissDisable:hsw */
6778 I915_WRITE(GEN7_FF_THREAD_MODE,
6779 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6780
4e04632e
AG		 6781 /* WaDisable_RenderCache_OperationalFlush:hsw */
6782 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6783
fe27c606
CW		 6784 /* enable HiZ Raw Stall Optimization */
6785 I915_WRITE(CACHE_MODE_0_GEN7,
6786 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6787
ecdb4eb7 6788 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6789 I915_WRITE(CACHE_MODE_1,
6790 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6791
a12c4967
VS		 6792 /*
6793 * BSpec recommends 8x4 when MSAA is used,
6794 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6795 *
6796 * Note that PS/WM thread counts depend on the WIZ hashing
6797 * disable bit, which we don't touch here, but it's good
6798 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6799 */
6800 I915_WRITE(GEN7_GT_MODE,
98533251 6801 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6802
94411593
KG		 6803 /* WaSampleCChickenBitEnable:hsw */
6804 I915_WRITE(HALF_SLICE_CHICKEN3,
6805 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6806
ecdb4eb7 6807 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6808 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6809
90a88643
PZ		 6810 /* WaRsPkgCStateDisplayPMReq:hsw */
6811 I915_WRITE(CHICKEN_PAR1_1,
6812 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6813
17a303ec 6814 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6815}
6816
1fa61106 6817static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6818{
6819 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6820 uint32_t snpcr;
6f1d69b0 6821
017636cc 6822 ilk_init_lp_watermarks(dev);
6f1d69b0 6823
231e54f6 6824 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6825
ecdb4eb7 6826 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6827 I915_WRITE(_3D_CHICKEN3,
6828 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6829
ecdb4eb7 6830 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6831 I915_WRITE(IVB_CHICKEN3,
6832 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6833 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6834
ecdb4eb7 6835 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6836 if (IS_IVB_GT1(dev))
6837 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6838 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6839
4e04632e
AG		 6840 /* WaDisable_RenderCache_OperationalFlush:ivb */
6841 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6842
ecdb4eb7 6843 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6844 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6845 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6846
ecdb4eb7 6847 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6848 I915_WRITE(GEN7_L3CNTLREG1,
6849 GEN7_WA_FOR_GEN7_L3_CONTROL);
6850 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6851 GEN7_WA_L3_CHICKEN_MODE);
6852 if (IS_IVB_GT1(dev))
6853 I915_WRITE(GEN7_ROW_CHICKEN2,
6854 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6855 else {
6856 /* must write both registers */
6857 I915_WRITE(GEN7_ROW_CHICKEN2,
6858 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6859 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6860 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6861 }
6f1d69b0 6862
ecdb4eb7 6863 /* WaForceL3Serialization:ivb */
61939d97
JB		 6864 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6865 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6866
1b80a19a 6867 /*
0f846f81 6868 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6869 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6870 */
6871 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6872 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6873
ecdb4eb7 6874 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6875 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6876 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6877 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6878
0e088b8f 6879 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6880
6881 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6882
22721343
CW		 6883 if (0) { /* causes HiZ corruption on ivb:gt1 */
6884 /* enable HiZ Raw Stall Optimization */
6885 I915_WRITE(CACHE_MODE_0_GEN7,
6886 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6887 }
116f2b6d 6888
ecdb4eb7 6889 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6890 I915_WRITE(CACHE_MODE_1,
6891 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6892
a607c1a4
VS		 6893 /*
6894 * BSpec recommends 8x4 when MSAA is used,
6895 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6896 *
6897 * Note that PS/WM thread counts depend on the WIZ hashing
6898 * disable bit, which we don't touch here, but it's good
6899 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6900 */
6901 I915_WRITE(GEN7_GT_MODE,
98533251 6902 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6903
20848223
BW		 6904 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6905 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6906 snpcr |= GEN6_MBC_SNPCR_MED;
6907 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6908
ab5c608b
BW		 6909 if (!HAS_PCH_NOP(dev))
6910 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6911
6912 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6913}
6914
1fa61106 6915static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6916{
6917 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6918
ecdb4eb7 6919 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6920 I915_WRITE(_3D_CHICKEN3,
6921 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6922
ecdb4eb7 6923 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6924 I915_WRITE(IVB_CHICKEN3,
6925 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6926 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6927
fad7d36e 6928 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6929 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6930 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6931 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6932 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6933
4e04632e
AG		 6934 /* WaDisable_RenderCache_OperationalFlush:vlv */
6935 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6936
ecdb4eb7 6937 /* WaForceL3Serialization:vlv */
61939d97
JB		 6938 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6939 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6940
ecdb4eb7 6941 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6942 I915_WRITE(GEN7_ROW_CHICKEN2,
6943 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6944
ecdb4eb7 6945 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6946 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6947 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6948 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6949
46680e0a
VS		 6950 gen7_setup_fixed_func_scheduler(dev_priv);
6951
3c0edaeb 6952 /*
0f846f81 6953 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6954 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6955 */
6956 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6957 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6958
c98f5062
AG		 6959 /* WaDisableL3Bank2xClockGate:vlv
6960 * Disabling L3 clock gating- MMIO 940c[25] = 1
6961 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6962 I915_WRITE(GEN7_UCGCTL4,
6963 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6964
afd58e79
VS		 6965 /*
6966 * BSpec says this must be set, even though
6967 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6968 */
6b26c86d
DV		 6969 I915_WRITE(CACHE_MODE_1,
6970 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6971
da2518f9
VS		 6972 /*
6973 * BSpec recommends 8x4 when MSAA is used,
6974 * however in practice 16x4 seems fastest.
6975 *
6976 * Note that PS/WM thread counts depend on the WIZ hashing
6977 * disable bit, which we don't touch here, but it's good
6978 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6979 */
6980 I915_WRITE(GEN7_GT_MODE,
6981 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6982
031994ee
VS		 6983 /*
6984 * WaIncreaseL3CreditsForVLVB0:vlv
6985 * This is the hardware default actually.
6986 */
6987 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6988
2d809570 6989 /*
ecdb4eb7 6990 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6991 * Disable clock gating on th GCFG unit to prevent a delay
6992 * in the reporting of vblank events.
6993 */
7a0d1eed 6994 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6995}
6996
a4565da8
VS		 6997static void cherryview_init_clock_gating(struct drm_device *dev)
6998{
6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000
232ce337
VS		 7001 /* WaVSRefCountFullforceMissDisable:chv */
7002 /* WaDSRefCountFullforceMissDisable:chv */
7003 I915_WRITE(GEN7_FF_THREAD_MODE,
7004 I915_READ(GEN7_FF_THREAD_MODE) &
7005 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7006
7007 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7008 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7009 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7010
7011 /* WaDisableCSUnitClockGating:chv */
7012 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7013 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7014
7015 /* WaDisableSDEUnitClockGating:chv */
7016 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7017 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 7018
7019 /*
7020 * GTT cache may not work with big pages, so if those
7021 * are ever enabled GTT cache may need to be disabled.
7022 */
7023 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7024}
7025
1fa61106 7026static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7027{
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7029 uint32_t dspclk_gate;
7030
7031 I915_WRITE(RENCLK_GATE_D1, 0);
7032 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7033 GS_UNIT_CLOCK_GATE_DISABLE |
7034 CL_UNIT_CLOCK_GATE_DISABLE);
7035 I915_WRITE(RAMCLK_GATE_D, 0);
7036 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7037 OVRUNIT_CLOCK_GATE_DISABLE |
7038 OVCUNIT_CLOCK_GATE_DISABLE;
7039 if (IS_GM45(dev))
7040 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7041 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7042
7043 /* WaDisableRenderCachePipelinedFlush */
7044 I915_WRITE(CACHE_MODE_0,
7045 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7046
4e04632e
AG		 7047 /* WaDisable_RenderCache_OperationalFlush:g4x */
7048 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7049
0e088b8f 7050 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7051}
7052
1fa61106 7053static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7054{
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056
7057 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7058 I915_WRITE(RENCLK_GATE_D2, 0);
7059 I915_WRITE(DSPCLK_GATE_D, 0);
7060 I915_WRITE(RAMCLK_GATE_D, 0);
7061 I915_WRITE16(DEUC, 0);
20f94967
VS		 7062 I915_WRITE(MI_ARB_STATE,
7063 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7064
7065 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7066 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7067}
7068
1fa61106 7069static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7070{
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072
7073 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7074 I965_RCC_CLOCK_GATE_DISABLE |
7075 I965_RCPB_CLOCK_GATE_DISABLE |
7076 I965_ISC_CLOCK_GATE_DISABLE |
7077 I965_FBC_CLOCK_GATE_DISABLE);
7078 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7079 I915_WRITE(MI_ARB_STATE,
7080 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7081
7082 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7083 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7084}
7085
1fa61106 7086static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 u32 dstate = I915_READ(D_STATE);
7090
7091 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7092 DSTATE_DOT_CLOCK_GATING;
7093 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7094
7095 if (IS_PINEVIEW(dev))
7096 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7097
7098 /* IIR "flip pending" means done if this bit is set */
7099 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7100
7101 /* interrupts should cause a wake up from C3 */
3299254f 7102 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7103
7104 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7105 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7106
7107 I915_WRITE(MI_ARB_STATE,
7108 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7109}
7110
1fa61106 7111static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7112{
7113 struct drm_i915_private *dev_priv = dev->dev_private;
7114
7115 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7116
7117 /* interrupts should cause a wake up from C3 */
7118 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7119 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7120
7121 I915_WRITE(MEM_MODE,
7122 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7123}
7124
1fa61106 7125static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128
7129 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7130
7131 I915_WRITE(MEM_MODE,
7132 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7133 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7134}
7135
6f1d69b0
ED		 7136void intel_init_clock_gating(struct drm_device *dev)
7137{
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139
bb400da9 7140 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7141}
7142
7d708ee4
ID		 7143void intel_suspend_hw(struct drm_device *dev)
7144{
7145 if (HAS_PCH_LPT(dev))
7146 lpt_suspend_hw(dev);
7147}
7148
bb400da9
ID		 7149static void nop_init_clock_gating(struct drm_device *dev)
7150{
7151 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7152}
7153
7154/**
7155 * intel_init_clock_gating_hooks - setup the clock gating hooks
7156 * @dev_priv: device private
7157 *
7158 * Setup the hooks that configure which clocks of a given platform can be
7159 * gated and also apply various GT and display specific workarounds for these
7160 * platforms. Note that some GT specific workarounds are applied separately
7161 * when GPU contexts or batchbuffers start their execution.
7162 */
7163void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7164{
7165 if (IS_SKYLAKE(dev_priv))
7166 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7167 else if (IS_KABYLAKE(dev_priv))
7168 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7169 else if (IS_BROXTON(dev_priv))
7170 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7171 else if (IS_BROADWELL(dev_priv))
7172 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7173 else if (IS_CHERRYVIEW(dev_priv))
7174 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7175 else if (IS_HASWELL(dev_priv))
7176 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7177 else if (IS_IVYBRIDGE(dev_priv))
7178 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7179 else if (IS_VALLEYVIEW(dev_priv))
7180 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7181 else if (IS_GEN6(dev_priv))
7182 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7183 else if (IS_GEN5(dev_priv))
7184 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7185 else if (IS_G4X(dev_priv))
7186 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7187 else if (IS_CRESTLINE(dev_priv))
7188 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7189 else if (IS_BROADWATER(dev_priv))
7190 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7191 else if (IS_GEN3(dev_priv))
7192 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7193 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7194 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7195 else if (IS_GEN2(dev_priv))
7196 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7197 else {
7198 MISSING_CASE(INTEL_DEVID(dev_priv));
7199 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7200 }
7201}
7202
1fa61106
ED		 7203/* Set up chip specific power management-related functions */
7204void intel_init_pm(struct drm_device *dev)
7205{
7206 struct drm_i915_private *dev_priv = dev->dev_private;
7207
7ff0ebcc 7208 intel_fbc_init(dev_priv);
1fa61106 7209
c921aba8
DV		 7210 /* For cxsr */
7211 if (IS_PINEVIEW(dev))
7212 i915_pineview_get_mem_freq(dev);
7213 else if (IS_GEN5(dev))
7214 i915_ironlake_get_mem_freq(dev);
7215
1fa61106 7216 /* For FIFO watermark updates */
f5ed50cb 7217 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7218 skl_setup_wm_latency(dev);
2d41c0b5 7219 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7220 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7221 ilk_setup_wm_latency(dev);
53615a5e 7222
bd602544
VS		 7223 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7224 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7225 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7226 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7227 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7228 dev_priv->display.compute_intermediate_wm =
7229 ilk_compute_intermediate_wm;
7230 dev_priv->display.initial_watermarks =
7231 ilk_initial_watermarks;
7232 dev_priv->display.optimize_watermarks =
7233 ilk_optimize_watermarks;
bd602544
VS		 7234 } else {
7235 DRM_DEBUG_KMS("Failed to read display plane latency. "
7236 "Disable CxSR\n");
7237 }
a4565da8 7238 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7239 vlv_setup_wm_latency(dev);
262cd2e1 7240 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7241 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7242 vlv_setup_wm_latency(dev);
26e1fe4f 7243 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7244 } else if (IS_PINEVIEW(dev)) {
7245 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7246 dev_priv->is_ddr3,
7247 dev_priv->fsb_freq,
7248 dev_priv->mem_freq)) {
7249 DRM_INFO("failed to find known CxSR latency "
7250 "(found ddr%s fsb freq %d, mem freq %d), "
7251 "disabling CxSR\n",
7252 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7253 dev_priv->fsb_freq, dev_priv->mem_freq);
7254 /* Disable CxSR and never update its watermark again */
5209b1f4 7255 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7256 dev_priv->display.update_wm = NULL;
7257 } else
7258 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7259 } else if (IS_G4X(dev)) {
7260 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7261 } else if (IS_GEN4(dev)) {
7262 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7263 } else if (IS_GEN3(dev)) {
7264 dev_priv->display.update_wm = i9xx_update_wm;
7265 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7266 } else if (IS_GEN2(dev)) {
7267 if (INTEL_INFO(dev)->num_pipes == 1) {
7268 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7269 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7270 } else {
7271 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7272 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7273 }
feb56b93
DV		 7274 } else {
7275 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7276 }
7277}
7278
151a49d0 7279int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7280{
4fc688ce 7281 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7282
7283 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7284 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7285 return -EAGAIN;
7286 }
7287
7288 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7289 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7290 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7291
7292 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7293 500)) {
7294 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7295 return -ETIMEDOUT;
7296 }
7297
7298 *val = I915_READ(GEN6_PCODE_DATA);
7299 I915_WRITE(GEN6_PCODE_DATA, 0);
7300
7301 return 0;
7302}
7303
151a49d0 7304int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7305{
4fc688ce 7306 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7307
7308 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7309 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7310 return -EAGAIN;
7311 }
7312
7313 I915_WRITE(GEN6_PCODE_DATA, val);
7314 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7315
7316 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7317 500)) {
7318 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7319 return -ETIMEDOUT;
7320 }
7321
7322 I915_WRITE(GEN6_PCODE_DATA, 0);
7323
7324 return 0;
7325}
a0e4e199 7326
dd06f88c
VS		 7327static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7328{
c30fec65
VS		 7329 /*
7330 * N = val - 0xb7
7331 * Slow = Fast = GPLL ref * N
7332 */
7333 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7334}
7335
b55dd647 7336static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7337{
c30fec65 7338 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7339}
7340
b55dd647 7341static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7342{
c30fec65
VS		 7343 /*
7344 * N = val / 2
7345 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7346 */
7347 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7348}
7349
b55dd647 7350static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7351{
1c14762d 7352 /* CHV needs even values */
c30fec65 7353 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7354}
7355
616bc820 7356int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7357{
2d1fe073 7358 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7359 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7360 GEN9_FREQ_SCALER);
2d1fe073 7361 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7362 return chv_gpu_freq(dev_priv, val);
2d1fe073 7363 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7364 return byt_gpu_freq(dev_priv, val);
7365 else
7366 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7367}
7368
616bc820
VS		 7369int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7370{
2d1fe073 7371 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7372 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7373 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7374 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7375 return chv_freq_opcode(dev_priv, val);
2d1fe073 7376 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7377 return byt_freq_opcode(dev_priv, val);
7378 else
500a3d2e 7379 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7380}
22b1b2f8 7381
6ad790c0
CW		 7382struct request_boost {
7383 struct work_struct work;
eed29a5b 7384 struct drm_i915_gem_request *req;
6ad790c0
CW		 7385};
7386
7387static void __intel_rps_boost_work(struct work_struct *work)
7388{
7389 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7390 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7391
e61b9958 7392 if (!i915_gem_request_completed(req, true))
4a570db5 7393 gen6_rps_boost(to_i915(req->engine->dev), NULL,
e61b9958 7394 req->emitted_jiffies);
6ad790c0 7395
e61b9958 7396 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7397 kfree(boost);
7398}
7399
7400void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7401 struct drm_i915_gem_request *req)
6ad790c0
CW		 7402{
7403 struct request_boost *boost;
7404
eed29a5b 7405 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7406 return;
7407
e61b9958
CW		 7408 if (i915_gem_request_completed(req, true))
7409 return;
7410
6ad790c0
CW		 7411 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7412 if (boost == NULL)
7413 return;
7414
eed29a5b
DV		 7415 i915_gem_request_reference(req);
7416 boost->req = req;
6ad790c0
CW		 7417
7418 INIT_WORK(&boost->work, __intel_rps_boost_work);
7419 queue_work(to_i915(dev)->wq, &boost->work);
7420}
7421
f742a552 7422void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7423{
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425
f742a552 7426 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7427 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7428
907b28c5
CW		 7429 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7430 intel_gen6_powersave_work);
1854d5ca 7431 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7432 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7433 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7434
33688d95 7435 dev_priv->pm.suspended = false;
1f814dac 7436 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7437 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7438}
Linux kernel - Deliverables
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