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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
f9dcb0df | 33 | #include <linux/vgaarb.h> |
f4db9321 | 34 | #include <drm/i915_powerwell.h> |
8a187455 | 35 | #include <linux/pm_runtime.h> |
85208be0 | 36 | |
dc39fff7 BW |
37 | /** |
38 | * RC6 is a special power stage which allows the GPU to enter an very | |
39 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
40 | * stage is entered automatically when the GPU is idle when RC6 support is | |
41 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
42 | * | |
43 | * There are different RC6 modes available in Intel GPU, which differentiate | |
44 | * among each other with the latency required to enter and leave RC6 and | |
45 | * voltage consumed by the GPU in different states. | |
46 | * | |
47 | * The combination of the following flags define which states GPU is allowed | |
48 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
49 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
50 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
51 | * which brings the most power savings; deeper states save more power, but | |
52 | * require higher latency to switch to and wake up. | |
53 | */ | |
54 | #define INTEL_RC6_ENABLE (1<<0) | |
55 | #define INTEL_RC6p_ENABLE (1<<1) | |
56 | #define INTEL_RC6pp_ENABLE (1<<2) | |
57 | ||
f6750b3c ED |
58 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
59 | * framebuffer contents in-memory, aiming at reducing the required bandwidth | |
60 | * during in-memory transfers and, therefore, reduce the power packet. | |
85208be0 | 61 | * |
f6750b3c ED |
62 | * The benefits of FBC are mostly visible with solid backgrounds and |
63 | * variation-less patterns. | |
85208be0 | 64 | * |
f6750b3c ED |
65 | * FBC-related functionality can be enabled by the means of the |
66 | * i915.i915_enable_fbc parameter | |
85208be0 ED |
67 | */ |
68 | ||
1fa61106 | 69 | static void i8xx_disable_fbc(struct drm_device *dev) |
85208be0 ED |
70 | { |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
72 | u32 fbc_ctl; | |
73 | ||
74 | /* Disable compression */ | |
75 | fbc_ctl = I915_READ(FBC_CONTROL); | |
76 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
77 | return; | |
78 | ||
79 | fbc_ctl &= ~FBC_CTL_EN; | |
80 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
81 | ||
82 | /* Wait for compressing bit to clear */ | |
83 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
84 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
85 | return; | |
86 | } | |
87 | ||
88 | DRM_DEBUG_KMS("disabled FBC\n"); | |
89 | } | |
90 | ||
993495ae | 91 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
92 | { |
93 | struct drm_device *dev = crtc->dev; | |
94 | struct drm_i915_private *dev_priv = dev->dev_private; | |
95 | struct drm_framebuffer *fb = crtc->fb; | |
96 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
97 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
98 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
99 | int cfb_pitch; | |
7f2cf220 | 100 | int i; |
159f9875 | 101 | u32 fbc_ctl; |
85208be0 | 102 | |
5c3fe8b0 | 103 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
85208be0 ED |
104 | if (fb->pitches[0] < cfb_pitch) |
105 | cfb_pitch = fb->pitches[0]; | |
106 | ||
42a430f5 VS |
107 | /* FBC_CTL wants 32B or 64B units */ |
108 | if (IS_GEN2(dev)) | |
109 | cfb_pitch = (cfb_pitch / 32) - 1; | |
110 | else | |
111 | cfb_pitch = (cfb_pitch / 64) - 1; | |
85208be0 ED |
112 | |
113 | /* Clear old tags */ | |
114 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
115 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
116 | ||
159f9875 VS |
117 | if (IS_GEN4(dev)) { |
118 | u32 fbc_ctl2; | |
119 | ||
120 | /* Set it up... */ | |
121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
7f2cf220 | 122 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
159f9875 VS |
123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
125 | } | |
85208be0 ED |
126 | |
127 | /* enable it... */ | |
993495ae VS |
128 | fbc_ctl = I915_READ(FBC_CONTROL); |
129 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
130 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
85208be0 ED |
131 | if (IS_I945GM(dev)) |
132 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
133 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
85208be0 ED |
134 | fbc_ctl |= obj->fence_reg; |
135 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
136 | ||
5cd5410e | 137 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
84f44ce7 | 138 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
85208be0 ED |
139 | } |
140 | ||
1fa61106 | 141 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | ||
145 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
146 | } | |
147 | ||
993495ae | 148 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
149 | { |
150 | struct drm_device *dev = crtc->dev; | |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
152 | struct drm_framebuffer *fb = crtc->fb; | |
153 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
154 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
85208be0 ED |
156 | u32 dpfc_ctl; |
157 | ||
3fa2e0ee VS |
158 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
159 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
160 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
161 | else | |
162 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
85208be0 | 163 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
85208be0 | 164 | |
85208be0 ED |
165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
166 | ||
167 | /* enable it... */ | |
fe74c1a5 | 168 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
85208be0 | 169 | |
84f44ce7 | 170 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
171 | } |
172 | ||
1fa61106 | 173 | static void g4x_disable_fbc(struct drm_device *dev) |
85208be0 ED |
174 | { |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | u32 dpfc_ctl; | |
177 | ||
178 | /* Disable compression */ | |
179 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
180 | if (dpfc_ctl & DPFC_CTL_EN) { | |
181 | dpfc_ctl &= ~DPFC_CTL_EN; | |
182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
183 | ||
184 | DRM_DEBUG_KMS("disabled FBC\n"); | |
185 | } | |
186 | } | |
187 | ||
1fa61106 | 188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
189 | { |
190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
191 | ||
192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
193 | } | |
194 | ||
195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
196 | { | |
197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
198 | u32 blt_ecoskpd; | |
199 | ||
200 | /* Make sure blitter notifies FBC of writes */ | |
940aece4 D |
201 | |
202 | /* Blitter is part of Media powerwell on VLV. No impact of | |
203 | * his param in other platforms for now */ | |
204 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); | |
c8d9a590 | 205 | |
85208be0 ED |
206 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
207 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
208 | GEN6_BLITTER_LOCK_SHIFT; | |
209 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
210 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
211 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
212 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
213 | GEN6_BLITTER_LOCK_SHIFT); | |
214 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
215 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
c8d9a590 | 216 | |
940aece4 | 217 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
85208be0 ED |
218 | } |
219 | ||
993495ae | 220 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
221 | { |
222 | struct drm_device *dev = crtc->dev; | |
223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
224 | struct drm_framebuffer *fb = crtc->fb; | |
225 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
226 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
85208be0 ED |
228 | u32 dpfc_ctl; |
229 | ||
46f3dab9 | 230 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
3fa2e0ee VS |
231 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
232 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
233 | else | |
234 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
d629336b VS |
235 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
236 | if (IS_GEN5(dev)) | |
237 | dpfc_ctl |= obj->fence_reg; | |
85208be0 | 238 | |
85208be0 | 239 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
f343c5f6 | 240 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
85208be0 ED |
241 | /* enable it... */ |
242 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
243 | ||
244 | if (IS_GEN6(dev)) { | |
245 | I915_WRITE(SNB_DPFC_CTL_SA, | |
246 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
247 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
248 | sandybridge_blit_fbc_update(dev); | |
249 | } | |
250 | ||
84f44ce7 | 251 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
252 | } |
253 | ||
1fa61106 | 254 | static void ironlake_disable_fbc(struct drm_device *dev) |
85208be0 ED |
255 | { |
256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
257 | u32 dpfc_ctl; | |
258 | ||
259 | /* Disable compression */ | |
260 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
261 | if (dpfc_ctl & DPFC_CTL_EN) { | |
262 | dpfc_ctl &= ~DPFC_CTL_EN; | |
263 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
264 | ||
265 | DRM_DEBUG_KMS("disabled FBC\n"); | |
266 | } | |
267 | } | |
268 | ||
1fa61106 | 269 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
270 | { |
271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
272 | ||
273 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
274 | } | |
275 | ||
993495ae | 276 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
abe959c7 RV |
277 | { |
278 | struct drm_device *dev = crtc->dev; | |
279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
280 | struct drm_framebuffer *fb = crtc->fb; | |
281 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
282 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3fa2e0ee | 284 | u32 dpfc_ctl; |
abe959c7 | 285 | |
3fa2e0ee VS |
286 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
287 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
288 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
289 | else | |
290 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
291 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; | |
292 | ||
293 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
abe959c7 | 294 | |
891348b2 | 295 | if (IS_IVYBRIDGE(dev)) { |
7dd23ba0 | 296 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
2adb6db8 VS |
297 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
298 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
299 | ILK_FBCQ_DIS); | |
28554164 | 300 | } else { |
2adb6db8 | 301 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
8f670bb1 VS |
302 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
303 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
304 | HSW_FBCQ_DIS); | |
891348b2 | 305 | } |
b74ea102 | 306 | |
abe959c7 RV |
307 | I915_WRITE(SNB_DPFC_CTL_SA, |
308 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
309 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
310 | ||
311 | sandybridge_blit_fbc_update(dev); | |
312 | ||
b19870ee | 313 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
abe959c7 RV |
314 | } |
315 | ||
85208be0 ED |
316 | bool intel_fbc_enabled(struct drm_device *dev) |
317 | { | |
318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
319 | ||
320 | if (!dev_priv->display.fbc_enabled) | |
321 | return false; | |
322 | ||
323 | return dev_priv->display.fbc_enabled(dev); | |
324 | } | |
325 | ||
326 | static void intel_fbc_work_fn(struct work_struct *__work) | |
327 | { | |
328 | struct intel_fbc_work *work = | |
329 | container_of(to_delayed_work(__work), | |
330 | struct intel_fbc_work, work); | |
331 | struct drm_device *dev = work->crtc->dev; | |
332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
333 | ||
334 | mutex_lock(&dev->struct_mutex); | |
5c3fe8b0 | 335 | if (work == dev_priv->fbc.fbc_work) { |
85208be0 ED |
336 | /* Double check that we haven't switched fb without cancelling |
337 | * the prior work. | |
338 | */ | |
339 | if (work->crtc->fb == work->fb) { | |
993495ae | 340 | dev_priv->display.enable_fbc(work->crtc); |
85208be0 | 341 | |
5c3fe8b0 BW |
342 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
343 | dev_priv->fbc.fb_id = work->crtc->fb->base.id; | |
344 | dev_priv->fbc.y = work->crtc->y; | |
85208be0 ED |
345 | } |
346 | ||
5c3fe8b0 | 347 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
348 | } |
349 | mutex_unlock(&dev->struct_mutex); | |
350 | ||
351 | kfree(work); | |
352 | } | |
353 | ||
354 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
355 | { | |
5c3fe8b0 | 356 | if (dev_priv->fbc.fbc_work == NULL) |
85208be0 ED |
357 | return; |
358 | ||
359 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
360 | ||
361 | /* Synchronisation is provided by struct_mutex and checking of | |
5c3fe8b0 | 362 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
85208be0 ED |
363 | * entirely asynchronously. |
364 | */ | |
5c3fe8b0 | 365 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
85208be0 | 366 | /* tasklet was killed before being run, clean up */ |
5c3fe8b0 | 367 | kfree(dev_priv->fbc.fbc_work); |
85208be0 ED |
368 | |
369 | /* Mark the work as no longer wanted so that if it does | |
370 | * wake-up (because the work was already running and waiting | |
371 | * for our mutex), it will discover that is no longer | |
372 | * necessary to run. | |
373 | */ | |
5c3fe8b0 | 374 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
375 | } |
376 | ||
993495ae | 377 | static void intel_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
378 | { |
379 | struct intel_fbc_work *work; | |
380 | struct drm_device *dev = crtc->dev; | |
381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
382 | ||
383 | if (!dev_priv->display.enable_fbc) | |
384 | return; | |
385 | ||
386 | intel_cancel_fbc_work(dev_priv); | |
387 | ||
b14c5679 | 388 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
85208be0 | 389 | if (work == NULL) { |
6cdcb5e7 | 390 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
993495ae | 391 | dev_priv->display.enable_fbc(crtc); |
85208be0 ED |
392 | return; |
393 | } | |
394 | ||
395 | work->crtc = crtc; | |
396 | work->fb = crtc->fb; | |
85208be0 ED |
397 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
398 | ||
5c3fe8b0 | 399 | dev_priv->fbc.fbc_work = work; |
85208be0 | 400 | |
85208be0 ED |
401 | /* Delay the actual enabling to let pageflipping cease and the |
402 | * display to settle before starting the compression. Note that | |
403 | * this delay also serves a second purpose: it allows for a | |
404 | * vblank to pass after disabling the FBC before we attempt | |
405 | * to modify the control registers. | |
406 | * | |
407 | * A more complicated solution would involve tracking vblanks | |
408 | * following the termination of the page-flipping sequence | |
409 | * and indeed performing the enable as a co-routine and not | |
410 | * waiting synchronously upon the vblank. | |
7457d617 DL |
411 | * |
412 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
85208be0 ED |
413 | */ |
414 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
415 | } | |
416 | ||
417 | void intel_disable_fbc(struct drm_device *dev) | |
418 | { | |
419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
420 | ||
421 | intel_cancel_fbc_work(dev_priv); | |
422 | ||
423 | if (!dev_priv->display.disable_fbc) | |
424 | return; | |
425 | ||
426 | dev_priv->display.disable_fbc(dev); | |
5c3fe8b0 | 427 | dev_priv->fbc.plane = -1; |
85208be0 ED |
428 | } |
429 | ||
29ebf90f CW |
430 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
431 | enum no_fbc_reason reason) | |
432 | { | |
433 | if (dev_priv->fbc.no_fbc_reason == reason) | |
434 | return false; | |
435 | ||
436 | dev_priv->fbc.no_fbc_reason = reason; | |
437 | return true; | |
438 | } | |
439 | ||
85208be0 ED |
440 | /** |
441 | * intel_update_fbc - enable/disable FBC as needed | |
442 | * @dev: the drm_device | |
443 | * | |
444 | * Set up the framebuffer compression hardware at mode set time. We | |
445 | * enable it if possible: | |
446 | * - plane A only (on pre-965) | |
447 | * - no pixel mulitply/line duplication | |
448 | * - no alpha buffer discard | |
449 | * - no dual wide | |
f85da868 | 450 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
85208be0 ED |
451 | * |
452 | * We can't assume that any compression will take place (worst case), | |
453 | * so the compressed buffer has to be the same size as the uncompressed | |
454 | * one. It also must reside (along with the line length buffer) in | |
455 | * stolen memory. | |
456 | * | |
457 | * We need to enable/disable FBC on a global basis. | |
458 | */ | |
459 | void intel_update_fbc(struct drm_device *dev) | |
460 | { | |
461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
462 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
463 | struct intel_crtc *intel_crtc; | |
464 | struct drm_framebuffer *fb; | |
465 | struct intel_framebuffer *intel_fb; | |
466 | struct drm_i915_gem_object *obj; | |
ef644fda | 467 | const struct drm_display_mode *adjusted_mode; |
37327abd | 468 | unsigned int max_width, max_height; |
85208be0 | 469 | |
3a77c4c4 | 470 | if (!HAS_FBC(dev)) { |
29ebf90f | 471 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
85208be0 | 472 | return; |
29ebf90f | 473 | } |
85208be0 | 474 | |
d330a953 | 475 | if (!i915.powersave) { |
29ebf90f CW |
476 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
477 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 | 478 | return; |
29ebf90f | 479 | } |
85208be0 ED |
480 | |
481 | /* | |
482 | * If FBC is already on, we just have to verify that we can | |
483 | * keep it that way... | |
484 | * Need to disable if: | |
485 | * - more than one pipe is active | |
486 | * - changing FBC params (stride, fence, mode) | |
487 | * - new fb is too large to fit in compressed buffer | |
488 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
489 | */ | |
490 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { | |
3490ea5d | 491 | if (intel_crtc_active(tmp_crtc) && |
4c445e0e | 492 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
85208be0 | 493 | if (crtc) { |
29ebf90f CW |
494 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
495 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
85208be0 ED |
496 | goto out_disable; |
497 | } | |
498 | crtc = tmp_crtc; | |
499 | } | |
500 | } | |
501 | ||
502 | if (!crtc || crtc->fb == NULL) { | |
29ebf90f CW |
503 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
504 | DRM_DEBUG_KMS("no output, disabling\n"); | |
85208be0 ED |
505 | goto out_disable; |
506 | } | |
507 | ||
508 | intel_crtc = to_intel_crtc(crtc); | |
509 | fb = crtc->fb; | |
510 | intel_fb = to_intel_framebuffer(fb); | |
511 | obj = intel_fb->obj; | |
ef644fda | 512 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
85208be0 | 513 | |
d330a953 | 514 | if (i915.enable_fbc < 0 && |
8a5729a3 | 515 | INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { |
29ebf90f CW |
516 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
517 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
8a5729a3 | 518 | goto out_disable; |
85208be0 | 519 | } |
d330a953 | 520 | if (!i915.enable_fbc) { |
29ebf90f CW |
521 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
522 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 ED |
523 | goto out_disable; |
524 | } | |
ef644fda VS |
525 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
526 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
29ebf90f CW |
527 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
528 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
529 | "disabling\n"); | |
85208be0 ED |
530 | goto out_disable; |
531 | } | |
f85da868 PZ |
532 | |
533 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
37327abd VS |
534 | max_width = 4096; |
535 | max_height = 2048; | |
f85da868 | 536 | } else { |
37327abd VS |
537 | max_width = 2048; |
538 | max_height = 1536; | |
f85da868 | 539 | } |
37327abd VS |
540 | if (intel_crtc->config.pipe_src_w > max_width || |
541 | intel_crtc->config.pipe_src_h > max_height) { | |
29ebf90f CW |
542 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
543 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
85208be0 ED |
544 | goto out_disable; |
545 | } | |
8f94d24b | 546 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
c5a44aa0 | 547 | intel_crtc->plane != PLANE_A) { |
29ebf90f | 548 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
c5a44aa0 | 549 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
85208be0 ED |
550 | goto out_disable; |
551 | } | |
552 | ||
553 | /* The use of a CPU fence is mandatory in order to detect writes | |
554 | * by the CPU to the scanout and trigger updates to the FBC. | |
555 | */ | |
556 | if (obj->tiling_mode != I915_TILING_X || | |
557 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
29ebf90f CW |
558 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
559 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
85208be0 ED |
560 | goto out_disable; |
561 | } | |
562 | ||
563 | /* If the kernel debugger is active, always disable compression */ | |
564 | if (in_dbg_master()) | |
565 | goto out_disable; | |
566 | ||
11be49eb | 567 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
29ebf90f CW |
568 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
569 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
11be49eb CW |
570 | goto out_disable; |
571 | } | |
572 | ||
85208be0 ED |
573 | /* If the scanout has not changed, don't modify the FBC settings. |
574 | * Note that we make the fundamental assumption that the fb->obj | |
575 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
576 | * without first being decoupled from the scanout and FBC disabled. | |
577 | */ | |
5c3fe8b0 BW |
578 | if (dev_priv->fbc.plane == intel_crtc->plane && |
579 | dev_priv->fbc.fb_id == fb->base.id && | |
580 | dev_priv->fbc.y == crtc->y) | |
85208be0 ED |
581 | return; |
582 | ||
583 | if (intel_fbc_enabled(dev)) { | |
584 | /* We update FBC along two paths, after changing fb/crtc | |
585 | * configuration (modeswitching) and after page-flipping | |
586 | * finishes. For the latter, we know that not only did | |
587 | * we disable the FBC at the start of the page-flip | |
588 | * sequence, but also more than one vblank has passed. | |
589 | * | |
590 | * For the former case of modeswitching, it is possible | |
591 | * to switch between two FBC valid configurations | |
592 | * instantaneously so we do need to disable the FBC | |
593 | * before we can modify its control registers. We also | |
594 | * have to wait for the next vblank for that to take | |
595 | * effect. However, since we delay enabling FBC we can | |
596 | * assume that a vblank has passed since disabling and | |
597 | * that we can safely alter the registers in the deferred | |
598 | * callback. | |
599 | * | |
600 | * In the scenario that we go from a valid to invalid | |
601 | * and then back to valid FBC configuration we have | |
602 | * no strict enforcement that a vblank occurred since | |
603 | * disabling the FBC. However, along all current pipe | |
604 | * disabling paths we do need to wait for a vblank at | |
605 | * some point. And we wait before enabling FBC anyway. | |
606 | */ | |
607 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
608 | intel_disable_fbc(dev); | |
609 | } | |
610 | ||
993495ae | 611 | intel_enable_fbc(crtc); |
29ebf90f | 612 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
85208be0 ED |
613 | return; |
614 | ||
615 | out_disable: | |
616 | /* Multiple disables should be harmless */ | |
617 | if (intel_fbc_enabled(dev)) { | |
618 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
619 | intel_disable_fbc(dev); | |
620 | } | |
11be49eb | 621 | i915_gem_stolen_cleanup_compression(dev); |
85208be0 ED |
622 | } |
623 | ||
c921aba8 DV |
624 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
625 | { | |
626 | drm_i915_private_t *dev_priv = dev->dev_private; | |
627 | u32 tmp; | |
628 | ||
629 | tmp = I915_READ(CLKCFG); | |
630 | ||
631 | switch (tmp & CLKCFG_FSB_MASK) { | |
632 | case CLKCFG_FSB_533: | |
633 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
634 | break; | |
635 | case CLKCFG_FSB_800: | |
636 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
637 | break; | |
638 | case CLKCFG_FSB_667: | |
639 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
640 | break; | |
641 | case CLKCFG_FSB_400: | |
642 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
643 | break; | |
644 | } | |
645 | ||
646 | switch (tmp & CLKCFG_MEM_MASK) { | |
647 | case CLKCFG_MEM_533: | |
648 | dev_priv->mem_freq = 533; | |
649 | break; | |
650 | case CLKCFG_MEM_667: | |
651 | dev_priv->mem_freq = 667; | |
652 | break; | |
653 | case CLKCFG_MEM_800: | |
654 | dev_priv->mem_freq = 800; | |
655 | break; | |
656 | } | |
657 | ||
658 | /* detect pineview DDR3 setting */ | |
659 | tmp = I915_READ(CSHRDDR3CTL); | |
660 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
661 | } | |
662 | ||
663 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
664 | { | |
665 | drm_i915_private_t *dev_priv = dev->dev_private; | |
666 | u16 ddrpll, csipll; | |
667 | ||
668 | ddrpll = I915_READ16(DDRMPLL1); | |
669 | csipll = I915_READ16(CSIPLL0); | |
670 | ||
671 | switch (ddrpll & 0xff) { | |
672 | case 0xc: | |
673 | dev_priv->mem_freq = 800; | |
674 | break; | |
675 | case 0x10: | |
676 | dev_priv->mem_freq = 1066; | |
677 | break; | |
678 | case 0x14: | |
679 | dev_priv->mem_freq = 1333; | |
680 | break; | |
681 | case 0x18: | |
682 | dev_priv->mem_freq = 1600; | |
683 | break; | |
684 | default: | |
685 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
686 | ddrpll & 0xff); | |
687 | dev_priv->mem_freq = 0; | |
688 | break; | |
689 | } | |
690 | ||
20e4d407 | 691 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
692 | |
693 | switch (csipll & 0x3ff) { | |
694 | case 0x00c: | |
695 | dev_priv->fsb_freq = 3200; | |
696 | break; | |
697 | case 0x00e: | |
698 | dev_priv->fsb_freq = 3733; | |
699 | break; | |
700 | case 0x010: | |
701 | dev_priv->fsb_freq = 4266; | |
702 | break; | |
703 | case 0x012: | |
704 | dev_priv->fsb_freq = 4800; | |
705 | break; | |
706 | case 0x014: | |
707 | dev_priv->fsb_freq = 5333; | |
708 | break; | |
709 | case 0x016: | |
710 | dev_priv->fsb_freq = 5866; | |
711 | break; | |
712 | case 0x018: | |
713 | dev_priv->fsb_freq = 6400; | |
714 | break; | |
715 | default: | |
716 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
717 | csipll & 0x3ff); | |
718 | dev_priv->fsb_freq = 0; | |
719 | break; | |
720 | } | |
721 | ||
722 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 723 | dev_priv->ips.c_m = 0; |
c921aba8 | 724 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 725 | dev_priv->ips.c_m = 1; |
c921aba8 | 726 | } else { |
20e4d407 | 727 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
728 | } |
729 | } | |
730 | ||
b445e3b0 ED |
731 | static const struct cxsr_latency cxsr_latency_table[] = { |
732 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
733 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
734 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
735 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
736 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
737 | ||
738 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
739 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
740 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
741 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
742 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
743 | ||
744 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
745 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
746 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
747 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
748 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
749 | ||
750 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
751 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
752 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
753 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
754 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
755 | ||
756 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
757 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
758 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
759 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
760 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
761 | ||
762 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
763 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
764 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
765 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
766 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
767 | }; | |
768 | ||
63c62275 | 769 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
770 | int is_ddr3, |
771 | int fsb, | |
772 | int mem) | |
773 | { | |
774 | const struct cxsr_latency *latency; | |
775 | int i; | |
776 | ||
777 | if (fsb == 0 || mem == 0) | |
778 | return NULL; | |
779 | ||
780 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
781 | latency = &cxsr_latency_table[i]; | |
782 | if (is_desktop == latency->is_desktop && | |
783 | is_ddr3 == latency->is_ddr3 && | |
784 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
785 | return latency; | |
786 | } | |
787 | ||
788 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
789 | ||
790 | return NULL; | |
791 | } | |
792 | ||
1fa61106 | 793 | static void pineview_disable_cxsr(struct drm_device *dev) |
b445e3b0 ED |
794 | { |
795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
796 | ||
797 | /* deactivate cxsr */ | |
798 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); | |
799 | } | |
800 | ||
801 | /* | |
802 | * Latency for FIFO fetches is dependent on several factors: | |
803 | * - memory configuration (speed, channels) | |
804 | * - chipset | |
805 | * - current MCH state | |
806 | * It can be fairly high in some situations, so here we assume a fairly | |
807 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
808 | * set this value too high, the FIFO will fetch frequently to stay full) | |
809 | * and power consumption (set it too low to save power and we might see | |
810 | * FIFO underruns and display "flicker"). | |
811 | * | |
812 | * A value of 5us seems to be a good balance; safe for very low end | |
813 | * platforms but not overly aggressive on lower latency configs. | |
814 | */ | |
815 | static const int latency_ns = 5000; | |
816 | ||
1fa61106 | 817 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
818 | { |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | uint32_t dsparb = I915_READ(DSPARB); | |
821 | int size; | |
822 | ||
823 | size = dsparb & 0x7f; | |
824 | if (plane) | |
825 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
826 | ||
827 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
828 | plane ? "B" : "A", size); | |
829 | ||
830 | return size; | |
831 | } | |
832 | ||
feb56b93 | 833 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
834 | { |
835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
836 | uint32_t dsparb = I915_READ(DSPARB); | |
837 | int size; | |
838 | ||
839 | size = dsparb & 0x1ff; | |
840 | if (plane) | |
841 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
842 | size >>= 1; /* Convert to cachelines */ | |
843 | ||
844 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
845 | plane ? "B" : "A", size); | |
846 | ||
847 | return size; | |
848 | } | |
849 | ||
1fa61106 | 850 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
851 | { |
852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853 | uint32_t dsparb = I915_READ(DSPARB); | |
854 | int size; | |
855 | ||
856 | size = dsparb & 0x7f; | |
857 | size >>= 2; /* Convert to cachelines */ | |
858 | ||
859 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
860 | plane ? "B" : "A", | |
861 | size); | |
862 | ||
863 | return size; | |
864 | } | |
865 | ||
b445e3b0 ED |
866 | /* Pineview has different values for various configs */ |
867 | static const struct intel_watermark_params pineview_display_wm = { | |
868 | PINEVIEW_DISPLAY_FIFO, | |
869 | PINEVIEW_MAX_WM, | |
870 | PINEVIEW_DFT_WM, | |
871 | PINEVIEW_GUARD_WM, | |
872 | PINEVIEW_FIFO_LINE_SIZE | |
873 | }; | |
874 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
875 | PINEVIEW_DISPLAY_FIFO, | |
876 | PINEVIEW_MAX_WM, | |
877 | PINEVIEW_DFT_HPLLOFF_WM, | |
878 | PINEVIEW_GUARD_WM, | |
879 | PINEVIEW_FIFO_LINE_SIZE | |
880 | }; | |
881 | static const struct intel_watermark_params pineview_cursor_wm = { | |
882 | PINEVIEW_CURSOR_FIFO, | |
883 | PINEVIEW_CURSOR_MAX_WM, | |
884 | PINEVIEW_CURSOR_DFT_WM, | |
885 | PINEVIEW_CURSOR_GUARD_WM, | |
886 | PINEVIEW_FIFO_LINE_SIZE, | |
887 | }; | |
888 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
889 | PINEVIEW_CURSOR_FIFO, | |
890 | PINEVIEW_CURSOR_MAX_WM, | |
891 | PINEVIEW_CURSOR_DFT_WM, | |
892 | PINEVIEW_CURSOR_GUARD_WM, | |
893 | PINEVIEW_FIFO_LINE_SIZE | |
894 | }; | |
895 | static const struct intel_watermark_params g4x_wm_info = { | |
896 | G4X_FIFO_SIZE, | |
897 | G4X_MAX_WM, | |
898 | G4X_MAX_WM, | |
899 | 2, | |
900 | G4X_FIFO_LINE_SIZE, | |
901 | }; | |
902 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
903 | I965_CURSOR_FIFO, | |
904 | I965_CURSOR_MAX_WM, | |
905 | I965_CURSOR_DFT_WM, | |
906 | 2, | |
907 | G4X_FIFO_LINE_SIZE, | |
908 | }; | |
909 | static const struct intel_watermark_params valleyview_wm_info = { | |
910 | VALLEYVIEW_FIFO_SIZE, | |
911 | VALLEYVIEW_MAX_WM, | |
912 | VALLEYVIEW_MAX_WM, | |
913 | 2, | |
914 | G4X_FIFO_LINE_SIZE, | |
915 | }; | |
916 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
917 | I965_CURSOR_FIFO, | |
918 | VALLEYVIEW_CURSOR_MAX_WM, | |
919 | I965_CURSOR_DFT_WM, | |
920 | 2, | |
921 | G4X_FIFO_LINE_SIZE, | |
922 | }; | |
923 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
924 | I965_CURSOR_FIFO, | |
925 | I965_CURSOR_MAX_WM, | |
926 | I965_CURSOR_DFT_WM, | |
927 | 2, | |
928 | I915_FIFO_LINE_SIZE, | |
929 | }; | |
930 | static const struct intel_watermark_params i945_wm_info = { | |
931 | I945_FIFO_SIZE, | |
932 | I915_MAX_WM, | |
933 | 1, | |
934 | 2, | |
935 | I915_FIFO_LINE_SIZE | |
936 | }; | |
937 | static const struct intel_watermark_params i915_wm_info = { | |
938 | I915_FIFO_SIZE, | |
939 | I915_MAX_WM, | |
940 | 1, | |
941 | 2, | |
942 | I915_FIFO_LINE_SIZE | |
943 | }; | |
feb56b93 | 944 | static const struct intel_watermark_params i830_wm_info = { |
b445e3b0 ED |
945 | I855GM_FIFO_SIZE, |
946 | I915_MAX_WM, | |
947 | 1, | |
948 | 2, | |
949 | I830_FIFO_LINE_SIZE | |
950 | }; | |
feb56b93 | 951 | static const struct intel_watermark_params i845_wm_info = { |
b445e3b0 ED |
952 | I830_FIFO_SIZE, |
953 | I915_MAX_WM, | |
954 | 1, | |
955 | 2, | |
956 | I830_FIFO_LINE_SIZE | |
957 | }; | |
958 | ||
b445e3b0 ED |
959 | /** |
960 | * intel_calculate_wm - calculate watermark level | |
961 | * @clock_in_khz: pixel clock | |
962 | * @wm: chip FIFO params | |
963 | * @pixel_size: display pixel size | |
964 | * @latency_ns: memory latency for the platform | |
965 | * | |
966 | * Calculate the watermark level (the level at which the display plane will | |
967 | * start fetching from memory again). Each chip has a different display | |
968 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
969 | * in the correct intel_watermark_params structure. | |
970 | * | |
971 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
972 | * on the pixel size. When it reaches the watermark level, it'll start | |
973 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
974 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
975 | * will occur, and a display engine hang could result. | |
976 | */ | |
977 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
978 | const struct intel_watermark_params *wm, | |
979 | int fifo_size, | |
980 | int pixel_size, | |
981 | unsigned long latency_ns) | |
982 | { | |
983 | long entries_required, wm_size; | |
984 | ||
985 | /* | |
986 | * Note: we need to make sure we don't overflow for various clock & | |
987 | * latency values. | |
988 | * clocks go from a few thousand to several hundred thousand. | |
989 | * latency is usually a few thousand | |
990 | */ | |
991 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
992 | 1000; | |
993 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
994 | ||
995 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
996 | ||
997 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
998 | ||
999 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
1000 | ||
1001 | /* Don't promote wm_size to unsigned... */ | |
1002 | if (wm_size > (long)wm->max_wm) | |
1003 | wm_size = wm->max_wm; | |
1004 | if (wm_size <= 0) | |
1005 | wm_size = wm->default_wm; | |
1006 | return wm_size; | |
1007 | } | |
1008 | ||
1009 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
1010 | { | |
1011 | struct drm_crtc *crtc, *enabled = NULL; | |
1012 | ||
1013 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3490ea5d | 1014 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
1015 | if (enabled) |
1016 | return NULL; | |
1017 | enabled = crtc; | |
1018 | } | |
1019 | } | |
1020 | ||
1021 | return enabled; | |
1022 | } | |
1023 | ||
46ba614c | 1024 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1025 | { |
46ba614c | 1026 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1027 | struct drm_i915_private *dev_priv = dev->dev_private; |
1028 | struct drm_crtc *crtc; | |
1029 | const struct cxsr_latency *latency; | |
1030 | u32 reg; | |
1031 | unsigned long wm; | |
1032 | ||
1033 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
1034 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
1035 | if (!latency) { | |
1036 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
1037 | pineview_disable_cxsr(dev); | |
1038 | return; | |
1039 | } | |
1040 | ||
1041 | crtc = single_enabled_crtc(dev); | |
1042 | if (crtc) { | |
241bfc38 | 1043 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 | 1044 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
241bfc38 DL |
1045 | int clock; |
1046 | ||
1047 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | |
1048 | clock = adjusted_mode->crtc_clock; | |
b445e3b0 ED |
1049 | |
1050 | /* Display SR */ | |
1051 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
1052 | pineview_display_wm.fifo_size, | |
1053 | pixel_size, latency->display_sr); | |
1054 | reg = I915_READ(DSPFW1); | |
1055 | reg &= ~DSPFW_SR_MASK; | |
1056 | reg |= wm << DSPFW_SR_SHIFT; | |
1057 | I915_WRITE(DSPFW1, reg); | |
1058 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
1059 | ||
1060 | /* cursor SR */ | |
1061 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
1062 | pineview_display_wm.fifo_size, | |
1063 | pixel_size, latency->cursor_sr); | |
1064 | reg = I915_READ(DSPFW3); | |
1065 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
1066 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
1067 | I915_WRITE(DSPFW3, reg); | |
1068 | ||
1069 | /* Display HPLL off SR */ | |
1070 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
1071 | pineview_display_hplloff_wm.fifo_size, | |
1072 | pixel_size, latency->display_hpll_disable); | |
1073 | reg = I915_READ(DSPFW3); | |
1074 | reg &= ~DSPFW_HPLL_SR_MASK; | |
1075 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
1076 | I915_WRITE(DSPFW3, reg); | |
1077 | ||
1078 | /* cursor HPLL off SR */ | |
1079 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
1080 | pineview_display_hplloff_wm.fifo_size, | |
1081 | pixel_size, latency->cursor_hpll_disable); | |
1082 | reg = I915_READ(DSPFW3); | |
1083 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
1084 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
1085 | I915_WRITE(DSPFW3, reg); | |
1086 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
1087 | ||
1088 | /* activate cxsr */ | |
1089 | I915_WRITE(DSPFW3, | |
1090 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
1091 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); | |
1092 | } else { | |
1093 | pineview_disable_cxsr(dev); | |
1094 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | static bool g4x_compute_wm0(struct drm_device *dev, | |
1099 | int plane, | |
1100 | const struct intel_watermark_params *display, | |
1101 | int display_latency_ns, | |
1102 | const struct intel_watermark_params *cursor, | |
1103 | int cursor_latency_ns, | |
1104 | int *plane_wm, | |
1105 | int *cursor_wm) | |
1106 | { | |
1107 | struct drm_crtc *crtc; | |
4fe8590a | 1108 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1109 | int htotal, hdisplay, clock, pixel_size; |
1110 | int line_time_us, line_count; | |
1111 | int entries, tlb_miss; | |
1112 | ||
1113 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1114 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
1115 | *cursor_wm = cursor->guard_size; |
1116 | *plane_wm = display->guard_size; | |
1117 | return false; | |
1118 | } | |
1119 | ||
4fe8590a | 1120 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1121 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1122 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1123 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
b445e3b0 ED |
1124 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1125 | ||
1126 | /* Use the small buffer method to calculate plane watermark */ | |
1127 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1128 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
1129 | if (tlb_miss > 0) | |
1130 | entries += tlb_miss; | |
1131 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1132 | *plane_wm = entries + display->guard_size; | |
1133 | if (*plane_wm > (int)display->max_wm) | |
1134 | *plane_wm = display->max_wm; | |
1135 | ||
1136 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 1137 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 1138 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
7bb836dd | 1139 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
b445e3b0 ED |
1140 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1141 | if (tlb_miss > 0) | |
1142 | entries += tlb_miss; | |
1143 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1144 | *cursor_wm = entries + cursor->guard_size; | |
1145 | if (*cursor_wm > (int)cursor->max_wm) | |
1146 | *cursor_wm = (int)cursor->max_wm; | |
1147 | ||
1148 | return true; | |
1149 | } | |
1150 | ||
1151 | /* | |
1152 | * Check the wm result. | |
1153 | * | |
1154 | * If any calculated watermark values is larger than the maximum value that | |
1155 | * can be programmed into the associated watermark register, that watermark | |
1156 | * must be disabled. | |
1157 | */ | |
1158 | static bool g4x_check_srwm(struct drm_device *dev, | |
1159 | int display_wm, int cursor_wm, | |
1160 | const struct intel_watermark_params *display, | |
1161 | const struct intel_watermark_params *cursor) | |
1162 | { | |
1163 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1164 | display_wm, cursor_wm); | |
1165 | ||
1166 | if (display_wm > display->max_wm) { | |
1167 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1168 | display_wm, display->max_wm); | |
1169 | return false; | |
1170 | } | |
1171 | ||
1172 | if (cursor_wm > cursor->max_wm) { | |
1173 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1174 | cursor_wm, cursor->max_wm); | |
1175 | return false; | |
1176 | } | |
1177 | ||
1178 | if (!(display_wm || cursor_wm)) { | |
1179 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1180 | return false; | |
1181 | } | |
1182 | ||
1183 | return true; | |
1184 | } | |
1185 | ||
1186 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1187 | int plane, | |
1188 | int latency_ns, | |
1189 | const struct intel_watermark_params *display, | |
1190 | const struct intel_watermark_params *cursor, | |
1191 | int *display_wm, int *cursor_wm) | |
1192 | { | |
1193 | struct drm_crtc *crtc; | |
4fe8590a | 1194 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1195 | int hdisplay, htotal, pixel_size, clock; |
1196 | unsigned long line_time_us; | |
1197 | int line_count, line_size; | |
1198 | int small, large; | |
1199 | int entries; | |
1200 | ||
1201 | if (!latency_ns) { | |
1202 | *display_wm = *cursor_wm = 0; | |
1203 | return false; | |
1204 | } | |
1205 | ||
1206 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4fe8590a | 1207 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1208 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1209 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1210 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
b445e3b0 ED |
1211 | pixel_size = crtc->fb->bits_per_pixel / 8; |
1212 | ||
922044c9 | 1213 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1214 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1215 | line_size = hdisplay * pixel_size; | |
1216 | ||
1217 | /* Use the minimum of the small and large buffer method for primary */ | |
1218 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1219 | large = line_count * line_size; | |
1220 | ||
1221 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1222 | *display_wm = entries + display->guard_size; | |
1223 | ||
1224 | /* calculate the self-refresh watermark for display cursor */ | |
7bb836dd | 1225 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1226 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1227 | *cursor_wm = entries + cursor->guard_size; | |
1228 | ||
1229 | return g4x_check_srwm(dev, | |
1230 | *display_wm, *cursor_wm, | |
1231 | display, cursor); | |
1232 | } | |
1233 | ||
1234 | static bool vlv_compute_drain_latency(struct drm_device *dev, | |
1235 | int plane, | |
1236 | int *plane_prec_mult, | |
1237 | int *plane_dl, | |
1238 | int *cursor_prec_mult, | |
1239 | int *cursor_dl) | |
1240 | { | |
1241 | struct drm_crtc *crtc; | |
1242 | int clock, pixel_size; | |
1243 | int entries; | |
1244 | ||
1245 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1246 | if (!intel_crtc_active(crtc)) |
b445e3b0 ED |
1247 | return false; |
1248 | ||
241bfc38 | 1249 | clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
b445e3b0 ED |
1250 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ |
1251 | ||
1252 | entries = (clock / 1000) * pixel_size; | |
1253 | *plane_prec_mult = (entries > 256) ? | |
1254 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1255 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * | |
1256 | pixel_size); | |
1257 | ||
1258 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ | |
1259 | *cursor_prec_mult = (entries > 256) ? | |
1260 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1261 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); | |
1262 | ||
1263 | return true; | |
1264 | } | |
1265 | ||
1266 | /* | |
1267 | * Update drain latency registers of memory arbiter | |
1268 | * | |
1269 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1270 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1271 | * latency value. | |
1272 | */ | |
1273 | ||
1274 | static void vlv_update_drain_latency(struct drm_device *dev) | |
1275 | { | |
1276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1277 | int planea_prec, planea_dl, planeb_prec, planeb_dl; | |
1278 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; | |
1279 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is | |
1280 | either 16 or 32 */ | |
1281 | ||
1282 | /* For plane A, Cursor A */ | |
1283 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, | |
1284 | &cursor_prec_mult, &cursora_dl)) { | |
1285 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1286 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; | |
1287 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1288 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; | |
1289 | ||
1290 | I915_WRITE(VLV_DDL1, cursora_prec | | |
1291 | (cursora_dl << DDL_CURSORA_SHIFT) | | |
1292 | planea_prec | planea_dl); | |
1293 | } | |
1294 | ||
1295 | /* For plane B, Cursor B */ | |
1296 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, | |
1297 | &cursor_prec_mult, &cursorb_dl)) { | |
1298 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1299 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; | |
1300 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1301 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; | |
1302 | ||
1303 | I915_WRITE(VLV_DDL2, cursorb_prec | | |
1304 | (cursorb_dl << DDL_CURSORB_SHIFT) | | |
1305 | planeb_prec | planeb_dl); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1310 | ||
46ba614c | 1311 | static void valleyview_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1312 | { |
46ba614c | 1313 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1314 | static const int sr_latency_ns = 12000; |
1315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1316 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1317 | int plane_sr, cursor_sr; | |
af6c4575 | 1318 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 ED |
1319 | unsigned int enabled = 0; |
1320 | ||
1321 | vlv_update_drain_latency(dev); | |
1322 | ||
51cea1f4 | 1323 | if (g4x_compute_wm0(dev, PIPE_A, |
b445e3b0 ED |
1324 | &valleyview_wm_info, latency_ns, |
1325 | &valleyview_cursor_wm_info, latency_ns, | |
1326 | &planea_wm, &cursora_wm)) | |
51cea1f4 | 1327 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1328 | |
51cea1f4 | 1329 | if (g4x_compute_wm0(dev, PIPE_B, |
b445e3b0 ED |
1330 | &valleyview_wm_info, latency_ns, |
1331 | &valleyview_cursor_wm_info, latency_ns, | |
1332 | &planeb_wm, &cursorb_wm)) | |
51cea1f4 | 1333 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1334 | |
b445e3b0 ED |
1335 | if (single_plane_enabled(enabled) && |
1336 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1337 | sr_latency_ns, | |
1338 | &valleyview_wm_info, | |
1339 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
1340 | &plane_sr, &ignore_cursor_sr) && |
1341 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1342 | 2*sr_latency_ns, | |
1343 | &valleyview_wm_info, | |
1344 | &valleyview_cursor_wm_info, | |
52bd02d8 | 1345 | &ignore_plane_sr, &cursor_sr)) { |
b445e3b0 | 1346 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
52bd02d8 | 1347 | } else { |
b445e3b0 ED |
1348 | I915_WRITE(FW_BLC_SELF_VLV, |
1349 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); | |
52bd02d8 CW |
1350 | plane_sr = cursor_sr = 0; |
1351 | } | |
b445e3b0 ED |
1352 | |
1353 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1354 | planea_wm, cursora_wm, | |
1355 | planeb_wm, cursorb_wm, | |
1356 | plane_sr, cursor_sr); | |
1357 | ||
1358 | I915_WRITE(DSPFW1, | |
1359 | (plane_sr << DSPFW_SR_SHIFT) | | |
1360 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1361 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1362 | planea_wm); | |
1363 | I915_WRITE(DSPFW2, | |
8c919b28 | 1364 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1365 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1366 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
1367 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1368 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
b445e3b0 ED |
1369 | } |
1370 | ||
46ba614c | 1371 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1372 | { |
46ba614c | 1373 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1374 | static const int sr_latency_ns = 12000; |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1376 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1377 | int plane_sr, cursor_sr; | |
1378 | unsigned int enabled = 0; | |
1379 | ||
51cea1f4 | 1380 | if (g4x_compute_wm0(dev, PIPE_A, |
b445e3b0 ED |
1381 | &g4x_wm_info, latency_ns, |
1382 | &g4x_cursor_wm_info, latency_ns, | |
1383 | &planea_wm, &cursora_wm)) | |
51cea1f4 | 1384 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1385 | |
51cea1f4 | 1386 | if (g4x_compute_wm0(dev, PIPE_B, |
b445e3b0 ED |
1387 | &g4x_wm_info, latency_ns, |
1388 | &g4x_cursor_wm_info, latency_ns, | |
1389 | &planeb_wm, &cursorb_wm)) | |
51cea1f4 | 1390 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1391 | |
b445e3b0 ED |
1392 | if (single_plane_enabled(enabled) && |
1393 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1394 | sr_latency_ns, | |
1395 | &g4x_wm_info, | |
1396 | &g4x_cursor_wm_info, | |
52bd02d8 | 1397 | &plane_sr, &cursor_sr)) { |
b445e3b0 | 1398 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
52bd02d8 | 1399 | } else { |
b445e3b0 ED |
1400 | I915_WRITE(FW_BLC_SELF, |
1401 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
52bd02d8 CW |
1402 | plane_sr = cursor_sr = 0; |
1403 | } | |
b445e3b0 ED |
1404 | |
1405 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1406 | planea_wm, cursora_wm, | |
1407 | planeb_wm, cursorb_wm, | |
1408 | plane_sr, cursor_sr); | |
1409 | ||
1410 | I915_WRITE(DSPFW1, | |
1411 | (plane_sr << DSPFW_SR_SHIFT) | | |
1412 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1413 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1414 | planea_wm); | |
1415 | I915_WRITE(DSPFW2, | |
8c919b28 | 1416 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1417 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1418 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1419 | I915_WRITE(DSPFW3, | |
8c919b28 | 1420 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 ED |
1421 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1422 | } | |
1423 | ||
46ba614c | 1424 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1425 | { |
46ba614c | 1426 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1427 | struct drm_i915_private *dev_priv = dev->dev_private; |
1428 | struct drm_crtc *crtc; | |
1429 | int srwm = 1; | |
1430 | int cursor_sr = 16; | |
1431 | ||
1432 | /* Calc sr entries for one plane configs */ | |
1433 | crtc = single_enabled_crtc(dev); | |
1434 | if (crtc) { | |
1435 | /* self-refresh has much higher latency */ | |
1436 | static const int sr_latency_ns = 12000; | |
4fe8590a VS |
1437 | const struct drm_display_mode *adjusted_mode = |
1438 | &to_intel_crtc(crtc)->config.adjusted_mode; | |
241bfc38 | 1439 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1440 | int htotal = adjusted_mode->crtc_htotal; |
37327abd | 1441 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
b445e3b0 ED |
1442 | int pixel_size = crtc->fb->bits_per_pixel / 8; |
1443 | unsigned long line_time_us; | |
1444 | int entries; | |
1445 | ||
922044c9 | 1446 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1447 | |
1448 | /* Use ns/us then divide to preserve precision */ | |
1449 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1450 | pixel_size * hdisplay; | |
1451 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1452 | srwm = I965_FIFO_SIZE - entries; | |
1453 | if (srwm < 0) | |
1454 | srwm = 1; | |
1455 | srwm &= 0x1ff; | |
1456 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1457 | entries, srwm); | |
1458 | ||
1459 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
7bb836dd | 1460 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1461 | entries = DIV_ROUND_UP(entries, |
1462 | i965_cursor_wm_info.cacheline_size); | |
1463 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1464 | (entries + i965_cursor_wm_info.guard_size); | |
1465 | ||
1466 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1467 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1468 | ||
1469 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1470 | "cursor %d\n", srwm, cursor_sr); | |
1471 | ||
1472 | if (IS_CRESTLINE(dev)) | |
1473 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
1474 | } else { | |
1475 | /* Turn off self refresh if both pipes are enabled */ | |
1476 | if (IS_CRESTLINE(dev)) | |
1477 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
1478 | & ~FW_BLC_SELF_EN); | |
1479 | } | |
1480 | ||
1481 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1482 | srwm); | |
1483 | ||
1484 | /* 965 has limitations... */ | |
1485 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
1486 | (8 << 16) | (8 << 8) | (8 << 0)); | |
1487 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1488 | /* update cursor SR watermark */ | |
1489 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1490 | } | |
1491 | ||
46ba614c | 1492 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1493 | { |
46ba614c | 1494 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
1496 | const struct intel_watermark_params *wm_info; | |
1497 | uint32_t fwater_lo; | |
1498 | uint32_t fwater_hi; | |
1499 | int cwm, srwm = 1; | |
1500 | int fifo_size; | |
1501 | int planea_wm, planeb_wm; | |
1502 | struct drm_crtc *crtc, *enabled = NULL; | |
1503 | ||
1504 | if (IS_I945GM(dev)) | |
1505 | wm_info = &i945_wm_info; | |
1506 | else if (!IS_GEN2(dev)) | |
1507 | wm_info = &i915_wm_info; | |
1508 | else | |
feb56b93 | 1509 | wm_info = &i830_wm_info; |
b445e3b0 ED |
1510 | |
1511 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1512 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1513 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1514 | const struct drm_display_mode *adjusted_mode; |
b9e0bda3 CW |
1515 | int cpp = crtc->fb->bits_per_pixel / 8; |
1516 | if (IS_GEN2(dev)) | |
1517 | cpp = 4; | |
1518 | ||
241bfc38 DL |
1519 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1520 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1521 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1522 | latency_ns); |
1523 | enabled = crtc; | |
1524 | } else | |
1525 | planea_wm = fifo_size - wm_info->guard_size; | |
1526 | ||
1527 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1528 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1529 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1530 | const struct drm_display_mode *adjusted_mode; |
b9e0bda3 CW |
1531 | int cpp = crtc->fb->bits_per_pixel / 8; |
1532 | if (IS_GEN2(dev)) | |
1533 | cpp = 4; | |
1534 | ||
241bfc38 DL |
1535 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1536 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1537 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1538 | latency_ns); |
1539 | if (enabled == NULL) | |
1540 | enabled = crtc; | |
1541 | else | |
1542 | enabled = NULL; | |
1543 | } else | |
1544 | planeb_wm = fifo_size - wm_info->guard_size; | |
1545 | ||
1546 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1547 | ||
1548 | /* | |
1549 | * Overlay gets an aggressive default since video jitter is bad. | |
1550 | */ | |
1551 | cwm = 2; | |
1552 | ||
1553 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
1554 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1555 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
1556 | else if (IS_I915GM(dev)) | |
3f2dc5ac | 1557 | I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN)); |
b445e3b0 ED |
1558 | |
1559 | /* Calc sr entries for one plane configs */ | |
1560 | if (HAS_FW_BLC(dev) && enabled) { | |
1561 | /* self-refresh has much higher latency */ | |
1562 | static const int sr_latency_ns = 6000; | |
4fe8590a VS |
1563 | const struct drm_display_mode *adjusted_mode = |
1564 | &to_intel_crtc(enabled)->config.adjusted_mode; | |
241bfc38 | 1565 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1566 | int htotal = adjusted_mode->crtc_htotal; |
f727b490 | 1567 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
b445e3b0 ED |
1568 | int pixel_size = enabled->fb->bits_per_pixel / 8; |
1569 | unsigned long line_time_us; | |
1570 | int entries; | |
1571 | ||
922044c9 | 1572 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1573 | |
1574 | /* Use ns/us then divide to preserve precision */ | |
1575 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1576 | pixel_size * hdisplay; | |
1577 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1578 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1579 | srwm = wm_info->fifo_size - entries; | |
1580 | if (srwm < 0) | |
1581 | srwm = 1; | |
1582 | ||
1583 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1584 | I915_WRITE(FW_BLC_SELF, | |
1585 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1586 | else if (IS_I915GM(dev)) | |
1587 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1588 | } | |
1589 | ||
1590 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1591 | planea_wm, planeb_wm, cwm, srwm); | |
1592 | ||
1593 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1594 | fwater_hi = (cwm & 0x1f); | |
1595 | ||
1596 | /* Set request length to 8 cachelines per fetch */ | |
1597 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1598 | fwater_hi = fwater_hi | (1 << 8); | |
1599 | ||
1600 | I915_WRITE(FW_BLC, fwater_lo); | |
1601 | I915_WRITE(FW_BLC2, fwater_hi); | |
1602 | ||
1603 | if (HAS_FW_BLC(dev)) { | |
1604 | if (enabled) { | |
1605 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1606 | I915_WRITE(FW_BLC_SELF, | |
1607 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
1608 | else if (IS_I915GM(dev)) | |
3f2dc5ac | 1609 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN)); |
b445e3b0 ED |
1610 | DRM_DEBUG_KMS("memory self refresh enabled\n"); |
1611 | } else | |
1612 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
1613 | } | |
1614 | } | |
1615 | ||
feb56b93 | 1616 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1617 | { |
46ba614c | 1618 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1619 | struct drm_i915_private *dev_priv = dev->dev_private; |
1620 | struct drm_crtc *crtc; | |
241bfc38 | 1621 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1622 | uint32_t fwater_lo; |
1623 | int planea_wm; | |
1624 | ||
1625 | crtc = single_enabled_crtc(dev); | |
1626 | if (crtc == NULL) | |
1627 | return; | |
1628 | ||
241bfc38 DL |
1629 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1630 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
feb56b93 | 1631 | &i845_wm_info, |
b445e3b0 | 1632 | dev_priv->display.get_fifo_size(dev, 0), |
b9e0bda3 | 1633 | 4, latency_ns); |
b445e3b0 ED |
1634 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1635 | fwater_lo |= (3<<8) | planea_wm; | |
1636 | ||
1637 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1638 | ||
1639 | I915_WRITE(FW_BLC, fwater_lo); | |
1640 | } | |
1641 | ||
3658729a VS |
1642 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1643 | struct drm_crtc *crtc) | |
801bcfff PZ |
1644 | { |
1645 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1646 | uint32_t pixel_rate; |
801bcfff | 1647 | |
241bfc38 | 1648 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
801bcfff PZ |
1649 | |
1650 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1651 | * adjust the pixel_rate here. */ | |
1652 | ||
fd4daa9c | 1653 | if (intel_crtc->config.pch_pfit.enabled) { |
801bcfff | 1654 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
fd4daa9c | 1655 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
801bcfff | 1656 | |
37327abd VS |
1657 | pipe_w = intel_crtc->config.pipe_src_w; |
1658 | pipe_h = intel_crtc->config.pipe_src_h; | |
801bcfff PZ |
1659 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1660 | pfit_h = pfit_size & 0xFFFF; | |
1661 | if (pipe_w < pfit_w) | |
1662 | pipe_w = pfit_w; | |
1663 | if (pipe_h < pfit_h) | |
1664 | pipe_h = pfit_h; | |
1665 | ||
1666 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1667 | pfit_w * pfit_h); | |
1668 | } | |
1669 | ||
1670 | return pixel_rate; | |
1671 | } | |
1672 | ||
37126462 | 1673 | /* latency must be in 0.1us units. */ |
23297044 | 1674 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1675 | uint32_t latency) |
1676 | { | |
1677 | uint64_t ret; | |
1678 | ||
3312ba65 VS |
1679 | if (WARN(latency == 0, "Latency value missing\n")) |
1680 | return UINT_MAX; | |
1681 | ||
801bcfff PZ |
1682 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1683 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1684 | ||
1685 | return ret; | |
1686 | } | |
1687 | ||
37126462 | 1688 | /* latency must be in 0.1us units. */ |
23297044 | 1689 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1690 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1691 | uint32_t latency) | |
1692 | { | |
1693 | uint32_t ret; | |
1694 | ||
3312ba65 VS |
1695 | if (WARN(latency == 0, "Latency value missing\n")) |
1696 | return UINT_MAX; | |
1697 | ||
801bcfff PZ |
1698 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1699 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1700 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1701 | return ret; | |
1702 | } | |
1703 | ||
23297044 | 1704 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1705 | uint8_t bytes_per_pixel) |
1706 | { | |
1707 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1708 | } | |
1709 | ||
820c1980 | 1710 | struct ilk_pipe_wm_parameters { |
801bcfff | 1711 | bool active; |
801bcfff PZ |
1712 | uint32_t pipe_htotal; |
1713 | uint32_t pixel_rate; | |
c35426d2 VS |
1714 | struct intel_plane_wm_parameters pri; |
1715 | struct intel_plane_wm_parameters spr; | |
1716 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1717 | }; |
1718 | ||
820c1980 | 1719 | struct ilk_wm_maximums { |
cca32e9a PZ |
1720 | uint16_t pri; |
1721 | uint16_t spr; | |
1722 | uint16_t cur; | |
1723 | uint16_t fbc; | |
1724 | }; | |
1725 | ||
240264f4 VS |
1726 | /* used in computing the new watermarks state */ |
1727 | struct intel_wm_config { | |
1728 | unsigned int num_pipes_active; | |
1729 | bool sprites_enabled; | |
1730 | bool sprites_scaled; | |
240264f4 VS |
1731 | }; |
1732 | ||
37126462 VS |
1733 | /* |
1734 | * For both WM_PIPE and WM_LP. | |
1735 | * mem_value must be in 0.1us units. | |
1736 | */ | |
820c1980 | 1737 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1738 | uint32_t mem_value, |
1739 | bool is_lp) | |
801bcfff | 1740 | { |
cca32e9a PZ |
1741 | uint32_t method1, method2; |
1742 | ||
c35426d2 | 1743 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1744 | return 0; |
1745 | ||
23297044 | 1746 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1747 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1748 | mem_value); |
1749 | ||
1750 | if (!is_lp) | |
1751 | return method1; | |
1752 | ||
23297044 | 1753 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1754 | params->pipe_htotal, |
c35426d2 VS |
1755 | params->pri.horiz_pixels, |
1756 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1757 | mem_value); |
1758 | ||
1759 | return min(method1, method2); | |
801bcfff PZ |
1760 | } |
1761 | ||
37126462 VS |
1762 | /* |
1763 | * For both WM_PIPE and WM_LP. | |
1764 | * mem_value must be in 0.1us units. | |
1765 | */ | |
820c1980 | 1766 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1767 | uint32_t mem_value) |
1768 | { | |
1769 | uint32_t method1, method2; | |
1770 | ||
c35426d2 | 1771 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1772 | return 0; |
1773 | ||
23297044 | 1774 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1775 | params->spr.bytes_per_pixel, |
801bcfff | 1776 | mem_value); |
23297044 | 1777 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1778 | params->pipe_htotal, |
c35426d2 VS |
1779 | params->spr.horiz_pixels, |
1780 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1781 | mem_value); |
1782 | return min(method1, method2); | |
1783 | } | |
1784 | ||
37126462 VS |
1785 | /* |
1786 | * For both WM_PIPE and WM_LP. | |
1787 | * mem_value must be in 0.1us units. | |
1788 | */ | |
820c1980 | 1789 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1790 | uint32_t mem_value) |
1791 | { | |
c35426d2 | 1792 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1793 | return 0; |
1794 | ||
23297044 | 1795 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1796 | params->pipe_htotal, |
c35426d2 VS |
1797 | params->cur.horiz_pixels, |
1798 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
1799 | mem_value); |
1800 | } | |
1801 | ||
cca32e9a | 1802 | /* Only for WM_LP. */ |
820c1980 | 1803 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 1804 | uint32_t pri_val) |
cca32e9a | 1805 | { |
c35426d2 | 1806 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
1807 | return 0; |
1808 | ||
23297044 | 1809 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
1810 | params->pri.horiz_pixels, |
1811 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
1812 | } |
1813 | ||
158ae64f VS |
1814 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1815 | { | |
416f4727 VS |
1816 | if (INTEL_INFO(dev)->gen >= 8) |
1817 | return 3072; | |
1818 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1819 | return 768; |
1820 | else | |
1821 | return 512; | |
1822 | } | |
1823 | ||
1824 | /* Calculate the maximum primary/sprite plane watermark */ | |
1825 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1826 | int level, | |
240264f4 | 1827 | const struct intel_wm_config *config, |
158ae64f VS |
1828 | enum intel_ddb_partitioning ddb_partitioning, |
1829 | bool is_sprite) | |
1830 | { | |
1831 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
1832 | unsigned int max; | |
1833 | ||
1834 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1835 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1836 | return 0; |
1837 | ||
1838 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1839 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1840 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1841 | ||
1842 | /* | |
1843 | * For some reason the non self refresh | |
1844 | * FIFO size is only half of the self | |
1845 | * refresh FIFO size on ILK/SNB. | |
1846 | */ | |
1847 | if (INTEL_INFO(dev)->gen <= 6) | |
1848 | fifo_size /= 2; | |
1849 | } | |
1850 | ||
240264f4 | 1851 | if (config->sprites_enabled) { |
158ae64f VS |
1852 | /* level 0 is always calculated with 1:1 split */ |
1853 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1854 | if (is_sprite) | |
1855 | fifo_size *= 5; | |
1856 | fifo_size /= 6; | |
1857 | } else { | |
1858 | fifo_size /= 2; | |
1859 | } | |
1860 | } | |
1861 | ||
1862 | /* clamp to max that the registers can hold */ | |
416f4727 VS |
1863 | if (INTEL_INFO(dev)->gen >= 8) |
1864 | max = level == 0 ? 255 : 2047; | |
1865 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1866 | /* IVB/HSW primary/sprite plane watermarks */ |
1867 | max = level == 0 ? 127 : 1023; | |
1868 | else if (!is_sprite) | |
1869 | /* ILK/SNB primary plane watermarks */ | |
1870 | max = level == 0 ? 127 : 511; | |
1871 | else | |
1872 | /* ILK/SNB sprite plane watermarks */ | |
1873 | max = level == 0 ? 63 : 255; | |
1874 | ||
1875 | return min(fifo_size, max); | |
1876 | } | |
1877 | ||
1878 | /* Calculate the maximum cursor plane watermark */ | |
1879 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1880 | int level, |
1881 | const struct intel_wm_config *config) | |
158ae64f VS |
1882 | { |
1883 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1884 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1885 | return 64; |
1886 | ||
1887 | /* otherwise just report max that registers can hold */ | |
1888 | if (INTEL_INFO(dev)->gen >= 7) | |
1889 | return level == 0 ? 63 : 255; | |
1890 | else | |
1891 | return level == 0 ? 31 : 63; | |
1892 | } | |
1893 | ||
1894 | /* Calculate the maximum FBC watermark */ | |
d34ff9c6 | 1895 | static unsigned int ilk_fbc_wm_max(const struct drm_device *dev) |
158ae64f VS |
1896 | { |
1897 | /* max that registers can hold */ | |
416f4727 VS |
1898 | if (INTEL_INFO(dev)->gen >= 8) |
1899 | return 31; | |
1900 | else | |
1901 | return 15; | |
158ae64f VS |
1902 | } |
1903 | ||
d34ff9c6 | 1904 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1905 | int level, |
1906 | const struct intel_wm_config *config, | |
1907 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1908 | struct ilk_wm_maximums *max) |
158ae64f | 1909 | { |
240264f4 VS |
1910 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1911 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1912 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
416f4727 | 1913 | max->fbc = ilk_fbc_wm_max(dev); |
158ae64f VS |
1914 | } |
1915 | ||
d9395655 | 1916 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1917 | const struct ilk_wm_maximums *max, |
d9395655 | 1918 | struct intel_wm_level *result) |
a9786a11 VS |
1919 | { |
1920 | bool ret; | |
1921 | ||
1922 | /* already determined to be invalid? */ | |
1923 | if (!result->enable) | |
1924 | return false; | |
1925 | ||
1926 | result->enable = result->pri_val <= max->pri && | |
1927 | result->spr_val <= max->spr && | |
1928 | result->cur_val <= max->cur; | |
1929 | ||
1930 | ret = result->enable; | |
1931 | ||
1932 | /* | |
1933 | * HACK until we can pre-compute everything, | |
1934 | * and thus fail gracefully if LP0 watermarks | |
1935 | * are exceeded... | |
1936 | */ | |
1937 | if (level == 0 && !result->enable) { | |
1938 | if (result->pri_val > max->pri) | |
1939 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1940 | level, result->pri_val, max->pri); | |
1941 | if (result->spr_val > max->spr) | |
1942 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1943 | level, result->spr_val, max->spr); | |
1944 | if (result->cur_val > max->cur) | |
1945 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1946 | level, result->cur_val, max->cur); | |
1947 | ||
1948 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1949 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1950 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1951 | result->enable = true; | |
1952 | } | |
1953 | ||
a9786a11 VS |
1954 | return ret; |
1955 | } | |
1956 | ||
d34ff9c6 | 1957 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 1958 | int level, |
820c1980 | 1959 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 1960 | struct intel_wm_level *result) |
6f5ddd17 VS |
1961 | { |
1962 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1963 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1964 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1965 | ||
1966 | /* WM1+ latency values stored in 0.5us units */ | |
1967 | if (level > 0) { | |
1968 | pri_latency *= 5; | |
1969 | spr_latency *= 5; | |
1970 | cur_latency *= 5; | |
1971 | } | |
1972 | ||
1973 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
1974 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
1975 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
1976 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
1977 | result->enable = true; | |
1978 | } | |
1979 | ||
801bcfff PZ |
1980 | static uint32_t |
1981 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
1982 | { |
1983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 1984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1011d8c4 | 1985 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
85a02deb | 1986 | u32 linetime, ips_linetime; |
1f8eeabf | 1987 | |
801bcfff PZ |
1988 | if (!intel_crtc_active(crtc)) |
1989 | return 0; | |
1011d8c4 | 1990 | |
1f8eeabf ED |
1991 | /* The WM are computed with base on how long it takes to fill a single |
1992 | * row at the given clock rate, multiplied by 8. | |
1993 | * */ | |
fec8cba3 JB |
1994 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
1995 | mode->crtc_clock); | |
1996 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 1997 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 1998 | |
801bcfff PZ |
1999 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2000 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2001 | } |
2002 | ||
12b134df VS |
2003 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2004 | { | |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2006 | ||
a42a5719 | 2007 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2008 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2009 | ||
2010 | wm[0] = (sskpd >> 56) & 0xFF; | |
2011 | if (wm[0] == 0) | |
2012 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2013 | wm[1] = (sskpd >> 4) & 0xFF; |
2014 | wm[2] = (sskpd >> 12) & 0xFF; | |
2015 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2016 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2017 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2018 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2019 | ||
2020 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2021 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2022 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2023 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2024 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2025 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2026 | ||
2027 | /* ILK primary LP0 latency is 700 ns */ | |
2028 | wm[0] = 7; | |
2029 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2030 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2031 | } |
2032 | } | |
2033 | ||
53615a5e VS |
2034 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2035 | { | |
2036 | /* ILK sprite LP0 latency is 1300 ns */ | |
2037 | if (INTEL_INFO(dev)->gen == 5) | |
2038 | wm[0] = 13; | |
2039 | } | |
2040 | ||
2041 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2042 | { | |
2043 | /* ILK cursor LP0 latency is 1300 ns */ | |
2044 | if (INTEL_INFO(dev)->gen == 5) | |
2045 | wm[0] = 13; | |
2046 | ||
2047 | /* WaDoubleCursorLP3Latency:ivb */ | |
2048 | if (IS_IVYBRIDGE(dev)) | |
2049 | wm[3] *= 2; | |
2050 | } | |
2051 | ||
ad0d6dc4 | 2052 | static int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2053 | { |
26ec971e | 2054 | /* how many WM levels are we expecting */ |
a42a5719 | 2055 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ad0d6dc4 | 2056 | return 4; |
26ec971e | 2057 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2058 | return 3; |
26ec971e | 2059 | else |
ad0d6dc4 VS |
2060 | return 2; |
2061 | } | |
2062 | ||
2063 | static void intel_print_wm_latency(struct drm_device *dev, | |
2064 | const char *name, | |
2065 | const uint16_t wm[5]) | |
2066 | { | |
2067 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2068 | |
2069 | for (level = 0; level <= max_level; level++) { | |
2070 | unsigned int latency = wm[level]; | |
2071 | ||
2072 | if (latency == 0) { | |
2073 | DRM_ERROR("%s WM%d latency not provided\n", | |
2074 | name, level); | |
2075 | continue; | |
2076 | } | |
2077 | ||
2078 | /* WM1+ latency values in 0.5us units */ | |
2079 | if (level > 0) | |
2080 | latency *= 5; | |
2081 | ||
2082 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2083 | name, level, wm[level], | |
2084 | latency / 10, latency % 10); | |
2085 | } | |
2086 | } | |
2087 | ||
fa50ad61 | 2088 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2089 | { |
2090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2091 | ||
2092 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2093 | ||
2094 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2095 | sizeof(dev_priv->wm.pri_latency)); | |
2096 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2097 | sizeof(dev_priv->wm.pri_latency)); | |
2098 | ||
2099 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2100 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2101 | |
2102 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2103 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2104 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
53615a5e VS |
2105 | } |
2106 | ||
820c1980 ID |
2107 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2108 | struct ilk_pipe_wm_parameters *p, | |
a485bfb8 | 2109 | struct intel_wm_config *config) |
1011d8c4 | 2110 | { |
7c4a395f VS |
2111 | struct drm_device *dev = crtc->dev; |
2112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2113 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2114 | struct drm_plane *plane; |
1011d8c4 | 2115 | |
7c4a395f VS |
2116 | p->active = intel_crtc_active(crtc); |
2117 | if (p->active) { | |
576b259e | 2118 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; |
3658729a | 2119 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
c35426d2 VS |
2120 | p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8; |
2121 | p->cur.bytes_per_pixel = 4; | |
37327abd | 2122 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; |
7bb836dd | 2123 | p->cur.horiz_pixels = intel_crtc->cursor_width; |
c35426d2 VS |
2124 | /* TODO: for now, assume primary and cursor planes are always enabled. */ |
2125 | p->pri.enabled = true; | |
2126 | p->cur.enabled = true; | |
801bcfff PZ |
2127 | } |
2128 | ||
7c4a395f | 2129 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
a485bfb8 | 2130 | config->num_pipes_active += intel_crtc_active(crtc); |
7c4a395f | 2131 | |
801bcfff PZ |
2132 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { |
2133 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
801bcfff | 2134 | |
7c4a395f VS |
2135 | if (intel_plane->pipe == pipe) |
2136 | p->spr = intel_plane->wm; | |
cca32e9a | 2137 | |
a485bfb8 VS |
2138 | config->sprites_enabled |= intel_plane->wm.enabled; |
2139 | config->sprites_scaled |= intel_plane->wm.scaled; | |
cca32e9a | 2140 | } |
801bcfff PZ |
2141 | } |
2142 | ||
0b2ae6d7 VS |
2143 | /* Compute new watermarks for the pipe */ |
2144 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2145 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2146 | struct intel_pipe_wm *pipe_wm) |
2147 | { | |
2148 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2149 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2150 | int level, max_level = ilk_wm_max_level(dev); |
2151 | /* LP0 watermark maximums depend on this pipe alone */ | |
2152 | struct intel_wm_config config = { | |
2153 | .num_pipes_active = 1, | |
2154 | .sprites_enabled = params->spr.enabled, | |
2155 | .sprites_scaled = params->spr.scaled, | |
2156 | }; | |
820c1980 | 2157 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2158 | |
0b2ae6d7 | 2159 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
34982fe1 | 2160 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
0b2ae6d7 | 2161 | |
7b39a0b7 VS |
2162 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2163 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2164 | max_level = 1; | |
2165 | ||
2166 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2167 | if (params->spr.scaled) | |
2168 | max_level = 0; | |
2169 | ||
0b2ae6d7 VS |
2170 | for (level = 0; level <= max_level; level++) |
2171 | ilk_compute_wm_level(dev_priv, level, params, | |
2172 | &pipe_wm->wm[level]); | |
2173 | ||
a42a5719 | 2174 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2175 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 VS |
2176 | |
2177 | /* At least LP0 must be valid */ | |
d9395655 | 2178 | return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]); |
0b2ae6d7 VS |
2179 | } |
2180 | ||
2181 | /* | |
2182 | * Merge the watermarks from all active pipes for a specific level. | |
2183 | */ | |
2184 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2185 | int level, | |
2186 | struct intel_wm_level *ret_wm) | |
2187 | { | |
2188 | const struct intel_crtc *intel_crtc; | |
2189 | ||
2190 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { | |
2191 | const struct intel_wm_level *wm = | |
2192 | &intel_crtc->wm.active.wm[level]; | |
2193 | ||
2194 | if (!wm->enable) | |
2195 | return; | |
2196 | ||
2197 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2198 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2199 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2200 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2201 | } | |
2202 | ||
2203 | ret_wm->enable = true; | |
2204 | } | |
2205 | ||
2206 | /* | |
2207 | * Merge all low power watermarks for all active pipes. | |
2208 | */ | |
2209 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2210 | const struct intel_wm_config *config, |
820c1980 | 2211 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2212 | struct intel_pipe_wm *merged) |
2213 | { | |
2214 | int level, max_level = ilk_wm_max_level(dev); | |
2215 | ||
0ba22e26 VS |
2216 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2217 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2218 | config->num_pipes_active > 1) | |
2219 | return; | |
2220 | ||
6c8b6c28 VS |
2221 | /* ILK: FBC WM must be disabled always */ |
2222 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2223 | |
2224 | /* merge each WM1+ level */ | |
2225 | for (level = 1; level <= max_level; level++) { | |
2226 | struct intel_wm_level *wm = &merged->wm[level]; | |
2227 | ||
2228 | ilk_merge_wm_level(dev, level, wm); | |
2229 | ||
d9395655 | 2230 | if (!ilk_validate_wm_level(level, max, wm)) |
0b2ae6d7 VS |
2231 | break; |
2232 | ||
2233 | /* | |
2234 | * The spec says it is preferred to disable | |
2235 | * FBC WMs instead of disabling a WM level. | |
2236 | */ | |
2237 | if (wm->fbc_val > max->fbc) { | |
2238 | merged->fbc_wm_enabled = false; | |
2239 | wm->fbc_val = 0; | |
2240 | } | |
2241 | } | |
6c8b6c28 VS |
2242 | |
2243 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2244 | /* | |
2245 | * FIXME this is racy. FBC might get enabled later. | |
2246 | * What we should check here is whether FBC can be | |
2247 | * enabled sometime later. | |
2248 | */ | |
2249 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2250 | for (level = 2; level <= max_level; level++) { | |
2251 | struct intel_wm_level *wm = &merged->wm[level]; | |
2252 | ||
2253 | wm->enable = false; | |
2254 | } | |
2255 | } | |
0b2ae6d7 VS |
2256 | } |
2257 | ||
b380ca3c VS |
2258 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2259 | { | |
2260 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2261 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2262 | } | |
2263 | ||
a68d68ee VS |
2264 | /* The value we need to program into the WM_LPx latency field */ |
2265 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2266 | { | |
2267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2268 | ||
a42a5719 | 2269 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2270 | return 2 * level; |
2271 | else | |
2272 | return dev_priv->wm.pri_latency[level]; | |
2273 | } | |
2274 | ||
820c1980 | 2275 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2276 | const struct intel_pipe_wm *merged, |
609cedef | 2277 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2278 | struct ilk_wm_values *results) |
801bcfff | 2279 | { |
0b2ae6d7 VS |
2280 | struct intel_crtc *intel_crtc; |
2281 | int level, wm_lp; | |
cca32e9a | 2282 | |
0362c781 | 2283 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2284 | results->partitioning = partitioning; |
cca32e9a | 2285 | |
0b2ae6d7 | 2286 | /* LP1+ register values */ |
cca32e9a | 2287 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2288 | const struct intel_wm_level *r; |
801bcfff | 2289 | |
b380ca3c | 2290 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2291 | |
0362c781 | 2292 | r = &merged->wm[level]; |
0b2ae6d7 | 2293 | if (!r->enable) |
cca32e9a PZ |
2294 | break; |
2295 | ||
416f4727 | 2296 | results->wm_lp[wm_lp - 1] = WM3_LP_EN | |
a68d68ee | 2297 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2298 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2299 | r->cur_val; | |
2300 | ||
2301 | if (INTEL_INFO(dev)->gen >= 8) | |
2302 | results->wm_lp[wm_lp - 1] |= | |
2303 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2304 | else | |
2305 | results->wm_lp[wm_lp - 1] |= | |
2306 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2307 | ||
6cef2b8a VS |
2308 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2309 | WARN_ON(wm_lp != 1); | |
2310 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2311 | } else | |
2312 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2313 | } |
801bcfff | 2314 | |
0b2ae6d7 VS |
2315 | /* LP0 register values */ |
2316 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) { | |
2317 | enum pipe pipe = intel_crtc->pipe; | |
2318 | const struct intel_wm_level *r = | |
2319 | &intel_crtc->wm.active.wm[0]; | |
2320 | ||
2321 | if (WARN_ON(!r->enable)) | |
2322 | continue; | |
2323 | ||
2324 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2325 | |
0b2ae6d7 VS |
2326 | results->wm_pipe[pipe] = |
2327 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2328 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2329 | r->cur_val; | |
801bcfff PZ |
2330 | } |
2331 | } | |
2332 | ||
861f3389 PZ |
2333 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2334 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2335 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2336 | struct intel_pipe_wm *r1, |
2337 | struct intel_pipe_wm *r2) | |
861f3389 | 2338 | { |
198a1e9b VS |
2339 | int level, max_level = ilk_wm_max_level(dev); |
2340 | int level1 = 0, level2 = 0; | |
861f3389 | 2341 | |
198a1e9b VS |
2342 | for (level = 1; level <= max_level; level++) { |
2343 | if (r1->wm[level].enable) | |
2344 | level1 = level; | |
2345 | if (r2->wm[level].enable) | |
2346 | level2 = level; | |
861f3389 PZ |
2347 | } |
2348 | ||
198a1e9b VS |
2349 | if (level1 == level2) { |
2350 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2351 | return r2; |
2352 | else | |
2353 | return r1; | |
198a1e9b | 2354 | } else if (level1 > level2) { |
861f3389 PZ |
2355 | return r1; |
2356 | } else { | |
2357 | return r2; | |
2358 | } | |
2359 | } | |
2360 | ||
49a687c4 VS |
2361 | /* dirty bits used to track which watermarks need changes */ |
2362 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2363 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2364 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2365 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2366 | #define WM_DIRTY_FBC (1 << 24) | |
2367 | #define WM_DIRTY_DDB (1 << 25) | |
2368 | ||
2369 | static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, | |
820c1980 ID |
2370 | const struct ilk_wm_values *old, |
2371 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2372 | { |
2373 | unsigned int dirty = 0; | |
2374 | enum pipe pipe; | |
2375 | int wm_lp; | |
2376 | ||
2377 | for_each_pipe(pipe) { | |
2378 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { | |
2379 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2380 | /* Must disable LP1+ watermarks too */ | |
2381 | dirty |= WM_DIRTY_LP_ALL; | |
2382 | } | |
2383 | ||
2384 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2385 | dirty |= WM_DIRTY_PIPE(pipe); | |
2386 | /* Must disable LP1+ watermarks too */ | |
2387 | dirty |= WM_DIRTY_LP_ALL; | |
2388 | } | |
2389 | } | |
2390 | ||
2391 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2392 | dirty |= WM_DIRTY_FBC; | |
2393 | /* Must disable LP1+ watermarks too */ | |
2394 | dirty |= WM_DIRTY_LP_ALL; | |
2395 | } | |
2396 | ||
2397 | if (old->partitioning != new->partitioning) { | |
2398 | dirty |= WM_DIRTY_DDB; | |
2399 | /* Must disable LP1+ watermarks too */ | |
2400 | dirty |= WM_DIRTY_LP_ALL; | |
2401 | } | |
2402 | ||
2403 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2404 | if (dirty & WM_DIRTY_LP_ALL) | |
2405 | return dirty; | |
2406 | ||
2407 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2408 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2409 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2410 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2411 | break; | |
2412 | } | |
2413 | ||
2414 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2415 | for (; wm_lp <= 3; wm_lp++) | |
2416 | dirty |= WM_DIRTY_LP(wm_lp); | |
2417 | ||
2418 | return dirty; | |
2419 | } | |
2420 | ||
8553c18e VS |
2421 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2422 | unsigned int dirty) | |
801bcfff | 2423 | { |
820c1980 | 2424 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2425 | bool changed = false; |
801bcfff | 2426 | |
facd619b VS |
2427 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2428 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2429 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2430 | changed = true; |
facd619b VS |
2431 | } |
2432 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2433 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2434 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2435 | changed = true; |
facd619b VS |
2436 | } |
2437 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2438 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2439 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2440 | changed = true; |
facd619b | 2441 | } |
801bcfff | 2442 | |
facd619b VS |
2443 | /* |
2444 | * Don't touch WM1S_LP_EN here. | |
2445 | * Doing so could cause underruns. | |
2446 | */ | |
6cef2b8a | 2447 | |
8553c18e VS |
2448 | return changed; |
2449 | } | |
2450 | ||
2451 | /* | |
2452 | * The spec says we shouldn't write when we don't need, because every write | |
2453 | * causes WMs to be re-evaluated, expending some power. | |
2454 | */ | |
820c1980 ID |
2455 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2456 | struct ilk_wm_values *results) | |
8553c18e VS |
2457 | { |
2458 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2459 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2460 | unsigned int dirty; |
2461 | uint32_t val; | |
2462 | ||
2463 | dirty = ilk_compute_wm_dirty(dev, previous, results); | |
2464 | if (!dirty) | |
2465 | return; | |
2466 | ||
2467 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2468 | ||
49a687c4 | 2469 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2470 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2471 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2472 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2473 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2474 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2475 | ||
49a687c4 | 2476 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2477 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2478 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2479 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2480 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2481 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2482 | ||
49a687c4 | 2483 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2484 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2485 | val = I915_READ(WM_MISC); |
2486 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2487 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2488 | else | |
2489 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2490 | I915_WRITE(WM_MISC, val); | |
2491 | } else { | |
2492 | val = I915_READ(DISP_ARB_CTL2); | |
2493 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2494 | val &= ~DISP_DATA_PARTITION_5_6; | |
2495 | else | |
2496 | val |= DISP_DATA_PARTITION_5_6; | |
2497 | I915_WRITE(DISP_ARB_CTL2, val); | |
2498 | } | |
1011d8c4 PZ |
2499 | } |
2500 | ||
49a687c4 | 2501 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2502 | val = I915_READ(DISP_ARB_CTL); |
2503 | if (results->enable_fbc_wm) | |
2504 | val &= ~DISP_FBC_WM_DIS; | |
2505 | else | |
2506 | val |= DISP_FBC_WM_DIS; | |
2507 | I915_WRITE(DISP_ARB_CTL, val); | |
2508 | } | |
2509 | ||
954911eb ID |
2510 | if (dirty & WM_DIRTY_LP(1) && |
2511 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2512 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2513 | ||
2514 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2515 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2516 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2517 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2518 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2519 | } | |
801bcfff | 2520 | |
facd619b | 2521 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2522 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2523 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2524 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2525 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2526 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2527 | |
2528 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2529 | } |
2530 | ||
8553c18e VS |
2531 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2532 | { | |
2533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2534 | ||
2535 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2536 | } | |
2537 | ||
820c1980 | 2538 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 2539 | { |
7c4a395f | 2540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 2541 | struct drm_device *dev = crtc->dev; |
801bcfff | 2542 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
2543 | struct ilk_wm_maximums max; |
2544 | struct ilk_pipe_wm_parameters params = {}; | |
2545 | struct ilk_wm_values results = {}; | |
77c122bc | 2546 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 2547 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 2548 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 2549 | struct intel_wm_config config = {}; |
7c4a395f | 2550 | |
820c1980 | 2551 | ilk_compute_wm_parameters(crtc, ¶ms, &config); |
7c4a395f VS |
2552 | |
2553 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
2554 | ||
2555 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
2556 | return; | |
861f3389 | 2557 | |
7c4a395f | 2558 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 2559 | |
34982fe1 | 2560 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 2561 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
2562 | |
2563 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
2564 | if (INTEL_INFO(dev)->gen >= 7 && |
2565 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 2566 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 2567 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 2568 | |
820c1980 | 2569 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 2570 | } else { |
198a1e9b | 2571 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
2572 | } |
2573 | ||
198a1e9b | 2574 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 2575 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 2576 | |
820c1980 | 2577 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 2578 | |
820c1980 | 2579 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
2580 | } |
2581 | ||
820c1980 | 2582 | static void ilk_update_sprite_wm(struct drm_plane *plane, |
adf3d35e | 2583 | struct drm_crtc *crtc, |
526682e9 | 2584 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 2585 | bool enabled, bool scaled) |
526682e9 | 2586 | { |
8553c18e | 2587 | struct drm_device *dev = plane->dev; |
adf3d35e | 2588 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 2589 | |
adf3d35e VS |
2590 | intel_plane->wm.enabled = enabled; |
2591 | intel_plane->wm.scaled = scaled; | |
2592 | intel_plane->wm.horiz_pixels = sprite_width; | |
2593 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
526682e9 | 2594 | |
8553c18e VS |
2595 | /* |
2596 | * IVB workaround: must disable low power watermarks for at least | |
2597 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
2598 | * when scaling is disabled. | |
2599 | * | |
2600 | * WaCxSRDisabledForSpriteScaling:ivb | |
2601 | */ | |
2602 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
2603 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
2604 | ||
820c1980 | 2605 | ilk_update_wm(crtc); |
526682e9 PZ |
2606 | } |
2607 | ||
243e6a44 VS |
2608 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
2609 | { | |
2610 | struct drm_device *dev = crtc->dev; | |
2611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2612 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2613 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2614 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
2615 | enum pipe pipe = intel_crtc->pipe; | |
2616 | static const unsigned int wm0_pipe_reg[] = { | |
2617 | [PIPE_A] = WM0_PIPEA_ILK, | |
2618 | [PIPE_B] = WM0_PIPEB_ILK, | |
2619 | [PIPE_C] = WM0_PIPEC_IVB, | |
2620 | }; | |
2621 | ||
2622 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 2623 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2624 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 VS |
2625 | |
2626 | if (intel_crtc_active(crtc)) { | |
2627 | u32 tmp = hw->wm_pipe[pipe]; | |
2628 | ||
2629 | /* | |
2630 | * For active pipes LP0 watermark is marked as | |
2631 | * enabled, and LP1+ watermaks as disabled since | |
2632 | * we can't really reverse compute them in case | |
2633 | * multiple pipes are active. | |
2634 | */ | |
2635 | active->wm[0].enable = true; | |
2636 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
2637 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
2638 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
2639 | active->linetime = hw->wm_linetime[pipe]; | |
2640 | } else { | |
2641 | int level, max_level = ilk_wm_max_level(dev); | |
2642 | ||
2643 | /* | |
2644 | * For inactive pipes, all watermark levels | |
2645 | * should be marked as enabled but zeroed, | |
2646 | * which is what we'd compute them to. | |
2647 | */ | |
2648 | for (level = 0; level <= max_level; level++) | |
2649 | active->wm[level].enable = true; | |
2650 | } | |
2651 | } | |
2652 | ||
2653 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
2654 | { | |
2655 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2656 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2657 | struct drm_crtc *crtc; |
2658 | ||
2659 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
2660 | ilk_pipe_wm_get_hw_state(crtc); | |
2661 | ||
2662 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
2663 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
2664 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
2665 | ||
2666 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
2667 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
2668 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
2669 | ||
a42a5719 | 2670 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
2671 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
2672 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
2673 | else if (IS_IVYBRIDGE(dev)) | |
2674 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
2675 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
2676 | |
2677 | hw->enable_fbc_wm = | |
2678 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
2679 | } | |
2680 | ||
b445e3b0 ED |
2681 | /** |
2682 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
2683 | * | |
2684 | * Calculate watermark values for the various WM regs based on current mode | |
2685 | * and plane configuration. | |
2686 | * | |
2687 | * There are several cases to deal with here: | |
2688 | * - normal (i.e. non-self-refresh) | |
2689 | * - self-refresh (SR) mode | |
2690 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
2691 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
2692 | * lines), so need to account for TLB latency | |
2693 | * | |
2694 | * The normal calculation is: | |
2695 | * watermark = dotclock * bytes per pixel * latency | |
2696 | * where latency is platform & configuration dependent (we assume pessimal | |
2697 | * values here). | |
2698 | * | |
2699 | * The SR calculation is: | |
2700 | * watermark = (trunc(latency/line time)+1) * surface width * | |
2701 | * bytes per pixel | |
2702 | * where | |
2703 | * line time = htotal / dotclock | |
2704 | * surface width = hdisplay for normal plane and 64 for cursor | |
2705 | * and latency is assumed to be high, as above. | |
2706 | * | |
2707 | * The final value programmed to the register should always be rounded up, | |
2708 | * and include an extra 2 entries to account for clock crossings. | |
2709 | * | |
2710 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
2711 | * to set the non-SR watermarks to 8. | |
2712 | */ | |
46ba614c | 2713 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 2714 | { |
46ba614c | 2715 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
2716 | |
2717 | if (dev_priv->display.update_wm) | |
46ba614c | 2718 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
2719 | } |
2720 | ||
adf3d35e VS |
2721 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
2722 | struct drm_crtc *crtc, | |
4c4ff43a | 2723 | uint32_t sprite_width, int pixel_size, |
39db4a4d | 2724 | bool enabled, bool scaled) |
b445e3b0 | 2725 | { |
adf3d35e | 2726 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
2727 | |
2728 | if (dev_priv->display.update_sprite_wm) | |
adf3d35e | 2729 | dev_priv->display.update_sprite_wm(plane, crtc, sprite_width, |
39db4a4d | 2730 | pixel_size, enabled, scaled); |
b445e3b0 ED |
2731 | } |
2732 | ||
2b4e57bd ED |
2733 | static struct drm_i915_gem_object * |
2734 | intel_alloc_context_page(struct drm_device *dev) | |
2735 | { | |
2736 | struct drm_i915_gem_object *ctx; | |
2737 | int ret; | |
2738 | ||
2739 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
2740 | ||
2741 | ctx = i915_gem_alloc_object(dev, 4096); | |
2742 | if (!ctx) { | |
2743 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
2744 | return NULL; | |
2745 | } | |
2746 | ||
c69766f2 | 2747 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
2b4e57bd ED |
2748 | if (ret) { |
2749 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
2750 | goto err_unref; | |
2751 | } | |
2752 | ||
2753 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
2754 | if (ret) { | |
2755 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
2756 | goto err_unpin; | |
2757 | } | |
2758 | ||
2759 | return ctx; | |
2760 | ||
2761 | err_unpin: | |
d7f46fc4 | 2762 | i915_gem_object_ggtt_unpin(ctx); |
2b4e57bd ED |
2763 | err_unref: |
2764 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
2765 | return NULL; |
2766 | } | |
2767 | ||
9270388e DV |
2768 | /** |
2769 | * Lock protecting IPS related data structures | |
9270388e DV |
2770 | */ |
2771 | DEFINE_SPINLOCK(mchdev_lock); | |
2772 | ||
2773 | /* Global for IPS driver to get at the current i915 device. Protected by | |
2774 | * mchdev_lock. */ | |
2775 | static struct drm_i915_private *i915_mch_dev; | |
2776 | ||
2b4e57bd ED |
2777 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2778 | { | |
2779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2780 | u16 rgvswctl; | |
2781 | ||
9270388e DV |
2782 | assert_spin_locked(&mchdev_lock); |
2783 | ||
2b4e57bd ED |
2784 | rgvswctl = I915_READ16(MEMSWCTL); |
2785 | if (rgvswctl & MEMCTL_CMD_STS) { | |
2786 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
2787 | return false; /* still busy with another command */ | |
2788 | } | |
2789 | ||
2790 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
2791 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
2792 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2793 | POSTING_READ16(MEMSWCTL); | |
2794 | ||
2795 | rgvswctl |= MEMCTL_CMD_STS; | |
2796 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2797 | ||
2798 | return true; | |
2799 | } | |
2800 | ||
8090c6b9 | 2801 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
2802 | { |
2803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2804 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
2805 | u8 fmax, fmin, fstart, vstart; | |
2806 | ||
9270388e DV |
2807 | spin_lock_irq(&mchdev_lock); |
2808 | ||
2b4e57bd ED |
2809 | /* Enable temp reporting */ |
2810 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
2811 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
2812 | ||
2813 | /* 100ms RC evaluation intervals */ | |
2814 | I915_WRITE(RCUPEI, 100000); | |
2815 | I915_WRITE(RCDNEI, 100000); | |
2816 | ||
2817 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
2818 | I915_WRITE(RCBMAXAVG, 90000); | |
2819 | I915_WRITE(RCBMINAVG, 80000); | |
2820 | ||
2821 | I915_WRITE(MEMIHYST, 1); | |
2822 | ||
2823 | /* Set up min, max, and cur for interrupt handling */ | |
2824 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
2825 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
2826 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
2827 | MEMMODE_FSTART_SHIFT; | |
2828 | ||
2829 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
2830 | PXVFREQ_PX_SHIFT; | |
2831 | ||
20e4d407 DV |
2832 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2833 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 2834 | |
20e4d407 DV |
2835 | dev_priv->ips.max_delay = fstart; |
2836 | dev_priv->ips.min_delay = fmin; | |
2837 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
2838 | |
2839 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
2840 | fmax, fmin, fstart); | |
2841 | ||
2842 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
2843 | ||
2844 | /* | |
2845 | * Interrupts will be enabled in ironlake_irq_postinstall | |
2846 | */ | |
2847 | ||
2848 | I915_WRITE(VIDSTART, vstart); | |
2849 | POSTING_READ(VIDSTART); | |
2850 | ||
2851 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
2852 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
2853 | ||
9270388e | 2854 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 2855 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 2856 | mdelay(1); |
2b4e57bd ED |
2857 | |
2858 | ironlake_set_drps(dev, fstart); | |
2859 | ||
20e4d407 | 2860 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 2861 | I915_READ(0x112e0); |
20e4d407 DV |
2862 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
2863 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
2864 | getrawmonotonic(&dev_priv->ips.last_time2); | |
9270388e DV |
2865 | |
2866 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
2867 | } |
2868 | ||
8090c6b9 | 2869 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
2870 | { |
2871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
2872 | u16 rgvswctl; |
2873 | ||
2874 | spin_lock_irq(&mchdev_lock); | |
2875 | ||
2876 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
2877 | |
2878 | /* Ack interrupts, disable EFC interrupt */ | |
2879 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
2880 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
2881 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
2882 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
2883 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
2884 | ||
2885 | /* Go back to the starting frequency */ | |
20e4d407 | 2886 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 2887 | mdelay(1); |
2b4e57bd ED |
2888 | rgvswctl |= MEMCTL_CMD_STS; |
2889 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 2890 | mdelay(1); |
2b4e57bd | 2891 | |
9270388e | 2892 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
2893 | } |
2894 | ||
acbe9475 DV |
2895 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2896 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
2897 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
2898 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
2899 | */ | |
6917c7b9 | 2900 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 2901 | { |
7b9e0ae6 | 2902 | u32 limits; |
2b4e57bd | 2903 | |
20b46e59 DV |
2904 | /* Only set the down limit when we've reached the lowest level to avoid |
2905 | * getting more interrupts, otherwise leave this clear. This prevents a | |
2906 | * race in the hw when coming out of rc6: There's a tiny window where | |
2907 | * the hw runs at the minimal clock before selecting the desired | |
2908 | * frequency, if the down threshold expires in that window we will not | |
2909 | * receive a down interrupt. */ | |
b39fb297 BW |
2910 | limits = dev_priv->rps.max_freq_softlimit << 24; |
2911 | if (val <= dev_priv->rps.min_freq_softlimit) | |
2912 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
2913 | |
2914 | return limits; | |
2915 | } | |
2916 | ||
dd75fdc8 CW |
2917 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
2918 | { | |
2919 | int new_power; | |
2920 | ||
2921 | new_power = dev_priv->rps.power; | |
2922 | switch (dev_priv->rps.power) { | |
2923 | case LOW_POWER: | |
b39fb297 | 2924 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
2925 | new_power = BETWEEN; |
2926 | break; | |
2927 | ||
2928 | case BETWEEN: | |
b39fb297 | 2929 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 2930 | new_power = LOW_POWER; |
b39fb297 | 2931 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
2932 | new_power = HIGH_POWER; |
2933 | break; | |
2934 | ||
2935 | case HIGH_POWER: | |
b39fb297 | 2936 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
2937 | new_power = BETWEEN; |
2938 | break; | |
2939 | } | |
2940 | /* Max/min bins are special */ | |
b39fb297 | 2941 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 2942 | new_power = LOW_POWER; |
b39fb297 | 2943 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
2944 | new_power = HIGH_POWER; |
2945 | if (new_power == dev_priv->rps.power) | |
2946 | return; | |
2947 | ||
2948 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
2949 | switch (new_power) { | |
2950 | case LOW_POWER: | |
2951 | /* Upclock if more than 95% busy over 16ms */ | |
2952 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
2953 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
2954 | ||
2955 | /* Downclock if less than 85% busy over 32ms */ | |
2956 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
2957 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
2958 | ||
2959 | I915_WRITE(GEN6_RP_CONTROL, | |
2960 | GEN6_RP_MEDIA_TURBO | | |
2961 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
2962 | GEN6_RP_MEDIA_IS_GFX | | |
2963 | GEN6_RP_ENABLE | | |
2964 | GEN6_RP_UP_BUSY_AVG | | |
2965 | GEN6_RP_DOWN_IDLE_AVG); | |
2966 | break; | |
2967 | ||
2968 | case BETWEEN: | |
2969 | /* Upclock if more than 90% busy over 13ms */ | |
2970 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
2971 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
2972 | ||
2973 | /* Downclock if less than 75% busy over 32ms */ | |
2974 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
2975 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
2976 | ||
2977 | I915_WRITE(GEN6_RP_CONTROL, | |
2978 | GEN6_RP_MEDIA_TURBO | | |
2979 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
2980 | GEN6_RP_MEDIA_IS_GFX | | |
2981 | GEN6_RP_ENABLE | | |
2982 | GEN6_RP_UP_BUSY_AVG | | |
2983 | GEN6_RP_DOWN_IDLE_AVG); | |
2984 | break; | |
2985 | ||
2986 | case HIGH_POWER: | |
2987 | /* Upclock if more than 85% busy over 10ms */ | |
2988 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
2989 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
2990 | ||
2991 | /* Downclock if less than 60% busy over 32ms */ | |
2992 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
2993 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
2994 | ||
2995 | I915_WRITE(GEN6_RP_CONTROL, | |
2996 | GEN6_RP_MEDIA_TURBO | | |
2997 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
2998 | GEN6_RP_MEDIA_IS_GFX | | |
2999 | GEN6_RP_ENABLE | | |
3000 | GEN6_RP_UP_BUSY_AVG | | |
3001 | GEN6_RP_DOWN_IDLE_AVG); | |
3002 | break; | |
3003 | } | |
3004 | ||
3005 | dev_priv->rps.power = new_power; | |
3006 | dev_priv->rps.last_adj = 0; | |
3007 | } | |
3008 | ||
b8a5ff8d JM |
3009 | /* gen6_set_rps is called to update the frequency request, but should also be |
3010 | * called when the range (min_delay and max_delay) is modified so that we can | |
3011 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
20b46e59 DV |
3012 | void gen6_set_rps(struct drm_device *dev, u8 val) |
3013 | { | |
3014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 3015 | |
4fc688ce | 3016 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3017 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3018 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 3019 | |
b39fb297 | 3020 | if (val == dev_priv->rps.cur_freq) { |
b8a5ff8d JM |
3021 | /* min/max delay may still have been modified so be sure to |
3022 | * write the limits value */ | |
3023 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
3024 | gen6_rps_limits(dev_priv, val)); | |
3025 | ||
7b9e0ae6 | 3026 | return; |
b8a5ff8d | 3027 | } |
7b9e0ae6 | 3028 | |
dd75fdc8 CW |
3029 | gen6_set_rps_thresholds(dev_priv, val); |
3030 | ||
92bd1bf0 RV |
3031 | if (IS_HASWELL(dev)) |
3032 | I915_WRITE(GEN6_RPNSWREQ, | |
3033 | HSW_FREQUENCY(val)); | |
3034 | else | |
3035 | I915_WRITE(GEN6_RPNSWREQ, | |
3036 | GEN6_FREQUENCY(val) | | |
3037 | GEN6_OFFSET(0) | | |
3038 | GEN6_AGGRESSIVE_TURBO); | |
7b9e0ae6 CW |
3039 | |
3040 | /* Make sure we continue to get interrupts | |
3041 | * until we hit the minimum or maximum frequencies. | |
3042 | */ | |
6917c7b9 CW |
3043 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
3044 | gen6_rps_limits(dev_priv, val)); | |
7b9e0ae6 | 3045 | |
d5570a72 BW |
3046 | POSTING_READ(GEN6_RPNSWREQ); |
3047 | ||
b39fb297 | 3048 | dev_priv->rps.cur_freq = val; |
be2cde9a DV |
3049 | |
3050 | trace_intel_gpu_freq_change(val * 50); | |
2b4e57bd ED |
3051 | } |
3052 | ||
76c3552f D |
3053 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
3054 | * | |
3055 | * * If Gfx is Idle, then | |
3056 | * 1. Mask Turbo interrupts | |
3057 | * 2. Bring up Gfx clock | |
3058 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3059 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3060 | * 5. Unmask Turbo interrupts | |
3061 | */ | |
3062 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
3063 | { | |
3064 | /* | |
3065 | * When we are idle. Drop to min voltage state. | |
3066 | */ | |
3067 | ||
b39fb297 | 3068 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
3069 | return; |
3070 | ||
3071 | /* Mask turbo interrupt so that they will not come in between */ | |
3072 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
3073 | ||
3074 | /* Bring up the Gfx clock */ | |
3075 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, | |
3076 | I915_READ(VLV_GTLC_SURVIVABILITY_REG) | | |
3077 | VLV_GFX_CLK_FORCE_ON_BIT); | |
3078 | ||
3079 | if (wait_for(((VLV_GFX_CLK_STATUS_BIT & | |
3080 | I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) { | |
3081 | DRM_ERROR("GFX_CLK_ON request timed out\n"); | |
3082 | return; | |
3083 | } | |
3084 | ||
b39fb297 | 3085 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
3086 | |
3087 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 3088 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
3089 | |
3090 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
3091 | & GENFREQSTATUS) == 0, 5)) | |
3092 | DRM_ERROR("timed out waiting for Punit\n"); | |
3093 | ||
3094 | /* Release the Gfx clock */ | |
3095 | I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, | |
3096 | I915_READ(VLV_GTLC_SURVIVABILITY_REG) & | |
3097 | ~VLV_GFX_CLK_FORCE_ON_BIT); | |
3098 | ||
3099 | /* Unmask Up interrupts */ | |
3100 | dev_priv->rps.rp_up_masked = true; | |
3101 | gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD, | |
b39fb297 | 3102 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
3103 | } |
3104 | ||
b29c19b6 CW |
3105 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
3106 | { | |
691bb717 DL |
3107 | struct drm_device *dev = dev_priv->dev; |
3108 | ||
b29c19b6 | 3109 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3110 | if (dev_priv->rps.enabled) { |
691bb717 | 3111 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 3112 | vlv_set_rps_idle(dev_priv); |
c0951f0c | 3113 | else |
b39fb297 | 3114 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c0951f0c CW |
3115 | dev_priv->rps.last_adj = 0; |
3116 | } | |
b29c19b6 CW |
3117 | mutex_unlock(&dev_priv->rps.hw_lock); |
3118 | } | |
3119 | ||
3120 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
3121 | { | |
691bb717 DL |
3122 | struct drm_device *dev = dev_priv->dev; |
3123 | ||
b29c19b6 | 3124 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3125 | if (dev_priv->rps.enabled) { |
691bb717 | 3126 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3127 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c | 3128 | else |
b39fb297 | 3129 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c CW |
3130 | dev_priv->rps.last_adj = 0; |
3131 | } | |
b29c19b6 CW |
3132 | mutex_unlock(&dev_priv->rps.hw_lock); |
3133 | } | |
3134 | ||
0a073b84 JB |
3135 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
3136 | { | |
3137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a67092a | 3138 | |
0a073b84 | 3139 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3140 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3141 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
0a073b84 | 3142 | |
73008b98 | 3143 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
b39fb297 BW |
3144 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
3145 | dev_priv->rps.cur_freq, | |
2ec3815f | 3146 | vlv_gpu_freq(dev_priv, val), val); |
0a073b84 | 3147 | |
b39fb297 | 3148 | if (val == dev_priv->rps.cur_freq) |
0a073b84 JB |
3149 | return; |
3150 | ||
ae99258f | 3151 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
0a073b84 | 3152 | |
b39fb297 | 3153 | dev_priv->rps.cur_freq = val; |
0a073b84 | 3154 | |
2ec3815f | 3155 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
3156 | } |
3157 | ||
44fc7d5c | 3158 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
2b4e57bd ED |
3159 | { |
3160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3161 | ||
2b4e57bd | 3162 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
a6706b45 D |
3163 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
3164 | ~dev_priv->pm_rps_events); | |
2b4e57bd ED |
3165 | /* Complete PM interrupt masking here doesn't race with the rps work |
3166 | * item again unmasking PM interrupts because that is using a different | |
3167 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
3168 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
3169 | ||
59cdb63d | 3170 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 | 3171 | dev_priv->rps.pm_iir = 0; |
59cdb63d | 3172 | spin_unlock_irq(&dev_priv->irq_lock); |
2b4e57bd | 3173 | |
a6706b45 | 3174 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
2b4e57bd ED |
3175 | } |
3176 | ||
44fc7d5c | 3177 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
3178 | { |
3179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3180 | ||
3181 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 3182 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
d20d4f0c | 3183 | |
44fc7d5c DV |
3184 | gen6_disable_rps_interrupts(dev); |
3185 | } | |
3186 | ||
3187 | static void valleyview_disable_rps(struct drm_device *dev) | |
3188 | { | |
3189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3190 | ||
3191 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
d20d4f0c | 3192 | |
44fc7d5c | 3193 | gen6_disable_rps_interrupts(dev); |
c9cddffc JB |
3194 | |
3195 | if (dev_priv->vlv_pctx) { | |
3196 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
3197 | dev_priv->vlv_pctx = NULL; | |
3198 | } | |
d20d4f0c JB |
3199 | } |
3200 | ||
dc39fff7 BW |
3201 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
3202 | { | |
dc39fff7 | 3203 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
1c79b42f BW |
3204 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
3205 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
3206 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
3207 | } |
3208 | ||
2b4e57bd ED |
3209 | int intel_enable_rc6(const struct drm_device *dev) |
3210 | { | |
eb4926e4 DL |
3211 | /* No RC6 before Ironlake */ |
3212 | if (INTEL_INFO(dev)->gen < 5) | |
3213 | return 0; | |
3214 | ||
456470eb | 3215 | /* Respect the kernel parameter if it is set */ |
d330a953 JN |
3216 | if (i915.enable_rc6 >= 0) |
3217 | return i915.enable_rc6; | |
2b4e57bd | 3218 | |
6567d748 CW |
3219 | /* Disable RC6 on Ironlake */ |
3220 | if (INTEL_INFO(dev)->gen == 5) | |
3221 | return 0; | |
2b4e57bd | 3222 | |
8bade1ad | 3223 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 3224 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
3225 | |
3226 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
3227 | } |
3228 | ||
44fc7d5c DV |
3229 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
3230 | { | |
3231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a9c1f90c | 3232 | u32 enabled_intrs; |
44fc7d5c DV |
3233 | |
3234 | spin_lock_irq(&dev_priv->irq_lock); | |
a0b3335a | 3235 | WARN_ON(dev_priv->rps.pm_iir); |
a6706b45 D |
3236 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
3237 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); | |
44fc7d5c | 3238 | spin_unlock_irq(&dev_priv->irq_lock); |
a9c1f90c | 3239 | |
fd547d25 | 3240 | /* only unmask PM interrupts we need. Mask all others. */ |
a6706b45 | 3241 | enabled_intrs = dev_priv->pm_rps_events; |
a9c1f90c MK |
3242 | |
3243 | /* IVB and SNB hard hangs on looping batchbuffer | |
3244 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
3245 | */ | |
3246 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) | |
3247 | enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED; | |
3248 | ||
3249 | I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs); | |
44fc7d5c DV |
3250 | } |
3251 | ||
6edee7f3 BW |
3252 | static void gen8_enable_rps(struct drm_device *dev) |
3253 | { | |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3255 | struct intel_ring_buffer *ring; | |
3256 | uint32_t rc6_mask = 0, rp_state_cap; | |
3257 | int unused; | |
3258 | ||
3259 | /* 1a: Software RC state - RC0 */ | |
3260 | I915_WRITE(GEN6_RC_STATE, 0); | |
3261 | ||
3262 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
3263 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
c8d9a590 | 3264 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3265 | |
3266 | /* 2a: Disable RC states. */ | |
3267 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3268 | ||
3269 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3270 | ||
3271 | /* 2b: Program RC6 thresholds.*/ | |
3272 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
3273 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
3274 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3275 | for_each_ring(ring, dev_priv, unused) | |
3276 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
3277 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
3278 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
3279 | ||
3280 | /* 3: Enable RC6 */ | |
3281 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
3282 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 3283 | intel_print_rc6_info(dev, rc6_mask); |
6edee7f3 | 3284 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
abbf9d2c BW |
3285 | GEN6_RC_CTL_EI_MODE(1) | |
3286 | rc6_mask); | |
6edee7f3 BW |
3287 | |
3288 | /* 4 Program defaults and thresholds for RPS*/ | |
3289 | I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ | |
3290 | I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */ | |
3291 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ | |
3292 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
3293 | ||
3294 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
3295 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
b39fb297 BW |
3296 | dev_priv->rps.max_freq_softlimit << 24 | |
3297 | dev_priv->rps.min_freq_softlimit << 16); | |
6edee7f3 BW |
3298 | |
3299 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
3300 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
3301 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
3302 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
3303 | ||
3304 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
3305 | ||
3306 | /* 5: Enable RPS */ | |
3307 | I915_WRITE(GEN6_RP_CONTROL, | |
3308 | GEN6_RP_MEDIA_TURBO | | |
3309 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3310 | GEN6_RP_MEDIA_IS_GFX | | |
3311 | GEN6_RP_ENABLE | | |
3312 | GEN6_RP_UP_BUSY_AVG | | |
3313 | GEN6_RP_DOWN_IDLE_AVG); | |
3314 | ||
3315 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
3316 | ||
3317 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); | |
3318 | ||
3319 | gen6_enable_rps_interrupts(dev); | |
3320 | ||
c8d9a590 | 3321 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3322 | } |
3323 | ||
79f5b2c7 | 3324 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 3325 | { |
79f5b2c7 | 3326 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 3327 | struct intel_ring_buffer *ring; |
2a5913a8 | 3328 | u32 rp_state_cap; |
7b9e0ae6 | 3329 | u32 gt_perf_status; |
d060c169 | 3330 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 3331 | u32 gtfifodbg; |
2b4e57bd | 3332 | int rc6_mode; |
42c0526c | 3333 | int i, ret; |
2b4e57bd | 3334 | |
4fc688ce | 3335 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 3336 | |
2b4e57bd ED |
3337 | /* Here begins a magic sequence of register writes to enable |
3338 | * auto-downclocking. | |
3339 | * | |
3340 | * Perhaps there might be some value in exposing these to | |
3341 | * userspace... | |
3342 | */ | |
3343 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
3344 | |
3345 | /* Clear the DBG now so we don't confuse earlier errors */ | |
3346 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
3347 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
3348 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
3349 | } | |
3350 | ||
c8d9a590 | 3351 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 3352 | |
7b9e0ae6 CW |
3353 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
3354 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
3355 | ||
b39fb297 | 3356 | /* All of these values are in units of 50MHz */ |
2a5913a8 | 3357 | dev_priv->rps.cur_freq = 0; |
b39fb297 | 3358 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ |
2a5913a8 BW |
3359 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
3360 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
3361 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
3362 | /* XXX: only BYT has a special efficient freq */ | |
3363 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; | |
3364 | /* hw_max = RP0 until we check for overclocking */ | |
3365 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
7b9e0ae6 | 3366 | |
dd0a1aa1 | 3367 | /* Preserve min/max settings in case of re-init */ |
b39fb297 | 3368 | if (dev_priv->rps.max_freq_softlimit == 0) |
2a5913a8 | 3369 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
dd0a1aa1 | 3370 | |
b39fb297 | 3371 | if (dev_priv->rps.min_freq_softlimit == 0) |
2a5913a8 | 3372 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
dd0a1aa1 | 3373 | |
2b4e57bd ED |
3374 | /* disable the counters and set deterministic thresholds */ |
3375 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3376 | ||
3377 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
3378 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
3379 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
3380 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
3381 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
3382 | ||
b4519513 CW |
3383 | for_each_ring(ring, dev_priv, i) |
3384 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
3385 | |
3386 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
3387 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 3388 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
3389 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
3390 | else | |
3391 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 3392 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
3393 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
3394 | ||
5a7dc92a | 3395 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
3396 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
3397 | if (rc6_mode & INTEL_RC6_ENABLE) | |
3398 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
3399 | ||
5a7dc92a ED |
3400 | /* We don't use those on Haswell */ |
3401 | if (!IS_HASWELL(dev)) { | |
3402 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
3403 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 3404 | |
5a7dc92a ED |
3405 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
3406 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
3407 | } | |
2b4e57bd | 3408 | |
dc39fff7 | 3409 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
3410 | |
3411 | I915_WRITE(GEN6_RC_CONTROL, | |
3412 | rc6_mask | | |
3413 | GEN6_RC_CTL_EI_MODE(1) | | |
3414 | GEN6_RC_CTL_HW_ENABLE); | |
3415 | ||
dd75fdc8 CW |
3416 | /* Power down if completely idle for over 50ms */ |
3417 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 3418 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 3419 | |
42c0526c | 3420 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 3421 | if (ret) |
42c0526c | 3422 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
3423 | |
3424 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
3425 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
3426 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 3427 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 3428 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 3429 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
3430 | } |
3431 | ||
dd75fdc8 | 3432 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 3433 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 3434 | |
44fc7d5c | 3435 | gen6_enable_rps_interrupts(dev); |
2b4e57bd | 3436 | |
31643d54 BW |
3437 | rc6vids = 0; |
3438 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
3439 | if (IS_GEN6(dev) && ret) { | |
3440 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
3441 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
3442 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
3443 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
3444 | rc6vids &= 0xffff00; | |
3445 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
3446 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
3447 | if (ret) | |
3448 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
3449 | } | |
3450 | ||
c8d9a590 | 3451 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
3452 | } |
3453 | ||
c67a470b | 3454 | void gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 3455 | { |
79f5b2c7 | 3456 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 3457 | int min_freq = 15; |
3ebecd07 CW |
3458 | unsigned int gpu_freq; |
3459 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 3460 | int scaling_factor = 180; |
eda79642 | 3461 | struct cpufreq_policy *policy; |
2b4e57bd | 3462 | |
4fc688ce | 3463 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 3464 | |
eda79642 BW |
3465 | policy = cpufreq_cpu_get(0); |
3466 | if (policy) { | |
3467 | max_ia_freq = policy->cpuinfo.max_freq; | |
3468 | cpufreq_cpu_put(policy); | |
3469 | } else { | |
3470 | /* | |
3471 | * Default to measured freq if none found, PCU will ensure we | |
3472 | * don't go over | |
3473 | */ | |
2b4e57bd | 3474 | max_ia_freq = tsc_khz; |
eda79642 | 3475 | } |
2b4e57bd ED |
3476 | |
3477 | /* Convert from kHz to MHz */ | |
3478 | max_ia_freq /= 1000; | |
3479 | ||
153b4b95 | 3480 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
3481 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
3482 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 3483 | |
2b4e57bd ED |
3484 | /* |
3485 | * For each potential GPU frequency, load a ring frequency we'd like | |
3486 | * to use for memory access. We do this by specifying the IA frequency | |
3487 | * the PCU should use as a reference to determine the ring frequency. | |
3488 | */ | |
b39fb297 | 3489 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
2b4e57bd | 3490 | gpu_freq--) { |
b39fb297 | 3491 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
3ebecd07 CW |
3492 | unsigned int ia_freq = 0, ring_freq = 0; |
3493 | ||
46c764d4 BW |
3494 | if (INTEL_INFO(dev)->gen >= 8) { |
3495 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
3496 | ring_freq = max(min_ring_freq, gpu_freq); | |
3497 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 3498 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
3499 | ring_freq = max(min_ring_freq, ring_freq); |
3500 | /* leave ia_freq as the default, chosen by cpufreq */ | |
3501 | } else { | |
3502 | /* On older processors, there is no separate ring | |
3503 | * clock domain, so in order to boost the bandwidth | |
3504 | * of the ring, we need to upclock the CPU (ia_freq). | |
3505 | * | |
3506 | * For GPU frequencies less than 750MHz, | |
3507 | * just use the lowest ring freq. | |
3508 | */ | |
3509 | if (gpu_freq < min_freq) | |
3510 | ia_freq = 800; | |
3511 | else | |
3512 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
3513 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
3514 | } | |
2b4e57bd | 3515 | |
42c0526c BW |
3516 | sandybridge_pcode_write(dev_priv, |
3517 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
3518 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
3519 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
3520 | gpu_freq); | |
2b4e57bd | 3521 | } |
2b4e57bd ED |
3522 | } |
3523 | ||
0a073b84 JB |
3524 | int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
3525 | { | |
3526 | u32 val, rp0; | |
3527 | ||
64936258 | 3528 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
3529 | |
3530 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
3531 | /* Clamp to max */ | |
3532 | rp0 = min_t(u32, rp0, 0xea); | |
3533 | ||
3534 | return rp0; | |
3535 | } | |
3536 | ||
3537 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
3538 | { | |
3539 | u32 val, rpe; | |
3540 | ||
64936258 | 3541 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 3542 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 3543 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
3544 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
3545 | ||
3546 | return rpe; | |
3547 | } | |
3548 | ||
3549 | int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) | |
3550 | { | |
64936258 | 3551 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
3552 | } |
3553 | ||
c9cddffc JB |
3554 | static void valleyview_setup_pctx(struct drm_device *dev) |
3555 | { | |
3556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3557 | struct drm_i915_gem_object *pctx; | |
3558 | unsigned long pctx_paddr; | |
3559 | u32 pcbr; | |
3560 | int pctx_size = 24*1024; | |
3561 | ||
17b0c1f7 ID |
3562 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
3563 | ||
c9cddffc JB |
3564 | pcbr = I915_READ(VLV_PCBR); |
3565 | if (pcbr) { | |
3566 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
3567 | int pcbr_offset; | |
3568 | ||
3569 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
3570 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
3571 | pcbr_offset, | |
190d6cd5 | 3572 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
3573 | pctx_size); |
3574 | goto out; | |
3575 | } | |
3576 | ||
3577 | /* | |
3578 | * From the Gunit register HAS: | |
3579 | * The Gfx driver is expected to program this register and ensure | |
3580 | * proper allocation within Gfx stolen memory. For example, this | |
3581 | * register should be programmed such than the PCBR range does not | |
3582 | * overlap with other ranges, such as the frame buffer, protected | |
3583 | * memory, or any other relevant ranges. | |
3584 | */ | |
3585 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
3586 | if (!pctx) { | |
3587 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
3588 | return; | |
3589 | } | |
3590 | ||
3591 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
3592 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
3593 | ||
3594 | out: | |
3595 | dev_priv->vlv_pctx = pctx; | |
3596 | } | |
3597 | ||
0a073b84 JB |
3598 | static void valleyview_enable_rps(struct drm_device *dev) |
3599 | { | |
3600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3601 | struct intel_ring_buffer *ring; | |
2a5913a8 | 3602 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
3603 | int i; |
3604 | ||
3605 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
3606 | ||
3607 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
f7d85c1e JB |
3608 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
3609 | gtfifodbg); | |
0a073b84 JB |
3610 | I915_WRITE(GTFIFODBG, gtfifodbg); |
3611 | } | |
3612 | ||
c8d9a590 D |
3613 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
3614 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
0a073b84 JB |
3615 | |
3616 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
3617 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
3618 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
3619 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
3620 | ||
3621 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
3622 | ||
3623 | I915_WRITE(GEN6_RP_CONTROL, | |
3624 | GEN6_RP_MEDIA_TURBO | | |
3625 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3626 | GEN6_RP_MEDIA_IS_GFX | | |
3627 | GEN6_RP_ENABLE | | |
3628 | GEN6_RP_UP_BUSY_AVG | | |
3629 | GEN6_RP_DOWN_IDLE_CONT); | |
3630 | ||
3631 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
3632 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
3633 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
3634 | ||
3635 | for_each_ring(ring, dev_priv, i) | |
3636 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
3637 | ||
2f0aa304 | 3638 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
3639 | |
3640 | /* allows RC6 residency counter to work */ | |
49798eb2 JB |
3641 | I915_WRITE(VLV_COUNTER_CONTROL, |
3642 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
3643 | VLV_MEDIA_RC6_COUNT_EN | | |
3644 | VLV_RENDER_RC6_COUNT_EN)); | |
a2b23fe0 | 3645 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 3646 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
3647 | |
3648 | intel_print_rc6_info(dev, rc6_mode); | |
3649 | ||
a2b23fe0 | 3650 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 3651 | |
64936258 | 3652 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
3653 | |
3654 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
3655 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
3656 | ||
b39fb297 | 3657 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 3658 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
b39fb297 BW |
3659 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
3660 | dev_priv->rps.cur_freq); | |
0a073b84 | 3661 | |
2a5913a8 BW |
3662 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
3663 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
73008b98 | 3664 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
2a5913a8 BW |
3665 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
3666 | dev_priv->rps.max_freq); | |
0a073b84 | 3667 | |
b39fb297 | 3668 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
73008b98 | 3669 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
b39fb297 BW |
3670 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
3671 | dev_priv->rps.efficient_freq); | |
0a073b84 | 3672 | |
2a5913a8 | 3673 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
73008b98 | 3674 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
2a5913a8 BW |
3675 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
3676 | dev_priv->rps.min_freq); | |
dd0a1aa1 JM |
3677 | |
3678 | /* Preserve min/max settings in case of re-init */ | |
b39fb297 | 3679 | if (dev_priv->rps.max_freq_softlimit == 0) |
2a5913a8 | 3680 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
dd0a1aa1 | 3681 | |
b39fb297 | 3682 | if (dev_priv->rps.min_freq_softlimit == 0) |
2a5913a8 | 3683 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
0a073b84 | 3684 | |
73008b98 | 3685 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
b39fb297 BW |
3686 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
3687 | dev_priv->rps.efficient_freq); | |
0a073b84 | 3688 | |
b39fb297 | 3689 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 3690 | |
27544369 D |
3691 | dev_priv->rps.rp_up_masked = false; |
3692 | dev_priv->rps.rp_down_masked = false; | |
3693 | ||
44fc7d5c | 3694 | gen6_enable_rps_interrupts(dev); |
0a073b84 | 3695 | |
c8d9a590 | 3696 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
3697 | } |
3698 | ||
930ebb46 | 3699 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
3700 | { |
3701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3702 | ||
3e373948 | 3703 | if (dev_priv->ips.renderctx) { |
d7f46fc4 | 3704 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
3e373948 DV |
3705 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
3706 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
3707 | } |
3708 | ||
3e373948 | 3709 | if (dev_priv->ips.pwrctx) { |
d7f46fc4 | 3710 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
3e373948 DV |
3711 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
3712 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
3713 | } |
3714 | } | |
3715 | ||
930ebb46 | 3716 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
3717 | { |
3718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3719 | ||
3720 | if (I915_READ(PWRCTXA)) { | |
3721 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
3722 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
3723 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
3724 | 50); | |
3725 | ||
3726 | I915_WRITE(PWRCTXA, 0); | |
3727 | POSTING_READ(PWRCTXA); | |
3728 | ||
3729 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
3730 | POSTING_READ(RSTDBYCTL); | |
3731 | } | |
2b4e57bd ED |
3732 | } |
3733 | ||
3734 | static int ironlake_setup_rc6(struct drm_device *dev) | |
3735 | { | |
3736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3737 | ||
3e373948 DV |
3738 | if (dev_priv->ips.renderctx == NULL) |
3739 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
3740 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
3741 | return -ENOMEM; |
3742 | ||
3e373948 DV |
3743 | if (dev_priv->ips.pwrctx == NULL) |
3744 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
3745 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
3746 | ironlake_teardown_rc6(dev); |
3747 | return -ENOMEM; | |
3748 | } | |
3749 | ||
3750 | return 0; | |
3751 | } | |
3752 | ||
930ebb46 | 3753 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
3754 | { |
3755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d90c952 | 3756 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
3e960501 | 3757 | bool was_interruptible; |
2b4e57bd ED |
3758 | int ret; |
3759 | ||
3760 | /* rc6 disabled by default due to repeated reports of hanging during | |
3761 | * boot and resume. | |
3762 | */ | |
3763 | if (!intel_enable_rc6(dev)) | |
3764 | return; | |
3765 | ||
79f5b2c7 DV |
3766 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
3767 | ||
2b4e57bd | 3768 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 3769 | if (ret) |
2b4e57bd | 3770 | return; |
2b4e57bd | 3771 | |
3e960501 CW |
3772 | was_interruptible = dev_priv->mm.interruptible; |
3773 | dev_priv->mm.interruptible = false; | |
3774 | ||
2b4e57bd ED |
3775 | /* |
3776 | * GPU can automatically power down the render unit if given a page | |
3777 | * to save state. | |
3778 | */ | |
6d90c952 | 3779 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
3780 | if (ret) { |
3781 | ironlake_teardown_rc6(dev); | |
3e960501 | 3782 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
3783 | return; |
3784 | } | |
3785 | ||
6d90c952 DV |
3786 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
3787 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 3788 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
6d90c952 DV |
3789 | MI_MM_SPACE_GTT | |
3790 | MI_SAVE_EXT_STATE_EN | | |
3791 | MI_RESTORE_EXT_STATE_EN | | |
3792 | MI_RESTORE_INHIBIT); | |
3793 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
3794 | intel_ring_emit(ring, MI_NOOP); | |
3795 | intel_ring_emit(ring, MI_FLUSH); | |
3796 | intel_ring_advance(ring); | |
2b4e57bd ED |
3797 | |
3798 | /* | |
3799 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
3800 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
3801 | * safe to assume that renderctx is valid | |
3802 | */ | |
3e960501 CW |
3803 | ret = intel_ring_idle(ring); |
3804 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 3805 | if (ret) { |
def27a58 | 3806 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 3807 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
3808 | return; |
3809 | } | |
3810 | ||
f343c5f6 | 3811 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
2b4e57bd | 3812 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
dc39fff7 BW |
3813 | |
3814 | intel_print_rc6_info(dev, INTEL_RC6_ENABLE); | |
2b4e57bd ED |
3815 | } |
3816 | ||
dde18883 ED |
3817 | static unsigned long intel_pxfreq(u32 vidfreq) |
3818 | { | |
3819 | unsigned long freq; | |
3820 | int div = (vidfreq & 0x3f0000) >> 16; | |
3821 | int post = (vidfreq & 0x3000) >> 12; | |
3822 | int pre = (vidfreq & 0x7); | |
3823 | ||
3824 | if (!pre) | |
3825 | return 0; | |
3826 | ||
3827 | freq = ((div * 133333) / ((1<<post) * pre)); | |
3828 | ||
3829 | return freq; | |
3830 | } | |
3831 | ||
eb48eb00 DV |
3832 | static const struct cparams { |
3833 | u16 i; | |
3834 | u16 t; | |
3835 | u16 m; | |
3836 | u16 c; | |
3837 | } cparams[] = { | |
3838 | { 1, 1333, 301, 28664 }, | |
3839 | { 1, 1066, 294, 24460 }, | |
3840 | { 1, 800, 294, 25192 }, | |
3841 | { 0, 1333, 276, 27605 }, | |
3842 | { 0, 1066, 276, 27605 }, | |
3843 | { 0, 800, 231, 23784 }, | |
3844 | }; | |
3845 | ||
f531dcb2 | 3846 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
3847 | { |
3848 | u64 total_count, diff, ret; | |
3849 | u32 count1, count2, count3, m = 0, c = 0; | |
3850 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
3851 | int i; | |
3852 | ||
02d71956 DV |
3853 | assert_spin_locked(&mchdev_lock); |
3854 | ||
20e4d407 | 3855 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
3856 | |
3857 | /* Prevent division-by-zero if we are asking too fast. | |
3858 | * Also, we don't get interesting results if we are polling | |
3859 | * faster than once in 10ms, so just return the saved value | |
3860 | * in such cases. | |
3861 | */ | |
3862 | if (diff1 <= 10) | |
20e4d407 | 3863 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
3864 | |
3865 | count1 = I915_READ(DMIEC); | |
3866 | count2 = I915_READ(DDREC); | |
3867 | count3 = I915_READ(CSIEC); | |
3868 | ||
3869 | total_count = count1 + count2 + count3; | |
3870 | ||
3871 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
3872 | if (total_count < dev_priv->ips.last_count1) { |
3873 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
3874 | diff += total_count; |
3875 | } else { | |
20e4d407 | 3876 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
3877 | } |
3878 | ||
3879 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
3880 | if (cparams[i].i == dev_priv->ips.c_m && |
3881 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
3882 | m = cparams[i].m; |
3883 | c = cparams[i].c; | |
3884 | break; | |
3885 | } | |
3886 | } | |
3887 | ||
3888 | diff = div_u64(diff, diff1); | |
3889 | ret = ((m * diff) + c); | |
3890 | ret = div_u64(ret, 10); | |
3891 | ||
20e4d407 DV |
3892 | dev_priv->ips.last_count1 = total_count; |
3893 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 3894 | |
20e4d407 | 3895 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
3896 | |
3897 | return ret; | |
3898 | } | |
3899 | ||
f531dcb2 CW |
3900 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
3901 | { | |
3d13ef2e | 3902 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
3903 | unsigned long val; |
3904 | ||
3d13ef2e | 3905 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
3906 | return 0; |
3907 | ||
3908 | spin_lock_irq(&mchdev_lock); | |
3909 | ||
3910 | val = __i915_chipset_val(dev_priv); | |
3911 | ||
3912 | spin_unlock_irq(&mchdev_lock); | |
3913 | ||
3914 | return val; | |
3915 | } | |
3916 | ||
eb48eb00 DV |
3917 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
3918 | { | |
3919 | unsigned long m, x, b; | |
3920 | u32 tsfs; | |
3921 | ||
3922 | tsfs = I915_READ(TSFS); | |
3923 | ||
3924 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
3925 | x = I915_READ8(TR1); | |
3926 | ||
3927 | b = tsfs & TSFS_INTR_MASK; | |
3928 | ||
3929 | return ((m * x) / 127) - b; | |
3930 | } | |
3931 | ||
3932 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
3933 | { | |
3d13ef2e | 3934 | struct drm_device *dev = dev_priv->dev; |
eb48eb00 DV |
3935 | static const struct v_table { |
3936 | u16 vd; /* in .1 mil */ | |
3937 | u16 vm; /* in .1 mil */ | |
3938 | } v_table[] = { | |
3939 | { 0, 0, }, | |
3940 | { 375, 0, }, | |
3941 | { 500, 0, }, | |
3942 | { 625, 0, }, | |
3943 | { 750, 0, }, | |
3944 | { 875, 0, }, | |
3945 | { 1000, 0, }, | |
3946 | { 1125, 0, }, | |
3947 | { 4125, 3000, }, | |
3948 | { 4125, 3000, }, | |
3949 | { 4125, 3000, }, | |
3950 | { 4125, 3000, }, | |
3951 | { 4125, 3000, }, | |
3952 | { 4125, 3000, }, | |
3953 | { 4125, 3000, }, | |
3954 | { 4125, 3000, }, | |
3955 | { 4125, 3000, }, | |
3956 | { 4125, 3000, }, | |
3957 | { 4125, 3000, }, | |
3958 | { 4125, 3000, }, | |
3959 | { 4125, 3000, }, | |
3960 | { 4125, 3000, }, | |
3961 | { 4125, 3000, }, | |
3962 | { 4125, 3000, }, | |
3963 | { 4125, 3000, }, | |
3964 | { 4125, 3000, }, | |
3965 | { 4125, 3000, }, | |
3966 | { 4125, 3000, }, | |
3967 | { 4125, 3000, }, | |
3968 | { 4125, 3000, }, | |
3969 | { 4125, 3000, }, | |
3970 | { 4125, 3000, }, | |
3971 | { 4250, 3125, }, | |
3972 | { 4375, 3250, }, | |
3973 | { 4500, 3375, }, | |
3974 | { 4625, 3500, }, | |
3975 | { 4750, 3625, }, | |
3976 | { 4875, 3750, }, | |
3977 | { 5000, 3875, }, | |
3978 | { 5125, 4000, }, | |
3979 | { 5250, 4125, }, | |
3980 | { 5375, 4250, }, | |
3981 | { 5500, 4375, }, | |
3982 | { 5625, 4500, }, | |
3983 | { 5750, 4625, }, | |
3984 | { 5875, 4750, }, | |
3985 | { 6000, 4875, }, | |
3986 | { 6125, 5000, }, | |
3987 | { 6250, 5125, }, | |
3988 | { 6375, 5250, }, | |
3989 | { 6500, 5375, }, | |
3990 | { 6625, 5500, }, | |
3991 | { 6750, 5625, }, | |
3992 | { 6875, 5750, }, | |
3993 | { 7000, 5875, }, | |
3994 | { 7125, 6000, }, | |
3995 | { 7250, 6125, }, | |
3996 | { 7375, 6250, }, | |
3997 | { 7500, 6375, }, | |
3998 | { 7625, 6500, }, | |
3999 | { 7750, 6625, }, | |
4000 | { 7875, 6750, }, | |
4001 | { 8000, 6875, }, | |
4002 | { 8125, 7000, }, | |
4003 | { 8250, 7125, }, | |
4004 | { 8375, 7250, }, | |
4005 | { 8500, 7375, }, | |
4006 | { 8625, 7500, }, | |
4007 | { 8750, 7625, }, | |
4008 | { 8875, 7750, }, | |
4009 | { 9000, 7875, }, | |
4010 | { 9125, 8000, }, | |
4011 | { 9250, 8125, }, | |
4012 | { 9375, 8250, }, | |
4013 | { 9500, 8375, }, | |
4014 | { 9625, 8500, }, | |
4015 | { 9750, 8625, }, | |
4016 | { 9875, 8750, }, | |
4017 | { 10000, 8875, }, | |
4018 | { 10125, 9000, }, | |
4019 | { 10250, 9125, }, | |
4020 | { 10375, 9250, }, | |
4021 | { 10500, 9375, }, | |
4022 | { 10625, 9500, }, | |
4023 | { 10750, 9625, }, | |
4024 | { 10875, 9750, }, | |
4025 | { 11000, 9875, }, | |
4026 | { 11125, 10000, }, | |
4027 | { 11250, 10125, }, | |
4028 | { 11375, 10250, }, | |
4029 | { 11500, 10375, }, | |
4030 | { 11625, 10500, }, | |
4031 | { 11750, 10625, }, | |
4032 | { 11875, 10750, }, | |
4033 | { 12000, 10875, }, | |
4034 | { 12125, 11000, }, | |
4035 | { 12250, 11125, }, | |
4036 | { 12375, 11250, }, | |
4037 | { 12500, 11375, }, | |
4038 | { 12625, 11500, }, | |
4039 | { 12750, 11625, }, | |
4040 | { 12875, 11750, }, | |
4041 | { 13000, 11875, }, | |
4042 | { 13125, 12000, }, | |
4043 | { 13250, 12125, }, | |
4044 | { 13375, 12250, }, | |
4045 | { 13500, 12375, }, | |
4046 | { 13625, 12500, }, | |
4047 | { 13750, 12625, }, | |
4048 | { 13875, 12750, }, | |
4049 | { 14000, 12875, }, | |
4050 | { 14125, 13000, }, | |
4051 | { 14250, 13125, }, | |
4052 | { 14375, 13250, }, | |
4053 | { 14500, 13375, }, | |
4054 | { 14625, 13500, }, | |
4055 | { 14750, 13625, }, | |
4056 | { 14875, 13750, }, | |
4057 | { 15000, 13875, }, | |
4058 | { 15125, 14000, }, | |
4059 | { 15250, 14125, }, | |
4060 | { 15375, 14250, }, | |
4061 | { 15500, 14375, }, | |
4062 | { 15625, 14500, }, | |
4063 | { 15750, 14625, }, | |
4064 | { 15875, 14750, }, | |
4065 | { 16000, 14875, }, | |
4066 | { 16125, 15000, }, | |
4067 | }; | |
3d13ef2e | 4068 | if (INTEL_INFO(dev)->is_mobile) |
eb48eb00 DV |
4069 | return v_table[pxvid].vm; |
4070 | else | |
4071 | return v_table[pxvid].vd; | |
4072 | } | |
4073 | ||
02d71956 | 4074 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4075 | { |
4076 | struct timespec now, diff1; | |
4077 | u64 diff; | |
4078 | unsigned long diffms; | |
4079 | u32 count; | |
4080 | ||
02d71956 | 4081 | assert_spin_locked(&mchdev_lock); |
eb48eb00 DV |
4082 | |
4083 | getrawmonotonic(&now); | |
20e4d407 | 4084 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
eb48eb00 DV |
4085 | |
4086 | /* Don't divide by 0 */ | |
4087 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
4088 | if (!diffms) | |
4089 | return; | |
4090 | ||
4091 | count = I915_READ(GFXEC); | |
4092 | ||
20e4d407 DV |
4093 | if (count < dev_priv->ips.last_count2) { |
4094 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
4095 | diff += count; |
4096 | } else { | |
20e4d407 | 4097 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
4098 | } |
4099 | ||
20e4d407 DV |
4100 | dev_priv->ips.last_count2 = count; |
4101 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
4102 | |
4103 | /* More magic constants... */ | |
4104 | diff = diff * 1181; | |
4105 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 4106 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
4107 | } |
4108 | ||
02d71956 DV |
4109 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
4110 | { | |
3d13ef2e DL |
4111 | struct drm_device *dev = dev_priv->dev; |
4112 | ||
4113 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
4114 | return; |
4115 | ||
9270388e | 4116 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
4117 | |
4118 | __i915_update_gfx_val(dev_priv); | |
4119 | ||
9270388e | 4120 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
4121 | } |
4122 | ||
f531dcb2 | 4123 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4124 | { |
4125 | unsigned long t, corr, state1, corr2, state2; | |
4126 | u32 pxvid, ext_v; | |
4127 | ||
02d71956 DV |
4128 | assert_spin_locked(&mchdev_lock); |
4129 | ||
b39fb297 | 4130 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
4131 | pxvid = (pxvid >> 24) & 0x7f; |
4132 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
4133 | ||
4134 | state1 = ext_v; | |
4135 | ||
4136 | t = i915_mch_val(dev_priv); | |
4137 | ||
4138 | /* Revel in the empirically derived constants */ | |
4139 | ||
4140 | /* Correction factor in 1/100000 units */ | |
4141 | if (t > 80) | |
4142 | corr = ((t * 2349) + 135940); | |
4143 | else if (t >= 50) | |
4144 | corr = ((t * 964) + 29317); | |
4145 | else /* < 50 */ | |
4146 | corr = ((t * 301) + 1004); | |
4147 | ||
4148 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
4149 | corr /= 100000; | |
20e4d407 | 4150 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
4151 | |
4152 | state2 = (corr2 * state1) / 10000; | |
4153 | state2 /= 100; /* convert to mW */ | |
4154 | ||
02d71956 | 4155 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 4156 | |
20e4d407 | 4157 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
4158 | } |
4159 | ||
f531dcb2 CW |
4160 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
4161 | { | |
3d13ef2e | 4162 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
4163 | unsigned long val; |
4164 | ||
3d13ef2e | 4165 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
4166 | return 0; |
4167 | ||
4168 | spin_lock_irq(&mchdev_lock); | |
4169 | ||
4170 | val = __i915_gfx_val(dev_priv); | |
4171 | ||
4172 | spin_unlock_irq(&mchdev_lock); | |
4173 | ||
4174 | return val; | |
4175 | } | |
4176 | ||
eb48eb00 DV |
4177 | /** |
4178 | * i915_read_mch_val - return value for IPS use | |
4179 | * | |
4180 | * Calculate and return a value for the IPS driver to use when deciding whether | |
4181 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
4182 | */ | |
4183 | unsigned long i915_read_mch_val(void) | |
4184 | { | |
4185 | struct drm_i915_private *dev_priv; | |
4186 | unsigned long chipset_val, graphics_val, ret = 0; | |
4187 | ||
9270388e | 4188 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4189 | if (!i915_mch_dev) |
4190 | goto out_unlock; | |
4191 | dev_priv = i915_mch_dev; | |
4192 | ||
f531dcb2 CW |
4193 | chipset_val = __i915_chipset_val(dev_priv); |
4194 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
4195 | |
4196 | ret = chipset_val + graphics_val; | |
4197 | ||
4198 | out_unlock: | |
9270388e | 4199 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4200 | |
4201 | return ret; | |
4202 | } | |
4203 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
4204 | ||
4205 | /** | |
4206 | * i915_gpu_raise - raise GPU frequency limit | |
4207 | * | |
4208 | * Raise the limit; IPS indicates we have thermal headroom. | |
4209 | */ | |
4210 | bool i915_gpu_raise(void) | |
4211 | { | |
4212 | struct drm_i915_private *dev_priv; | |
4213 | bool ret = true; | |
4214 | ||
9270388e | 4215 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4216 | if (!i915_mch_dev) { |
4217 | ret = false; | |
4218 | goto out_unlock; | |
4219 | } | |
4220 | dev_priv = i915_mch_dev; | |
4221 | ||
20e4d407 DV |
4222 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
4223 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
4224 | |
4225 | out_unlock: | |
9270388e | 4226 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4227 | |
4228 | return ret; | |
4229 | } | |
4230 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
4231 | ||
4232 | /** | |
4233 | * i915_gpu_lower - lower GPU frequency limit | |
4234 | * | |
4235 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
4236 | * frequency maximum. | |
4237 | */ | |
4238 | bool i915_gpu_lower(void) | |
4239 | { | |
4240 | struct drm_i915_private *dev_priv; | |
4241 | bool ret = true; | |
4242 | ||
9270388e | 4243 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4244 | if (!i915_mch_dev) { |
4245 | ret = false; | |
4246 | goto out_unlock; | |
4247 | } | |
4248 | dev_priv = i915_mch_dev; | |
4249 | ||
20e4d407 DV |
4250 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
4251 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
4252 | |
4253 | out_unlock: | |
9270388e | 4254 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4255 | |
4256 | return ret; | |
4257 | } | |
4258 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
4259 | ||
4260 | /** | |
4261 | * i915_gpu_busy - indicate GPU business to IPS | |
4262 | * | |
4263 | * Tell the IPS driver whether or not the GPU is busy. | |
4264 | */ | |
4265 | bool i915_gpu_busy(void) | |
4266 | { | |
4267 | struct drm_i915_private *dev_priv; | |
f047e395 | 4268 | struct intel_ring_buffer *ring; |
eb48eb00 | 4269 | bool ret = false; |
f047e395 | 4270 | int i; |
eb48eb00 | 4271 | |
9270388e | 4272 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4273 | if (!i915_mch_dev) |
4274 | goto out_unlock; | |
4275 | dev_priv = i915_mch_dev; | |
4276 | ||
f047e395 CW |
4277 | for_each_ring(ring, dev_priv, i) |
4278 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
4279 | |
4280 | out_unlock: | |
9270388e | 4281 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4282 | |
4283 | return ret; | |
4284 | } | |
4285 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
4286 | ||
4287 | /** | |
4288 | * i915_gpu_turbo_disable - disable graphics turbo | |
4289 | * | |
4290 | * Disable graphics turbo by resetting the max frequency and setting the | |
4291 | * current frequency to the default. | |
4292 | */ | |
4293 | bool i915_gpu_turbo_disable(void) | |
4294 | { | |
4295 | struct drm_i915_private *dev_priv; | |
4296 | bool ret = true; | |
4297 | ||
9270388e | 4298 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4299 | if (!i915_mch_dev) { |
4300 | ret = false; | |
4301 | goto out_unlock; | |
4302 | } | |
4303 | dev_priv = i915_mch_dev; | |
4304 | ||
20e4d407 | 4305 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 4306 | |
20e4d407 | 4307 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
4308 | ret = false; |
4309 | ||
4310 | out_unlock: | |
9270388e | 4311 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4312 | |
4313 | return ret; | |
4314 | } | |
4315 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
4316 | ||
4317 | /** | |
4318 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
4319 | * IPS got loaded first. | |
4320 | * | |
4321 | * This awkward dance is so that neither module has to depend on the | |
4322 | * other in order for IPS to do the appropriate communication of | |
4323 | * GPU turbo limits to i915. | |
4324 | */ | |
4325 | static void | |
4326 | ips_ping_for_i915_load(void) | |
4327 | { | |
4328 | void (*link)(void); | |
4329 | ||
4330 | link = symbol_get(ips_link_to_i915_driver); | |
4331 | if (link) { | |
4332 | link(); | |
4333 | symbol_put(ips_link_to_i915_driver); | |
4334 | } | |
4335 | } | |
4336 | ||
4337 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
4338 | { | |
02d71956 DV |
4339 | /* We only register the i915 ips part with intel-ips once everything is |
4340 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 4341 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 4342 | i915_mch_dev = dev_priv; |
9270388e | 4343 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4344 | |
4345 | ips_ping_for_i915_load(); | |
4346 | } | |
4347 | ||
4348 | void intel_gpu_ips_teardown(void) | |
4349 | { | |
9270388e | 4350 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 4351 | i915_mch_dev = NULL; |
9270388e | 4352 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 4353 | } |
76c3552f | 4354 | |
8090c6b9 | 4355 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
4356 | { |
4357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4358 | u32 lcfuse; | |
4359 | u8 pxw[16]; | |
4360 | int i; | |
4361 | ||
4362 | /* Disable to program */ | |
4363 | I915_WRITE(ECR, 0); | |
4364 | POSTING_READ(ECR); | |
4365 | ||
4366 | /* Program energy weights for various events */ | |
4367 | I915_WRITE(SDEW, 0x15040d00); | |
4368 | I915_WRITE(CSIEW0, 0x007f0000); | |
4369 | I915_WRITE(CSIEW1, 0x1e220004); | |
4370 | I915_WRITE(CSIEW2, 0x04000004); | |
4371 | ||
4372 | for (i = 0; i < 5; i++) | |
4373 | I915_WRITE(PEW + (i * 4), 0); | |
4374 | for (i = 0; i < 3; i++) | |
4375 | I915_WRITE(DEW + (i * 4), 0); | |
4376 | ||
4377 | /* Program P-state weights to account for frequency power adjustment */ | |
4378 | for (i = 0; i < 16; i++) { | |
4379 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
4380 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
4381 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
4382 | PXVFREQ_PX_SHIFT; | |
4383 | unsigned long val; | |
4384 | ||
4385 | val = vid * vid; | |
4386 | val *= (freq / 1000); | |
4387 | val *= 255; | |
4388 | val /= (127*127*900); | |
4389 | if (val > 0xff) | |
4390 | DRM_ERROR("bad pxval: %ld\n", val); | |
4391 | pxw[i] = val; | |
4392 | } | |
4393 | /* Render standby states get 0 weight */ | |
4394 | pxw[14] = 0; | |
4395 | pxw[15] = 0; | |
4396 | ||
4397 | for (i = 0; i < 4; i++) { | |
4398 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
4399 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
4400 | I915_WRITE(PXW + (i * 4), val); | |
4401 | } | |
4402 | ||
4403 | /* Adjust magic regs to magic values (more experimental results) */ | |
4404 | I915_WRITE(OGW0, 0); | |
4405 | I915_WRITE(OGW1, 0); | |
4406 | I915_WRITE(EG0, 0x00007f00); | |
4407 | I915_WRITE(EG1, 0x0000000e); | |
4408 | I915_WRITE(EG2, 0x000e0000); | |
4409 | I915_WRITE(EG3, 0x68000300); | |
4410 | I915_WRITE(EG4, 0x42000000); | |
4411 | I915_WRITE(EG5, 0x00140031); | |
4412 | I915_WRITE(EG6, 0); | |
4413 | I915_WRITE(EG7, 0); | |
4414 | ||
4415 | for (i = 0; i < 8; i++) | |
4416 | I915_WRITE(PXWL + (i * 4), 0); | |
4417 | ||
4418 | /* Enable PMON + select events */ | |
4419 | I915_WRITE(ECR, 0x80000019); | |
4420 | ||
4421 | lcfuse = I915_READ(LCFUSE02); | |
4422 | ||
20e4d407 | 4423 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
4424 | } |
4425 | ||
8090c6b9 DV |
4426 | void intel_disable_gt_powersave(struct drm_device *dev) |
4427 | { | |
1a01ab3b JB |
4428 | struct drm_i915_private *dev_priv = dev->dev_private; |
4429 | ||
fd0c0642 DV |
4430 | /* Interrupts should be disabled already to avoid re-arming. */ |
4431 | WARN_ON(dev->irq_enabled); | |
4432 | ||
930ebb46 | 4433 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 4434 | ironlake_disable_drps(dev); |
930ebb46 | 4435 | ironlake_disable_rc6(dev); |
0a073b84 | 4436 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b | 4437 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
250848ca | 4438 | cancel_work_sync(&dev_priv->rps.work); |
4fc688ce | 4439 | mutex_lock(&dev_priv->rps.hw_lock); |
d20d4f0c JB |
4440 | if (IS_VALLEYVIEW(dev)) |
4441 | valleyview_disable_rps(dev); | |
4442 | else | |
4443 | gen6_disable_rps(dev); | |
c0951f0c | 4444 | dev_priv->rps.enabled = false; |
4fc688ce | 4445 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 4446 | } |
8090c6b9 DV |
4447 | } |
4448 | ||
1a01ab3b JB |
4449 | static void intel_gen6_powersave_work(struct work_struct *work) |
4450 | { | |
4451 | struct drm_i915_private *dev_priv = | |
4452 | container_of(work, struct drm_i915_private, | |
4453 | rps.delayed_resume_work.work); | |
4454 | struct drm_device *dev = dev_priv->dev; | |
4455 | ||
4fc688ce | 4456 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 JB |
4457 | |
4458 | if (IS_VALLEYVIEW(dev)) { | |
4459 | valleyview_enable_rps(dev); | |
6edee7f3 BW |
4460 | } else if (IS_BROADWELL(dev)) { |
4461 | gen8_enable_rps(dev); | |
4462 | gen6_update_ring_freq(dev); | |
0a073b84 JB |
4463 | } else { |
4464 | gen6_enable_rps(dev); | |
4465 | gen6_update_ring_freq(dev); | |
4466 | } | |
c0951f0c | 4467 | dev_priv->rps.enabled = true; |
4fc688ce | 4468 | mutex_unlock(&dev_priv->rps.hw_lock); |
1a01ab3b JB |
4469 | } |
4470 | ||
8090c6b9 DV |
4471 | void intel_enable_gt_powersave(struct drm_device *dev) |
4472 | { | |
1a01ab3b JB |
4473 | struct drm_i915_private *dev_priv = dev->dev_private; |
4474 | ||
8090c6b9 DV |
4475 | if (IS_IRONLAKE_M(dev)) { |
4476 | ironlake_enable_drps(dev); | |
4477 | ironlake_enable_rc6(dev); | |
4478 | intel_init_emon(dev); | |
0a073b84 | 4479 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
17b0c1f7 ID |
4480 | if (IS_VALLEYVIEW(dev)) |
4481 | valleyview_setup_pctx(dev); | |
1a01ab3b JB |
4482 | /* |
4483 | * PCU communication is slow and this doesn't need to be | |
4484 | * done at any specific time, so do this out of our fast path | |
4485 | * to make resume and init faster. | |
4486 | */ | |
4487 | schedule_delayed_work(&dev_priv->rps.delayed_resume_work, | |
4488 | round_jiffies_up_relative(HZ)); | |
8090c6b9 DV |
4489 | } |
4490 | } | |
4491 | ||
3107bd48 DV |
4492 | static void ibx_init_clock_gating(struct drm_device *dev) |
4493 | { | |
4494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4495 | ||
4496 | /* | |
4497 | * On Ibex Peak and Cougar Point, we need to disable clock | |
4498 | * gating for the panel power sequencer or it will fail to | |
4499 | * start up when no ports are active. | |
4500 | */ | |
4501 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
4502 | } | |
4503 | ||
0e088b8f VS |
4504 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
4505 | { | |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4507 | int pipe; | |
4508 | ||
4509 | for_each_pipe(pipe) { | |
4510 | I915_WRITE(DSPCNTR(pipe), | |
4511 | I915_READ(DSPCNTR(pipe)) | | |
4512 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 4513 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
4514 | } |
4515 | } | |
4516 | ||
017636cc VS |
4517 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
4518 | { | |
4519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4520 | ||
4521 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
4522 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
4523 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
4524 | ||
4525 | /* | |
4526 | * Don't touch WM1S_LP_EN here. | |
4527 | * Doing so could cause underruns. | |
4528 | */ | |
4529 | } | |
4530 | ||
1fa61106 | 4531 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4532 | { |
4533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 4534 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 4535 | |
f1e8fa56 DL |
4536 | /* |
4537 | * Required for FBC | |
4538 | * WaFbcDisableDpfcClockGating:ilk | |
4539 | */ | |
4d47e4f5 DL |
4540 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
4541 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
4542 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
4543 | |
4544 | I915_WRITE(PCH_3DCGDIS0, | |
4545 | MARIUNIT_CLOCK_GATE_DISABLE | | |
4546 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
4547 | I915_WRITE(PCH_3DCGDIS1, | |
4548 | VFMUNIT_CLOCK_GATE_DISABLE); | |
4549 | ||
6f1d69b0 ED |
4550 | /* |
4551 | * According to the spec the following bits should be set in | |
4552 | * order to enable memory self-refresh | |
4553 | * The bit 22/21 of 0x42004 | |
4554 | * The bit 5 of 0x42020 | |
4555 | * The bit 15 of 0x45000 | |
4556 | */ | |
4557 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
4558 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
4559 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 4560 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
4561 | I915_WRITE(DISP_ARB_CTL, |
4562 | (I915_READ(DISP_ARB_CTL) | | |
4563 | DISP_FBC_WM_DIS)); | |
017636cc VS |
4564 | |
4565 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
4566 | |
4567 | /* | |
4568 | * Based on the document from hardware guys the following bits | |
4569 | * should be set unconditionally in order to enable FBC. | |
4570 | * The bit 22 of 0x42000 | |
4571 | * The bit 22 of 0x42004 | |
4572 | * The bit 7,8,9 of 0x42020. | |
4573 | */ | |
4574 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 4575 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
4576 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
4577 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
4578 | ILK_FBCQ_DIS); | |
4579 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
4580 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
4581 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
4582 | } |
4583 | ||
4d47e4f5 DL |
4584 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
4585 | ||
6f1d69b0 ED |
4586 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
4587 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
4588 | ILK_ELPIN_409_SELECT); | |
4589 | I915_WRITE(_3D_CHICKEN2, | |
4590 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
4591 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 4592 | |
ecdb4eb7 | 4593 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
4594 | I915_WRITE(CACHE_MODE_0, |
4595 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 4596 | |
0e088b8f | 4597 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 4598 | |
3107bd48 DV |
4599 | ibx_init_clock_gating(dev); |
4600 | } | |
4601 | ||
4602 | static void cpt_init_clock_gating(struct drm_device *dev) | |
4603 | { | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | int pipe; | |
3f704fa2 | 4606 | uint32_t val; |
3107bd48 DV |
4607 | |
4608 | /* | |
4609 | * On Ibex Peak and Cougar Point, we need to disable clock | |
4610 | * gating for the panel power sequencer or it will fail to | |
4611 | * start up when no ports are active. | |
4612 | */ | |
cd664078 JB |
4613 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
4614 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
4615 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
4616 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
4617 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
4618 | /* The below fixes the weird display corruption, a few pixels shifted |
4619 | * downward, on (only) LVDS of some HP laptops with IVY. | |
4620 | */ | |
3f704fa2 | 4621 | for_each_pipe(pipe) { |
dc4bd2d1 PZ |
4622 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
4623 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
4624 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 4625 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 4626 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
4627 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
4628 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
4629 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
4630 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
4631 | } | |
3107bd48 DV |
4632 | /* WADP0ClockGatingDisable */ |
4633 | for_each_pipe(pipe) { | |
4634 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
4635 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
4636 | } | |
6f1d69b0 ED |
4637 | } |
4638 | ||
1d7aaa0c DV |
4639 | static void gen6_check_mch_setup(struct drm_device *dev) |
4640 | { | |
4641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4642 | uint32_t tmp; | |
4643 | ||
4644 | tmp = I915_READ(MCH_SSKPD); | |
4645 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { | |
4646 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); | |
4647 | DRM_INFO("This can cause pipe underruns and display issues.\n"); | |
4648 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); | |
4649 | } | |
4650 | } | |
4651 | ||
1fa61106 | 4652 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4653 | { |
4654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 4655 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 4656 | |
231e54f6 | 4657 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
4658 | |
4659 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
4660 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
4661 | ILK_ELPIN_409_SELECT); | |
4662 | ||
ecdb4eb7 | 4663 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
4664 | I915_WRITE(_3D_CHICKEN, |
4665 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
4666 | ||
ecdb4eb7 | 4667 | /* WaSetupGtModeTdRowDispatch:snb */ |
6547fbdb DV |
4668 | if (IS_SNB_GT1(dev)) |
4669 | I915_WRITE(GEN6_GT_MODE, | |
4670 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); | |
4671 | ||
8d85d272 VS |
4672 | /* |
4673 | * BSpec recoomends 8x4 when MSAA is used, | |
4674 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
4675 | * |
4676 | * Note that PS/WM thread counts depend on the WIZ hashing | |
4677 | * disable bit, which we don't touch here, but it's good | |
4678 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
4679 | */ |
4680 | I915_WRITE(GEN6_GT_MODE, | |
4681 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
4682 | ||
017636cc | 4683 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 4684 | |
6f1d69b0 | 4685 | I915_WRITE(CACHE_MODE_0, |
50743298 | 4686 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
4687 | |
4688 | I915_WRITE(GEN6_UCGCTL1, | |
4689 | I915_READ(GEN6_UCGCTL1) | | |
4690 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
4691 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
4692 | ||
4693 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
4694 | * gating disable must be set. Failure to set it results in | |
4695 | * flickering pixels due to Z write ordering failures after | |
4696 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
4697 | * Sanctuary and Tropics, and apparently anything else with | |
4698 | * alpha test or pixel discard. | |
4699 | * | |
4700 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
4701 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 4702 | * |
ef59318c VS |
4703 | * WaDisableRCCUnitClockGating:snb |
4704 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
4705 | */ |
4706 | I915_WRITE(GEN6_UCGCTL2, | |
4707 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
4708 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
4709 | ||
5eb146dd | 4710 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
4711 | I915_WRITE(_3D_CHICKEN3, |
4712 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 4713 | |
e927ecde VS |
4714 | /* |
4715 | * Bspec says: | |
4716 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
4717 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
4718 | */ | |
4719 | I915_WRITE(_3D_CHICKEN3, | |
4720 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
4721 | ||
6f1d69b0 ED |
4722 | /* |
4723 | * According to the spec the following bits should be | |
4724 | * set in order to enable memory self-refresh and fbc: | |
4725 | * The bit21 and bit22 of 0x42000 | |
4726 | * The bit21 and bit22 of 0x42004 | |
4727 | * The bit5 and bit7 of 0x42020 | |
4728 | * The bit14 of 0x70180 | |
4729 | * The bit14 of 0x71180 | |
4bb35334 DL |
4730 | * |
4731 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
4732 | */ |
4733 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
4734 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
4735 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
4736 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
4737 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
4738 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
4739 | I915_WRITE(ILK_DSPCLK_GATE_D, |
4740 | I915_READ(ILK_DSPCLK_GATE_D) | | |
4741 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
4742 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 4743 | |
0e088b8f | 4744 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 4745 | |
3107bd48 | 4746 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
4747 | |
4748 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
4749 | } |
4750 | ||
4751 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
4752 | { | |
4753 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
4754 | ||
3aad9059 | 4755 | /* |
46680e0a | 4756 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
4757 | * |
4758 | * This actually overrides the dispatch | |
4759 | * mode for all thread types. | |
4760 | */ | |
6f1d69b0 ED |
4761 | reg &= ~GEN7_FF_SCHED_MASK; |
4762 | reg |= GEN7_FF_TS_SCHED_HW; | |
4763 | reg |= GEN7_FF_VS_SCHED_HW; | |
4764 | reg |= GEN7_FF_DS_SCHED_HW; | |
4765 | ||
4766 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
4767 | } | |
4768 | ||
17a303ec PZ |
4769 | static void lpt_init_clock_gating(struct drm_device *dev) |
4770 | { | |
4771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4772 | ||
4773 | /* | |
4774 | * TODO: this bit should only be enabled when really needed, then | |
4775 | * disabled when not needed anymore in order to save power. | |
4776 | */ | |
4777 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
4778 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
4779 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
4780 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
4781 | |
4782 | /* WADPOClockGatingDisable:hsw */ | |
4783 | I915_WRITE(_TRANSA_CHICKEN1, | |
4784 | I915_READ(_TRANSA_CHICKEN1) | | |
4785 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
4786 | } |
4787 | ||
7d708ee4 ID |
4788 | static void lpt_suspend_hw(struct drm_device *dev) |
4789 | { | |
4790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4791 | ||
4792 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
4793 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
4794 | ||
4795 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
4796 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
4797 | } | |
4798 | } | |
4799 | ||
1020a5c2 BW |
4800 | static void gen8_init_clock_gating(struct drm_device *dev) |
4801 | { | |
4802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 4803 | enum pipe pipe; |
1020a5c2 BW |
4804 | |
4805 | I915_WRITE(WM3_LP_ILK, 0); | |
4806 | I915_WRITE(WM2_LP_ILK, 0); | |
4807 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd BW |
4808 | |
4809 | /* FIXME(BDW): Check all the w/a, some might only apply to | |
4810 | * pre-production hw. */ | |
4811 | ||
c8966e10 KG |
4812 | /* WaDisablePartialInstShootdown:bdw */ |
4813 | I915_WRITE(GEN8_ROW_CHICKEN, | |
4814 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); | |
4815 | ||
1411e6a5 KG |
4816 | /* WaDisableThreadStallDopClockGating:bdw */ |
4817 | /* FIXME: Unclear whether we really need this on production bdw. */ | |
4818 | I915_WRITE(GEN8_ROW_CHICKEN, | |
4819 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); | |
4820 | ||
4167e32c DL |
4821 | /* |
4822 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for | |
4823 | * pre-production hardware | |
4824 | */ | |
fd392b60 BW |
4825 | I915_WRITE(HALF_SLICE_CHICKEN3, |
4826 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); | |
bf66347c BW |
4827 | I915_WRITE(HALF_SLICE_CHICKEN3, |
4828 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); | |
4afe8d33 BW |
4829 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); |
4830 | ||
7f88da0c BW |
4831 | I915_WRITE(_3D_CHICKEN3, |
4832 | _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); | |
4833 | ||
a75f3628 BW |
4834 | I915_WRITE(COMMON_SLICE_CHICKEN2, |
4835 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); | |
4836 | ||
4c2e7a5f BW |
4837 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
4838 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); | |
4839 | ||
ab57fff1 | 4840 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 4841 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 4842 | |
ab57fff1 | 4843 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
4844 | I915_WRITE(CHICKEN_PAR1_1, |
4845 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
4846 | ||
ab57fff1 | 4847 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
07d27e20 DL |
4848 | for_each_pipe(pipe) { |
4849 | I915_WRITE(CHICKEN_PIPESL_1(pipe), | |
c7c65622 | 4850 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 4851 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 4852 | } |
63801f21 BW |
4853 | |
4854 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
4855 | * workaround for for a possible hang in the unlikely event a TLB | |
4856 | * invalidation occurs during a PSD flush. | |
4857 | */ | |
4858 | I915_WRITE(HDC_CHICKEN0, | |
4859 | I915_READ(HDC_CHICKEN0) | | |
4860 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); | |
ab57fff1 BW |
4861 | |
4862 | /* WaVSRefCountFullforceMissDisable:bdw */ | |
4863 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
4864 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
4865 | I915_READ(GEN7_FF_THREAD_MODE) & | |
4866 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c VS |
4867 | |
4868 | /* | |
4869 | * BSpec recommends 8x4 when MSAA is used, | |
4870 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
4871 | * |
4872 | * Note that PS/WM thread counts depend on the WIZ hashing | |
4873 | * disable bit, which we don't touch here, but it's good | |
4874 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
36075a4c VS |
4875 | */ |
4876 | I915_WRITE(GEN7_GT_MODE, | |
4877 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
295e8bb7 VS |
4878 | |
4879 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
4880 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
4881 | |
4882 | /* WaDisableSDEUnitClockGating:bdw */ | |
4883 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
4884 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 DL |
4885 | |
4886 | /* Wa4x4STCOptimizationDisable:bdw */ | |
4887 | I915_WRITE(CACHE_MODE_1, | |
4888 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); | |
1020a5c2 BW |
4889 | } |
4890 | ||
cad2a2d7 ED |
4891 | static void haswell_init_clock_gating(struct drm_device *dev) |
4892 | { | |
4893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 4894 | |
017636cc | 4895 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 4896 | |
f3fc4884 FJ |
4897 | /* L3 caching of data atomics doesn't work -- disable it. */ |
4898 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
4899 | I915_WRITE(HSW_ROW_CHICKEN3, | |
4900 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
4901 | ||
ecdb4eb7 | 4902 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
4903 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4904 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
4905 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
4906 | ||
e36ea7ff VS |
4907 | /* WaVSRefCountFullforceMissDisable:hsw */ |
4908 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
4909 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 4910 | |
fe27c606 CW |
4911 | /* enable HiZ Raw Stall Optimization */ |
4912 | I915_WRITE(CACHE_MODE_0_GEN7, | |
4913 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
4914 | ||
ecdb4eb7 | 4915 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
4916 | I915_WRITE(CACHE_MODE_1, |
4917 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 4918 | |
a12c4967 VS |
4919 | /* |
4920 | * BSpec recommends 8x4 when MSAA is used, | |
4921 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
4922 | * |
4923 | * Note that PS/WM thread counts depend on the WIZ hashing | |
4924 | * disable bit, which we don't touch here, but it's good | |
4925 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
4926 | */ |
4927 | I915_WRITE(GEN7_GT_MODE, | |
4928 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
4929 | ||
ecdb4eb7 | 4930 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
4931 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
4932 | ||
90a88643 PZ |
4933 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
4934 | I915_WRITE(CHICKEN_PAR1_1, | |
4935 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 4936 | |
17a303ec | 4937 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
4938 | } |
4939 | ||
1fa61106 | 4940 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4941 | { |
4942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 4943 | uint32_t snpcr; |
6f1d69b0 | 4944 | |
017636cc | 4945 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 4946 | |
231e54f6 | 4947 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 4948 | |
ecdb4eb7 | 4949 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
4950 | I915_WRITE(_3D_CHICKEN3, |
4951 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
4952 | ||
ecdb4eb7 | 4953 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
4954 | I915_WRITE(IVB_CHICKEN3, |
4955 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
4956 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
4957 | ||
ecdb4eb7 | 4958 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
4959 | if (IS_IVB_GT1(dev)) |
4960 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
4961 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 4962 | |
ecdb4eb7 | 4963 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
4964 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
4965 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
4966 | ||
ecdb4eb7 | 4967 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
4968 | I915_WRITE(GEN7_L3CNTLREG1, |
4969 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
4970 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
4971 | GEN7_WA_L3_CHICKEN_MODE); |
4972 | if (IS_IVB_GT1(dev)) | |
4973 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
4974 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
4975 | else { |
4976 | /* must write both registers */ | |
4977 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
4978 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
4979 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
4980 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 4981 | } |
6f1d69b0 | 4982 | |
ecdb4eb7 | 4983 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
4984 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
4985 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
4986 | ||
1b80a19a | 4987 | /* |
0f846f81 | 4988 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 4989 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
4990 | */ |
4991 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 4992 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 4993 | |
ecdb4eb7 | 4994 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
4995 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4996 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
4997 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
4998 | ||
0e088b8f | 4999 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
5000 | |
5001 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 5002 | |
22721343 CW |
5003 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
5004 | /* enable HiZ Raw Stall Optimization */ | |
5005 | I915_WRITE(CACHE_MODE_0_GEN7, | |
5006 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
5007 | } | |
116f2b6d | 5008 | |
ecdb4eb7 | 5009 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
5010 | I915_WRITE(CACHE_MODE_1, |
5011 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 5012 | |
a607c1a4 VS |
5013 | /* |
5014 | * BSpec recommends 8x4 when MSAA is used, | |
5015 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5016 | * |
5017 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5018 | * disable bit, which we don't touch here, but it's good | |
5019 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
5020 | */ |
5021 | I915_WRITE(GEN7_GT_MODE, | |
5022 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5023 | ||
20848223 BW |
5024 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
5025 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5026 | snpcr |= GEN6_MBC_SNPCR_MED; | |
5027 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 5028 | |
ab5c608b BW |
5029 | if (!HAS_PCH_NOP(dev)) |
5030 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
5031 | |
5032 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5033 | } |
5034 | ||
1fa61106 | 5035 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5036 | { |
5037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85b1d7b3 JB |
5038 | u32 val; |
5039 | ||
5040 | mutex_lock(&dev_priv->rps.hw_lock); | |
5041 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
5042 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5043 | switch ((val >> 6) & 3) { | |
5044 | case 0: | |
85b1d7b3 JB |
5045 | dev_priv->mem_freq = 800; |
5046 | break; | |
f64a28a7 | 5047 | case 1: |
85b1d7b3 JB |
5048 | dev_priv->mem_freq = 1066; |
5049 | break; | |
f64a28a7 | 5050 | case 2: |
85b1d7b3 JB |
5051 | dev_priv->mem_freq = 1333; |
5052 | break; | |
f64a28a7 | 5053 | case 3: |
2325991e | 5054 | dev_priv->mem_freq = 1333; |
f64a28a7 | 5055 | break; |
85b1d7b3 JB |
5056 | } |
5057 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
6f1d69b0 | 5058 | |
d7fe0cc0 | 5059 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 5060 | |
ecdb4eb7 | 5061 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
5062 | I915_WRITE(_3D_CHICKEN3, |
5063 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
5064 | ||
ecdb4eb7 | 5065 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
5066 | I915_WRITE(IVB_CHICKEN3, |
5067 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
5068 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
5069 | ||
fad7d36e | 5070 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 5071 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 5072 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
5073 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
5074 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 5075 | |
ecdb4eb7 | 5076 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
5077 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
5078 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
5079 | ||
ecdb4eb7 | 5080 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
5081 | I915_WRITE(GEN7_ROW_CHICKEN2, |
5082 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
5083 | ||
ecdb4eb7 | 5084 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
5085 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5086 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5087 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5088 | ||
46680e0a VS |
5089 | gen7_setup_fixed_func_scheduler(dev_priv); |
5090 | ||
3c0edaeb | 5091 | /* |
0f846f81 | 5092 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 5093 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
5094 | */ |
5095 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 5096 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 5097 | |
c5c32cda | 5098 | /* WaDisableL3Bank2xClockGate:vlv */ |
e3f33d46 JB |
5099 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
5100 | ||
e0d8d59b | 5101 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6f1d69b0 | 5102 | |
afd58e79 VS |
5103 | /* |
5104 | * BSpec says this must be set, even though | |
5105 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
5106 | */ | |
6b26c86d DV |
5107 | I915_WRITE(CACHE_MODE_1, |
5108 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 5109 | |
031994ee VS |
5110 | /* |
5111 | * WaIncreaseL3CreditsForVLVB0:vlv | |
5112 | * This is the hardware default actually. | |
5113 | */ | |
5114 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
5115 | ||
2d809570 | 5116 | /* |
ecdb4eb7 | 5117 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
5118 | * Disable clock gating on th GCFG unit to prevent a delay |
5119 | * in the reporting of vblank events. | |
5120 | */ | |
7a0d1eed | 5121 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
5122 | } |
5123 | ||
1fa61106 | 5124 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5125 | { |
5126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5127 | uint32_t dspclk_gate; | |
5128 | ||
5129 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5130 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5131 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5132 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5133 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5134 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5135 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5136 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5137 | if (IS_GM45(dev)) | |
5138 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5139 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
5140 | |
5141 | /* WaDisableRenderCachePipelinedFlush */ | |
5142 | I915_WRITE(CACHE_MODE_0, | |
5143 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 5144 | |
0e088b8f | 5145 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
5146 | } |
5147 | ||
1fa61106 | 5148 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5149 | { |
5150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5151 | ||
5152 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
5153 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5154 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5155 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5156 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
5157 | I915_WRITE(MI_ARB_STATE, |
5158 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
5159 | } |
5160 | ||
1fa61106 | 5161 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5162 | { |
5163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5164 | ||
5165 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
5166 | I965_RCC_CLOCK_GATE_DISABLE | | |
5167 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5168 | I965_ISC_CLOCK_GATE_DISABLE | | |
5169 | I965_FBC_CLOCK_GATE_DISABLE); | |
5170 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
5171 | I915_WRITE(MI_ARB_STATE, |
5172 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
5173 | } |
5174 | ||
1fa61106 | 5175 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5176 | { |
5177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5178 | u32 dstate = I915_READ(D_STATE); | |
5179 | ||
5180 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5181 | DSTATE_DOT_CLOCK_GATING; | |
5182 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
5183 | |
5184 | if (IS_PINEVIEW(dev)) | |
5185 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
5186 | |
5187 | /* IIR "flip pending" means done if this bit is set */ | |
5188 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
6f1d69b0 ED |
5189 | } |
5190 | ||
1fa61106 | 5191 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5192 | { |
5193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5194 | ||
5195 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
5196 | } | |
5197 | ||
1fa61106 | 5198 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5199 | { |
5200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5201 | ||
5202 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5203 | } | |
5204 | ||
6f1d69b0 ED |
5205 | void intel_init_clock_gating(struct drm_device *dev) |
5206 | { | |
5207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5208 | ||
5209 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
5210 | } |
5211 | ||
7d708ee4 ID |
5212 | void intel_suspend_hw(struct drm_device *dev) |
5213 | { | |
5214 | if (HAS_PCH_LPT(dev)) | |
5215 | lpt_suspend_hw(dev); | |
5216 | } | |
5217 | ||
c1ca727f ID |
5218 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
5219 | for (i = 0; \ | |
5220 | i < (power_domains)->power_well_count && \ | |
5221 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
5222 | i++) \ | |
5223 | if ((power_well)->domains & (domain_mask)) | |
5224 | ||
5225 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
5226 | for (i = (power_domains)->power_well_count - 1; \ | |
5227 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
5228 | i--) \ | |
5229 | if ((power_well)->domains & (domain_mask)) | |
5230 | ||
15d199ea PZ |
5231 | /** |
5232 | * We should only use the power well if we explicitly asked the hardware to | |
5233 | * enable it, so check if it's enabled and also check if we've requested it to | |
5234 | * be enabled. | |
5235 | */ | |
da7e29bd | 5236 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
c1ca727f ID |
5237 | struct i915_power_well *power_well) |
5238 | { | |
c1ca727f ID |
5239 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
5240 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
5241 | } | |
5242 | ||
da7e29bd | 5243 | bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, |
ddf9c536 ID |
5244 | enum intel_display_power_domain domain) |
5245 | { | |
ddf9c536 ID |
5246 | struct i915_power_domains *power_domains; |
5247 | ||
5248 | power_domains = &dev_priv->power_domains; | |
5249 | ||
5250 | return power_domains->domain_use_count[domain]; | |
5251 | } | |
5252 | ||
da7e29bd | 5253 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
b97186f0 | 5254 | enum intel_display_power_domain domain) |
15d199ea | 5255 | { |
c1ca727f ID |
5256 | struct i915_power_domains *power_domains; |
5257 | struct i915_power_well *power_well; | |
5258 | bool is_enabled; | |
5259 | int i; | |
15d199ea | 5260 | |
c1ca727f ID |
5261 | power_domains = &dev_priv->power_domains; |
5262 | ||
5263 | is_enabled = true; | |
5264 | ||
5265 | mutex_lock(&power_domains->lock); | |
5266 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
6f3ef5dd ID |
5267 | if (power_well->always_on) |
5268 | continue; | |
5269 | ||
c6cb582e | 5270 | if (!power_well->ops->is_enabled(dev_priv, power_well)) { |
c1ca727f ID |
5271 | is_enabled = false; |
5272 | break; | |
5273 | } | |
5274 | } | |
5275 | mutex_unlock(&power_domains->lock); | |
5276 | ||
5277 | return is_enabled; | |
15d199ea PZ |
5278 | } |
5279 | ||
93c73e8c ID |
5280 | /* |
5281 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
5282 | * when not needed anymore. We have 4 registers that can request the power well | |
5283 | * to be enabled, and it will only be disabled if none of the registers is | |
5284 | * requesting it to be enabled. | |
5285 | */ | |
d5e8fdc8 PZ |
5286 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
5287 | { | |
5288 | struct drm_device *dev = dev_priv->dev; | |
5289 | unsigned long irqflags; | |
5290 | ||
f9dcb0df PZ |
5291 | /* |
5292 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
5293 | * we'll get unclaimed register interrupts. This stops after we write | |
5294 | * anything to the VGA MSR register. The vgacon module uses this | |
5295 | * register all the time, so if we unbind our driver and, as a | |
5296 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
5297 | * console_unlock(). So make here we touch the VGA MSR register, making | |
5298 | * sure vgacon can keep working normally without triggering interrupts | |
5299 | * and error messages. | |
5300 | */ | |
5301 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
5302 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
5303 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
5304 | ||
d5e8fdc8 PZ |
5305 | if (IS_BROADWELL(dev)) { |
5306 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
5307 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B), | |
5308 | dev_priv->de_irq_mask[PIPE_B]); | |
5309 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B), | |
5310 | ~dev_priv->de_irq_mask[PIPE_B] | | |
5311 | GEN8_PIPE_VBLANK); | |
5312 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C), | |
5313 | dev_priv->de_irq_mask[PIPE_C]); | |
5314 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C), | |
5315 | ~dev_priv->de_irq_mask[PIPE_C] | | |
5316 | GEN8_PIPE_VBLANK); | |
5317 | POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C)); | |
5318 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
5319 | } | |
5320 | } | |
5321 | ||
dd7c0b66 ID |
5322 | static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe) |
5323 | { | |
5324 | assert_spin_locked(&dev->vbl_lock); | |
5325 | ||
5326 | dev->vblank[pipe].last = 0; | |
5327 | } | |
5328 | ||
d5e8fdc8 PZ |
5329 | static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv) |
5330 | { | |
5331 | struct drm_device *dev = dev_priv->dev; | |
07d27e20 | 5332 | enum pipe pipe; |
d5e8fdc8 PZ |
5333 | unsigned long irqflags; |
5334 | ||
5335 | /* | |
5336 | * After this, the registers on the pipes that are part of the power | |
5337 | * well will become zero, so we have to adjust our counters according to | |
5338 | * that. | |
5339 | * | |
5340 | * FIXME: Should we do this in general in drm_vblank_post_modeset? | |
5341 | */ | |
5342 | spin_lock_irqsave(&dev->vbl_lock, irqflags); | |
07d27e20 DL |
5343 | for_each_pipe(pipe) |
5344 | if (pipe != PIPE_A) | |
dd7c0b66 | 5345 | reset_vblank_counter(dev, pipe); |
d5e8fdc8 PZ |
5346 | spin_unlock_irqrestore(&dev->vbl_lock, irqflags); |
5347 | } | |
5348 | ||
da7e29bd | 5349 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
c1ca727f | 5350 | struct i915_power_well *power_well, bool enable) |
d0d3e513 | 5351 | { |
fa42e23c PZ |
5352 | bool is_enabled, enable_requested; |
5353 | uint32_t tmp; | |
d0d3e513 | 5354 | |
fa42e23c | 5355 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
6aedd1f5 PZ |
5356 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
5357 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
d0d3e513 | 5358 | |
fa42e23c PZ |
5359 | if (enable) { |
5360 | if (!enable_requested) | |
6aedd1f5 PZ |
5361 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
5362 | HSW_PWR_WELL_ENABLE_REQUEST); | |
d0d3e513 | 5363 | |
fa42e23c PZ |
5364 | if (!is_enabled) { |
5365 | DRM_DEBUG_KMS("Enabling power well\n"); | |
5366 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
6aedd1f5 | 5367 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
fa42e23c PZ |
5368 | DRM_ERROR("Timeout enabling power well\n"); |
5369 | } | |
596cc11e | 5370 | |
d5e8fdc8 | 5371 | hsw_power_well_post_enable(dev_priv); |
fa42e23c PZ |
5372 | } else { |
5373 | if (enable_requested) { | |
5374 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
9dbd8feb | 5375 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
fa42e23c | 5376 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
9dbd8feb | 5377 | |
d5e8fdc8 | 5378 | hsw_power_well_post_disable(dev_priv); |
d0d3e513 ED |
5379 | } |
5380 | } | |
fa42e23c | 5381 | } |
d0d3e513 | 5382 | |
c6cb582e ID |
5383 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
5384 | struct i915_power_well *power_well) | |
5385 | { | |
5386 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
5387 | ||
5388 | /* | |
5389 | * We're taking over the BIOS, so clear any requests made by it since | |
5390 | * the driver is in charge now. | |
5391 | */ | |
5392 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
5393 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
5394 | } | |
5395 | ||
5396 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
5397 | struct i915_power_well *power_well) | |
5398 | { | |
c6cb582e ID |
5399 | hsw_set_power_well(dev_priv, power_well, true); |
5400 | } | |
5401 | ||
5402 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
5403 | struct i915_power_well *power_well) | |
5404 | { | |
5405 | hsw_set_power_well(dev_priv, power_well, false); | |
c6cb582e ID |
5406 | } |
5407 | ||
a45f4466 ID |
5408 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
5409 | struct i915_power_well *power_well) | |
5410 | { | |
5411 | } | |
5412 | ||
5413 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
5414 | struct i915_power_well *power_well) | |
5415 | { | |
5416 | return true; | |
5417 | } | |
5418 | ||
77961eb9 ID |
5419 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
5420 | struct i915_power_well *power_well, bool enable) | |
5421 | { | |
5422 | enum punit_power_well power_well_id = power_well->data; | |
5423 | u32 mask; | |
5424 | u32 state; | |
5425 | u32 ctrl; | |
5426 | ||
5427 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
5428 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
5429 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
5430 | ||
5431 | mutex_lock(&dev_priv->rps.hw_lock); | |
5432 | ||
5433 | #define COND \ | |
5434 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
5435 | ||
5436 | if (COND) | |
5437 | goto out; | |
5438 | ||
5439 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
5440 | ctrl &= ~mask; | |
5441 | ctrl |= state; | |
5442 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
5443 | ||
5444 | if (wait_for(COND, 100)) | |
5445 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
5446 | state, | |
5447 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
5448 | ||
5449 | #undef COND | |
5450 | ||
5451 | out: | |
5452 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5453 | } | |
5454 | ||
5455 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
5456 | struct i915_power_well *power_well) | |
5457 | { | |
5458 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
5459 | } | |
5460 | ||
5461 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
5462 | struct i915_power_well *power_well) | |
5463 | { | |
5464 | vlv_set_power_well(dev_priv, power_well, true); | |
5465 | } | |
5466 | ||
5467 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
5468 | struct i915_power_well *power_well) | |
5469 | { | |
5470 | vlv_set_power_well(dev_priv, power_well, false); | |
5471 | } | |
5472 | ||
5473 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
5474 | struct i915_power_well *power_well) | |
5475 | { | |
5476 | int power_well_id = power_well->data; | |
5477 | bool enabled = false; | |
5478 | u32 mask; | |
5479 | u32 state; | |
5480 | u32 ctrl; | |
5481 | ||
5482 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
5483 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
5484 | ||
5485 | mutex_lock(&dev_priv->rps.hw_lock); | |
5486 | ||
5487 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
5488 | /* | |
5489 | * We only ever set the power-on and power-gate states, anything | |
5490 | * else is unexpected. | |
5491 | */ | |
5492 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
5493 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
5494 | if (state == ctrl) | |
5495 | enabled = true; | |
5496 | ||
5497 | /* | |
5498 | * A transient state at this point would mean some unexpected party | |
5499 | * is poking at the power controls too. | |
5500 | */ | |
5501 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
5502 | WARN_ON(ctrl != state); | |
5503 | ||
5504 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5505 | ||
5506 | return enabled; | |
5507 | } | |
5508 | ||
5509 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
5510 | struct i915_power_well *power_well) | |
5511 | { | |
5512 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
5513 | ||
5514 | vlv_set_power_well(dev_priv, power_well, true); | |
5515 | ||
5516 | spin_lock_irq(&dev_priv->irq_lock); | |
5517 | valleyview_enable_display_irqs(dev_priv); | |
5518 | spin_unlock_irq(&dev_priv->irq_lock); | |
5519 | ||
5520 | /* | |
5521 | * During driver initialization we need to defer enabling hotplug | |
5522 | * processing until fbdev is set up. | |
5523 | */ | |
5524 | if (dev_priv->enable_hotplug_processing) | |
5525 | intel_hpd_init(dev_priv->dev); | |
5526 | ||
5527 | i915_redisable_vga_power_on(dev_priv->dev); | |
5528 | } | |
5529 | ||
5530 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, | |
5531 | struct i915_power_well *power_well) | |
5532 | { | |
5533 | struct drm_device *dev = dev_priv->dev; | |
5534 | enum pipe pipe; | |
5535 | ||
5536 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
5537 | ||
5538 | spin_lock_irq(&dev_priv->irq_lock); | |
5539 | for_each_pipe(pipe) | |
5540 | __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
5541 | ||
5542 | valleyview_disable_display_irqs(dev_priv); | |
5543 | spin_unlock_irq(&dev_priv->irq_lock); | |
5544 | ||
5545 | spin_lock_irq(&dev->vbl_lock); | |
5546 | for_each_pipe(pipe) | |
5547 | reset_vblank_counter(dev, pipe); | |
5548 | spin_unlock_irq(&dev->vbl_lock); | |
5549 | ||
5550 | vlv_set_power_well(dev_priv, power_well, false); | |
5551 | } | |
5552 | ||
25eaa003 ID |
5553 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
5554 | struct i915_power_well *power_well) | |
5555 | { | |
5556 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); | |
5557 | ||
5558 | if (power_well->always_on || !i915.disable_power_well) { | |
5559 | if (!enabled) | |
5560 | goto mismatch; | |
5561 | ||
5562 | return; | |
5563 | } | |
5564 | ||
5565 | if (enabled != (power_well->count > 0)) | |
5566 | goto mismatch; | |
5567 | ||
5568 | return; | |
5569 | ||
5570 | mismatch: | |
5571 | WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", | |
5572 | power_well->name, power_well->always_on, enabled, | |
5573 | power_well->count, i915.disable_power_well); | |
5574 | } | |
5575 | ||
da7e29bd | 5576 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
6765625e VS |
5577 | enum intel_display_power_domain domain) |
5578 | { | |
83c00f55 | 5579 | struct i915_power_domains *power_domains; |
c1ca727f ID |
5580 | struct i915_power_well *power_well; |
5581 | int i; | |
6765625e | 5582 | |
9e6ea71a PZ |
5583 | intel_runtime_pm_get(dev_priv); |
5584 | ||
83c00f55 ID |
5585 | power_domains = &dev_priv->power_domains; |
5586 | ||
5587 | mutex_lock(&power_domains->lock); | |
1da51581 | 5588 | |
25eaa003 ID |
5589 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
5590 | if (!power_well->count++) { | |
5591 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
c6cb582e | 5592 | power_well->ops->enable(dev_priv, power_well); |
25eaa003 ID |
5593 | } |
5594 | ||
5595 | check_power_well_state(dev_priv, power_well); | |
5596 | } | |
1da51581 | 5597 | |
ddf9c536 ID |
5598 | power_domains->domain_use_count[domain]++; |
5599 | ||
83c00f55 | 5600 | mutex_unlock(&power_domains->lock); |
6765625e VS |
5601 | } |
5602 | ||
da7e29bd | 5603 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
6765625e VS |
5604 | enum intel_display_power_domain domain) |
5605 | { | |
83c00f55 | 5606 | struct i915_power_domains *power_domains; |
c1ca727f ID |
5607 | struct i915_power_well *power_well; |
5608 | int i; | |
6765625e | 5609 | |
83c00f55 ID |
5610 | power_domains = &dev_priv->power_domains; |
5611 | ||
5612 | mutex_lock(&power_domains->lock); | |
1da51581 | 5613 | |
1da51581 ID |
5614 | WARN_ON(!power_domains->domain_use_count[domain]); |
5615 | power_domains->domain_use_count[domain]--; | |
ddf9c536 | 5616 | |
70bf407c ID |
5617 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
5618 | WARN_ON(!power_well->count); | |
5619 | ||
25eaa003 ID |
5620 | if (!--power_well->count && i915.disable_power_well) { |
5621 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
c6cb582e | 5622 | power_well->ops->disable(dev_priv, power_well); |
25eaa003 ID |
5623 | } |
5624 | ||
5625 | check_power_well_state(dev_priv, power_well); | |
70bf407c | 5626 | } |
1da51581 | 5627 | |
83c00f55 | 5628 | mutex_unlock(&power_domains->lock); |
9e6ea71a PZ |
5629 | |
5630 | intel_runtime_pm_put(dev_priv); | |
6765625e VS |
5631 | } |
5632 | ||
83c00f55 | 5633 | static struct i915_power_domains *hsw_pwr; |
a38911a3 WX |
5634 | |
5635 | /* Display audio driver power well request */ | |
5636 | void i915_request_power_well(void) | |
5637 | { | |
b4ed4484 ID |
5638 | struct drm_i915_private *dev_priv; |
5639 | ||
a38911a3 WX |
5640 | if (WARN_ON(!hsw_pwr)) |
5641 | return; | |
5642 | ||
b4ed4484 ID |
5643 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
5644 | power_domains); | |
da7e29bd | 5645 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
a38911a3 WX |
5646 | } |
5647 | EXPORT_SYMBOL_GPL(i915_request_power_well); | |
5648 | ||
5649 | /* Display audio driver power well release */ | |
5650 | void i915_release_power_well(void) | |
5651 | { | |
b4ed4484 ID |
5652 | struct drm_i915_private *dev_priv; |
5653 | ||
a38911a3 WX |
5654 | if (WARN_ON(!hsw_pwr)) |
5655 | return; | |
5656 | ||
b4ed4484 ID |
5657 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
5658 | power_domains); | |
da7e29bd | 5659 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
a38911a3 WX |
5660 | } |
5661 | EXPORT_SYMBOL_GPL(i915_release_power_well); | |
5662 | ||
efcad917 ID |
5663 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
5664 | ||
5665 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
5666 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
f5938f36 | 5667 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
319be8ae ID |
5668 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
5669 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
5670 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
5671 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
5672 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
5673 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
5674 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
5675 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
5676 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
f5938f36 | 5677 | BIT(POWER_DOMAIN_INIT)) |
efcad917 ID |
5678 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
5679 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
5680 | BIT(POWER_DOMAIN_INIT)) | |
5681 | ||
5682 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
5683 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
5684 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
5685 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
5686 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
5687 | BIT(POWER_DOMAIN_INIT)) | |
5688 | ||
77961eb9 ID |
5689 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
5690 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
5691 | ||
5692 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
5693 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
5694 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
5695 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
5696 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
5697 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
5698 | BIT(POWER_DOMAIN_INIT)) | |
5699 | ||
5700 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
5701 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
5702 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
5703 | BIT(POWER_DOMAIN_INIT)) | |
5704 | ||
5705 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
5706 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
5707 | BIT(POWER_DOMAIN_INIT)) | |
5708 | ||
5709 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
5710 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
5711 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
5712 | BIT(POWER_DOMAIN_INIT)) | |
5713 | ||
5714 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
5715 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
5716 | BIT(POWER_DOMAIN_INIT)) | |
5717 | ||
a45f4466 ID |
5718 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
5719 | .sync_hw = i9xx_always_on_power_well_noop, | |
5720 | .enable = i9xx_always_on_power_well_noop, | |
5721 | .disable = i9xx_always_on_power_well_noop, | |
5722 | .is_enabled = i9xx_always_on_power_well_enabled, | |
5723 | }; | |
c6cb582e | 5724 | |
1c2256df ID |
5725 | static struct i915_power_well i9xx_always_on_power_well[] = { |
5726 | { | |
5727 | .name = "always-on", | |
5728 | .always_on = 1, | |
5729 | .domains = POWER_DOMAIN_MASK, | |
c6cb582e | 5730 | .ops = &i9xx_always_on_power_well_ops, |
1c2256df ID |
5731 | }, |
5732 | }; | |
5733 | ||
c6cb582e ID |
5734 | static const struct i915_power_well_ops hsw_power_well_ops = { |
5735 | .sync_hw = hsw_power_well_sync_hw, | |
5736 | .enable = hsw_power_well_enable, | |
5737 | .disable = hsw_power_well_disable, | |
5738 | .is_enabled = hsw_power_well_enabled, | |
5739 | }; | |
5740 | ||
c1ca727f | 5741 | static struct i915_power_well hsw_power_wells[] = { |
6f3ef5dd ID |
5742 | { |
5743 | .name = "always-on", | |
5744 | .always_on = 1, | |
5745 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 5746 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 5747 | }, |
c1ca727f ID |
5748 | { |
5749 | .name = "display", | |
efcad917 | 5750 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 5751 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
5752 | }, |
5753 | }; | |
5754 | ||
5755 | static struct i915_power_well bdw_power_wells[] = { | |
6f3ef5dd ID |
5756 | { |
5757 | .name = "always-on", | |
5758 | .always_on = 1, | |
5759 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 5760 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 5761 | }, |
c1ca727f ID |
5762 | { |
5763 | .name = "display", | |
efcad917 | 5764 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 5765 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
5766 | }, |
5767 | }; | |
5768 | ||
77961eb9 ID |
5769 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
5770 | .sync_hw = vlv_power_well_sync_hw, | |
5771 | .enable = vlv_display_power_well_enable, | |
5772 | .disable = vlv_display_power_well_disable, | |
5773 | .is_enabled = vlv_power_well_enabled, | |
5774 | }; | |
5775 | ||
5776 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
5777 | .sync_hw = vlv_power_well_sync_hw, | |
5778 | .enable = vlv_power_well_enable, | |
5779 | .disable = vlv_power_well_disable, | |
5780 | .is_enabled = vlv_power_well_enabled, | |
5781 | }; | |
5782 | ||
5783 | static struct i915_power_well vlv_power_wells[] = { | |
5784 | { | |
5785 | .name = "always-on", | |
5786 | .always_on = 1, | |
5787 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
5788 | .ops = &i9xx_always_on_power_well_ops, | |
5789 | }, | |
5790 | { | |
5791 | .name = "display", | |
5792 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
5793 | .data = PUNIT_POWER_WELL_DISP2D, | |
5794 | .ops = &vlv_display_power_well_ops, | |
5795 | }, | |
5796 | { | |
5797 | .name = "dpio-common", | |
5798 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
5799 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
5800 | .ops = &vlv_dpio_power_well_ops, | |
5801 | }, | |
5802 | { | |
5803 | .name = "dpio-tx-b-01", | |
5804 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
5805 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
5806 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
5807 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
5808 | .ops = &vlv_dpio_power_well_ops, | |
5809 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
5810 | }, | |
5811 | { | |
5812 | .name = "dpio-tx-b-23", | |
5813 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
5814 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
5815 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
5816 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
5817 | .ops = &vlv_dpio_power_well_ops, | |
5818 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
5819 | }, | |
5820 | { | |
5821 | .name = "dpio-tx-c-01", | |
5822 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
5823 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
5824 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
5825 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
5826 | .ops = &vlv_dpio_power_well_ops, | |
5827 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
5828 | }, | |
5829 | { | |
5830 | .name = "dpio-tx-c-23", | |
5831 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
5832 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
5833 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
5834 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
5835 | .ops = &vlv_dpio_power_well_ops, | |
5836 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
5837 | }, | |
5838 | }; | |
5839 | ||
c1ca727f ID |
5840 | #define set_power_wells(power_domains, __power_wells) ({ \ |
5841 | (power_domains)->power_wells = (__power_wells); \ | |
5842 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
5843 | }) | |
5844 | ||
da7e29bd | 5845 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
a38911a3 | 5846 | { |
83c00f55 | 5847 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
c1ca727f | 5848 | |
83c00f55 | 5849 | mutex_init(&power_domains->lock); |
a38911a3 | 5850 | |
c1ca727f ID |
5851 | /* |
5852 | * The enabling order will be from lower to higher indexed wells, | |
5853 | * the disabling order is reversed. | |
5854 | */ | |
da7e29bd | 5855 | if (IS_HASWELL(dev_priv->dev)) { |
c1ca727f ID |
5856 | set_power_wells(power_domains, hsw_power_wells); |
5857 | hsw_pwr = power_domains; | |
da7e29bd | 5858 | } else if (IS_BROADWELL(dev_priv->dev)) { |
c1ca727f ID |
5859 | set_power_wells(power_domains, bdw_power_wells); |
5860 | hsw_pwr = power_domains; | |
77961eb9 ID |
5861 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
5862 | set_power_wells(power_domains, vlv_power_wells); | |
c1ca727f | 5863 | } else { |
1c2256df | 5864 | set_power_wells(power_domains, i9xx_always_on_power_well); |
c1ca727f | 5865 | } |
a38911a3 WX |
5866 | |
5867 | return 0; | |
5868 | } | |
5869 | ||
da7e29bd | 5870 | void intel_power_domains_remove(struct drm_i915_private *dev_priv) |
a38911a3 WX |
5871 | { |
5872 | hsw_pwr = NULL; | |
5873 | } | |
5874 | ||
da7e29bd | 5875 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
9cdb826c | 5876 | { |
83c00f55 ID |
5877 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
5878 | struct i915_power_well *power_well; | |
c1ca727f | 5879 | int i; |
9cdb826c | 5880 | |
83c00f55 | 5881 | mutex_lock(&power_domains->lock); |
a45f4466 ID |
5882 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) |
5883 | power_well->ops->sync_hw(dev_priv, power_well); | |
83c00f55 | 5884 | mutex_unlock(&power_domains->lock); |
a38911a3 WX |
5885 | } |
5886 | ||
da7e29bd | 5887 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
d0d3e513 | 5888 | { |
fa42e23c | 5889 | /* For now, we need the power well to be always enabled. */ |
da7e29bd ID |
5890 | intel_display_set_init_power(dev_priv, true); |
5891 | intel_power_domains_resume(dev_priv); | |
d0d3e513 ED |
5892 | } |
5893 | ||
c67a470b PZ |
5894 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
5895 | { | |
d361ae26 | 5896 | intel_runtime_pm_get(dev_priv); |
c67a470b PZ |
5897 | } |
5898 | ||
5899 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) | |
5900 | { | |
d361ae26 | 5901 | intel_runtime_pm_put(dev_priv); |
c67a470b PZ |
5902 | } |
5903 | ||
8a187455 PZ |
5904 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
5905 | { | |
5906 | struct drm_device *dev = dev_priv->dev; | |
5907 | struct device *device = &dev->pdev->dev; | |
5908 | ||
5909 | if (!HAS_RUNTIME_PM(dev)) | |
5910 | return; | |
5911 | ||
5912 | pm_runtime_get_sync(device); | |
5913 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
5914 | } | |
5915 | ||
5916 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) | |
5917 | { | |
5918 | struct drm_device *dev = dev_priv->dev; | |
5919 | struct device *device = &dev->pdev->dev; | |
5920 | ||
5921 | if (!HAS_RUNTIME_PM(dev)) | |
5922 | return; | |
5923 | ||
5924 | pm_runtime_mark_last_busy(device); | |
5925 | pm_runtime_put_autosuspend(device); | |
5926 | } | |
5927 | ||
5928 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv) | |
5929 | { | |
5930 | struct drm_device *dev = dev_priv->dev; | |
5931 | struct device *device = &dev->pdev->dev; | |
5932 | ||
8a187455 PZ |
5933 | if (!HAS_RUNTIME_PM(dev)) |
5934 | return; | |
5935 | ||
5936 | pm_runtime_set_active(device); | |
5937 | ||
5938 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
5939 | pm_runtime_mark_last_busy(device); | |
5940 | pm_runtime_use_autosuspend(device); | |
ba0239e0 PZ |
5941 | |
5942 | pm_runtime_put_autosuspend(device); | |
8a187455 PZ |
5943 | } |
5944 | ||
5945 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) | |
5946 | { | |
5947 | struct drm_device *dev = dev_priv->dev; | |
5948 | struct device *device = &dev->pdev->dev; | |
5949 | ||
5950 | if (!HAS_RUNTIME_PM(dev)) | |
5951 | return; | |
5952 | ||
5953 | /* Make sure we're not suspended first. */ | |
5954 | pm_runtime_get_sync(device); | |
5955 | pm_runtime_disable(device); | |
5956 | } | |
5957 | ||
1fa61106 ED |
5958 | /* Set up chip specific power management-related functions */ |
5959 | void intel_init_pm(struct drm_device *dev) | |
5960 | { | |
5961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5962 | ||
3a77c4c4 | 5963 | if (HAS_FBC(dev)) { |
40045465 | 5964 | if (INTEL_INFO(dev)->gen >= 7) { |
1fa61106 | 5965 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
40045465 VS |
5966 | dev_priv->display.enable_fbc = gen7_enable_fbc; |
5967 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
5968 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
5969 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
5970 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
1fa61106 ED |
5971 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
5972 | } else if (IS_GM45(dev)) { | |
5973 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
5974 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
5975 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
40045465 | 5976 | } else { |
1fa61106 ED |
5977 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
5978 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
5979 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
993495ae VS |
5980 | |
5981 | /* This value was pulled out of someone's hat */ | |
5982 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1fa61106 | 5983 | } |
1fa61106 ED |
5984 | } |
5985 | ||
c921aba8 DV |
5986 | /* For cxsr */ |
5987 | if (IS_PINEVIEW(dev)) | |
5988 | i915_pineview_get_mem_freq(dev); | |
5989 | else if (IS_GEN5(dev)) | |
5990 | i915_ironlake_get_mem_freq(dev); | |
5991 | ||
1fa61106 ED |
5992 | /* For FIFO watermark updates */ |
5993 | if (HAS_PCH_SPLIT(dev)) { | |
fa50ad61 | 5994 | ilk_setup_wm_latency(dev); |
53615a5e | 5995 | |
bd602544 VS |
5996 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
5997 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
5998 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
5999 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6000 | dev_priv->display.update_wm = ilk_update_wm; | |
6001 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6002 | } else { | |
6003 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6004 | "Disable CxSR\n"); | |
6005 | } | |
6006 | ||
6007 | if (IS_GEN5(dev)) | |
1fa61106 | 6008 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6009 | else if (IS_GEN6(dev)) |
1fa61106 | 6010 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6011 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6012 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6013 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6014 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6015 | else if (INTEL_INFO(dev)->gen == 8) |
1020a5c2 | 6016 | dev_priv->display.init_clock_gating = gen8_init_clock_gating; |
1fa61106 ED |
6017 | } else if (IS_VALLEYVIEW(dev)) { |
6018 | dev_priv->display.update_wm = valleyview_update_wm; | |
6019 | dev_priv->display.init_clock_gating = | |
6020 | valleyview_init_clock_gating; | |
1fa61106 ED |
6021 | } else if (IS_PINEVIEW(dev)) { |
6022 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6023 | dev_priv->is_ddr3, | |
6024 | dev_priv->fsb_freq, | |
6025 | dev_priv->mem_freq)) { | |
6026 | DRM_INFO("failed to find known CxSR latency " | |
6027 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6028 | "disabling CxSR\n", | |
6029 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6030 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6031 | /* Disable CxSR and never update its watermark again */ | |
6032 | pineview_disable_cxsr(dev); | |
6033 | dev_priv->display.update_wm = NULL; | |
6034 | } else | |
6035 | dev_priv->display.update_wm = pineview_update_wm; | |
6036 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6037 | } else if (IS_G4X(dev)) { | |
6038 | dev_priv->display.update_wm = g4x_update_wm; | |
6039 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6040 | } else if (IS_GEN4(dev)) { | |
6041 | dev_priv->display.update_wm = i965_update_wm; | |
6042 | if (IS_CRESTLINE(dev)) | |
6043 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6044 | else if (IS_BROADWATER(dev)) | |
6045 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6046 | } else if (IS_GEN3(dev)) { | |
6047 | dev_priv->display.update_wm = i9xx_update_wm; | |
6048 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6049 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6050 | } else if (IS_GEN2(dev)) { |
6051 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6052 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6053 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6054 | } else { |
6055 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6056 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6057 | } |
6058 | ||
6059 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6060 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6061 | else | |
6062 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6063 | } else { | |
6064 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6065 | } |
6066 | } | |
6067 | ||
42c0526c BW |
6068 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
6069 | { | |
4fc688ce | 6070 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6071 | |
6072 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6073 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6074 | return -EAGAIN; | |
6075 | } | |
6076 | ||
6077 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
6078 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6079 | ||
6080 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6081 | 500)) { | |
6082 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6083 | return -ETIMEDOUT; | |
6084 | } | |
6085 | ||
6086 | *val = I915_READ(GEN6_PCODE_DATA); | |
6087 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6088 | ||
6089 | return 0; | |
6090 | } | |
6091 | ||
6092 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) | |
6093 | { | |
4fc688ce | 6094 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6095 | |
6096 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6097 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6098 | return -EAGAIN; | |
6099 | } | |
6100 | ||
6101 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6102 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6103 | ||
6104 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6105 | 500)) { | |
6106 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6107 | return -ETIMEDOUT; | |
6108 | } | |
6109 | ||
6110 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6111 | ||
6112 | return 0; | |
6113 | } | |
a0e4e199 | 6114 | |
2ec3815f | 6115 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6116 | { |
07ab118b | 6117 | int div; |
855ba3be | 6118 | |
07ab118b | 6119 | /* 4 x czclk */ |
2ec3815f | 6120 | switch (dev_priv->mem_freq) { |
855ba3be | 6121 | case 800: |
07ab118b | 6122 | div = 10; |
855ba3be JB |
6123 | break; |
6124 | case 1066: | |
07ab118b | 6125 | div = 12; |
855ba3be JB |
6126 | break; |
6127 | case 1333: | |
07ab118b | 6128 | div = 16; |
855ba3be JB |
6129 | break; |
6130 | default: | |
6131 | return -1; | |
6132 | } | |
6133 | ||
2ec3815f | 6134 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
855ba3be JB |
6135 | } |
6136 | ||
2ec3815f | 6137 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6138 | { |
07ab118b | 6139 | int mul; |
855ba3be | 6140 | |
07ab118b | 6141 | /* 4 x czclk */ |
2ec3815f | 6142 | switch (dev_priv->mem_freq) { |
855ba3be | 6143 | case 800: |
07ab118b | 6144 | mul = 10; |
855ba3be JB |
6145 | break; |
6146 | case 1066: | |
07ab118b | 6147 | mul = 12; |
855ba3be JB |
6148 | break; |
6149 | case 1333: | |
07ab118b | 6150 | mul = 16; |
855ba3be JB |
6151 | break; |
6152 | default: | |
6153 | return -1; | |
6154 | } | |
6155 | ||
2ec3815f | 6156 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
855ba3be JB |
6157 | } |
6158 | ||
f742a552 | 6159 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
6160 | { |
6161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6162 | ||
f742a552 DV |
6163 | mutex_init(&dev_priv->rps.hw_lock); |
6164 | ||
907b28c5 CW |
6165 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6166 | intel_gen6_powersave_work); | |
5d584b2e | 6167 | |
33688d95 | 6168 | dev_priv->pm.suspended = false; |
5d584b2e | 6169 | dev_priv->pm.irqs_disabled = false; |
907b28c5 | 6170 | } |